1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, NVIDIA CORPORATION.
5 * Portions based on U-Boot's rtl8169.c.
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
22 * The following configurations are currently supported:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
47 #define EQOS_MAC_REGS_BASE 0x000
48 struct eqos_mac_regs {
49 uint32_t configuration; /* 0x000 */
50 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
51 uint32_t q0_tx_flow_ctrl; /* 0x070 */
52 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
53 uint32_t rx_flow_ctrl; /* 0x090 */
54 uint32_t unused_094; /* 0x094 */
55 uint32_t txq_prty_map0; /* 0x098 */
56 uint32_t unused_09c; /* 0x09c */
57 uint32_t rxq_ctrl0; /* 0x0a0 */
58 uint32_t unused_0a4; /* 0x0a4 */
59 uint32_t rxq_ctrl2; /* 0x0a8 */
60 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
61 uint32_t us_tic_counter; /* 0x0dc */
62 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
63 uint32_t hw_feature0; /* 0x11c */
64 uint32_t hw_feature1; /* 0x120 */
65 uint32_t hw_feature2; /* 0x124 */
66 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
67 uint32_t mdio_address; /* 0x200 */
68 uint32_t mdio_data; /* 0x204 */
69 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
70 uint32_t address0_high; /* 0x300 */
71 uint32_t address0_low; /* 0x304 */
74 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
75 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
76 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
77 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
78 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
79 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
80 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
81 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
82 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
83 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
84 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
86 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
87 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
88 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
90 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
92 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
93 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
95 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
96 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
99 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
101 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
102 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
104 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
105 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
106 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
107 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
109 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
110 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
111 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
112 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
113 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
114 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
115 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
116 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
117 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
118 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
119 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
121 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
123 #define EQOS_MTL_REGS_BASE 0xd00
124 struct eqos_mtl_regs {
125 uint32_t txq0_operation_mode; /* 0xd00 */
126 uint32_t unused_d04; /* 0xd04 */
127 uint32_t txq0_debug; /* 0xd08 */
128 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
129 uint32_t txq0_quantum_weight; /* 0xd18 */
130 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
131 uint32_t rxq0_operation_mode; /* 0xd30 */
132 uint32_t unused_d34; /* 0xd34 */
133 uint32_t rxq0_debug; /* 0xd38 */
136 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
137 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
138 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
139 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
140 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
141 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
142 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
144 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
145 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
146 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
148 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
149 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
150 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
151 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
152 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
153 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
154 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
155 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
157 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
158 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
159 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
160 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
162 #define EQOS_DMA_REGS_BASE 0x1000
163 struct eqos_dma_regs {
164 uint32_t mode; /* 0x1000 */
165 uint32_t sysbus_mode; /* 0x1004 */
166 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
167 uint32_t ch0_control; /* 0x1100 */
168 uint32_t ch0_tx_control; /* 0x1104 */
169 uint32_t ch0_rx_control; /* 0x1108 */
170 uint32_t unused_110c; /* 0x110c */
171 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
172 uint32_t ch0_txdesc_list_address; /* 0x1114 */
173 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
174 uint32_t ch0_rxdesc_list_address; /* 0x111c */
175 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
176 uint32_t unused_1124; /* 0x1124 */
177 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
178 uint32_t ch0_txdesc_ring_length; /* 0x112c */
179 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
182 #define EQOS_DMA_MODE_SWR BIT(0)
184 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
185 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
186 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
187 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
188 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
189 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
191 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
193 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
194 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
195 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
196 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
198 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
199 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
200 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
201 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
202 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
204 /* These registers are Tegra186-specific */
205 #define EQOS_TEGRA186_REGS_BASE 0x8800
206 struct eqos_tegra186_regs {
207 uint32_t sdmemcomppadctrl; /* 0x8800 */
208 uint32_t auto_cal_config; /* 0x8804 */
209 uint32_t unused_8808; /* 0x8808 */
210 uint32_t auto_cal_status; /* 0x880c */
213 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
215 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
216 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
218 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
222 #define EQOS_DESCRIPTOR_WORDS 4
223 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
224 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
225 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
226 #define EQOS_DESCRIPTORS_TX 4
227 #define EQOS_DESCRIPTORS_RX 4
228 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
229 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
230 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
231 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
232 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
233 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
236 * Warn if the cache-line size is larger than the descriptor size. In such
237 * cases the driver will likely fail because the CPU needs to flush the cache
238 * when requeuing RX buffers, therefore descriptors written by the hardware
239 * may be discarded. Architectures with full IO coherence, such as x86, do not
240 * experience this issue, and hence are excluded from this condition.
242 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
243 * the driver to allocate descriptors from a pool of non-cached memory.
245 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
246 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
247 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
248 #warning Cache line size is larger than descriptor size
259 #define EQOS_DESC3_OWN BIT(31)
260 #define EQOS_DESC3_FD BIT(29)
261 #define EQOS_DESC3_LD BIT(28)
262 #define EQOS_DESC3_BUF1V BIT(24)
265 bool reg_access_always_ok;
270 phy_interface_t (*interface)(struct udevice *dev);
271 struct eqos_ops *ops;
275 void (*eqos_inval_desc)(void *desc);
276 void (*eqos_flush_desc)(void *desc);
277 void (*eqos_inval_buffer)(void *buf, size_t size);
278 void (*eqos_flush_buffer)(void *buf, size_t size);
279 int (*eqos_probe_resources)(struct udevice *dev);
280 int (*eqos_remove_resources)(struct udevice *dev);
281 int (*eqos_stop_resets)(struct udevice *dev);
282 int (*eqos_start_resets)(struct udevice *dev);
283 void (*eqos_stop_clks)(struct udevice *dev);
284 int (*eqos_start_clks)(struct udevice *dev);
285 int (*eqos_calibrate_pads)(struct udevice *dev);
286 int (*eqos_disable_calibration)(struct udevice *dev);
287 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
288 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
293 const struct eqos_config *config;
295 struct eqos_mac_regs *mac_regs;
296 struct eqos_mtl_regs *mtl_regs;
297 struct eqos_dma_regs *dma_regs;
298 struct eqos_tegra186_regs *tegra186_regs;
299 struct reset_ctl reset_ctl;
300 struct gpio_desc phy_reset_gpio;
301 struct clk clk_master_bus;
303 struct clk clk_ptp_ref;
306 struct clk clk_slave_bus;
308 struct phy_device *phy;
310 struct eqos_desc *tx_descs;
311 struct eqos_desc *rx_descs;
312 int tx_desc_idx, rx_desc_idx;
321 * TX and RX descriptors are 16 bytes. This causes problems with the cache
322 * maintenance on CPUs where the cache-line size exceeds the size of these
323 * descriptors. What will happen is that when the driver receives a packet
324 * it will be immediately requeued for the hardware to reuse. The CPU will
325 * therefore need to flush the cache-line containing the descriptor, which
326 * will cause all other descriptors in the same cache-line to be flushed
327 * along with it. If one of those descriptors had been written to by the
328 * device those changes (and the associated packet) will be lost.
330 * To work around this, we make use of non-cached memory if available. If
331 * descriptors are mapped uncached there's no need to manually flush them
332 * or invalidate them.
334 * Note that this only applies to descriptors. The packet data buffers do
335 * not have the same constraints since they are 1536 bytes large, so they
336 * are unlikely to share cache-lines.
338 static void *eqos_alloc_descs(unsigned int num)
340 #ifdef CONFIG_SYS_NONCACHED_MEMORY
341 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
342 EQOS_DESCRIPTOR_ALIGN);
344 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
348 static void eqos_free_descs(void *descs)
350 #ifdef CONFIG_SYS_NONCACHED_MEMORY
351 /* FIXME: noncached_alloc() has no opposite */
357 static void eqos_inval_desc_tegra186(void *desc)
359 #ifndef CONFIG_SYS_NONCACHED_MEMORY
360 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
361 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
364 invalidate_dcache_range(start, end);
368 static void eqos_inval_desc_stm32(void *desc)
370 #ifndef CONFIG_SYS_NONCACHED_MEMORY
371 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
372 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
375 invalidate_dcache_range(start, end);
379 static void eqos_flush_desc_tegra186(void *desc)
381 #ifndef CONFIG_SYS_NONCACHED_MEMORY
382 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
386 static void eqos_flush_desc_stm32(void *desc)
388 #ifndef CONFIG_SYS_NONCACHED_MEMORY
389 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
390 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
393 flush_dcache_range(start, end);
397 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
399 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
400 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
402 invalidate_dcache_range(start, end);
405 static void eqos_inval_buffer_stm32(void *buf, size_t size)
407 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
408 unsigned long end = roundup((unsigned long)buf + size,
411 invalidate_dcache_range(start, end);
414 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
416 flush_cache((unsigned long)buf, size);
419 static void eqos_flush_buffer_stm32(void *buf, size_t size)
421 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
422 unsigned long end = roundup((unsigned long)buf + size,
425 flush_dcache_range(start, end);
428 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
430 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
431 EQOS_MAC_MDIO_ADDRESS_GB, false,
435 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
438 struct eqos_priv *eqos = bus->priv;
442 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
445 ret = eqos_mdio_wait_idle(eqos);
447 pr_err("MDIO not idle at entry");
451 val = readl(&eqos->mac_regs->mdio_address);
452 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
453 EQOS_MAC_MDIO_ADDRESS_C45E;
454 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
455 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
456 (eqos->config->config_mac_mdio <<
457 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
458 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
459 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
460 EQOS_MAC_MDIO_ADDRESS_GB;
461 writel(val, &eqos->mac_regs->mdio_address);
463 udelay(eqos->config->mdio_wait);
465 ret = eqos_mdio_wait_idle(eqos);
467 pr_err("MDIO read didn't complete");
471 val = readl(&eqos->mac_regs->mdio_data);
472 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
474 debug("%s: val=%x\n", __func__, val);
479 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
480 int mdio_reg, u16 mdio_val)
482 struct eqos_priv *eqos = bus->priv;
486 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
487 mdio_addr, mdio_reg, mdio_val);
489 ret = eqos_mdio_wait_idle(eqos);
491 pr_err("MDIO not idle at entry");
495 writel(mdio_val, &eqos->mac_regs->mdio_data);
497 val = readl(&eqos->mac_regs->mdio_address);
498 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
499 EQOS_MAC_MDIO_ADDRESS_C45E;
500 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
501 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
502 (eqos->config->config_mac_mdio <<
503 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
504 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
505 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
506 EQOS_MAC_MDIO_ADDRESS_GB;
507 writel(val, &eqos->mac_regs->mdio_address);
509 udelay(eqos->config->mdio_wait);
511 ret = eqos_mdio_wait_idle(eqos);
513 pr_err("MDIO read didn't complete");
520 static int eqos_start_clks_tegra186(struct udevice *dev)
522 struct eqos_priv *eqos = dev_get_priv(dev);
525 debug("%s(dev=%p):\n", __func__, dev);
527 ret = clk_enable(&eqos->clk_slave_bus);
529 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
533 ret = clk_enable(&eqos->clk_master_bus);
535 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
536 goto err_disable_clk_slave_bus;
539 ret = clk_enable(&eqos->clk_rx);
541 pr_err("clk_enable(clk_rx) failed: %d", ret);
542 goto err_disable_clk_master_bus;
545 ret = clk_enable(&eqos->clk_ptp_ref);
547 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
548 goto err_disable_clk_rx;
551 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
553 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
554 goto err_disable_clk_ptp_ref;
557 ret = clk_enable(&eqos->clk_tx);
559 pr_err("clk_enable(clk_tx) failed: %d", ret);
560 goto err_disable_clk_ptp_ref;
563 debug("%s: OK\n", __func__);
566 err_disable_clk_ptp_ref:
567 clk_disable(&eqos->clk_ptp_ref);
569 clk_disable(&eqos->clk_rx);
570 err_disable_clk_master_bus:
571 clk_disable(&eqos->clk_master_bus);
572 err_disable_clk_slave_bus:
573 clk_disable(&eqos->clk_slave_bus);
575 debug("%s: FAILED: %d\n", __func__, ret);
579 static int eqos_start_clks_stm32(struct udevice *dev)
581 struct eqos_priv *eqos = dev_get_priv(dev);
584 debug("%s(dev=%p):\n", __func__, dev);
586 ret = clk_enable(&eqos->clk_master_bus);
588 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
592 ret = clk_enable(&eqos->clk_rx);
594 pr_err("clk_enable(clk_rx) failed: %d", ret);
595 goto err_disable_clk_master_bus;
598 ret = clk_enable(&eqos->clk_tx);
600 pr_err("clk_enable(clk_tx) failed: %d", ret);
601 goto err_disable_clk_rx;
604 if (clk_valid(&eqos->clk_ck)) {
605 ret = clk_enable(&eqos->clk_ck);
607 pr_err("clk_enable(clk_ck) failed: %d", ret);
608 goto err_disable_clk_tx;
612 debug("%s: OK\n", __func__);
616 clk_disable(&eqos->clk_tx);
618 clk_disable(&eqos->clk_rx);
619 err_disable_clk_master_bus:
620 clk_disable(&eqos->clk_master_bus);
622 debug("%s: FAILED: %d\n", __func__, ret);
626 static void eqos_stop_clks_tegra186(struct udevice *dev)
628 struct eqos_priv *eqos = dev_get_priv(dev);
630 debug("%s(dev=%p):\n", __func__, dev);
632 clk_disable(&eqos->clk_tx);
633 clk_disable(&eqos->clk_ptp_ref);
634 clk_disable(&eqos->clk_rx);
635 clk_disable(&eqos->clk_master_bus);
636 clk_disable(&eqos->clk_slave_bus);
638 debug("%s: OK\n", __func__);
641 static void eqos_stop_clks_stm32(struct udevice *dev)
643 struct eqos_priv *eqos = dev_get_priv(dev);
645 debug("%s(dev=%p):\n", __func__, dev);
647 clk_disable(&eqos->clk_tx);
648 clk_disable(&eqos->clk_rx);
649 clk_disable(&eqos->clk_master_bus);
650 if (clk_valid(&eqos->clk_ck))
651 clk_disable(&eqos->clk_ck);
653 debug("%s: OK\n", __func__);
656 static int eqos_start_resets_tegra186(struct udevice *dev)
658 struct eqos_priv *eqos = dev_get_priv(dev);
661 debug("%s(dev=%p):\n", __func__, dev);
663 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
665 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
671 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
673 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
677 ret = reset_assert(&eqos->reset_ctl);
679 pr_err("reset_assert() failed: %d", ret);
685 ret = reset_deassert(&eqos->reset_ctl);
687 pr_err("reset_deassert() failed: %d", ret);
691 debug("%s: OK\n", __func__);
695 static int eqos_start_resets_stm32(struct udevice *dev)
700 static int eqos_stop_resets_tegra186(struct udevice *dev)
702 struct eqos_priv *eqos = dev_get_priv(dev);
704 reset_assert(&eqos->reset_ctl);
705 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
710 static int eqos_stop_resets_stm32(struct udevice *dev)
715 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
717 struct eqos_priv *eqos = dev_get_priv(dev);
720 debug("%s(dev=%p):\n", __func__, dev);
722 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
723 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
727 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
728 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
730 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
731 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
733 pr_err("calibrate didn't start");
737 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
738 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
740 pr_err("calibrate didn't finish");
747 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
748 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
750 debug("%s: returns %d\n", __func__, ret);
755 static int eqos_disable_calibration_tegra186(struct udevice *dev)
757 struct eqos_priv *eqos = dev_get_priv(dev);
759 debug("%s(dev=%p):\n", __func__, dev);
761 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
762 EQOS_AUTO_CAL_CONFIG_ENABLE);
767 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
769 struct eqos_priv *eqos = dev_get_priv(dev);
771 return clk_get_rate(&eqos->clk_slave_bus);
774 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
776 struct eqos_priv *eqos = dev_get_priv(dev);
778 return clk_get_rate(&eqos->clk_master_bus);
781 static int eqos_calibrate_pads_stm32(struct udevice *dev)
786 static int eqos_disable_calibration_stm32(struct udevice *dev)
791 static int eqos_set_full_duplex(struct udevice *dev)
793 struct eqos_priv *eqos = dev_get_priv(dev);
795 debug("%s(dev=%p):\n", __func__, dev);
797 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
802 static int eqos_set_half_duplex(struct udevice *dev)
804 struct eqos_priv *eqos = dev_get_priv(dev);
806 debug("%s(dev=%p):\n", __func__, dev);
808 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
810 /* WAR: Flush TX queue when switching to half-duplex */
811 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
812 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
817 static int eqos_set_gmii_speed(struct udevice *dev)
819 struct eqos_priv *eqos = dev_get_priv(dev);
821 debug("%s(dev=%p):\n", __func__, dev);
823 clrbits_le32(&eqos->mac_regs->configuration,
824 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
829 static int eqos_set_mii_speed_100(struct udevice *dev)
831 struct eqos_priv *eqos = dev_get_priv(dev);
833 debug("%s(dev=%p):\n", __func__, dev);
835 setbits_le32(&eqos->mac_regs->configuration,
836 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
841 static int eqos_set_mii_speed_10(struct udevice *dev)
843 struct eqos_priv *eqos = dev_get_priv(dev);
845 debug("%s(dev=%p):\n", __func__, dev);
847 clrsetbits_le32(&eqos->mac_regs->configuration,
848 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
853 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
855 struct eqos_priv *eqos = dev_get_priv(dev);
859 debug("%s(dev=%p):\n", __func__, dev);
861 switch (eqos->phy->speed) {
863 rate = 125 * 1000 * 1000;
866 rate = 25 * 1000 * 1000;
869 rate = 2.5 * 1000 * 1000;
872 pr_err("invalid speed %d", eqos->phy->speed);
876 ret = clk_set_rate(&eqos->clk_tx, rate);
878 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
885 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
890 static int eqos_adjust_link(struct udevice *dev)
892 struct eqos_priv *eqos = dev_get_priv(dev);
896 debug("%s(dev=%p):\n", __func__, dev);
898 if (eqos->phy->duplex)
899 ret = eqos_set_full_duplex(dev);
901 ret = eqos_set_half_duplex(dev);
903 pr_err("eqos_set_*_duplex() failed: %d", ret);
907 switch (eqos->phy->speed) {
909 en_calibration = true;
910 ret = eqos_set_gmii_speed(dev);
913 en_calibration = true;
914 ret = eqos_set_mii_speed_100(dev);
917 en_calibration = false;
918 ret = eqos_set_mii_speed_10(dev);
921 pr_err("invalid speed %d", eqos->phy->speed);
925 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
929 if (en_calibration) {
930 ret = eqos->config->ops->eqos_calibrate_pads(dev);
932 pr_err("eqos_calibrate_pads() failed: %d",
937 ret = eqos->config->ops->eqos_disable_calibration(dev);
939 pr_err("eqos_disable_calibration() failed: %d",
944 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
946 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
953 static int eqos_write_hwaddr(struct udevice *dev)
955 struct eth_pdata *plat = dev_get_platdata(dev);
956 struct eqos_priv *eqos = dev_get_priv(dev);
960 * This function may be called before start() or after stop(). At that
961 * time, on at least some configurations of the EQoS HW, all clocks to
962 * the EQoS HW block will be stopped, and a reset signal applied. If
963 * any register access is attempted in this state, bus timeouts or CPU
964 * hangs may occur. This check prevents that.
966 * A simple solution to this problem would be to not implement
967 * write_hwaddr(), since start() always writes the MAC address into HW
968 * anyway. However, it is desirable to implement write_hwaddr() to
969 * support the case of SW that runs subsequent to U-Boot which expects
970 * the MAC address to already be programmed into the EQoS registers,
971 * which must happen irrespective of whether the U-Boot user (or
972 * scripts) actually made use of the EQoS device, and hence
973 * irrespective of whether start() was ever called.
975 * Note that this requirement by subsequent SW is not valid for
976 * Tegra186, and is likely not valid for any non-PCI instantiation of
977 * the EQoS HW block. This function is implemented solely as
978 * future-proofing with the expectation the driver will eventually be
979 * ported to some system where the expectation above is true.
981 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
984 /* Update the MAC address */
985 val = (plat->enetaddr[5] << 8) |
987 writel(val, &eqos->mac_regs->address0_high);
988 val = (plat->enetaddr[3] << 24) |
989 (plat->enetaddr[2] << 16) |
990 (plat->enetaddr[1] << 8) |
992 writel(val, &eqos->mac_regs->address0_low);
997 static int eqos_start(struct udevice *dev)
999 struct eqos_priv *eqos = dev_get_priv(dev);
1002 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1005 debug("%s(dev=%p):\n", __func__, dev);
1007 eqos->tx_desc_idx = 0;
1008 eqos->rx_desc_idx = 0;
1010 ret = eqos->config->ops->eqos_start_clks(dev);
1012 pr_err("eqos_start_clks() failed: %d", ret);
1016 ret = eqos->config->ops->eqos_start_resets(dev);
1018 pr_err("eqos_start_resets() failed: %d", ret);
1024 eqos->reg_access_ok = true;
1026 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
1027 EQOS_DMA_MODE_SWR, false,
1028 eqos->config->swr_wait, false);
1030 pr_err("EQOS_DMA_MODE_SWR stuck");
1031 goto err_stop_resets;
1034 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1036 pr_err("eqos_calibrate_pads() failed: %d", ret);
1037 goto err_stop_resets;
1039 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
1041 val = (rate / 1000000) - 1;
1042 writel(val, &eqos->mac_regs->us_tic_counter);
1045 * if PHY was already connected and configured,
1046 * don't need to reconnect/reconfigure again
1049 eqos->phy = phy_connect(eqos->mii, -1, dev,
1050 eqos->config->interface(dev));
1052 pr_err("phy_connect() failed");
1053 goto err_stop_resets;
1055 ret = phy_config(eqos->phy);
1057 pr_err("phy_config() failed: %d", ret);
1058 goto err_shutdown_phy;
1062 ret = phy_startup(eqos->phy);
1064 pr_err("phy_startup() failed: %d", ret);
1065 goto err_shutdown_phy;
1068 if (!eqos->phy->link) {
1070 goto err_shutdown_phy;
1073 ret = eqos_adjust_link(dev);
1075 pr_err("eqos_adjust_link() failed: %d", ret);
1076 goto err_shutdown_phy;
1081 /* Enable Store and Forward mode for TX */
1082 /* Program Tx operating mode */
1083 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1084 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1085 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1086 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1088 /* Transmit Queue weight */
1089 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1091 /* Enable Store and Forward mode for RX, since no jumbo frame */
1092 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1093 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
1095 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1096 val = readl(&eqos->mac_regs->hw_feature1);
1097 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1098 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1099 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1100 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1103 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1104 * r/tqs is encoded as (n / 256) - 1.
1106 tqs = (128 << tx_fifo_sz) / 256 - 1;
1107 rqs = (128 << rx_fifo_sz) / 256 - 1;
1109 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1110 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1111 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1112 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1113 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1114 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1115 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1116 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1118 /* Flow control used only if each channel gets 4KB or more FIFO */
1119 if (rqs >= ((4096 / 256) - 1)) {
1122 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1123 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1126 * Set Threshold for Activating Flow Contol space for min 2
1127 * frames ie, (1500 * 1) = 1500 bytes.
1129 * Set Threshold for Deactivating Flow Contol for space of
1130 * min 1 frame (frame size 1500bytes) in receive fifo
1132 if (rqs == ((4096 / 256) - 1)) {
1134 * This violates the above formula because of FIFO size
1135 * limit therefore overflow may occur inspite of this.
1137 rfd = 0x3; /* Full-3K */
1138 rfa = 0x1; /* Full-1.5K */
1139 } else if (rqs == ((8192 / 256) - 1)) {
1140 rfd = 0x6; /* Full-4K */
1141 rfa = 0xa; /* Full-6K */
1142 } else if (rqs == ((16384 / 256) - 1)) {
1143 rfd = 0x6; /* Full-4K */
1144 rfa = 0x12; /* Full-10K */
1146 rfd = 0x6; /* Full-4K */
1147 rfa = 0x1E; /* Full-16K */
1150 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1151 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1152 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1153 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1154 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1156 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1158 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1163 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1164 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1165 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1166 eqos->config->config_mac <<
1167 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1169 /* Set TX flow control parameters */
1170 /* Set Pause Time */
1171 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1172 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1173 /* Assign priority for TX flow control */
1174 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1175 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1176 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1177 /* Assign priority for RX flow control */
1178 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1179 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1180 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1181 /* Enable flow control */
1182 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1183 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1184 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1185 EQOS_MAC_RX_FLOW_CTRL_RFE);
1187 clrsetbits_le32(&eqos->mac_regs->configuration,
1188 EQOS_MAC_CONFIGURATION_GPSLCE |
1189 EQOS_MAC_CONFIGURATION_WD |
1190 EQOS_MAC_CONFIGURATION_JD |
1191 EQOS_MAC_CONFIGURATION_JE,
1192 EQOS_MAC_CONFIGURATION_CST |
1193 EQOS_MAC_CONFIGURATION_ACS);
1195 eqos_write_hwaddr(dev);
1199 /* Enable OSP mode */
1200 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1201 EQOS_DMA_CH0_TX_CONTROL_OSP);
1203 /* RX buffer size. Must be a multiple of bus width */
1204 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1205 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1206 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1207 EQOS_MAX_PACKET_SIZE <<
1208 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1210 setbits_le32(&eqos->dma_regs->ch0_control,
1211 EQOS_DMA_CH0_CONTROL_PBLX8);
1214 * Burst length must be < 1/2 FIFO size.
1215 * FIFO size in tqs is encoded as (n / 256) - 1.
1216 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1217 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1222 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1223 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1224 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1225 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1227 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1228 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1229 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1230 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1232 /* DMA performance configuration */
1233 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1234 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1235 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1236 writel(val, &eqos->dma_regs->sysbus_mode);
1238 /* Set up descriptors */
1240 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1241 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1242 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1243 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1244 (i * EQOS_MAX_PACKET_SIZE));
1245 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1247 eqos->config->ops->eqos_flush_desc(eqos->descs);
1249 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1250 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1251 writel(EQOS_DESCRIPTORS_TX - 1,
1252 &eqos->dma_regs->ch0_txdesc_ring_length);
1254 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1255 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1256 writel(EQOS_DESCRIPTORS_RX - 1,
1257 &eqos->dma_regs->ch0_rxdesc_ring_length);
1259 /* Enable everything */
1261 setbits_le32(&eqos->mac_regs->configuration,
1262 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1264 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1265 EQOS_DMA_CH0_TX_CONTROL_ST);
1266 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1267 EQOS_DMA_CH0_RX_CONTROL_SR);
1269 /* TX tail pointer not written until we need to TX a packet */
1271 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1272 * first descriptor, implying all descriptors were available. However,
1273 * that's not distinguishable from none of the descriptors being
1276 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1277 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1279 eqos->started = true;
1281 debug("%s: OK\n", __func__);
1285 phy_shutdown(eqos->phy);
1287 eqos->config->ops->eqos_stop_resets(dev);
1289 eqos->config->ops->eqos_stop_clks(dev);
1291 pr_err("FAILED: %d", ret);
1295 static void eqos_stop(struct udevice *dev)
1297 struct eqos_priv *eqos = dev_get_priv(dev);
1300 debug("%s(dev=%p):\n", __func__, dev);
1304 eqos->started = false;
1305 eqos->reg_access_ok = false;
1307 /* Disable TX DMA */
1308 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1309 EQOS_DMA_CH0_TX_CONTROL_ST);
1311 /* Wait for TX all packets to drain out of MTL */
1312 for (i = 0; i < 1000000; i++) {
1313 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1314 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1315 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1316 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1317 if ((trcsts != 1) && (!txqsts))
1321 /* Turn off MAC TX and RX */
1322 clrbits_le32(&eqos->mac_regs->configuration,
1323 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1325 /* Wait for all RX packets to drain out of MTL */
1326 for (i = 0; i < 1000000; i++) {
1327 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1328 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1329 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1330 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1331 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1332 if ((!prxq) && (!rxqsts))
1336 /* Turn off RX DMA */
1337 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1338 EQOS_DMA_CH0_RX_CONTROL_SR);
1341 phy_shutdown(eqos->phy);
1343 eqos->config->ops->eqos_stop_resets(dev);
1344 eqos->config->ops->eqos_stop_clks(dev);
1346 debug("%s: OK\n", __func__);
1349 static int eqos_send(struct udevice *dev, void *packet, int length)
1351 struct eqos_priv *eqos = dev_get_priv(dev);
1352 struct eqos_desc *tx_desc;
1355 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1358 memcpy(eqos->tx_dma_buf, packet, length);
1359 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1361 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1362 eqos->tx_desc_idx++;
1363 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1365 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1367 tx_desc->des2 = length;
1369 * Make sure that if HW sees the _OWN write below, it will see all the
1370 * writes to the rest of the descriptor too.
1373 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1374 eqos->config->ops->eqos_flush_desc(tx_desc);
1376 writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
1378 for (i = 0; i < 1000000; i++) {
1379 eqos->config->ops->eqos_inval_desc(tx_desc);
1380 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1385 debug("%s: TX timeout\n", __func__);
1390 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1392 struct eqos_priv *eqos = dev_get_priv(dev);
1393 struct eqos_desc *rx_desc;
1396 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1398 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1399 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1400 debug("%s: RX packet not available\n", __func__);
1404 *packetp = eqos->rx_dma_buf +
1405 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1406 length = rx_desc->des3 & 0x7fff;
1407 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1409 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1414 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1416 struct eqos_priv *eqos = dev_get_priv(dev);
1417 uchar *packet_expected;
1418 struct eqos_desc *rx_desc;
1420 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1422 packet_expected = eqos->rx_dma_buf +
1423 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1424 if (packet != packet_expected) {
1425 debug("%s: Unexpected packet (expected %p)\n", __func__,
1430 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1431 rx_desc->des0 = (u32)(ulong)packet;
1435 * Make sure that if HW sees the _OWN write below, it will see all the
1436 * writes to the rest of the descriptor too.
1439 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1440 eqos->config->ops->eqos_flush_desc(rx_desc);
1442 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1444 eqos->rx_desc_idx++;
1445 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1450 static int eqos_probe_resources_core(struct udevice *dev)
1452 struct eqos_priv *eqos = dev_get_priv(dev);
1455 debug("%s(dev=%p):\n", __func__, dev);
1457 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1458 EQOS_DESCRIPTORS_RX);
1460 debug("%s: eqos_alloc_descs() failed\n", __func__);
1464 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1465 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1466 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1469 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1470 if (!eqos->tx_dma_buf) {
1471 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1473 goto err_free_descs;
1475 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1477 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1478 if (!eqos->rx_dma_buf) {
1479 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1481 goto err_free_tx_dma_buf;
1483 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1485 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1486 if (!eqos->rx_pkt) {
1487 debug("%s: malloc(rx_pkt) failed\n", __func__);
1489 goto err_free_rx_dma_buf;
1491 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1493 debug("%s: OK\n", __func__);
1496 err_free_rx_dma_buf:
1497 free(eqos->rx_dma_buf);
1498 err_free_tx_dma_buf:
1499 free(eqos->tx_dma_buf);
1501 eqos_free_descs(eqos->descs);
1504 debug("%s: returns %d\n", __func__, ret);
1508 static int eqos_remove_resources_core(struct udevice *dev)
1510 struct eqos_priv *eqos = dev_get_priv(dev);
1512 debug("%s(dev=%p):\n", __func__, dev);
1515 free(eqos->rx_dma_buf);
1516 free(eqos->tx_dma_buf);
1517 eqos_free_descs(eqos->descs);
1519 debug("%s: OK\n", __func__);
1523 static int eqos_probe_resources_tegra186(struct udevice *dev)
1525 struct eqos_priv *eqos = dev_get_priv(dev);
1528 debug("%s(dev=%p):\n", __func__, dev);
1530 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1532 pr_err("reset_get_by_name(rst) failed: %d", ret);
1536 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1537 &eqos->phy_reset_gpio,
1538 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1540 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1541 goto err_free_reset_eqos;
1544 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1546 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1547 goto err_free_gpio_phy_reset;
1550 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1552 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1553 goto err_free_clk_slave_bus;
1556 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1558 pr_err("clk_get_by_name(rx) failed: %d", ret);
1559 goto err_free_clk_master_bus;
1562 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1564 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1565 goto err_free_clk_rx;
1569 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1571 pr_err("clk_get_by_name(tx) failed: %d", ret);
1572 goto err_free_clk_ptp_ref;
1575 debug("%s: OK\n", __func__);
1578 err_free_clk_ptp_ref:
1579 clk_free(&eqos->clk_ptp_ref);
1581 clk_free(&eqos->clk_rx);
1582 err_free_clk_master_bus:
1583 clk_free(&eqos->clk_master_bus);
1584 err_free_clk_slave_bus:
1585 clk_free(&eqos->clk_slave_bus);
1586 err_free_gpio_phy_reset:
1587 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1588 err_free_reset_eqos:
1589 reset_free(&eqos->reset_ctl);
1591 debug("%s: returns %d\n", __func__, ret);
1595 /* board-specific Ethernet Interface initializations. */
1596 __weak int board_interface_eth_init(struct udevice *dev,
1597 phy_interface_t interface_type)
1602 static int eqos_probe_resources_stm32(struct udevice *dev)
1604 struct eqos_priv *eqos = dev_get_priv(dev);
1606 phy_interface_t interface;
1608 debug("%s(dev=%p):\n", __func__, dev);
1610 interface = eqos->config->interface(dev);
1612 if (interface == PHY_INTERFACE_MODE_NONE) {
1613 pr_err("Invalid PHY interface\n");
1617 ret = board_interface_eth_init(dev, interface);
1621 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1623 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1627 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1629 pr_err("clk_get_by_name(rx) failed: %d", ret);
1630 goto err_free_clk_master_bus;
1633 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1635 pr_err("clk_get_by_name(tx) failed: %d", ret);
1636 goto err_free_clk_rx;
1639 /* Get ETH_CLK clocks (optional) */
1640 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1642 pr_warn("No phy clock provided %d", ret);
1644 debug("%s: OK\n", __func__);
1648 clk_free(&eqos->clk_rx);
1649 err_free_clk_master_bus:
1650 clk_free(&eqos->clk_master_bus);
1653 debug("%s: returns %d\n", __func__, ret);
1657 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1659 const char *phy_mode;
1660 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1662 debug("%s(dev=%p):\n", __func__, dev);
1664 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1667 interface = phy_get_interface_by_name(phy_mode);
1672 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1674 return PHY_INTERFACE_MODE_MII;
1677 static int eqos_remove_resources_tegra186(struct udevice *dev)
1679 struct eqos_priv *eqos = dev_get_priv(dev);
1681 debug("%s(dev=%p):\n", __func__, dev);
1683 clk_free(&eqos->clk_tx);
1684 clk_free(&eqos->clk_ptp_ref);
1685 clk_free(&eqos->clk_rx);
1686 clk_free(&eqos->clk_slave_bus);
1687 clk_free(&eqos->clk_master_bus);
1688 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1689 reset_free(&eqos->reset_ctl);
1691 debug("%s: OK\n", __func__);
1695 static int eqos_remove_resources_stm32(struct udevice *dev)
1697 struct eqos_priv *eqos = dev_get_priv(dev);
1699 debug("%s(dev=%p):\n", __func__, dev);
1701 clk_free(&eqos->clk_tx);
1702 clk_free(&eqos->clk_rx);
1703 clk_free(&eqos->clk_master_bus);
1704 if (clk_valid(&eqos->clk_ck))
1705 clk_free(&eqos->clk_ck);
1707 debug("%s: OK\n", __func__);
1711 static int eqos_probe(struct udevice *dev)
1713 struct eqos_priv *eqos = dev_get_priv(dev);
1716 debug("%s(dev=%p):\n", __func__, dev);
1719 eqos->config = (void *)dev_get_driver_data(dev);
1721 eqos->regs = devfdt_get_addr(dev);
1722 if (eqos->regs == FDT_ADDR_T_NONE) {
1723 pr_err("devfdt_get_addr() failed");
1726 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1727 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1728 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1729 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1731 ret = eqos_probe_resources_core(dev);
1733 pr_err("eqos_probe_resources_core() failed: %d", ret);
1737 ret = eqos->config->ops->eqos_probe_resources(dev);
1739 pr_err("eqos_probe_resources() failed: %d", ret);
1740 goto err_remove_resources_core;
1743 eqos->mii = mdio_alloc();
1745 pr_err("mdio_alloc() failed");
1747 goto err_remove_resources_tegra;
1749 eqos->mii->read = eqos_mdio_read;
1750 eqos->mii->write = eqos_mdio_write;
1751 eqos->mii->priv = eqos;
1752 strcpy(eqos->mii->name, dev->name);
1754 ret = mdio_register(eqos->mii);
1756 pr_err("mdio_register() failed: %d", ret);
1760 debug("%s: OK\n", __func__);
1764 mdio_free(eqos->mii);
1765 err_remove_resources_tegra:
1766 eqos->config->ops->eqos_remove_resources(dev);
1767 err_remove_resources_core:
1768 eqos_remove_resources_core(dev);
1770 debug("%s: returns %d\n", __func__, ret);
1774 static int eqos_remove(struct udevice *dev)
1776 struct eqos_priv *eqos = dev_get_priv(dev);
1778 debug("%s(dev=%p):\n", __func__, dev);
1780 mdio_unregister(eqos->mii);
1781 mdio_free(eqos->mii);
1782 eqos->config->ops->eqos_remove_resources(dev);
1784 eqos_probe_resources_core(dev);
1786 debug("%s: OK\n", __func__);
1790 static const struct eth_ops eqos_ops = {
1791 .start = eqos_start,
1795 .free_pkt = eqos_free_pkt,
1796 .write_hwaddr = eqos_write_hwaddr,
1799 static struct eqos_ops eqos_tegra186_ops = {
1800 .eqos_inval_desc = eqos_inval_desc_tegra186,
1801 .eqos_flush_desc = eqos_flush_desc_tegra186,
1802 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1803 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1804 .eqos_probe_resources = eqos_probe_resources_tegra186,
1805 .eqos_remove_resources = eqos_remove_resources_tegra186,
1806 .eqos_stop_resets = eqos_stop_resets_tegra186,
1807 .eqos_start_resets = eqos_start_resets_tegra186,
1808 .eqos_stop_clks = eqos_stop_clks_tegra186,
1809 .eqos_start_clks = eqos_start_clks_tegra186,
1810 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1811 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1812 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1813 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1816 static const struct eqos_config eqos_tegra186_config = {
1817 .reg_access_always_ok = false,
1820 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1821 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
1822 .interface = eqos_get_interface_tegra186,
1823 .ops = &eqos_tegra186_ops
1826 static struct eqos_ops eqos_stm32_ops = {
1827 .eqos_inval_desc = eqos_inval_desc_stm32,
1828 .eqos_flush_desc = eqos_flush_desc_stm32,
1829 .eqos_inval_buffer = eqos_inval_buffer_stm32,
1830 .eqos_flush_buffer = eqos_flush_buffer_stm32,
1831 .eqos_probe_resources = eqos_probe_resources_stm32,
1832 .eqos_remove_resources = eqos_remove_resources_stm32,
1833 .eqos_stop_resets = eqos_stop_resets_stm32,
1834 .eqos_start_resets = eqos_start_resets_stm32,
1835 .eqos_stop_clks = eqos_stop_clks_stm32,
1836 .eqos_start_clks = eqos_start_clks_stm32,
1837 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
1838 .eqos_disable_calibration = eqos_disable_calibration_stm32,
1839 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
1840 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1843 static const struct eqos_config eqos_stm32_config = {
1844 .reg_access_always_ok = false,
1847 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1848 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
1849 .interface = eqos_get_interface_stm32,
1850 .ops = &eqos_stm32_ops
1853 static const struct udevice_id eqos_ids[] = {
1855 .compatible = "nvidia,tegra186-eqos",
1856 .data = (ulong)&eqos_tegra186_config
1859 .compatible = "snps,dwmac-4.20a",
1860 .data = (ulong)&eqos_stm32_config
1866 U_BOOT_DRIVER(eth_eqos) = {
1869 .of_match = eqos_ids,
1870 .probe = eqos_probe,
1871 .remove = eqos_remove,
1873 .priv_auto_alloc_size = sizeof(struct eqos_priv),
1874 .platdata_auto_alloc_size = sizeof(struct eth_pdata),