1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, NVIDIA CORPORATION.
5 * Portions based on U-Boot's rtl8169.c.
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
22 * The following configurations are currently supported:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
48 #define EQOS_MAC_REGS_BASE 0x000
49 struct eqos_mac_regs {
50 uint32_t configuration; /* 0x000 */
51 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
52 uint32_t q0_tx_flow_ctrl; /* 0x070 */
53 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
54 uint32_t rx_flow_ctrl; /* 0x090 */
55 uint32_t unused_094; /* 0x094 */
56 uint32_t txq_prty_map0; /* 0x098 */
57 uint32_t unused_09c; /* 0x09c */
58 uint32_t rxq_ctrl0; /* 0x0a0 */
59 uint32_t unused_0a4; /* 0x0a4 */
60 uint32_t rxq_ctrl2; /* 0x0a8 */
61 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
62 uint32_t us_tic_counter; /* 0x0dc */
63 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
64 uint32_t hw_feature0; /* 0x11c */
65 uint32_t hw_feature1; /* 0x120 */
66 uint32_t hw_feature2; /* 0x124 */
67 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
68 uint32_t mdio_address; /* 0x200 */
69 uint32_t mdio_data; /* 0x204 */
70 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
71 uint32_t address0_high; /* 0x300 */
72 uint32_t address0_low; /* 0x304 */
75 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
76 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
77 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
78 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
79 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
80 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
81 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
82 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
83 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
84 #define EQOS_MAC_CONFIGURATION_LM BIT(12)
85 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
86 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
88 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
89 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
90 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
92 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
94 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
95 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
99 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
100 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
101 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
103 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
104 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
106 #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
107 #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
108 #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
109 #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
111 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
112 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
113 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
114 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
116 #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
117 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
119 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
120 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
121 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
122 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
123 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
124 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
125 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
126 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
127 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
128 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
129 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
131 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
133 #define EQOS_MTL_REGS_BASE 0xd00
134 struct eqos_mtl_regs {
135 uint32_t txq0_operation_mode; /* 0xd00 */
136 uint32_t unused_d04; /* 0xd04 */
137 uint32_t txq0_debug; /* 0xd08 */
138 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
139 uint32_t txq0_quantum_weight; /* 0xd18 */
140 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
141 uint32_t rxq0_operation_mode; /* 0xd30 */
142 uint32_t unused_d34; /* 0xd34 */
143 uint32_t rxq0_debug; /* 0xd38 */
146 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
147 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
148 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
149 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
150 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
151 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
152 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
154 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
155 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
156 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
158 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
159 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
160 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
161 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
162 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
163 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
164 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
165 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
166 #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
167 #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
169 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
170 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
171 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
172 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
174 #define EQOS_DMA_REGS_BASE 0x1000
175 struct eqos_dma_regs {
176 uint32_t mode; /* 0x1000 */
177 uint32_t sysbus_mode; /* 0x1004 */
178 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
179 uint32_t ch0_control; /* 0x1100 */
180 uint32_t ch0_tx_control; /* 0x1104 */
181 uint32_t ch0_rx_control; /* 0x1108 */
182 uint32_t unused_110c; /* 0x110c */
183 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
184 uint32_t ch0_txdesc_list_address; /* 0x1114 */
185 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
186 uint32_t ch0_rxdesc_list_address; /* 0x111c */
187 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
188 uint32_t unused_1124; /* 0x1124 */
189 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
190 uint32_t ch0_txdesc_ring_length; /* 0x112c */
191 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
194 #define EQOS_DMA_MODE_SWR BIT(0)
196 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
197 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
198 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
199 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
200 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
201 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
203 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
205 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
206 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
207 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
208 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
210 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
211 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
212 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
213 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
214 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
216 /* These registers are Tegra186-specific */
217 #define EQOS_TEGRA186_REGS_BASE 0x8800
218 struct eqos_tegra186_regs {
219 uint32_t sdmemcomppadctrl; /* 0x8800 */
220 uint32_t auto_cal_config; /* 0x8804 */
221 uint32_t unused_8808; /* 0x8808 */
222 uint32_t auto_cal_status; /* 0x880c */
225 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
227 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
228 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
230 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
234 #define EQOS_DESCRIPTOR_WORDS 4
235 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
236 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
237 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
238 #define EQOS_DESCRIPTORS_TX 4
239 #define EQOS_DESCRIPTORS_RX 4
240 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
241 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
242 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
243 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
244 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
245 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
248 * Warn if the cache-line size is larger than the descriptor size. In such
249 * cases the driver will likely fail because the CPU needs to flush the cache
250 * when requeuing RX buffers, therefore descriptors written by the hardware
251 * may be discarded. Architectures with full IO coherence, such as x86, do not
252 * experience this issue, and hence are excluded from this condition.
254 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
255 * the driver to allocate descriptors from a pool of non-cached memory.
257 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
258 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
259 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
260 #warning Cache line size is larger than descriptor size
271 #define EQOS_DESC3_OWN BIT(31)
272 #define EQOS_DESC3_FD BIT(29)
273 #define EQOS_DESC3_LD BIT(28)
274 #define EQOS_DESC3_BUF1V BIT(24)
277 bool reg_access_always_ok;
282 phy_interface_t (*interface)(struct udevice *dev);
283 struct eqos_ops *ops;
287 void (*eqos_inval_desc)(void *desc);
288 void (*eqos_flush_desc)(void *desc);
289 void (*eqos_inval_buffer)(void *buf, size_t size);
290 void (*eqos_flush_buffer)(void *buf, size_t size);
291 int (*eqos_probe_resources)(struct udevice *dev);
292 int (*eqos_remove_resources)(struct udevice *dev);
293 int (*eqos_stop_resets)(struct udevice *dev);
294 int (*eqos_start_resets)(struct udevice *dev);
295 void (*eqos_stop_clks)(struct udevice *dev);
296 int (*eqos_start_clks)(struct udevice *dev);
297 int (*eqos_calibrate_pads)(struct udevice *dev);
298 int (*eqos_disable_calibration)(struct udevice *dev);
299 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
300 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
305 const struct eqos_config *config;
307 struct eqos_mac_regs *mac_regs;
308 struct eqos_mtl_regs *mtl_regs;
309 struct eqos_dma_regs *dma_regs;
310 struct eqos_tegra186_regs *tegra186_regs;
311 struct reset_ctl reset_ctl;
312 struct gpio_desc phy_reset_gpio;
313 struct clk clk_master_bus;
315 struct clk clk_ptp_ref;
318 struct clk clk_slave_bus;
320 struct phy_device *phy;
324 struct eqos_desc *tx_descs;
325 struct eqos_desc *rx_descs;
326 int tx_desc_idx, rx_desc_idx;
335 * TX and RX descriptors are 16 bytes. This causes problems with the cache
336 * maintenance on CPUs where the cache-line size exceeds the size of these
337 * descriptors. What will happen is that when the driver receives a packet
338 * it will be immediately requeued for the hardware to reuse. The CPU will
339 * therefore need to flush the cache-line containing the descriptor, which
340 * will cause all other descriptors in the same cache-line to be flushed
341 * along with it. If one of those descriptors had been written to by the
342 * device those changes (and the associated packet) will be lost.
344 * To work around this, we make use of non-cached memory if available. If
345 * descriptors are mapped uncached there's no need to manually flush them
346 * or invalidate them.
348 * Note that this only applies to descriptors. The packet data buffers do
349 * not have the same constraints since they are 1536 bytes large, so they
350 * are unlikely to share cache-lines.
352 static void *eqos_alloc_descs(unsigned int num)
354 #ifdef CONFIG_SYS_NONCACHED_MEMORY
355 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
356 EQOS_DESCRIPTOR_ALIGN);
358 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
362 static void eqos_free_descs(void *descs)
364 #ifdef CONFIG_SYS_NONCACHED_MEMORY
365 /* FIXME: noncached_alloc() has no opposite */
371 static void eqos_inval_desc_tegra186(void *desc)
373 #ifndef CONFIG_SYS_NONCACHED_MEMORY
374 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
375 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
378 invalidate_dcache_range(start, end);
382 static void eqos_inval_desc_generic(void *desc)
384 #ifndef CONFIG_SYS_NONCACHED_MEMORY
385 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
386 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
389 invalidate_dcache_range(start, end);
393 static void eqos_flush_desc_tegra186(void *desc)
395 #ifndef CONFIG_SYS_NONCACHED_MEMORY
396 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
400 static void eqos_flush_desc_generic(void *desc)
402 #ifndef CONFIG_SYS_NONCACHED_MEMORY
403 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
404 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
407 flush_dcache_range(start, end);
411 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
413 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
414 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
416 invalidate_dcache_range(start, end);
419 static void eqos_inval_buffer_generic(void *buf, size_t size)
421 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
422 unsigned long end = roundup((unsigned long)buf + size,
425 invalidate_dcache_range(start, end);
428 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
430 flush_cache((unsigned long)buf, size);
433 static void eqos_flush_buffer_generic(void *buf, size_t size)
435 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
436 unsigned long end = roundup((unsigned long)buf + size,
439 flush_dcache_range(start, end);
442 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
444 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
445 EQOS_MAC_MDIO_ADDRESS_GB, false,
449 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
452 struct eqos_priv *eqos = bus->priv;
456 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
459 ret = eqos_mdio_wait_idle(eqos);
461 pr_err("MDIO not idle at entry");
465 val = readl(&eqos->mac_regs->mdio_address);
466 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
467 EQOS_MAC_MDIO_ADDRESS_C45E;
468 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
469 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
470 (eqos->config->config_mac_mdio <<
471 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
472 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
473 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
474 EQOS_MAC_MDIO_ADDRESS_GB;
475 writel(val, &eqos->mac_regs->mdio_address);
477 udelay(eqos->config->mdio_wait);
479 ret = eqos_mdio_wait_idle(eqos);
481 pr_err("MDIO read didn't complete");
485 val = readl(&eqos->mac_regs->mdio_data);
486 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
488 debug("%s: val=%x\n", __func__, val);
493 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
494 int mdio_reg, u16 mdio_val)
496 struct eqos_priv *eqos = bus->priv;
500 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
501 mdio_addr, mdio_reg, mdio_val);
503 ret = eqos_mdio_wait_idle(eqos);
505 pr_err("MDIO not idle at entry");
509 writel(mdio_val, &eqos->mac_regs->mdio_data);
511 val = readl(&eqos->mac_regs->mdio_address);
512 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
513 EQOS_MAC_MDIO_ADDRESS_C45E;
514 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
515 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
516 (eqos->config->config_mac_mdio <<
517 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
518 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
519 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
520 EQOS_MAC_MDIO_ADDRESS_GB;
521 writel(val, &eqos->mac_regs->mdio_address);
523 udelay(eqos->config->mdio_wait);
525 ret = eqos_mdio_wait_idle(eqos);
527 pr_err("MDIO read didn't complete");
534 static int eqos_start_clks_tegra186(struct udevice *dev)
537 struct eqos_priv *eqos = dev_get_priv(dev);
540 debug("%s(dev=%p):\n", __func__, dev);
542 ret = clk_enable(&eqos->clk_slave_bus);
544 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
548 ret = clk_enable(&eqos->clk_master_bus);
550 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
551 goto err_disable_clk_slave_bus;
554 ret = clk_enable(&eqos->clk_rx);
556 pr_err("clk_enable(clk_rx) failed: %d", ret);
557 goto err_disable_clk_master_bus;
560 ret = clk_enable(&eqos->clk_ptp_ref);
562 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
563 goto err_disable_clk_rx;
566 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
568 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
569 goto err_disable_clk_ptp_ref;
572 ret = clk_enable(&eqos->clk_tx);
574 pr_err("clk_enable(clk_tx) failed: %d", ret);
575 goto err_disable_clk_ptp_ref;
579 debug("%s: OK\n", __func__);
583 err_disable_clk_ptp_ref:
584 clk_disable(&eqos->clk_ptp_ref);
586 clk_disable(&eqos->clk_rx);
587 err_disable_clk_master_bus:
588 clk_disable(&eqos->clk_master_bus);
589 err_disable_clk_slave_bus:
590 clk_disable(&eqos->clk_slave_bus);
592 debug("%s: FAILED: %d\n", __func__, ret);
597 static int eqos_start_clks_stm32(struct udevice *dev)
600 struct eqos_priv *eqos = dev_get_priv(dev);
603 debug("%s(dev=%p):\n", __func__, dev);
605 ret = clk_enable(&eqos->clk_master_bus);
607 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
611 ret = clk_enable(&eqos->clk_rx);
613 pr_err("clk_enable(clk_rx) failed: %d", ret);
614 goto err_disable_clk_master_bus;
617 ret = clk_enable(&eqos->clk_tx);
619 pr_err("clk_enable(clk_tx) failed: %d", ret);
620 goto err_disable_clk_rx;
623 if (clk_valid(&eqos->clk_ck)) {
624 ret = clk_enable(&eqos->clk_ck);
626 pr_err("clk_enable(clk_ck) failed: %d", ret);
627 goto err_disable_clk_tx;
632 debug("%s: OK\n", __func__);
637 clk_disable(&eqos->clk_tx);
639 clk_disable(&eqos->clk_rx);
640 err_disable_clk_master_bus:
641 clk_disable(&eqos->clk_master_bus);
643 debug("%s: FAILED: %d\n", __func__, ret);
648 static int eqos_start_clks_imx(struct udevice *dev)
653 static void eqos_stop_clks_tegra186(struct udevice *dev)
656 struct eqos_priv *eqos = dev_get_priv(dev);
658 debug("%s(dev=%p):\n", __func__, dev);
660 clk_disable(&eqos->clk_tx);
661 clk_disable(&eqos->clk_ptp_ref);
662 clk_disable(&eqos->clk_rx);
663 clk_disable(&eqos->clk_master_bus);
664 clk_disable(&eqos->clk_slave_bus);
667 debug("%s: OK\n", __func__);
670 static void eqos_stop_clks_stm32(struct udevice *dev)
673 struct eqos_priv *eqos = dev_get_priv(dev);
675 debug("%s(dev=%p):\n", __func__, dev);
677 clk_disable(&eqos->clk_tx);
678 clk_disable(&eqos->clk_rx);
679 clk_disable(&eqos->clk_master_bus);
680 if (clk_valid(&eqos->clk_ck))
681 clk_disable(&eqos->clk_ck);
684 debug("%s: OK\n", __func__);
687 static void eqos_stop_clks_imx(struct udevice *dev)
692 static int eqos_start_resets_tegra186(struct udevice *dev)
694 struct eqos_priv *eqos = dev_get_priv(dev);
697 debug("%s(dev=%p):\n", __func__, dev);
699 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
701 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
707 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
709 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
713 ret = reset_assert(&eqos->reset_ctl);
715 pr_err("reset_assert() failed: %d", ret);
721 ret = reset_deassert(&eqos->reset_ctl);
723 pr_err("reset_deassert() failed: %d", ret);
727 debug("%s: OK\n", __func__);
731 static int eqos_start_resets_stm32(struct udevice *dev)
733 struct eqos_priv *eqos = dev_get_priv(dev);
736 debug("%s(dev=%p):\n", __func__, dev);
737 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
738 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
740 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
747 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
749 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
754 debug("%s: OK\n", __func__);
759 static int eqos_start_resets_imx(struct udevice *dev)
764 static int eqos_stop_resets_tegra186(struct udevice *dev)
766 struct eqos_priv *eqos = dev_get_priv(dev);
768 reset_assert(&eqos->reset_ctl);
769 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
774 static int eqos_stop_resets_stm32(struct udevice *dev)
776 struct eqos_priv *eqos = dev_get_priv(dev);
779 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
780 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
782 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
791 static int eqos_stop_resets_imx(struct udevice *dev)
796 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
798 struct eqos_priv *eqos = dev_get_priv(dev);
801 debug("%s(dev=%p):\n", __func__, dev);
803 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
804 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
808 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
809 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
811 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
812 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
814 pr_err("calibrate didn't start");
818 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
819 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
821 pr_err("calibrate didn't finish");
828 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
829 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
831 debug("%s: returns %d\n", __func__, ret);
836 static int eqos_disable_calibration_tegra186(struct udevice *dev)
838 struct eqos_priv *eqos = dev_get_priv(dev);
840 debug("%s(dev=%p):\n", __func__, dev);
842 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
843 EQOS_AUTO_CAL_CONFIG_ENABLE);
848 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
851 struct eqos_priv *eqos = dev_get_priv(dev);
853 return clk_get_rate(&eqos->clk_slave_bus);
859 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
862 struct eqos_priv *eqos = dev_get_priv(dev);
864 return clk_get_rate(&eqos->clk_master_bus);
870 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
872 /* TODO: retrieve from CSR clock */
873 return 100 * 1000000;
876 static int eqos_calibrate_pads_stm32(struct udevice *dev)
881 static int eqos_calibrate_pads_imx(struct udevice *dev)
886 static int eqos_disable_calibration_stm32(struct udevice *dev)
891 static int eqos_disable_calibration_imx(struct udevice *dev)
896 static int eqos_set_full_duplex(struct udevice *dev)
898 struct eqos_priv *eqos = dev_get_priv(dev);
900 debug("%s(dev=%p):\n", __func__, dev);
902 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
907 static int eqos_set_half_duplex(struct udevice *dev)
909 struct eqos_priv *eqos = dev_get_priv(dev);
911 debug("%s(dev=%p):\n", __func__, dev);
913 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
915 /* WAR: Flush TX queue when switching to half-duplex */
916 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
917 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
922 static int eqos_set_gmii_speed(struct udevice *dev)
924 struct eqos_priv *eqos = dev_get_priv(dev);
926 debug("%s(dev=%p):\n", __func__, dev);
928 clrbits_le32(&eqos->mac_regs->configuration,
929 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
934 static int eqos_set_mii_speed_100(struct udevice *dev)
936 struct eqos_priv *eqos = dev_get_priv(dev);
938 debug("%s(dev=%p):\n", __func__, dev);
940 setbits_le32(&eqos->mac_regs->configuration,
941 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
946 static int eqos_set_mii_speed_10(struct udevice *dev)
948 struct eqos_priv *eqos = dev_get_priv(dev);
950 debug("%s(dev=%p):\n", __func__, dev);
952 clrsetbits_le32(&eqos->mac_regs->configuration,
953 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
958 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
961 struct eqos_priv *eqos = dev_get_priv(dev);
965 debug("%s(dev=%p):\n", __func__, dev);
967 switch (eqos->phy->speed) {
969 rate = 125 * 1000 * 1000;
972 rate = 25 * 1000 * 1000;
975 rate = 2.5 * 1000 * 1000;
978 pr_err("invalid speed %d", eqos->phy->speed);
982 ret = clk_set_rate(&eqos->clk_tx, rate);
984 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
992 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
997 static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
1002 static int eqos_adjust_link(struct udevice *dev)
1004 struct eqos_priv *eqos = dev_get_priv(dev);
1006 bool en_calibration;
1008 debug("%s(dev=%p):\n", __func__, dev);
1010 if (eqos->phy->duplex)
1011 ret = eqos_set_full_duplex(dev);
1013 ret = eqos_set_half_duplex(dev);
1015 pr_err("eqos_set_*_duplex() failed: %d", ret);
1019 switch (eqos->phy->speed) {
1021 en_calibration = true;
1022 ret = eqos_set_gmii_speed(dev);
1025 en_calibration = true;
1026 ret = eqos_set_mii_speed_100(dev);
1029 en_calibration = false;
1030 ret = eqos_set_mii_speed_10(dev);
1033 pr_err("invalid speed %d", eqos->phy->speed);
1037 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
1041 if (en_calibration) {
1042 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1044 pr_err("eqos_calibrate_pads() failed: %d",
1049 ret = eqos->config->ops->eqos_disable_calibration(dev);
1051 pr_err("eqos_disable_calibration() failed: %d",
1056 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
1058 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
1065 static int eqos_write_hwaddr(struct udevice *dev)
1067 struct eth_pdata *plat = dev_get_platdata(dev);
1068 struct eqos_priv *eqos = dev_get_priv(dev);
1072 * This function may be called before start() or after stop(). At that
1073 * time, on at least some configurations of the EQoS HW, all clocks to
1074 * the EQoS HW block will be stopped, and a reset signal applied. If
1075 * any register access is attempted in this state, bus timeouts or CPU
1076 * hangs may occur. This check prevents that.
1078 * A simple solution to this problem would be to not implement
1079 * write_hwaddr(), since start() always writes the MAC address into HW
1080 * anyway. However, it is desirable to implement write_hwaddr() to
1081 * support the case of SW that runs subsequent to U-Boot which expects
1082 * the MAC address to already be programmed into the EQoS registers,
1083 * which must happen irrespective of whether the U-Boot user (or
1084 * scripts) actually made use of the EQoS device, and hence
1085 * irrespective of whether start() was ever called.
1087 * Note that this requirement by subsequent SW is not valid for
1088 * Tegra186, and is likely not valid for any non-PCI instantiation of
1089 * the EQoS HW block. This function is implemented solely as
1090 * future-proofing with the expectation the driver will eventually be
1091 * ported to some system where the expectation above is true.
1093 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1096 /* Update the MAC address */
1097 val = (plat->enetaddr[5] << 8) |
1098 (plat->enetaddr[4]);
1099 writel(val, &eqos->mac_regs->address0_high);
1100 val = (plat->enetaddr[3] << 24) |
1101 (plat->enetaddr[2] << 16) |
1102 (plat->enetaddr[1] << 8) |
1103 (plat->enetaddr[0]);
1104 writel(val, &eqos->mac_regs->address0_low);
1109 static int eqos_start(struct udevice *dev)
1111 struct eqos_priv *eqos = dev_get_priv(dev);
1114 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1117 debug("%s(dev=%p):\n", __func__, dev);
1119 eqos->tx_desc_idx = 0;
1120 eqos->rx_desc_idx = 0;
1122 ret = eqos->config->ops->eqos_start_clks(dev);
1124 pr_err("eqos_start_clks() failed: %d", ret);
1128 ret = eqos->config->ops->eqos_start_resets(dev);
1130 pr_err("eqos_start_resets() failed: %d", ret);
1136 eqos->reg_access_ok = true;
1138 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
1139 EQOS_DMA_MODE_SWR, false,
1140 eqos->config->swr_wait, false);
1142 pr_err("EQOS_DMA_MODE_SWR stuck");
1143 goto err_stop_resets;
1146 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1148 pr_err("eqos_calibrate_pads() failed: %d", ret);
1149 goto err_stop_resets;
1151 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
1153 val = (rate / 1000000) - 1;
1154 writel(val, &eqos->mac_regs->us_tic_counter);
1157 * if PHY was already connected and configured,
1158 * don't need to reconnect/reconfigure again
1162 #ifdef CONFIG_DM_ETH_PHY
1163 addr = eth_phy_get_addr(dev);
1165 #ifdef DWC_NET_PHYADDR
1166 addr = DWC_NET_PHYADDR;
1168 eqos->phy = phy_connect(eqos->mii, addr, dev,
1169 eqos->config->interface(dev));
1171 pr_err("phy_connect() failed");
1172 goto err_stop_resets;
1175 if (eqos->max_speed) {
1176 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1178 pr_err("phy_set_supported() failed: %d", ret);
1179 goto err_shutdown_phy;
1183 ret = phy_config(eqos->phy);
1185 pr_err("phy_config() failed: %d", ret);
1186 goto err_shutdown_phy;
1190 ret = phy_startup(eqos->phy);
1192 pr_err("phy_startup() failed: %d", ret);
1193 goto err_shutdown_phy;
1196 if (!eqos->phy->link) {
1198 goto err_shutdown_phy;
1201 ret = eqos_adjust_link(dev);
1203 pr_err("eqos_adjust_link() failed: %d", ret);
1204 goto err_shutdown_phy;
1208 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
1210 /* Enable Store and Forward mode for TX */
1211 /* Program Tx operating mode */
1212 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1213 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1214 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1215 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1217 /* Transmit Queue weight */
1218 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1220 /* Enable Store and Forward mode for RX, since no jumbo frame */
1221 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1222 EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
1223 EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
1224 EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
1226 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1227 val = readl(&eqos->mac_regs->hw_feature1);
1228 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1229 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1230 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1231 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1234 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1235 * r/tqs is encoded as (n / 256) - 1.
1237 tqs = (128 << tx_fifo_sz) / 256 - 1;
1238 rqs = (128 << rx_fifo_sz) / 256 - 1;
1240 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1241 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1242 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1243 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1244 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1245 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1246 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1247 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1249 /* Flow control used only if each channel gets 4KB or more FIFO */
1250 if (rqs >= ((4096 / 256) - 1)) {
1253 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1254 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1257 * Set Threshold for Activating Flow Contol space for min 2
1258 * frames ie, (1500 * 1) = 1500 bytes.
1260 * Set Threshold for Deactivating Flow Contol for space of
1261 * min 1 frame (frame size 1500bytes) in receive fifo
1263 if (rqs == ((4096 / 256) - 1)) {
1265 * This violates the above formula because of FIFO size
1266 * limit therefore overflow may occur inspite of this.
1268 rfd = 0x3; /* Full-3K */
1269 rfa = 0x1; /* Full-1.5K */
1270 } else if (rqs == ((8192 / 256) - 1)) {
1271 rfd = 0x6; /* Full-4K */
1272 rfa = 0xa; /* Full-6K */
1273 } else if (rqs == ((16384 / 256) - 1)) {
1274 rfd = 0x6; /* Full-4K */
1275 rfa = 0x12; /* Full-10K */
1277 rfd = 0x6; /* Full-4K */
1278 rfa = 0x1E; /* Full-16K */
1281 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1282 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1283 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1284 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1285 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1287 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1289 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1294 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1295 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1296 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1297 eqos->config->config_mac <<
1298 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1300 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1301 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1302 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1304 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1306 /* Multicast and Broadcast Queue Enable */
1307 setbits_le32(&eqos->mac_regs->unused_0a4,
1309 /* enable promise mode */
1310 setbits_le32(&eqos->mac_regs->unused_004[1],
1313 /* Set TX flow control parameters */
1314 /* Set Pause Time */
1315 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1316 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1317 /* Assign priority for TX flow control */
1318 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1319 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1320 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1321 /* Assign priority for RX flow control */
1322 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1323 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1324 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1325 /* Enable flow control */
1326 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1327 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1328 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1329 EQOS_MAC_RX_FLOW_CTRL_RFE);
1331 clrsetbits_le32(&eqos->mac_regs->configuration,
1332 EQOS_MAC_CONFIGURATION_GPSLCE |
1333 EQOS_MAC_CONFIGURATION_WD |
1334 EQOS_MAC_CONFIGURATION_JD |
1335 EQOS_MAC_CONFIGURATION_JE,
1336 EQOS_MAC_CONFIGURATION_CST |
1337 EQOS_MAC_CONFIGURATION_ACS);
1339 eqos_write_hwaddr(dev);
1343 /* Enable OSP mode */
1344 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1345 EQOS_DMA_CH0_TX_CONTROL_OSP);
1347 /* RX buffer size. Must be a multiple of bus width */
1348 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1349 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1350 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1351 EQOS_MAX_PACKET_SIZE <<
1352 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1354 setbits_le32(&eqos->dma_regs->ch0_control,
1355 EQOS_DMA_CH0_CONTROL_PBLX8);
1358 * Burst length must be < 1/2 FIFO size.
1359 * FIFO size in tqs is encoded as (n / 256) - 1.
1360 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1361 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1366 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1367 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1368 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1369 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1371 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1372 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1373 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1374 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1376 /* DMA performance configuration */
1377 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1378 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1379 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1380 writel(val, &eqos->dma_regs->sysbus_mode);
1382 /* Set up descriptors */
1384 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1385 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1386 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1387 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1388 (i * EQOS_MAX_PACKET_SIZE));
1389 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1391 eqos->config->ops->eqos_flush_desc(rx_desc);
1392 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1393 (i * EQOS_MAX_PACKET_SIZE),
1394 EQOS_MAX_PACKET_SIZE);
1397 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1398 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1399 writel(EQOS_DESCRIPTORS_TX - 1,
1400 &eqos->dma_regs->ch0_txdesc_ring_length);
1402 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1403 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1404 writel(EQOS_DESCRIPTORS_RX - 1,
1405 &eqos->dma_regs->ch0_rxdesc_ring_length);
1407 /* Enable everything */
1408 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1409 EQOS_DMA_CH0_TX_CONTROL_ST);
1410 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1411 EQOS_DMA_CH0_RX_CONTROL_SR);
1412 setbits_le32(&eqos->mac_regs->configuration,
1413 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1415 /* TX tail pointer not written until we need to TX a packet */
1417 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1418 * first descriptor, implying all descriptors were available. However,
1419 * that's not distinguishable from none of the descriptors being
1422 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1423 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1425 eqos->started = true;
1427 debug("%s: OK\n", __func__);
1431 phy_shutdown(eqos->phy);
1433 eqos->config->ops->eqos_stop_resets(dev);
1435 eqos->config->ops->eqos_stop_clks(dev);
1437 pr_err("FAILED: %d", ret);
1441 static void eqos_stop(struct udevice *dev)
1443 struct eqos_priv *eqos = dev_get_priv(dev);
1446 debug("%s(dev=%p):\n", __func__, dev);
1450 eqos->started = false;
1451 eqos->reg_access_ok = false;
1453 /* Disable TX DMA */
1454 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1455 EQOS_DMA_CH0_TX_CONTROL_ST);
1457 /* Wait for TX all packets to drain out of MTL */
1458 for (i = 0; i < 1000000; i++) {
1459 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1460 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1461 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1462 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1463 if ((trcsts != 1) && (!txqsts))
1467 /* Turn off MAC TX and RX */
1468 clrbits_le32(&eqos->mac_regs->configuration,
1469 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1471 /* Wait for all RX packets to drain out of MTL */
1472 for (i = 0; i < 1000000; i++) {
1473 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1474 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1475 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1476 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1477 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1478 if ((!prxq) && (!rxqsts))
1482 /* Turn off RX DMA */
1483 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1484 EQOS_DMA_CH0_RX_CONTROL_SR);
1487 phy_shutdown(eqos->phy);
1489 eqos->config->ops->eqos_stop_resets(dev);
1490 eqos->config->ops->eqos_stop_clks(dev);
1492 debug("%s: OK\n", __func__);
1495 static int eqos_send(struct udevice *dev, void *packet, int length)
1497 struct eqos_priv *eqos = dev_get_priv(dev);
1498 struct eqos_desc *tx_desc;
1501 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1504 memcpy(eqos->tx_dma_buf, packet, length);
1505 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1507 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1508 eqos->tx_desc_idx++;
1509 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1511 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1513 tx_desc->des2 = length;
1515 * Make sure that if HW sees the _OWN write below, it will see all the
1516 * writes to the rest of the descriptor too.
1519 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1520 eqos->config->ops->eqos_flush_desc(tx_desc);
1522 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
1523 &eqos->dma_regs->ch0_txdesc_tail_pointer);
1525 for (i = 0; i < 1000000; i++) {
1526 eqos->config->ops->eqos_inval_desc(tx_desc);
1527 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1532 debug("%s: TX timeout\n", __func__);
1537 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1539 struct eqos_priv *eqos = dev_get_priv(dev);
1540 struct eqos_desc *rx_desc;
1543 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1545 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1546 eqos->config->ops->eqos_inval_desc(rx_desc);
1547 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1548 debug("%s: RX packet not available\n", __func__);
1552 *packetp = eqos->rx_dma_buf +
1553 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1554 length = rx_desc->des3 & 0x7fff;
1555 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1557 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1562 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1564 struct eqos_priv *eqos = dev_get_priv(dev);
1565 uchar *packet_expected;
1566 struct eqos_desc *rx_desc;
1568 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1570 packet_expected = eqos->rx_dma_buf +
1571 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1572 if (packet != packet_expected) {
1573 debug("%s: Unexpected packet (expected %p)\n", __func__,
1578 eqos->config->ops->eqos_inval_buffer(packet, length);
1580 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1584 eqos->config->ops->eqos_flush_desc(rx_desc);
1585 eqos->config->ops->eqos_inval_buffer(packet, length);
1586 rx_desc->des0 = (u32)(ulong)packet;
1590 * Make sure that if HW sees the _OWN write below, it will see all the
1591 * writes to the rest of the descriptor too.
1594 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1595 eqos->config->ops->eqos_flush_desc(rx_desc);
1597 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1599 eqos->rx_desc_idx++;
1600 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1605 static int eqos_probe_resources_core(struct udevice *dev)
1607 struct eqos_priv *eqos = dev_get_priv(dev);
1610 debug("%s(dev=%p):\n", __func__, dev);
1612 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1613 EQOS_DESCRIPTORS_RX);
1615 debug("%s: eqos_alloc_descs() failed\n", __func__);
1619 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1620 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1621 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1624 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1625 if (!eqos->tx_dma_buf) {
1626 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1628 goto err_free_descs;
1630 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1632 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1633 if (!eqos->rx_dma_buf) {
1634 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1636 goto err_free_tx_dma_buf;
1638 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1640 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1641 if (!eqos->rx_pkt) {
1642 debug("%s: malloc(rx_pkt) failed\n", __func__);
1644 goto err_free_rx_dma_buf;
1646 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1648 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1649 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1651 debug("%s: OK\n", __func__);
1654 err_free_rx_dma_buf:
1655 free(eqos->rx_dma_buf);
1656 err_free_tx_dma_buf:
1657 free(eqos->tx_dma_buf);
1659 eqos_free_descs(eqos->descs);
1662 debug("%s: returns %d\n", __func__, ret);
1666 static int eqos_remove_resources_core(struct udevice *dev)
1668 struct eqos_priv *eqos = dev_get_priv(dev);
1670 debug("%s(dev=%p):\n", __func__, dev);
1673 free(eqos->rx_dma_buf);
1674 free(eqos->tx_dma_buf);
1675 eqos_free_descs(eqos->descs);
1677 debug("%s: OK\n", __func__);
1681 static int eqos_probe_resources_tegra186(struct udevice *dev)
1683 struct eqos_priv *eqos = dev_get_priv(dev);
1686 debug("%s(dev=%p):\n", __func__, dev);
1688 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1690 pr_err("reset_get_by_name(rst) failed: %d", ret);
1694 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1695 &eqos->phy_reset_gpio,
1696 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1698 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1699 goto err_free_reset_eqos;
1702 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1704 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1705 goto err_free_gpio_phy_reset;
1708 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1710 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1711 goto err_free_clk_slave_bus;
1714 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1716 pr_err("clk_get_by_name(rx) failed: %d", ret);
1717 goto err_free_clk_master_bus;
1720 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1722 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1723 goto err_free_clk_rx;
1727 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1729 pr_err("clk_get_by_name(tx) failed: %d", ret);
1730 goto err_free_clk_ptp_ref;
1733 debug("%s: OK\n", __func__);
1736 err_free_clk_ptp_ref:
1737 clk_free(&eqos->clk_ptp_ref);
1739 clk_free(&eqos->clk_rx);
1740 err_free_clk_master_bus:
1741 clk_free(&eqos->clk_master_bus);
1742 err_free_clk_slave_bus:
1743 clk_free(&eqos->clk_slave_bus);
1744 err_free_gpio_phy_reset:
1745 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1746 err_free_reset_eqos:
1747 reset_free(&eqos->reset_ctl);
1749 debug("%s: returns %d\n", __func__, ret);
1753 /* board-specific Ethernet Interface initializations. */
1754 __weak int board_interface_eth_init(struct udevice *dev,
1755 phy_interface_t interface_type)
1760 static int eqos_probe_resources_stm32(struct udevice *dev)
1762 struct eqos_priv *eqos = dev_get_priv(dev);
1764 phy_interface_t interface;
1765 struct ofnode_phandle_args phandle_args;
1767 debug("%s(dev=%p):\n", __func__, dev);
1769 interface = eqos->config->interface(dev);
1771 if (interface == PHY_INTERFACE_MODE_NONE) {
1772 pr_err("Invalid PHY interface\n");
1776 ret = board_interface_eth_init(dev, interface);
1780 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1782 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1784 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1788 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1790 pr_err("clk_get_by_name(rx) failed: %d", ret);
1791 goto err_free_clk_master_bus;
1794 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1796 pr_err("clk_get_by_name(tx) failed: %d", ret);
1797 goto err_free_clk_rx;
1800 /* Get ETH_CLK clocks (optional) */
1801 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1803 pr_warn("No phy clock provided %d", ret);
1806 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1809 /* search "reset-gpios" in phy node */
1810 ret = gpio_request_by_name_nodev(phandle_args.node,
1812 &eqos->phy_reset_gpio,
1814 GPIOD_IS_OUT_ACTIVE);
1816 pr_warn("gpio_request_by_name(phy reset) not provided %d",
1819 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
1823 debug("%s: OK\n", __func__);
1827 clk_free(&eqos->clk_rx);
1828 err_free_clk_master_bus:
1829 clk_free(&eqos->clk_master_bus);
1832 debug("%s: returns %d\n", __func__, ret);
1836 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1838 const char *phy_mode;
1839 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1841 debug("%s(dev=%p):\n", __func__, dev);
1843 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1846 interface = phy_get_interface_by_name(phy_mode);
1851 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1853 return PHY_INTERFACE_MODE_MII;
1856 static int eqos_probe_resources_imx(struct udevice *dev)
1858 struct eqos_priv *eqos = dev_get_priv(dev);
1859 phy_interface_t interface;
1861 debug("%s(dev=%p):\n", __func__, dev);
1863 interface = eqos->config->interface(dev);
1865 if (interface == PHY_INTERFACE_MODE_NONE) {
1866 pr_err("Invalid PHY interface\n");
1870 debug("%s: OK\n", __func__);
1874 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
1876 return PHY_INTERFACE_MODE_RGMII;
1879 static int eqos_remove_resources_tegra186(struct udevice *dev)
1881 struct eqos_priv *eqos = dev_get_priv(dev);
1883 debug("%s(dev=%p):\n", __func__, dev);
1886 clk_free(&eqos->clk_tx);
1887 clk_free(&eqos->clk_ptp_ref);
1888 clk_free(&eqos->clk_rx);
1889 clk_free(&eqos->clk_slave_bus);
1890 clk_free(&eqos->clk_master_bus);
1892 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1893 reset_free(&eqos->reset_ctl);
1895 debug("%s: OK\n", __func__);
1899 static int eqos_remove_resources_stm32(struct udevice *dev)
1902 struct eqos_priv *eqos = dev_get_priv(dev);
1904 debug("%s(dev=%p):\n", __func__, dev);
1906 clk_free(&eqos->clk_tx);
1907 clk_free(&eqos->clk_rx);
1908 clk_free(&eqos->clk_master_bus);
1909 if (clk_valid(&eqos->clk_ck))
1910 clk_free(&eqos->clk_ck);
1913 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
1914 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1916 debug("%s: OK\n", __func__);
1920 static int eqos_remove_resources_imx(struct udevice *dev)
1925 static int eqos_probe(struct udevice *dev)
1927 struct eqos_priv *eqos = dev_get_priv(dev);
1930 debug("%s(dev=%p):\n", __func__, dev);
1933 eqos->config = (void *)dev_get_driver_data(dev);
1935 eqos->regs = devfdt_get_addr(dev);
1936 if (eqos->regs == FDT_ADDR_T_NONE) {
1937 pr_err("devfdt_get_addr() failed");
1940 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1941 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1942 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1943 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1945 ret = eqos_probe_resources_core(dev);
1947 pr_err("eqos_probe_resources_core() failed: %d", ret);
1951 ret = eqos->config->ops->eqos_probe_resources(dev);
1953 pr_err("eqos_probe_resources() failed: %d", ret);
1954 goto err_remove_resources_core;
1957 #ifdef CONFIG_DM_ETH_PHY
1958 eqos->mii = eth_phy_get_mdio_bus(dev);
1961 eqos->mii = mdio_alloc();
1963 pr_err("mdio_alloc() failed");
1965 goto err_remove_resources_tegra;
1967 eqos->mii->read = eqos_mdio_read;
1968 eqos->mii->write = eqos_mdio_write;
1969 eqos->mii->priv = eqos;
1970 strcpy(eqos->mii->name, dev->name);
1972 ret = mdio_register(eqos->mii);
1974 pr_err("mdio_register() failed: %d", ret);
1979 #ifdef CONFIG_DM_ETH_PHY
1980 eth_phy_set_mdio_bus(dev, eqos->mii);
1983 debug("%s: OK\n", __func__);
1987 mdio_free(eqos->mii);
1988 err_remove_resources_tegra:
1989 eqos->config->ops->eqos_remove_resources(dev);
1990 err_remove_resources_core:
1991 eqos_remove_resources_core(dev);
1993 debug("%s: returns %d\n", __func__, ret);
1997 static int eqos_remove(struct udevice *dev)
1999 struct eqos_priv *eqos = dev_get_priv(dev);
2001 debug("%s(dev=%p):\n", __func__, dev);
2003 mdio_unregister(eqos->mii);
2004 mdio_free(eqos->mii);
2005 eqos->config->ops->eqos_remove_resources(dev);
2007 eqos_probe_resources_core(dev);
2009 debug("%s: OK\n", __func__);
2013 static const struct eth_ops eqos_ops = {
2014 .start = eqos_start,
2018 .free_pkt = eqos_free_pkt,
2019 .write_hwaddr = eqos_write_hwaddr,
2022 static struct eqos_ops eqos_tegra186_ops = {
2023 .eqos_inval_desc = eqos_inval_desc_tegra186,
2024 .eqos_flush_desc = eqos_flush_desc_tegra186,
2025 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
2026 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
2027 .eqos_probe_resources = eqos_probe_resources_tegra186,
2028 .eqos_remove_resources = eqos_remove_resources_tegra186,
2029 .eqos_stop_resets = eqos_stop_resets_tegra186,
2030 .eqos_start_resets = eqos_start_resets_tegra186,
2031 .eqos_stop_clks = eqos_stop_clks_tegra186,
2032 .eqos_start_clks = eqos_start_clks_tegra186,
2033 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
2034 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
2035 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
2036 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
2039 static const struct eqos_config eqos_tegra186_config = {
2040 .reg_access_always_ok = false,
2043 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2044 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
2045 .interface = eqos_get_interface_tegra186,
2046 .ops = &eqos_tegra186_ops
2049 static struct eqos_ops eqos_stm32_ops = {
2050 .eqos_inval_desc = eqos_inval_desc_generic,
2051 .eqos_flush_desc = eqos_flush_desc_generic,
2052 .eqos_inval_buffer = eqos_inval_buffer_generic,
2053 .eqos_flush_buffer = eqos_flush_buffer_generic,
2054 .eqos_probe_resources = eqos_probe_resources_stm32,
2055 .eqos_remove_resources = eqos_remove_resources_stm32,
2056 .eqos_stop_resets = eqos_stop_resets_stm32,
2057 .eqos_start_resets = eqos_start_resets_stm32,
2058 .eqos_stop_clks = eqos_stop_clks_stm32,
2059 .eqos_start_clks = eqos_start_clks_stm32,
2060 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
2061 .eqos_disable_calibration = eqos_disable_calibration_stm32,
2062 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
2063 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
2066 static const struct eqos_config eqos_stm32_config = {
2067 .reg_access_always_ok = false,
2070 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
2071 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2072 .interface = eqos_get_interface_stm32,
2073 .ops = &eqos_stm32_ops
2076 static struct eqos_ops eqos_imx_ops = {
2077 .eqos_inval_desc = eqos_inval_desc_generic,
2078 .eqos_flush_desc = eqos_flush_desc_generic,
2079 .eqos_inval_buffer = eqos_inval_buffer_generic,
2080 .eqos_flush_buffer = eqos_flush_buffer_generic,
2081 .eqos_probe_resources = eqos_probe_resources_imx,
2082 .eqos_remove_resources = eqos_remove_resources_imx,
2083 .eqos_stop_resets = eqos_stop_resets_imx,
2084 .eqos_start_resets = eqos_start_resets_imx,
2085 .eqos_stop_clks = eqos_stop_clks_imx,
2086 .eqos_start_clks = eqos_start_clks_imx,
2087 .eqos_calibrate_pads = eqos_calibrate_pads_imx,
2088 .eqos_disable_calibration = eqos_disable_calibration_imx,
2089 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
2090 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
2093 struct eqos_config eqos_imx_config = {
2094 .reg_access_always_ok = false,
2097 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2098 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2099 .interface = eqos_get_interface_imx,
2100 .ops = &eqos_imx_ops
2103 static const struct udevice_id eqos_ids[] = {
2105 .compatible = "nvidia,tegra186-eqos",
2106 .data = (ulong)&eqos_tegra186_config
2109 .compatible = "snps,dwmac-4.20a",
2110 .data = (ulong)&eqos_stm32_config
2113 .compatible = "fsl,imx-eqos",
2114 .data = (ulong)&eqos_imx_config
2120 U_BOOT_DRIVER(eth_eqos) = {
2123 .of_match = of_match_ptr(eqos_ids),
2124 .probe = eqos_probe,
2125 .remove = eqos_remove,
2127 .priv_auto_alloc_size = sizeof(struct eqos_priv),
2128 .platdata_auto_alloc_size = sizeof(struct eth_pdata),