1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, NVIDIA CORPORATION.
5 * Portions based on U-Boot's rtl8169.c.
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
22 * The following configurations are currently supported:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
43 #include <asm/cache.h>
47 #ifdef CONFIG_ARCH_IMX8M
48 #include <asm/arch/clock.h>
49 #include <asm/mach-imx/sys_proto.h>
51 #include <linux/bitops.h>
52 #include <linux/delay.h>
56 #define EQOS_MAC_REGS_BASE 0x000
57 struct eqos_mac_regs {
58 uint32_t configuration; /* 0x000 */
59 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
60 uint32_t q0_tx_flow_ctrl; /* 0x070 */
61 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
62 uint32_t rx_flow_ctrl; /* 0x090 */
63 uint32_t unused_094; /* 0x094 */
64 uint32_t txq_prty_map0; /* 0x098 */
65 uint32_t unused_09c; /* 0x09c */
66 uint32_t rxq_ctrl0; /* 0x0a0 */
67 uint32_t unused_0a4; /* 0x0a4 */
68 uint32_t rxq_ctrl2; /* 0x0a8 */
69 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
70 uint32_t us_tic_counter; /* 0x0dc */
71 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
72 uint32_t hw_feature0; /* 0x11c */
73 uint32_t hw_feature1; /* 0x120 */
74 uint32_t hw_feature2; /* 0x124 */
75 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
76 uint32_t mdio_address; /* 0x200 */
77 uint32_t mdio_data; /* 0x204 */
78 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
79 uint32_t address0_high; /* 0x300 */
80 uint32_t address0_low; /* 0x304 */
83 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
84 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
85 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
86 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
87 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
88 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
89 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
90 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
91 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
92 #define EQOS_MAC_CONFIGURATION_LM BIT(12)
93 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
94 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
96 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
97 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
98 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
100 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
102 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
103 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
105 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
106 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
107 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
108 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
109 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
111 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
112 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
114 #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
115 #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
116 #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
117 #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
119 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
120 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
121 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
122 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
124 #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
125 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
127 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
128 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
129 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
130 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
131 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
132 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
133 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
134 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
135 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
136 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
137 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
139 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
141 #define EQOS_MTL_REGS_BASE 0xd00
142 struct eqos_mtl_regs {
143 uint32_t txq0_operation_mode; /* 0xd00 */
144 uint32_t unused_d04; /* 0xd04 */
145 uint32_t txq0_debug; /* 0xd08 */
146 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
147 uint32_t txq0_quantum_weight; /* 0xd18 */
148 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
149 uint32_t rxq0_operation_mode; /* 0xd30 */
150 uint32_t unused_d34; /* 0xd34 */
151 uint32_t rxq0_debug; /* 0xd38 */
154 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
155 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
156 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
157 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
158 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
159 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
160 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
162 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
163 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
164 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
166 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
167 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
168 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
169 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
170 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
171 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
172 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
173 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
174 #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
175 #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
177 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
178 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
179 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
180 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
182 #define EQOS_DMA_REGS_BASE 0x1000
183 struct eqos_dma_regs {
184 uint32_t mode; /* 0x1000 */
185 uint32_t sysbus_mode; /* 0x1004 */
186 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
187 uint32_t ch0_control; /* 0x1100 */
188 uint32_t ch0_tx_control; /* 0x1104 */
189 uint32_t ch0_rx_control; /* 0x1108 */
190 uint32_t unused_110c; /* 0x110c */
191 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
192 uint32_t ch0_txdesc_list_address; /* 0x1114 */
193 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
194 uint32_t ch0_rxdesc_list_address; /* 0x111c */
195 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
196 uint32_t unused_1124; /* 0x1124 */
197 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
198 uint32_t ch0_txdesc_ring_length; /* 0x112c */
199 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
202 #define EQOS_DMA_MODE_SWR BIT(0)
204 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
205 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
206 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
207 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
208 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
209 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
211 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
213 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
214 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
215 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
216 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
218 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
219 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
220 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
221 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
222 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
224 /* These registers are Tegra186-specific */
225 #define EQOS_TEGRA186_REGS_BASE 0x8800
226 struct eqos_tegra186_regs {
227 uint32_t sdmemcomppadctrl; /* 0x8800 */
228 uint32_t auto_cal_config; /* 0x8804 */
229 uint32_t unused_8808; /* 0x8808 */
230 uint32_t auto_cal_status; /* 0x880c */
233 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
235 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
236 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
238 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
242 #define EQOS_DESCRIPTOR_WORDS 4
243 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
244 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
245 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
246 #define EQOS_DESCRIPTORS_TX 4
247 #define EQOS_DESCRIPTORS_RX 4
248 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
249 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
250 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
251 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
252 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
253 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
256 * Warn if the cache-line size is larger than the descriptor size. In such
257 * cases the driver will likely fail because the CPU needs to flush the cache
258 * when requeuing RX buffers, therefore descriptors written by the hardware
259 * may be discarded. Architectures with full IO coherence, such as x86, do not
260 * experience this issue, and hence are excluded from this condition.
262 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
263 * the driver to allocate descriptors from a pool of non-cached memory.
265 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
266 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
267 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
268 #warning Cache line size is larger than descriptor size
279 #define EQOS_DESC3_OWN BIT(31)
280 #define EQOS_DESC3_FD BIT(29)
281 #define EQOS_DESC3_LD BIT(28)
282 #define EQOS_DESC3_BUF1V BIT(24)
285 bool reg_access_always_ok;
290 phy_interface_t (*interface)(struct udevice *dev);
291 struct eqos_ops *ops;
295 void (*eqos_inval_desc)(void *desc);
296 void (*eqos_flush_desc)(void *desc);
297 void (*eqos_inval_buffer)(void *buf, size_t size);
298 void (*eqos_flush_buffer)(void *buf, size_t size);
299 int (*eqos_probe_resources)(struct udevice *dev);
300 int (*eqos_remove_resources)(struct udevice *dev);
301 int (*eqos_stop_resets)(struct udevice *dev);
302 int (*eqos_start_resets)(struct udevice *dev);
303 void (*eqos_stop_clks)(struct udevice *dev);
304 int (*eqos_start_clks)(struct udevice *dev);
305 int (*eqos_calibrate_pads)(struct udevice *dev);
306 int (*eqos_disable_calibration)(struct udevice *dev);
307 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
308 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
313 const struct eqos_config *config;
315 struct eqos_mac_regs *mac_regs;
316 struct eqos_mtl_regs *mtl_regs;
317 struct eqos_dma_regs *dma_regs;
318 struct eqos_tegra186_regs *tegra186_regs;
319 struct reset_ctl reset_ctl;
320 struct gpio_desc phy_reset_gpio;
321 struct clk clk_master_bus;
323 struct clk clk_ptp_ref;
326 struct clk clk_slave_bus;
328 struct phy_device *phy;
332 struct eqos_desc *tx_descs;
333 struct eqos_desc *rx_descs;
334 int tx_desc_idx, rx_desc_idx;
343 * TX and RX descriptors are 16 bytes. This causes problems with the cache
344 * maintenance on CPUs where the cache-line size exceeds the size of these
345 * descriptors. What will happen is that when the driver receives a packet
346 * it will be immediately requeued for the hardware to reuse. The CPU will
347 * therefore need to flush the cache-line containing the descriptor, which
348 * will cause all other descriptors in the same cache-line to be flushed
349 * along with it. If one of those descriptors had been written to by the
350 * device those changes (and the associated packet) will be lost.
352 * To work around this, we make use of non-cached memory if available. If
353 * descriptors are mapped uncached there's no need to manually flush them
354 * or invalidate them.
356 * Note that this only applies to descriptors. The packet data buffers do
357 * not have the same constraints since they are 1536 bytes large, so they
358 * are unlikely to share cache-lines.
360 static void *eqos_alloc_descs(unsigned int num)
362 #ifdef CONFIG_SYS_NONCACHED_MEMORY
363 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
364 EQOS_DESCRIPTOR_ALIGN);
366 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
370 static void eqos_free_descs(void *descs)
372 #ifdef CONFIG_SYS_NONCACHED_MEMORY
373 /* FIXME: noncached_alloc() has no opposite */
379 static void eqos_inval_desc_tegra186(void *desc)
381 #ifndef CONFIG_SYS_NONCACHED_MEMORY
382 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
383 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
386 invalidate_dcache_range(start, end);
390 static void eqos_inval_desc_generic(void *desc)
392 #ifndef CONFIG_SYS_NONCACHED_MEMORY
393 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
394 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
397 invalidate_dcache_range(start, end);
401 static void eqos_flush_desc_tegra186(void *desc)
403 #ifndef CONFIG_SYS_NONCACHED_MEMORY
404 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
408 static void eqos_flush_desc_generic(void *desc)
410 #ifndef CONFIG_SYS_NONCACHED_MEMORY
411 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
412 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
415 flush_dcache_range(start, end);
419 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
421 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
422 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
424 invalidate_dcache_range(start, end);
427 static void eqos_inval_buffer_generic(void *buf, size_t size)
429 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
430 unsigned long end = roundup((unsigned long)buf + size,
433 invalidate_dcache_range(start, end);
436 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
438 flush_cache((unsigned long)buf, size);
441 static void eqos_flush_buffer_generic(void *buf, size_t size)
443 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
444 unsigned long end = roundup((unsigned long)buf + size,
447 flush_dcache_range(start, end);
450 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
452 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
453 EQOS_MAC_MDIO_ADDRESS_GB, false,
457 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
460 struct eqos_priv *eqos = bus->priv;
464 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
467 ret = eqos_mdio_wait_idle(eqos);
469 pr_err("MDIO not idle at entry");
473 val = readl(&eqos->mac_regs->mdio_address);
474 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
475 EQOS_MAC_MDIO_ADDRESS_C45E;
476 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
477 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
478 (eqos->config->config_mac_mdio <<
479 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
480 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
481 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
482 EQOS_MAC_MDIO_ADDRESS_GB;
483 writel(val, &eqos->mac_regs->mdio_address);
485 udelay(eqos->config->mdio_wait);
487 ret = eqos_mdio_wait_idle(eqos);
489 pr_err("MDIO read didn't complete");
493 val = readl(&eqos->mac_regs->mdio_data);
494 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
496 debug("%s: val=%x\n", __func__, val);
501 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
502 int mdio_reg, u16 mdio_val)
504 struct eqos_priv *eqos = bus->priv;
508 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
509 mdio_addr, mdio_reg, mdio_val);
511 ret = eqos_mdio_wait_idle(eqos);
513 pr_err("MDIO not idle at entry");
517 writel(mdio_val, &eqos->mac_regs->mdio_data);
519 val = readl(&eqos->mac_regs->mdio_address);
520 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
521 EQOS_MAC_MDIO_ADDRESS_C45E;
522 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
523 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
524 (eqos->config->config_mac_mdio <<
525 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
526 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
527 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
528 EQOS_MAC_MDIO_ADDRESS_GB;
529 writel(val, &eqos->mac_regs->mdio_address);
531 udelay(eqos->config->mdio_wait);
533 ret = eqos_mdio_wait_idle(eqos);
535 pr_err("MDIO read didn't complete");
542 static int eqos_start_clks_tegra186(struct udevice *dev)
545 struct eqos_priv *eqos = dev_get_priv(dev);
548 debug("%s(dev=%p):\n", __func__, dev);
550 ret = clk_enable(&eqos->clk_slave_bus);
552 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
556 ret = clk_enable(&eqos->clk_master_bus);
558 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
559 goto err_disable_clk_slave_bus;
562 ret = clk_enable(&eqos->clk_rx);
564 pr_err("clk_enable(clk_rx) failed: %d", ret);
565 goto err_disable_clk_master_bus;
568 ret = clk_enable(&eqos->clk_ptp_ref);
570 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
571 goto err_disable_clk_rx;
574 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
576 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
577 goto err_disable_clk_ptp_ref;
580 ret = clk_enable(&eqos->clk_tx);
582 pr_err("clk_enable(clk_tx) failed: %d", ret);
583 goto err_disable_clk_ptp_ref;
587 debug("%s: OK\n", __func__);
591 err_disable_clk_ptp_ref:
592 clk_disable(&eqos->clk_ptp_ref);
594 clk_disable(&eqos->clk_rx);
595 err_disable_clk_master_bus:
596 clk_disable(&eqos->clk_master_bus);
597 err_disable_clk_slave_bus:
598 clk_disable(&eqos->clk_slave_bus);
600 debug("%s: FAILED: %d\n", __func__, ret);
605 static int eqos_start_clks_stm32(struct udevice *dev)
608 struct eqos_priv *eqos = dev_get_priv(dev);
611 debug("%s(dev=%p):\n", __func__, dev);
613 ret = clk_enable(&eqos->clk_master_bus);
615 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
619 ret = clk_enable(&eqos->clk_rx);
621 pr_err("clk_enable(clk_rx) failed: %d", ret);
622 goto err_disable_clk_master_bus;
625 ret = clk_enable(&eqos->clk_tx);
627 pr_err("clk_enable(clk_tx) failed: %d", ret);
628 goto err_disable_clk_rx;
631 if (clk_valid(&eqos->clk_ck)) {
632 ret = clk_enable(&eqos->clk_ck);
634 pr_err("clk_enable(clk_ck) failed: %d", ret);
635 goto err_disable_clk_tx;
640 debug("%s: OK\n", __func__);
645 clk_disable(&eqos->clk_tx);
647 clk_disable(&eqos->clk_rx);
648 err_disable_clk_master_bus:
649 clk_disable(&eqos->clk_master_bus);
651 debug("%s: FAILED: %d\n", __func__, ret);
656 static int eqos_start_clks_imx(struct udevice *dev)
661 static void eqos_stop_clks_tegra186(struct udevice *dev)
664 struct eqos_priv *eqos = dev_get_priv(dev);
666 debug("%s(dev=%p):\n", __func__, dev);
668 clk_disable(&eqos->clk_tx);
669 clk_disable(&eqos->clk_ptp_ref);
670 clk_disable(&eqos->clk_rx);
671 clk_disable(&eqos->clk_master_bus);
672 clk_disable(&eqos->clk_slave_bus);
675 debug("%s: OK\n", __func__);
678 static void eqos_stop_clks_stm32(struct udevice *dev)
681 struct eqos_priv *eqos = dev_get_priv(dev);
683 debug("%s(dev=%p):\n", __func__, dev);
685 clk_disable(&eqos->clk_tx);
686 clk_disable(&eqos->clk_rx);
687 clk_disable(&eqos->clk_master_bus);
688 if (clk_valid(&eqos->clk_ck))
689 clk_disable(&eqos->clk_ck);
692 debug("%s: OK\n", __func__);
695 static void eqos_stop_clks_imx(struct udevice *dev)
700 static int eqos_start_resets_tegra186(struct udevice *dev)
702 struct eqos_priv *eqos = dev_get_priv(dev);
705 debug("%s(dev=%p):\n", __func__, dev);
707 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
709 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
715 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
717 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
721 ret = reset_assert(&eqos->reset_ctl);
723 pr_err("reset_assert() failed: %d", ret);
729 ret = reset_deassert(&eqos->reset_ctl);
731 pr_err("reset_deassert() failed: %d", ret);
735 debug("%s: OK\n", __func__);
739 static int eqos_start_resets_stm32(struct udevice *dev)
741 struct eqos_priv *eqos = dev_get_priv(dev);
744 debug("%s(dev=%p):\n", __func__, dev);
745 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
746 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
748 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
755 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
757 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
762 debug("%s: OK\n", __func__);
767 static int eqos_start_resets_imx(struct udevice *dev)
772 static int eqos_stop_resets_tegra186(struct udevice *dev)
774 struct eqos_priv *eqos = dev_get_priv(dev);
776 reset_assert(&eqos->reset_ctl);
777 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
782 static int eqos_stop_resets_stm32(struct udevice *dev)
784 struct eqos_priv *eqos = dev_get_priv(dev);
787 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
788 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
790 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
799 static int eqos_stop_resets_imx(struct udevice *dev)
804 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
806 struct eqos_priv *eqos = dev_get_priv(dev);
809 debug("%s(dev=%p):\n", __func__, dev);
811 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
812 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
816 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
817 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
819 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
820 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
822 pr_err("calibrate didn't start");
826 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
827 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
829 pr_err("calibrate didn't finish");
836 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
837 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
839 debug("%s: returns %d\n", __func__, ret);
844 static int eqos_disable_calibration_tegra186(struct udevice *dev)
846 struct eqos_priv *eqos = dev_get_priv(dev);
848 debug("%s(dev=%p):\n", __func__, dev);
850 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
851 EQOS_AUTO_CAL_CONFIG_ENABLE);
856 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
859 struct eqos_priv *eqos = dev_get_priv(dev);
861 return clk_get_rate(&eqos->clk_slave_bus);
867 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
870 struct eqos_priv *eqos = dev_get_priv(dev);
872 return clk_get_rate(&eqos->clk_master_bus);
878 __weak u32 imx_get_eqos_csr_clk(void)
880 return 100 * 1000000;
882 __weak int imx_eqos_txclk_set_rate(unsigned long rate)
887 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
889 return imx_get_eqos_csr_clk();
892 static int eqos_calibrate_pads_stm32(struct udevice *dev)
897 static int eqos_calibrate_pads_imx(struct udevice *dev)
902 static int eqos_disable_calibration_stm32(struct udevice *dev)
907 static int eqos_disable_calibration_imx(struct udevice *dev)
912 static int eqos_set_full_duplex(struct udevice *dev)
914 struct eqos_priv *eqos = dev_get_priv(dev);
916 debug("%s(dev=%p):\n", __func__, dev);
918 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
923 static int eqos_set_half_duplex(struct udevice *dev)
925 struct eqos_priv *eqos = dev_get_priv(dev);
927 debug("%s(dev=%p):\n", __func__, dev);
929 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
931 /* WAR: Flush TX queue when switching to half-duplex */
932 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
933 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
938 static int eqos_set_gmii_speed(struct udevice *dev)
940 struct eqos_priv *eqos = dev_get_priv(dev);
942 debug("%s(dev=%p):\n", __func__, dev);
944 clrbits_le32(&eqos->mac_regs->configuration,
945 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
950 static int eqos_set_mii_speed_100(struct udevice *dev)
952 struct eqos_priv *eqos = dev_get_priv(dev);
954 debug("%s(dev=%p):\n", __func__, dev);
956 setbits_le32(&eqos->mac_regs->configuration,
957 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
962 static int eqos_set_mii_speed_10(struct udevice *dev)
964 struct eqos_priv *eqos = dev_get_priv(dev);
966 debug("%s(dev=%p):\n", __func__, dev);
968 clrsetbits_le32(&eqos->mac_regs->configuration,
969 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
974 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
977 struct eqos_priv *eqos = dev_get_priv(dev);
981 debug("%s(dev=%p):\n", __func__, dev);
983 switch (eqos->phy->speed) {
985 rate = 125 * 1000 * 1000;
988 rate = 25 * 1000 * 1000;
991 rate = 2.5 * 1000 * 1000;
994 pr_err("invalid speed %d", eqos->phy->speed);
998 ret = clk_set_rate(&eqos->clk_tx, rate);
1000 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
1008 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
1013 static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
1015 struct eqos_priv *eqos = dev_get_priv(dev);
1019 debug("%s(dev=%p):\n", __func__, dev);
1021 switch (eqos->phy->speed) {
1023 rate = 125 * 1000 * 1000;
1026 rate = 25 * 1000 * 1000;
1029 rate = 2.5 * 1000 * 1000;
1032 pr_err("invalid speed %d", eqos->phy->speed);
1036 ret = imx_eqos_txclk_set_rate(rate);
1038 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
1045 static int eqos_adjust_link(struct udevice *dev)
1047 struct eqos_priv *eqos = dev_get_priv(dev);
1049 bool en_calibration;
1051 debug("%s(dev=%p):\n", __func__, dev);
1053 if (eqos->phy->duplex)
1054 ret = eqos_set_full_duplex(dev);
1056 ret = eqos_set_half_duplex(dev);
1058 pr_err("eqos_set_*_duplex() failed: %d", ret);
1062 switch (eqos->phy->speed) {
1064 en_calibration = true;
1065 ret = eqos_set_gmii_speed(dev);
1068 en_calibration = true;
1069 ret = eqos_set_mii_speed_100(dev);
1072 en_calibration = false;
1073 ret = eqos_set_mii_speed_10(dev);
1076 pr_err("invalid speed %d", eqos->phy->speed);
1080 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
1084 if (en_calibration) {
1085 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1087 pr_err("eqos_calibrate_pads() failed: %d",
1092 ret = eqos->config->ops->eqos_disable_calibration(dev);
1094 pr_err("eqos_disable_calibration() failed: %d",
1099 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
1101 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
1108 static int eqos_write_hwaddr(struct udevice *dev)
1110 struct eth_pdata *plat = dev_get_platdata(dev);
1111 struct eqos_priv *eqos = dev_get_priv(dev);
1115 * This function may be called before start() or after stop(). At that
1116 * time, on at least some configurations of the EQoS HW, all clocks to
1117 * the EQoS HW block will be stopped, and a reset signal applied. If
1118 * any register access is attempted in this state, bus timeouts or CPU
1119 * hangs may occur. This check prevents that.
1121 * A simple solution to this problem would be to not implement
1122 * write_hwaddr(), since start() always writes the MAC address into HW
1123 * anyway. However, it is desirable to implement write_hwaddr() to
1124 * support the case of SW that runs subsequent to U-Boot which expects
1125 * the MAC address to already be programmed into the EQoS registers,
1126 * which must happen irrespective of whether the U-Boot user (or
1127 * scripts) actually made use of the EQoS device, and hence
1128 * irrespective of whether start() was ever called.
1130 * Note that this requirement by subsequent SW is not valid for
1131 * Tegra186, and is likely not valid for any non-PCI instantiation of
1132 * the EQoS HW block. This function is implemented solely as
1133 * future-proofing with the expectation the driver will eventually be
1134 * ported to some system where the expectation above is true.
1136 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1139 /* Update the MAC address */
1140 val = (plat->enetaddr[5] << 8) |
1141 (plat->enetaddr[4]);
1142 writel(val, &eqos->mac_regs->address0_high);
1143 val = (plat->enetaddr[3] << 24) |
1144 (plat->enetaddr[2] << 16) |
1145 (plat->enetaddr[1] << 8) |
1146 (plat->enetaddr[0]);
1147 writel(val, &eqos->mac_regs->address0_low);
1152 static int eqos_read_rom_hwaddr(struct udevice *dev)
1154 struct eth_pdata *pdata = dev_get_platdata(dev);
1156 #ifdef CONFIG_ARCH_IMX8M
1157 imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
1159 return !is_valid_ethaddr(pdata->enetaddr);
1162 static int eqos_start(struct udevice *dev)
1164 struct eqos_priv *eqos = dev_get_priv(dev);
1167 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1170 debug("%s(dev=%p):\n", __func__, dev);
1172 eqos->tx_desc_idx = 0;
1173 eqos->rx_desc_idx = 0;
1175 ret = eqos->config->ops->eqos_start_clks(dev);
1177 pr_err("eqos_start_clks() failed: %d", ret);
1181 ret = eqos->config->ops->eqos_start_resets(dev);
1183 pr_err("eqos_start_resets() failed: %d", ret);
1189 eqos->reg_access_ok = true;
1191 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
1192 EQOS_DMA_MODE_SWR, false,
1193 eqos->config->swr_wait, false);
1195 pr_err("EQOS_DMA_MODE_SWR stuck");
1196 goto err_stop_resets;
1199 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1201 pr_err("eqos_calibrate_pads() failed: %d", ret);
1202 goto err_stop_resets;
1204 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
1206 val = (rate / 1000000) - 1;
1207 writel(val, &eqos->mac_regs->us_tic_counter);
1210 * if PHY was already connected and configured,
1211 * don't need to reconnect/reconfigure again
1215 #ifdef CONFIG_DM_ETH_PHY
1216 addr = eth_phy_get_addr(dev);
1218 #ifdef DWC_NET_PHYADDR
1219 addr = DWC_NET_PHYADDR;
1221 eqos->phy = phy_connect(eqos->mii, addr, dev,
1222 eqos->config->interface(dev));
1224 pr_err("phy_connect() failed");
1225 goto err_stop_resets;
1228 if (eqos->max_speed) {
1229 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1231 pr_err("phy_set_supported() failed: %d", ret);
1232 goto err_shutdown_phy;
1236 ret = phy_config(eqos->phy);
1238 pr_err("phy_config() failed: %d", ret);
1239 goto err_shutdown_phy;
1243 ret = phy_startup(eqos->phy);
1245 pr_err("phy_startup() failed: %d", ret);
1246 goto err_shutdown_phy;
1249 if (!eqos->phy->link) {
1251 goto err_shutdown_phy;
1254 ret = eqos_adjust_link(dev);
1256 pr_err("eqos_adjust_link() failed: %d", ret);
1257 goto err_shutdown_phy;
1261 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
1263 /* Enable Store and Forward mode for TX */
1264 /* Program Tx operating mode */
1265 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1266 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1267 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1268 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1270 /* Transmit Queue weight */
1271 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1273 /* Enable Store and Forward mode for RX, since no jumbo frame */
1274 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1275 EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
1276 EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
1277 EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
1279 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1280 val = readl(&eqos->mac_regs->hw_feature1);
1281 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1282 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1283 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1284 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1287 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1288 * r/tqs is encoded as (n / 256) - 1.
1290 tqs = (128 << tx_fifo_sz) / 256 - 1;
1291 rqs = (128 << rx_fifo_sz) / 256 - 1;
1293 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1294 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1295 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1296 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1297 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1298 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1299 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1300 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1302 /* Flow control used only if each channel gets 4KB or more FIFO */
1303 if (rqs >= ((4096 / 256) - 1)) {
1306 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1307 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1310 * Set Threshold for Activating Flow Contol space for min 2
1311 * frames ie, (1500 * 1) = 1500 bytes.
1313 * Set Threshold for Deactivating Flow Contol for space of
1314 * min 1 frame (frame size 1500bytes) in receive fifo
1316 if (rqs == ((4096 / 256) - 1)) {
1318 * This violates the above formula because of FIFO size
1319 * limit therefore overflow may occur inspite of this.
1321 rfd = 0x3; /* Full-3K */
1322 rfa = 0x1; /* Full-1.5K */
1323 } else if (rqs == ((8192 / 256) - 1)) {
1324 rfd = 0x6; /* Full-4K */
1325 rfa = 0xa; /* Full-6K */
1326 } else if (rqs == ((16384 / 256) - 1)) {
1327 rfd = 0x6; /* Full-4K */
1328 rfa = 0x12; /* Full-10K */
1330 rfd = 0x6; /* Full-4K */
1331 rfa = 0x1E; /* Full-16K */
1334 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1335 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1336 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1337 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1338 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1340 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1342 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1347 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1348 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1349 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1350 eqos->config->config_mac <<
1351 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1353 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1354 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1355 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1357 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1359 /* Multicast and Broadcast Queue Enable */
1360 setbits_le32(&eqos->mac_regs->unused_0a4,
1362 /* enable promise mode */
1363 setbits_le32(&eqos->mac_regs->unused_004[1],
1366 /* Set TX flow control parameters */
1367 /* Set Pause Time */
1368 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1369 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1370 /* Assign priority for TX flow control */
1371 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1372 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1373 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1374 /* Assign priority for RX flow control */
1375 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1376 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1377 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1378 /* Enable flow control */
1379 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1380 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1381 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1382 EQOS_MAC_RX_FLOW_CTRL_RFE);
1384 clrsetbits_le32(&eqos->mac_regs->configuration,
1385 EQOS_MAC_CONFIGURATION_GPSLCE |
1386 EQOS_MAC_CONFIGURATION_WD |
1387 EQOS_MAC_CONFIGURATION_JD |
1388 EQOS_MAC_CONFIGURATION_JE,
1389 EQOS_MAC_CONFIGURATION_CST |
1390 EQOS_MAC_CONFIGURATION_ACS);
1392 eqos_write_hwaddr(dev);
1396 /* Enable OSP mode */
1397 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1398 EQOS_DMA_CH0_TX_CONTROL_OSP);
1400 /* RX buffer size. Must be a multiple of bus width */
1401 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1402 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1403 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1404 EQOS_MAX_PACKET_SIZE <<
1405 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1407 setbits_le32(&eqos->dma_regs->ch0_control,
1408 EQOS_DMA_CH0_CONTROL_PBLX8);
1411 * Burst length must be < 1/2 FIFO size.
1412 * FIFO size in tqs is encoded as (n / 256) - 1.
1413 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1414 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1419 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1420 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1421 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1422 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1424 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1425 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1426 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1427 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1429 /* DMA performance configuration */
1430 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1431 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1432 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1433 writel(val, &eqos->dma_regs->sysbus_mode);
1435 /* Set up descriptors */
1437 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1438 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1439 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1440 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1441 (i * EQOS_MAX_PACKET_SIZE));
1442 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1444 eqos->config->ops->eqos_flush_desc(rx_desc);
1445 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1446 (i * EQOS_MAX_PACKET_SIZE),
1447 EQOS_MAX_PACKET_SIZE);
1450 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1451 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1452 writel(EQOS_DESCRIPTORS_TX - 1,
1453 &eqos->dma_regs->ch0_txdesc_ring_length);
1455 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1456 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1457 writel(EQOS_DESCRIPTORS_RX - 1,
1458 &eqos->dma_regs->ch0_rxdesc_ring_length);
1460 /* Enable everything */
1461 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1462 EQOS_DMA_CH0_TX_CONTROL_ST);
1463 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1464 EQOS_DMA_CH0_RX_CONTROL_SR);
1465 setbits_le32(&eqos->mac_regs->configuration,
1466 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1468 /* TX tail pointer not written until we need to TX a packet */
1470 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1471 * first descriptor, implying all descriptors were available. However,
1472 * that's not distinguishable from none of the descriptors being
1475 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1476 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1478 eqos->started = true;
1480 debug("%s: OK\n", __func__);
1484 phy_shutdown(eqos->phy);
1486 eqos->config->ops->eqos_stop_resets(dev);
1488 eqos->config->ops->eqos_stop_clks(dev);
1490 pr_err("FAILED: %d", ret);
1494 static void eqos_stop(struct udevice *dev)
1496 struct eqos_priv *eqos = dev_get_priv(dev);
1499 debug("%s(dev=%p):\n", __func__, dev);
1503 eqos->started = false;
1504 eqos->reg_access_ok = false;
1506 /* Disable TX DMA */
1507 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1508 EQOS_DMA_CH0_TX_CONTROL_ST);
1510 /* Wait for TX all packets to drain out of MTL */
1511 for (i = 0; i < 1000000; i++) {
1512 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1513 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1514 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1515 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1516 if ((trcsts != 1) && (!txqsts))
1520 /* Turn off MAC TX and RX */
1521 clrbits_le32(&eqos->mac_regs->configuration,
1522 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1524 /* Wait for all RX packets to drain out of MTL */
1525 for (i = 0; i < 1000000; i++) {
1526 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1527 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1528 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1529 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1530 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1531 if ((!prxq) && (!rxqsts))
1535 /* Turn off RX DMA */
1536 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1537 EQOS_DMA_CH0_RX_CONTROL_SR);
1540 phy_shutdown(eqos->phy);
1542 eqos->config->ops->eqos_stop_resets(dev);
1543 eqos->config->ops->eqos_stop_clks(dev);
1545 debug("%s: OK\n", __func__);
1548 static int eqos_send(struct udevice *dev, void *packet, int length)
1550 struct eqos_priv *eqos = dev_get_priv(dev);
1551 struct eqos_desc *tx_desc;
1554 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1557 memcpy(eqos->tx_dma_buf, packet, length);
1558 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1560 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1561 eqos->tx_desc_idx++;
1562 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1564 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1566 tx_desc->des2 = length;
1568 * Make sure that if HW sees the _OWN write below, it will see all the
1569 * writes to the rest of the descriptor too.
1572 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1573 eqos->config->ops->eqos_flush_desc(tx_desc);
1575 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
1576 &eqos->dma_regs->ch0_txdesc_tail_pointer);
1578 for (i = 0; i < 1000000; i++) {
1579 eqos->config->ops->eqos_inval_desc(tx_desc);
1580 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1585 debug("%s: TX timeout\n", __func__);
1590 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1592 struct eqos_priv *eqos = dev_get_priv(dev);
1593 struct eqos_desc *rx_desc;
1596 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1598 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1599 eqos->config->ops->eqos_inval_desc(rx_desc);
1600 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1601 debug("%s: RX packet not available\n", __func__);
1605 *packetp = eqos->rx_dma_buf +
1606 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1607 length = rx_desc->des3 & 0x7fff;
1608 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1610 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1615 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1617 struct eqos_priv *eqos = dev_get_priv(dev);
1618 uchar *packet_expected;
1619 struct eqos_desc *rx_desc;
1621 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1623 packet_expected = eqos->rx_dma_buf +
1624 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1625 if (packet != packet_expected) {
1626 debug("%s: Unexpected packet (expected %p)\n", __func__,
1631 eqos->config->ops->eqos_inval_buffer(packet, length);
1633 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1637 eqos->config->ops->eqos_flush_desc(rx_desc);
1638 eqos->config->ops->eqos_inval_buffer(packet, length);
1639 rx_desc->des0 = (u32)(ulong)packet;
1643 * Make sure that if HW sees the _OWN write below, it will see all the
1644 * writes to the rest of the descriptor too.
1647 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1648 eqos->config->ops->eqos_flush_desc(rx_desc);
1650 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1652 eqos->rx_desc_idx++;
1653 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1658 static int eqos_probe_resources_core(struct udevice *dev)
1660 struct eqos_priv *eqos = dev_get_priv(dev);
1663 debug("%s(dev=%p):\n", __func__, dev);
1665 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1666 EQOS_DESCRIPTORS_RX);
1668 debug("%s: eqos_alloc_descs() failed\n", __func__);
1672 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1673 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1674 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1677 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1678 if (!eqos->tx_dma_buf) {
1679 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1681 goto err_free_descs;
1683 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1685 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1686 if (!eqos->rx_dma_buf) {
1687 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1689 goto err_free_tx_dma_buf;
1691 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1693 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1694 if (!eqos->rx_pkt) {
1695 debug("%s: malloc(rx_pkt) failed\n", __func__);
1697 goto err_free_rx_dma_buf;
1699 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1701 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1702 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1704 debug("%s: OK\n", __func__);
1707 err_free_rx_dma_buf:
1708 free(eqos->rx_dma_buf);
1709 err_free_tx_dma_buf:
1710 free(eqos->tx_dma_buf);
1712 eqos_free_descs(eqos->descs);
1715 debug("%s: returns %d\n", __func__, ret);
1719 static int eqos_remove_resources_core(struct udevice *dev)
1721 struct eqos_priv *eqos = dev_get_priv(dev);
1723 debug("%s(dev=%p):\n", __func__, dev);
1726 free(eqos->rx_dma_buf);
1727 free(eqos->tx_dma_buf);
1728 eqos_free_descs(eqos->descs);
1730 debug("%s: OK\n", __func__);
1734 static int eqos_probe_resources_tegra186(struct udevice *dev)
1736 struct eqos_priv *eqos = dev_get_priv(dev);
1739 debug("%s(dev=%p):\n", __func__, dev);
1741 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1743 pr_err("reset_get_by_name(rst) failed: %d", ret);
1747 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1748 &eqos->phy_reset_gpio,
1749 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1751 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1752 goto err_free_reset_eqos;
1755 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1757 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1758 goto err_free_gpio_phy_reset;
1761 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1763 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1764 goto err_free_clk_slave_bus;
1767 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1769 pr_err("clk_get_by_name(rx) failed: %d", ret);
1770 goto err_free_clk_master_bus;
1773 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1775 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1776 goto err_free_clk_rx;
1780 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1782 pr_err("clk_get_by_name(tx) failed: %d", ret);
1783 goto err_free_clk_ptp_ref;
1786 debug("%s: OK\n", __func__);
1789 err_free_clk_ptp_ref:
1790 clk_free(&eqos->clk_ptp_ref);
1792 clk_free(&eqos->clk_rx);
1793 err_free_clk_master_bus:
1794 clk_free(&eqos->clk_master_bus);
1795 err_free_clk_slave_bus:
1796 clk_free(&eqos->clk_slave_bus);
1797 err_free_gpio_phy_reset:
1798 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1799 err_free_reset_eqos:
1800 reset_free(&eqos->reset_ctl);
1802 debug("%s: returns %d\n", __func__, ret);
1806 /* board-specific Ethernet Interface initializations. */
1807 __weak int board_interface_eth_init(struct udevice *dev,
1808 phy_interface_t interface_type)
1813 static int eqos_probe_resources_stm32(struct udevice *dev)
1815 struct eqos_priv *eqos = dev_get_priv(dev);
1817 phy_interface_t interface;
1818 struct ofnode_phandle_args phandle_args;
1820 debug("%s(dev=%p):\n", __func__, dev);
1822 interface = eqos->config->interface(dev);
1824 if (interface == PHY_INTERFACE_MODE_NONE) {
1825 pr_err("Invalid PHY interface\n");
1829 ret = board_interface_eth_init(dev, interface);
1833 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1835 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1837 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1841 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1843 pr_err("clk_get_by_name(rx) failed: %d", ret);
1844 goto err_free_clk_master_bus;
1847 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1849 pr_err("clk_get_by_name(tx) failed: %d", ret);
1850 goto err_free_clk_rx;
1853 /* Get ETH_CLK clocks (optional) */
1854 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1856 pr_warn("No phy clock provided %d", ret);
1859 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1862 /* search "reset-gpios" in phy node */
1863 ret = gpio_request_by_name_nodev(phandle_args.node,
1865 &eqos->phy_reset_gpio,
1867 GPIOD_IS_OUT_ACTIVE);
1869 pr_warn("gpio_request_by_name(phy reset) not provided %d",
1872 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
1876 debug("%s: OK\n", __func__);
1880 clk_free(&eqos->clk_rx);
1881 err_free_clk_master_bus:
1882 clk_free(&eqos->clk_master_bus);
1885 debug("%s: returns %d\n", __func__, ret);
1889 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1891 const char *phy_mode;
1892 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1894 debug("%s(dev=%p):\n", __func__, dev);
1896 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1899 interface = phy_get_interface_by_name(phy_mode);
1904 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1906 return PHY_INTERFACE_MODE_MII;
1909 static int eqos_probe_resources_imx(struct udevice *dev)
1911 struct eqos_priv *eqos = dev_get_priv(dev);
1912 phy_interface_t interface;
1914 debug("%s(dev=%p):\n", __func__, dev);
1916 interface = eqos->config->interface(dev);
1918 if (interface == PHY_INTERFACE_MODE_NONE) {
1919 pr_err("Invalid PHY interface\n");
1923 debug("%s: OK\n", __func__);
1927 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
1929 const char *phy_mode;
1930 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1932 debug("%s(dev=%p):\n", __func__, dev);
1934 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1937 interface = phy_get_interface_by_name(phy_mode);
1942 static int eqos_remove_resources_tegra186(struct udevice *dev)
1944 struct eqos_priv *eqos = dev_get_priv(dev);
1946 debug("%s(dev=%p):\n", __func__, dev);
1949 clk_free(&eqos->clk_tx);
1950 clk_free(&eqos->clk_ptp_ref);
1951 clk_free(&eqos->clk_rx);
1952 clk_free(&eqos->clk_slave_bus);
1953 clk_free(&eqos->clk_master_bus);
1955 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1956 reset_free(&eqos->reset_ctl);
1958 debug("%s: OK\n", __func__);
1962 static int eqos_remove_resources_stm32(struct udevice *dev)
1965 struct eqos_priv *eqos = dev_get_priv(dev);
1967 debug("%s(dev=%p):\n", __func__, dev);
1969 clk_free(&eqos->clk_tx);
1970 clk_free(&eqos->clk_rx);
1971 clk_free(&eqos->clk_master_bus);
1972 if (clk_valid(&eqos->clk_ck))
1973 clk_free(&eqos->clk_ck);
1976 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
1977 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1979 debug("%s: OK\n", __func__);
1983 static int eqos_remove_resources_imx(struct udevice *dev)
1988 static int eqos_probe(struct udevice *dev)
1990 struct eqos_priv *eqos = dev_get_priv(dev);
1993 debug("%s(dev=%p):\n", __func__, dev);
1996 eqos->config = (void *)dev_get_driver_data(dev);
1998 eqos->regs = devfdt_get_addr(dev);
1999 if (eqos->regs == FDT_ADDR_T_NONE) {
2000 pr_err("devfdt_get_addr() failed");
2003 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
2004 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
2005 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
2006 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
2008 ret = eqos_probe_resources_core(dev);
2010 pr_err("eqos_probe_resources_core() failed: %d", ret);
2014 ret = eqos->config->ops->eqos_probe_resources(dev);
2016 pr_err("eqos_probe_resources() failed: %d", ret);
2017 goto err_remove_resources_core;
2020 #ifdef CONFIG_DM_ETH_PHY
2021 eqos->mii = eth_phy_get_mdio_bus(dev);
2024 eqos->mii = mdio_alloc();
2026 pr_err("mdio_alloc() failed");
2028 goto err_remove_resources_tegra;
2030 eqos->mii->read = eqos_mdio_read;
2031 eqos->mii->write = eqos_mdio_write;
2032 eqos->mii->priv = eqos;
2033 strcpy(eqos->mii->name, dev->name);
2035 ret = mdio_register(eqos->mii);
2037 pr_err("mdio_register() failed: %d", ret);
2042 #ifdef CONFIG_DM_ETH_PHY
2043 eth_phy_set_mdio_bus(dev, eqos->mii);
2046 debug("%s: OK\n", __func__);
2050 mdio_free(eqos->mii);
2051 err_remove_resources_tegra:
2052 eqos->config->ops->eqos_remove_resources(dev);
2053 err_remove_resources_core:
2054 eqos_remove_resources_core(dev);
2056 debug("%s: returns %d\n", __func__, ret);
2060 static int eqos_remove(struct udevice *dev)
2062 struct eqos_priv *eqos = dev_get_priv(dev);
2064 debug("%s(dev=%p):\n", __func__, dev);
2066 mdio_unregister(eqos->mii);
2067 mdio_free(eqos->mii);
2068 eqos->config->ops->eqos_remove_resources(dev);
2070 eqos_probe_resources_core(dev);
2072 debug("%s: OK\n", __func__);
2076 static const struct eth_ops eqos_ops = {
2077 .start = eqos_start,
2081 .free_pkt = eqos_free_pkt,
2082 .write_hwaddr = eqos_write_hwaddr,
2083 .read_rom_hwaddr = eqos_read_rom_hwaddr,
2086 static struct eqos_ops eqos_tegra186_ops = {
2087 .eqos_inval_desc = eqos_inval_desc_tegra186,
2088 .eqos_flush_desc = eqos_flush_desc_tegra186,
2089 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
2090 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
2091 .eqos_probe_resources = eqos_probe_resources_tegra186,
2092 .eqos_remove_resources = eqos_remove_resources_tegra186,
2093 .eqos_stop_resets = eqos_stop_resets_tegra186,
2094 .eqos_start_resets = eqos_start_resets_tegra186,
2095 .eqos_stop_clks = eqos_stop_clks_tegra186,
2096 .eqos_start_clks = eqos_start_clks_tegra186,
2097 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
2098 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
2099 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
2100 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
2103 static const struct eqos_config eqos_tegra186_config = {
2104 .reg_access_always_ok = false,
2107 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2108 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
2109 .interface = eqos_get_interface_tegra186,
2110 .ops = &eqos_tegra186_ops
2113 static struct eqos_ops eqos_stm32_ops = {
2114 .eqos_inval_desc = eqos_inval_desc_generic,
2115 .eqos_flush_desc = eqos_flush_desc_generic,
2116 .eqos_inval_buffer = eqos_inval_buffer_generic,
2117 .eqos_flush_buffer = eqos_flush_buffer_generic,
2118 .eqos_probe_resources = eqos_probe_resources_stm32,
2119 .eqos_remove_resources = eqos_remove_resources_stm32,
2120 .eqos_stop_resets = eqos_stop_resets_stm32,
2121 .eqos_start_resets = eqos_start_resets_stm32,
2122 .eqos_stop_clks = eqos_stop_clks_stm32,
2123 .eqos_start_clks = eqos_start_clks_stm32,
2124 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
2125 .eqos_disable_calibration = eqos_disable_calibration_stm32,
2126 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
2127 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
2130 static const struct eqos_config eqos_stm32_config = {
2131 .reg_access_always_ok = false,
2134 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
2135 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2136 .interface = eqos_get_interface_stm32,
2137 .ops = &eqos_stm32_ops
2140 static struct eqos_ops eqos_imx_ops = {
2141 .eqos_inval_desc = eqos_inval_desc_generic,
2142 .eqos_flush_desc = eqos_flush_desc_generic,
2143 .eqos_inval_buffer = eqos_inval_buffer_generic,
2144 .eqos_flush_buffer = eqos_flush_buffer_generic,
2145 .eqos_probe_resources = eqos_probe_resources_imx,
2146 .eqos_remove_resources = eqos_remove_resources_imx,
2147 .eqos_stop_resets = eqos_stop_resets_imx,
2148 .eqos_start_resets = eqos_start_resets_imx,
2149 .eqos_stop_clks = eqos_stop_clks_imx,
2150 .eqos_start_clks = eqos_start_clks_imx,
2151 .eqos_calibrate_pads = eqos_calibrate_pads_imx,
2152 .eqos_disable_calibration = eqos_disable_calibration_imx,
2153 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
2154 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
2157 struct eqos_config eqos_imx_config = {
2158 .reg_access_always_ok = false,
2161 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2162 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2163 .interface = eqos_get_interface_imx,
2164 .ops = &eqos_imx_ops
2167 static const struct udevice_id eqos_ids[] = {
2169 .compatible = "nvidia,tegra186-eqos",
2170 .data = (ulong)&eqos_tegra186_config
2173 .compatible = "st,stm32mp1-dwmac",
2174 .data = (ulong)&eqos_stm32_config
2177 .compatible = "fsl,imx-eqos",
2178 .data = (ulong)&eqos_imx_config
2184 U_BOOT_DRIVER(eth_eqos) = {
2187 .of_match = of_match_ptr(eqos_ids),
2188 .probe = eqos_probe,
2189 .remove = eqos_remove,
2191 .priv_auto_alloc_size = sizeof(struct eqos_priv),
2192 .platdata_auto_alloc_size = sizeof(struct eth_pdata),