1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/timecounter.h>
10 #include <linux/dsa/sja1105.h>
11 #include <linux/dsa/8021q.h>
13 #include <linux/mutex.h>
14 #include "sja1105_static_config.h"
16 #define SJA1105ET_FDB_BIN_SIZE 4
17 /* The hardware value is in multiples of 10 ms.
18 * The passed parameter is in multiples of 1 ms.
20 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10)
21 #define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT
23 /* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period)
24 * To avoid floating point operations, we'll multiply the degrees by 10
25 * to get a "phase" and get 1 decimal point precision.
27 #define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \
29 #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
30 ((800 * (phase)) / 360)
31 #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
33 #define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \
34 SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps))
36 /* Valid range in degrees is a value between 73.8 and 101.7
37 * in 0.9 degree increments
39 #define SJA1105_RGMII_DELAY_MIN_PS \
40 SJA1105_RGMII_DELAY_PHASE_TO_PS(738)
41 #define SJA1105_RGMII_DELAY_MAX_PS \
42 SJA1105_RGMII_DELAY_PHASE_TO_PS(1017)
47 } sja1105_spi_rw_mode_t;
49 #include "sja1105_tas.h"
50 #include "sja1105_ptp.h"
52 enum sja1105_stats_area {
57 __MAX_SJA1105_STATS_AREA,
60 /* Keeps the different addresses between E/T and P/Q/R/S */
78 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
79 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
80 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
81 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
82 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
83 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
84 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
85 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
86 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
87 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
88 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
89 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
90 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
93 u64 pcs_base[SJA1105_MAX_NUM_PORTS];
96 struct sja1105_mdio_private {
97 struct sja1105_private *priv;
102 SJA1105_SPEED_10MBPS,
103 SJA1105_SPEED_100MBPS,
104 SJA1105_SPEED_1000MBPS,
105 SJA1105_SPEED_2500MBPS,
109 enum sja1105_internal_phy_t {
115 struct sja1105_info {
117 /* Needed for distinction between P and R, and between Q and S
118 * (since the parts with/without SGMII share the same
119 * switch core and device_id)
122 /* E/T and P/Q/R/S have partial timestamps of different sizes.
123 * They must be reconstructed on both families anyway to get the full
124 * 64-bit values back.
127 /* Also SPI commands are of different sizes to retrieve
128 * the egress timestamps.
134 bool multiple_cascade_ports;
135 enum dsa_tag_protocol tag_proto;
136 const struct sja1105_dynamic_table_ops *dyn_ops;
137 const struct sja1105_table_ops *static_ops;
138 const struct sja1105_regs *regs;
139 bool can_limit_mcast_flood;
140 int (*reset_cmd)(struct dsa_switch *ds);
141 int (*setup_rgmii_delay)(const void *ctx, int port);
142 /* Prototypes from include/net/dsa.h */
143 int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
144 const unsigned char *addr, u16 vid);
145 int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
146 const unsigned char *addr, u16 vid);
147 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
149 bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
150 void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
151 int (*clocking_setup)(struct sja1105_private *priv);
152 int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);
153 int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);
154 int (*disable_microcontroller)(struct sja1105_private *priv);
156 bool supports_mii[SJA1105_MAX_NUM_PORTS];
157 bool supports_rmii[SJA1105_MAX_NUM_PORTS];
158 bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
159 bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
160 bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
161 enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
162 const u64 port_speed[SJA1105_SPEED_MAX];
165 enum sja1105_key_type {
168 SJA1105_KEY_VLAN_UNAWARE_VL,
169 SJA1105_KEY_VLAN_AWARE_VL,
173 enum sja1105_key_type type;
181 /* SJA1105_KEY_VLAN_UNAWARE_VL */
182 /* SJA1105_KEY_VLAN_AWARE_VL */
191 enum sja1105_rule_type {
192 SJA1105_RULE_BCAST_POLICER,
193 SJA1105_RULE_TC_POLICER,
197 enum sja1105_vl_type {
198 SJA1105_VL_NONCRITICAL,
199 SJA1105_VL_RATE_CONSTRAINED,
200 SJA1105_VL_TIME_TRIGGERED,
203 struct sja1105_rule {
204 struct list_head list;
205 unsigned long cookie;
206 unsigned long port_mask;
207 struct sja1105_key key;
208 enum sja1105_rule_type type;
212 /* SJA1105_RULE_BCAST_POLICER */
217 /* SJA1105_RULE_TC_POLICER */
222 /* SJA1105_RULE_VL */
224 enum sja1105_vl_type type;
225 unsigned long destports;
232 struct action_gate_entry *entries;
233 struct flow_stats stats;
238 struct sja1105_flow_block {
239 struct list_head rules;
240 bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
241 int num_virtual_links;
244 struct sja1105_private {
245 struct sja1105_static_config static_config;
246 int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
247 int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
248 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
249 bool fixed_link[SJA1105_MAX_NUM_PORTS];
250 unsigned long ucast_egress_floods;
251 unsigned long bcast_egress_floods;
252 unsigned long hwts_tx_en;
253 unsigned long hwts_rx_en;
254 const struct sja1105_info *info;
256 struct spi_device *spidev;
257 struct dsa_switch *ds;
258 u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
259 u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
260 struct sja1105_flow_block flow_block;
261 /* Serializes transmission of management frames so that
262 * the switch doesn't confuse them with one another.
264 struct mutex mgmt_lock;
265 /* PTP two-step TX timestamp ID, and its serialization lock */
266 spinlock_t ts_id_lock;
268 /* Serializes access to the dynamic config interface */
269 struct mutex dynamic_config_lock;
270 struct devlink_region **regions;
271 struct sja1105_cbs_entry *cbs;
272 struct mii_bus *mdio_base_t1;
273 struct mii_bus *mdio_base_tx;
274 struct mii_bus *mdio_pcs;
275 struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
276 struct sja1105_ptp_data ptp_data;
277 struct sja1105_tas_data tas_data;
280 #include "sja1105_dynamic_config.h"
282 struct sja1105_spi_message {
288 /* From sja1105_main.c */
289 enum sja1105_reset_reason {
290 SJA1105_VLAN_FILTERING = 0,
293 SJA1105_BEST_EFFORT_POLICING,
294 SJA1105_VIRTUAL_LINKS,
297 int sja1105_static_config_reload(struct sja1105_private *priv,
298 enum sja1105_reset_reason reason);
299 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
300 struct netlink_ext_ack *extack);
301 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
303 /* From sja1105_mdio.c */
304 int sja1105_mdiobus_register(struct dsa_switch *ds);
305 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
306 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
307 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
308 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
309 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
311 /* From sja1105_devlink.c */
312 int sja1105_devlink_setup(struct dsa_switch *ds);
313 void sja1105_devlink_teardown(struct dsa_switch *ds);
314 int sja1105_devlink_info_get(struct dsa_switch *ds,
315 struct devlink_info_req *req,
316 struct netlink_ext_ack *extack);
318 /* From sja1105_spi.c */
319 int sja1105_xfer_buf(const struct sja1105_private *priv,
320 sja1105_spi_rw_mode_t rw, u64 reg_addr,
321 u8 *buf, size_t len);
322 int sja1105_xfer_u32(const struct sja1105_private *priv,
323 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
324 struct ptp_system_timestamp *ptp_sts);
325 int sja1105_xfer_u64(const struct sja1105_private *priv,
326 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
327 struct ptp_system_timestamp *ptp_sts);
328 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
329 void *config_buf, int buf_len);
330 int sja1105_static_config_upload(struct sja1105_private *priv);
331 int sja1105_inhibit_tx(const struct sja1105_private *priv,
332 unsigned long port_bitmap, bool tx_inhibited);
334 extern const struct sja1105_info sja1105e_info;
335 extern const struct sja1105_info sja1105t_info;
336 extern const struct sja1105_info sja1105p_info;
337 extern const struct sja1105_info sja1105q_info;
338 extern const struct sja1105_info sja1105r_info;
339 extern const struct sja1105_info sja1105s_info;
340 extern const struct sja1105_info sja1110a_info;
341 extern const struct sja1105_info sja1110b_info;
342 extern const struct sja1105_info sja1110c_info;
343 extern const struct sja1105_info sja1110d_info;
345 /* From sja1105_clocking.c */
350 } sja1105_mii_role_t;
357 } sja1105_phy_interface_t;
359 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
360 int sja1110_setup_rgmii_delay(const void *ctx, int port);
361 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
362 int sja1105_clocking_setup(struct sja1105_private *priv);
363 int sja1110_disable_microcontroller(struct sja1105_private *priv);
365 /* From sja1105_ethtool.c */
366 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
367 void sja1105_get_strings(struct dsa_switch *ds, int port,
368 u32 stringset, u8 *data);
369 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
371 /* From sja1105_dynamic_config.c */
372 int sja1105_dynamic_config_read(struct sja1105_private *priv,
373 enum sja1105_blk_idx blk_idx,
374 int index, void *entry);
375 int sja1105_dynamic_config_write(struct sja1105_private *priv,
376 enum sja1105_blk_idx blk_idx,
377 int index, void *entry, bool keep);
380 SJA1105_C_TAG = 0, /* Inner VLAN header */
381 SJA1105_S_TAG = 1, /* Outer VLAN header */
384 enum sja1110_vlan_type {
385 SJA1110_VLAN_INVALID = 0,
386 SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
387 SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
388 SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
391 enum sja1110_shaper_type {
392 SJA1110_LEAKY_BUCKET_SHAPER = 0,
393 SJA1110_CBS_SHAPER = 1,
396 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
397 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
398 const unsigned char *addr, u16 vid);
399 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
400 const unsigned char *addr, u16 vid);
401 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
402 const unsigned char *addr, u16 vid);
403 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
404 const unsigned char *addr, u16 vid);
406 /* From sja1105_flower.c */
407 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
408 struct flow_cls_offload *cls, bool ingress);
409 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
410 struct flow_cls_offload *cls, bool ingress);
411 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
412 struct flow_cls_offload *cls, bool ingress);
413 void sja1105_flower_setup(struct dsa_switch *ds);
414 void sja1105_flower_teardown(struct dsa_switch *ds);
415 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
416 unsigned long cookie);