drivers/net/dsa/qca8k.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef __QCA8K_H
   9 #define __QCA8K_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/regmap.h>
  13 #include <linux/gpio.h>
  14
  15 #define QCA8K_NUM_PORTS                                 7
  16 #define QCA8K_MAX_MTU                                   9000
  17
  18 #define PHY_ID_QCA8337                                  0x004dd036
  19 #define QCA8K_ID_QCA8337                                0x13
  20
  21 #define QCA8K_NUM_FDB_RECORDS                           2048
  22
  23 #define QCA8K_CPU_PORT                                  0
  24
  25 /* Global control registers */
  26 #define QCA8K_REG_MASK_CTRL                             0x000
  27 #define   QCA8K_MASK_CTRL_ID_M                          0xff
  28 #define   QCA8K_MASK_CTRL_ID_S                          8
  29 #define QCA8K_REG_PORT0_PAD_CTRL                        0x004
  30 #define QCA8K_REG_PORT5_PAD_CTRL                        0x008
  31 #define QCA8K_REG_PORT6_PAD_CTRL                        0x00c
  32 #define   QCA8K_PORT_PAD_RGMII_EN                       BIT(26)
  33 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)              \
  34                                                 ((0x8 + (x & 0x3)) << 22)
  35 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)              \
  36                                                 ((0x10 + (x & 0x3)) << 20)
  37 #define   QCA8K_MAX_DELAY                               3
  38 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN              BIT(24)
  39 #define   QCA8K_PORT_PAD_SGMII_EN                       BIT(7)
  40 #define QCA8K_REG_PWS                                   0x010
  41 #define   QCA8K_PWS_SERDES_AEN_DIS                      BIT(7)
  42 #define QCA8K_REG_MODULE_EN                             0x030
  43 #define   QCA8K_MODULE_EN_MIB                           BIT(0)
  44 #define QCA8K_REG_MIB                                   0x034
  45 #define   QCA8K_MIB_FLUSH                               BIT(24)
  46 #define   QCA8K_MIB_CPU_KEEP                            BIT(20)
  47 #define   QCA8K_MIB_BUSY                                BIT(17)
  48 #define QCA8K_MDIO_MASTER_CTRL                          0x3c
  49 #define   QCA8K_MDIO_MASTER_BUSY                        BIT(31)
  50 #define   QCA8K_MDIO_MASTER_EN                          BIT(30)
  51 #define   QCA8K_MDIO_MASTER_READ                        BIT(27)
  52 #define   QCA8K_MDIO_MASTER_WRITE                       0
  53 #define   QCA8K_MDIO_MASTER_SUP_PRE                     BIT(26)
  54 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)                 ((x) << 21)
  55 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)                 ((x) << 16)
  56 #define   QCA8K_MDIO_MASTER_DATA(x)                     (x)
  57 #define   QCA8K_MDIO_MASTER_DATA_MASK                   GENMASK(15, 0)
  58 #define   QCA8K_MDIO_MASTER_MAX_PORTS                   5
  59 #define   QCA8K_MDIO_MASTER_MAX_REG                     32
  60 #define QCA8K_GOL_MAC_ADDR0                             0x60
  61 #define QCA8K_GOL_MAC_ADDR1                             0x64
  62 #define QCA8K_MAX_FRAME_SIZE                            0x78
  63 #define QCA8K_REG_PORT_STATUS(_i)                       (0x07c + (_i) * 4)
  64 #define   QCA8K_PORT_STATUS_SPEED                       GENMASK(1, 0)
  65 #define   QCA8K_PORT_STATUS_SPEED_10                    0
  66 #define   QCA8K_PORT_STATUS_SPEED_100                   0x1
  67 #define   QCA8K_PORT_STATUS_SPEED_1000                  0x2
  68 #define   QCA8K_PORT_STATUS_TXMAC                       BIT(2)
  69 #define   QCA8K_PORT_STATUS_RXMAC                       BIT(3)
  70 #define   QCA8K_PORT_STATUS_TXFLOW                      BIT(4)
  71 #define   QCA8K_PORT_STATUS_RXFLOW                      BIT(5)
  72 #define   QCA8K_PORT_STATUS_DUPLEX                      BIT(6)
  73 #define   QCA8K_PORT_STATUS_LINK_UP                     BIT(8)
  74 #define   QCA8K_PORT_STATUS_LINK_AUTO                   BIT(9)
  75 #define   QCA8K_PORT_STATUS_LINK_PAUSE                  BIT(10)
  76 #define   QCA8K_PORT_STATUS_FLOW_AUTO                   BIT(12)
  77 #define QCA8K_REG_PORT_HDR_CTRL(_i)                     (0x9c + (_i * 4))
  78 #define   QCA8K_PORT_HDR_CTRL_RX_MASK                   GENMASK(3, 2)
  79 #define   QCA8K_PORT_HDR_CTRL_RX_S                      2
  80 #define   QCA8K_PORT_HDR_CTRL_TX_MASK                   GENMASK(1, 0)
  81 #define   QCA8K_PORT_HDR_CTRL_TX_S                      0
  82 #define   QCA8K_PORT_HDR_CTRL_ALL                       2
  83 #define   QCA8K_PORT_HDR_CTRL_MGMT                      1
  84 #define   QCA8K_PORT_HDR_CTRL_NONE                      0
  85 #define QCA8K_REG_SGMII_CTRL                            0x0e0
  86 #define   QCA8K_SGMII_EN_PLL                            BIT(1)
  87 #define   QCA8K_SGMII_EN_RX                             BIT(2)
  88 #define   QCA8K_SGMII_EN_TX                             BIT(3)
  89 #define   QCA8K_SGMII_EN_SD                             BIT(4)
  90 #define   QCA8K_SGMII_CLK125M_DELAY                     BIT(7)
  91 #define   QCA8K_SGMII_MODE_CTRL_MASK                    (BIT(22) | BIT(23))
  92 #define   QCA8K_SGMII_MODE_CTRL_BASEX                   (0 << 22)
  93 #define   QCA8K_SGMII_MODE_CTRL_PHY                     (1 << 22)
  94 #define   QCA8K_SGMII_MODE_CTRL_MAC                     (2 << 22)
  95
  96 /* EEE control registers */
  97 #define QCA8K_REG_EEE_CTRL                              0x100
  98 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                  ((_i + 1) * 2)
  99
 100 /* ACL registers */
 101 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)                   (0x420 + (_i * 8))
 102 #define   QCA8K_PORT_VLAN_CVID(x)                       (x << 16)
 103 #define   QCA8K_PORT_VLAN_SVID(x)                       x
 104 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)                   (0x424 + (_i * 8))
 105 #define QCA8K_REG_IPV4_PRI_BASE_ADDR                    0x470
 106 #define QCA8K_REG_IPV4_PRI_ADDR_MASK                    0x474
 107
 108 /* Lookup registers */
 109 #define QCA8K_REG_ATU_DATA0                             0x600
 110 #define   QCA8K_ATU_ADDR2_S                             24
 111 #define   QCA8K_ATU_ADDR3_S                             16
 112 #define   QCA8K_ATU_ADDR4_S                             8
 113 #define QCA8K_REG_ATU_DATA1                             0x604
 114 #define   QCA8K_ATU_PORT_M                              0x7f
 115 #define   QCA8K_ATU_PORT_S                              16
 116 #define   QCA8K_ATU_ADDR0_S                             8
 117 #define QCA8K_REG_ATU_DATA2                             0x608
 118 #define   QCA8K_ATU_VID_M                               0xfff
 119 #define   QCA8K_ATU_VID_S                               8
 120 #define   QCA8K_ATU_STATUS_M                            0xf
 121 #define   QCA8K_ATU_STATUS_STATIC                       0xf
 122 #define QCA8K_REG_ATU_FUNC                              0x60c
 123 #define   QCA8K_ATU_FUNC_BUSY                           BIT(31)
 124 #define   QCA8K_ATU_FUNC_PORT_EN                        BIT(14)
 125 #define   QCA8K_ATU_FUNC_MULTI_EN                       BIT(13)
 126 #define   QCA8K_ATU_FUNC_FULL                           BIT(12)
 127 #define   QCA8K_ATU_FUNC_PORT_M                         0xf
 128 #define   QCA8K_ATU_FUNC_PORT_S                         8
 129 #define QCA8K_REG_GLOBAL_FW_CTRL0                       0x620
 130 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN             BIT(10)
 131 #define QCA8K_REG_GLOBAL_FW_CTRL1                       0x624
 132 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S               24
 133 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_S                 16
 134 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_S                 8
 135 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_S                 0
 136 #define QCA8K_PORT_LOOKUP_CTRL(_i)                      (0x660 + (_i) * 0xc)
 137 #define   QCA8K_PORT_LOOKUP_MEMBER                      GENMASK(6, 0)
 138 #define   QCA8K_PORT_LOOKUP_STATE_MASK                  GENMASK(18, 16)
 139 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED              (0 << 16)
 140 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING              (1 << 16)
 141 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING             (2 << 16)
 142 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING              (3 << 16)
 143 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD               (4 << 16)
 144 #define   QCA8K_PORT_LOOKUP_STATE                       GENMASK(18, 16)
 145 #define   QCA8K_PORT_LOOKUP_LEARN                       BIT(20)
 146
 147 /* Pkt edit registers */
 148 #define QCA8K_EGRESS_VLAN(x)                            (0x0c70 + (4 * (x / 2)))
 149
 150 /* L3 registers */
 151 #define QCA8K_HROUTER_CONTROL                           0xe00
 152 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M          GENMASK(17, 16)
 153 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S          16
 154 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE            1
 155 #define QCA8K_HROUTER_PBASED_CONTROL1                   0xe08
 156 #define QCA8K_HROUTER_PBASED_CONTROL2                   0xe0c
 157 #define QCA8K_HNAT_CONTROL                              0xe38
 158
 159 /* MIB registers */
 160 #define QCA8K_PORT_MIB_COUNTER(_i)                      (0x1000 + (_i) * 0x100)
 161
 162 /* QCA specific MII registers */
 163 #define MII_ATH_MMD_ADDR                                0x0d
 164 #define MII_ATH_MMD_DATA                                0x0e
 165
 166 enum {
 167         QCA8K_PORT_SPEED_10M = 0,
 168         QCA8K_PORT_SPEED_100M = 1,
 169         QCA8K_PORT_SPEED_1000M = 2,
 170         QCA8K_PORT_SPEED_ERR = 3,
 171 };
 172
 173 enum qca8k_fdb_cmd {
 174         QCA8K_FDB_FLUSH = 1,
 175         QCA8K_FDB_LOAD = 2,
 176         QCA8K_FDB_PURGE = 3,
 177         QCA8K_FDB_NEXT = 6,
 178         QCA8K_FDB_SEARCH = 7,
 179 };
 180
 181 struct ar8xxx_port_status {
 182         int enabled;
 183 };
 184
 185 struct qca8k_priv {
 186         struct regmap *regmap;
 187         struct mii_bus *bus;
 188         struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
 189         struct dsa_switch *ds;
 190         struct mutex reg_mutex;
 191         struct device *dev;
 192         struct dsa_switch_ops ops;
 193         struct gpio_desc *reset_gpio;
 194         unsigned int port_mtu[QCA8K_NUM_PORTS];
 195 };
 196
 197 struct qca8k_mib_desc {
 198         unsigned int size;
 199         unsigned int offset;
 200         const char *name;
 201 };
 202
 203 struct qca8k_fdb {
 204         u16 vid;
 205         u8 port_mask;
 206         u8 aging;
 207         u8 mac[6];
 208 };
 209
 210 #endif /* __QCA8K_H */