1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/bitfield.h>
13 #include <linux/regmap.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_platform.h>
18 #include <linux/mdio.h>
19 #include <linux/phylink.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dsa/tag_qca.h>
25 #include "qca8k_leds.h"
28 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
37 *page = regaddr & 0x3ff;
41 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
47 ret = bus->write(bus, phy_id, regnum, lo);
49 dev_err_ratelimited(&bus->dev,
50 "failed to write qca8k 32bit lo register\n");
56 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
61 hi = (u16)(val >> 16);
62 ret = bus->write(bus, phy_id, regnum, hi);
64 dev_err_ratelimited(&bus->dev,
65 "failed to write qca8k 32bit hi register\n");
71 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
75 ret = bus->read(bus, phy_id, regnum);
83 dev_err_ratelimited(&bus->dev,
84 "failed to read qca8k 32bit lo register\n");
91 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
95 ret = bus->read(bus, phy_id, regnum);
103 dev_err_ratelimited(&bus->dev,
104 "failed to read qca8k 32bit hi register\n");
111 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
118 ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
122 ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
133 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
135 if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
138 qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
142 qca8k_set_page(struct qca8k_priv *priv, u16 page)
144 u16 *cached_page = &priv->mdio_cache.page;
145 struct mii_bus *bus = priv->bus;
148 if (page == *cached_page)
151 ret = bus->write(bus, 0x18, 0, page);
153 dev_err_ratelimited(&bus->dev,
154 "failed to set qca8k page\n");
159 usleep_range(1000, 2000);
163 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
165 struct qca8k_mgmt_eth_data *mgmt_eth_data;
166 struct qca8k_priv *priv = ds->priv;
167 struct qca_mgmt_ethhdr *mgmt_ethhdr;
172 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
173 mgmt_eth_data = &priv->mgmt_eth_data;
175 command = get_unaligned_le32(&mgmt_ethhdr->command);
176 cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
178 len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
179 /* Special case for len of 15 as this is the max value for len and needs to
180 * be increased before converting it from word to dword.
185 /* We can ignore odd value, we always round up them in the alloc function. */
188 /* Make sure the seq match the requested packet */
189 if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
190 mgmt_eth_data->ack = true;
192 if (cmd == MDIO_READ) {
193 u32 *val = mgmt_eth_data->data;
195 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data);
197 /* Get the rest of the 12 byte of data.
198 * The read/write function will extract the requested data.
200 if (len > QCA_HDR_MGMT_DATA1_LEN) {
201 __le32 *data2 = (__le32 *)skb->data;
202 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
203 len - QCA_HDR_MGMT_DATA1_LEN);
207 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
208 *val = get_unaligned_le32(data2);
215 complete(&mgmt_eth_data->rw_done);
218 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
219 int priority, unsigned int len)
221 struct qca_mgmt_ethhdr *mgmt_ethhdr;
222 unsigned int real_len;
229 skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
233 /* Hdr mgmt length value is in step of word size.
234 * As an example to process 4 byte of data the correct length to set is 2.
235 * To process 8 byte 4, 12 byte 6, 16 byte 8...
237 * Odd values will always return the next size on the ack packet.
238 * (length of 3 (6 byte) will always return 8 bytes of data)
240 * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
243 * To correctly calculate the length we devide the requested len by word and
245 * On the ack function we can skip the odd check as we already handle the
248 real_len = DIV_ROUND_UP(len, sizeof(u16));
250 /* We check if the result len is odd and we round up another time to
251 * the next size. (length of 3 will be increased to 4 as switch will always
254 if (real_len % sizeof(u16) != 0)
257 /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
261 skb_reset_mac_header(skb);
262 skb_set_network_header(skb, skb->len);
264 mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
266 hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
267 hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
268 hdr |= QCA_HDR_XMIT_FROM_CPU;
269 hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
270 hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
272 command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
273 command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
274 command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
275 command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
276 QCA_HDR_MGMT_CHECK_CODE_VAL);
278 put_unaligned_le32(command, &mgmt_ethhdr->command);
280 if (cmd == MDIO_WRITE)
281 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data);
283 mgmt_ethhdr->hdr = htons(hdr);
285 data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
286 if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) {
287 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
288 len - QCA_HDR_MGMT_DATA1_LEN);
292 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
293 put_unaligned_le32(*val, data2);
302 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
304 struct qca_mgmt_ethhdr *mgmt_ethhdr;
307 seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
308 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
309 put_unaligned_le32(seq, &mgmt_ethhdr->seq);
312 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
314 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
319 skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
320 QCA8K_ETHERNET_MDIO_PRIORITY, len);
324 mutex_lock(&mgmt_eth_data->mutex);
326 /* Check mgmt_master if is operational */
327 if (!priv->mgmt_master) {
329 mutex_unlock(&mgmt_eth_data->mutex);
333 skb->dev = priv->mgmt_master;
335 reinit_completion(&mgmt_eth_data->rw_done);
337 /* Increment seq_num and set it in the mdio pkt */
338 mgmt_eth_data->seq++;
339 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
340 mgmt_eth_data->ack = false;
344 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
345 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
347 *val = mgmt_eth_data->data[0];
348 if (len > QCA_HDR_MGMT_DATA1_LEN)
349 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
351 ack = mgmt_eth_data->ack;
353 mutex_unlock(&mgmt_eth_data->mutex);
364 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
366 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
371 skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
372 QCA8K_ETHERNET_MDIO_PRIORITY, len);
376 mutex_lock(&mgmt_eth_data->mutex);
378 /* Check mgmt_master if is operational */
379 if (!priv->mgmt_master) {
381 mutex_unlock(&mgmt_eth_data->mutex);
385 skb->dev = priv->mgmt_master;
387 reinit_completion(&mgmt_eth_data->rw_done);
389 /* Increment seq_num and set it in the mdio pkt */
390 mgmt_eth_data->seq++;
391 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
392 mgmt_eth_data->ack = false;
396 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
397 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
399 ack = mgmt_eth_data->ack;
401 mutex_unlock(&mgmt_eth_data->mutex);
413 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
418 ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
425 return qca8k_write_eth(priv, reg, &val, sizeof(val));
429 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)
431 struct mii_bus *bus = priv->bus;
435 qca8k_split_addr(reg, &r1, &r2, &page);
437 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
439 ret = qca8k_set_page(priv, page);
443 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
446 mutex_unlock(&bus->mdio_lock);
451 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)
453 struct mii_bus *bus = priv->bus;
457 qca8k_split_addr(reg, &r1, &r2, &page);
459 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
461 ret = qca8k_set_page(priv, page);
465 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
468 mutex_unlock(&bus->mdio_lock);
473 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,
474 uint32_t mask, uint32_t write_val)
476 struct mii_bus *bus = priv->bus;
481 qca8k_split_addr(reg, &r1, &r2, &page);
483 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
485 ret = qca8k_set_page(priv, page);
489 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
495 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
498 mutex_unlock(&bus->mdio_lock);
504 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,
505 void *val_buf, size_t val_len)
507 int i, count = val_len / sizeof(u32), ret;
508 u32 reg = *(u32 *)reg_buf & U16_MAX;
509 struct qca8k_priv *priv = ctx;
511 if (priv->mgmt_master &&
512 !qca8k_read_eth(priv, reg, val_buf, val_len))
515 /* loop count times and increment reg of 4 */
516 for (i = 0; i < count; i++, reg += sizeof(u32)) {
517 ret = qca8k_read_mii(priv, reg, val_buf + i);
526 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,
527 const void *val_buf, size_t val_len)
529 int i, count = val_len / sizeof(u32), ret;
530 u32 reg = *(u32 *)reg_buf & U16_MAX;
531 struct qca8k_priv *priv = ctx;
532 u32 *val = (u32 *)val_buf;
534 if (priv->mgmt_master &&
535 !qca8k_write_eth(priv, reg, val, val_len))
538 /* loop count times, increment reg of 4 and increment val ptr to
541 for (i = 0; i < count; i++, reg += sizeof(u32), val++) {
542 ret = qca8k_write_mii(priv, reg, *val);
551 qca8k_bulk_write(void *ctx, const void *data, size_t bytes)
553 return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),
554 bytes - sizeof(u16));
558 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
560 struct qca8k_priv *priv = ctx;
562 if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
565 return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);
568 static struct regmap_config qca8k_regmap_config = {
572 .max_register = 0x16ac, /* end MIB - Port6 range */
573 .read = qca8k_bulk_read,
574 .write = qca8k_bulk_write,
575 .reg_update_bits = qca8k_regmap_update_bits,
576 .rd_table = &qca8k_readable_table,
577 .disable_locking = true, /* Locking is handled by qca8k read/write */
578 .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
579 .max_raw_read = 32, /* mgmt eth can read up to 8 registers at time */
580 /* ATU regs suffer from a bug where some data are not correctly
581 * written. Disable bulk write to correctly write ATU entry.
583 .use_single_write = true,
587 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
588 struct sk_buff *read_skb, u32 *val)
590 struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
597 reinit_completion(&mgmt_eth_data->rw_done);
599 /* Increment seq_num and set it in the copy pkt */
600 mgmt_eth_data->seq++;
601 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
602 mgmt_eth_data->ack = false;
606 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
607 QCA8K_ETHERNET_TIMEOUT);
609 ack = mgmt_eth_data->ack;
617 *val = mgmt_eth_data->data[0];
623 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
624 int regnum, u16 data)
626 struct sk_buff *write_skb, *clear_skb, *read_skb;
627 struct qca8k_mgmt_eth_data *mgmt_eth_data;
628 u32 write_val, clear_val = 0, val;
629 struct net_device *mgmt_master;
633 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
636 mgmt_eth_data = &priv->mgmt_eth_data;
638 write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
639 QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
640 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
643 write_val |= QCA8K_MDIO_MASTER_READ;
645 write_val |= QCA8K_MDIO_MASTER_WRITE;
646 write_val |= QCA8K_MDIO_MASTER_DATA(data);
649 /* Prealloc all the needed skb before the lock */
650 write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
651 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
655 clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
656 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
662 read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
663 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
669 /* Actually start the request:
670 * 1. Send mdio master packet
671 * 2. Busy Wait for mdio master command
672 * 3. Get the data if we are reading
673 * 4. Reset the mdio master (even with error)
675 mutex_lock(&mgmt_eth_data->mutex);
677 /* Check if mgmt_master is operational */
678 mgmt_master = priv->mgmt_master;
680 mutex_unlock(&mgmt_eth_data->mutex);
682 goto err_mgmt_master;
685 read_skb->dev = mgmt_master;
686 clear_skb->dev = mgmt_master;
687 write_skb->dev = mgmt_master;
689 reinit_completion(&mgmt_eth_data->rw_done);
691 /* Increment seq_num and set it in the write pkt */
692 mgmt_eth_data->seq++;
693 qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
694 mgmt_eth_data->ack = false;
696 dev_queue_xmit(write_skb);
698 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
699 QCA8K_ETHERNET_TIMEOUT);
701 ack = mgmt_eth_data->ack;
715 ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
716 !(val & QCA8K_MDIO_MASTER_BUSY), 0,
717 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
718 mgmt_eth_data, read_skb, &val);
720 if (ret < 0 && ret1 < 0) {
726 reinit_completion(&mgmt_eth_data->rw_done);
728 /* Increment seq_num and set it in the read pkt */
729 mgmt_eth_data->seq++;
730 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
731 mgmt_eth_data->ack = false;
733 dev_queue_xmit(read_skb);
735 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
736 QCA8K_ETHERNET_TIMEOUT);
738 ack = mgmt_eth_data->ack;
750 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
755 reinit_completion(&mgmt_eth_data->rw_done);
757 /* Increment seq_num and set it in the clear pkt */
758 mgmt_eth_data->seq++;
759 qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
760 mgmt_eth_data->ack = false;
762 dev_queue_xmit(clear_skb);
764 wait_for_completion_timeout(&mgmt_eth_data->rw_done,
765 QCA8K_ETHERNET_TIMEOUT);
767 mutex_unlock(&mgmt_eth_data->mutex);
771 /* Error handling before lock */
775 kfree_skb(clear_skb);
777 kfree_skb(write_skb);
783 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
789 qca8k_split_addr(reg, &r1, &r2, &page);
791 ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
792 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
793 bus, 0x10 | r2, r1 + 1, &val);
795 /* Check if qca8k_read has failed for a different reason
796 * before returnting -ETIMEDOUT
798 if (ret < 0 && ret1 < 0)
805 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
807 struct mii_bus *bus = priv->bus;
812 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
815 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
816 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
817 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
818 QCA8K_MDIO_MASTER_DATA(data);
820 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
822 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
824 ret = qca8k_set_page(priv, page);
828 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
830 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
831 QCA8K_MDIO_MASTER_BUSY);
834 /* even if the busy_wait timeouts try to clear the MASTER_EN */
835 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
837 mutex_unlock(&bus->mdio_lock);
843 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
845 struct mii_bus *bus = priv->bus;
850 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
853 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
854 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
855 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
857 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
859 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
861 ret = qca8k_set_page(priv, page);
865 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
867 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
868 QCA8K_MDIO_MASTER_BUSY);
872 ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
875 /* even if the busy_wait timeouts try to clear the MASTER_EN */
876 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
878 mutex_unlock(&bus->mdio_lock);
881 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
887 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
889 struct qca8k_priv *priv = slave_bus->priv;
892 /* Use mdio Ethernet when available, fallback to legacy one on error */
893 ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
897 return qca8k_mdio_write(priv, phy, regnum, data);
901 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
903 struct qca8k_priv *priv = slave_bus->priv;
906 /* Use mdio Ethernet when available, fallback to legacy one on error */
907 ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
911 ret = qca8k_mdio_read(priv, phy, regnum);
920 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
922 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
924 return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
928 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
930 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
932 return qca8k_internal_mdio_read(slave_bus, port, regnum);
936 qca8k_mdio_register(struct qca8k_priv *priv)
938 struct dsa_switch *ds = priv->ds;
939 struct device_node *mdio;
942 bus = devm_mdiobus_alloc(ds->dev);
946 bus->priv = (void *)priv;
947 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
948 ds->dst->index, ds->index);
949 bus->parent = ds->dev;
950 bus->phy_mask = ~ds->phys_mii_mask;
951 ds->slave_mii_bus = bus;
953 /* Check if the devicetree declare the port:phy mapping */
954 mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
955 if (of_device_is_available(mdio)) {
956 bus->name = "qca8k slave mii";
957 bus->read = qca8k_internal_mdio_read;
958 bus->write = qca8k_internal_mdio_write;
959 return devm_of_mdiobus_register(priv->dev, bus, mdio);
962 /* If a mapping can't be found the legacy mapping is used,
963 * using the qca8k_port_to_phy function
965 bus->name = "qca8k-legacy slave mii";
966 bus->read = qca8k_legacy_mdio_read;
967 bus->write = qca8k_legacy_mdio_write;
968 return devm_mdiobus_register(priv->dev, bus);
972 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
974 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
975 struct device_node *ports, *port;
976 phy_interface_t mode;
979 ports = of_get_child_by_name(priv->dev->of_node, "ports");
981 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
986 for_each_available_child_of_node(ports, port) {
987 err = of_property_read_u32(port, "reg", ®);
994 if (!dsa_is_user_port(priv->ds, reg))
997 of_get_phy_mode(port, &mode);
999 if (of_property_read_bool(port, "phy-handle") &&
1000 mode != PHY_INTERFACE_MODE_INTERNAL)
1001 external_mdio_mask |= BIT(reg);
1003 internal_mdio_mask |= BIT(reg);
1007 if (!external_mdio_mask && !internal_mdio_mask) {
1008 dev_err(priv->dev, "no PHYs are defined.\n");
1012 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
1013 * the MDIO_MASTER register also _disconnects_ the external MDC
1014 * passthrough to the internal PHYs. It's not possible to use both
1015 * configurations at the same time!
1017 * Because this came up during the review process:
1018 * If the external mdio-bus driver is capable magically disabling
1019 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
1020 * accessors for the time being, it would be possible to pull this
1023 if (!!external_mdio_mask && !!internal_mdio_mask) {
1024 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
1028 if (external_mdio_mask) {
1029 /* Make sure to disable the internal mdio bus in cases
1030 * a dt-overlay and driver reload changed the configuration
1033 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
1034 QCA8K_MDIO_MASTER_EN);
1037 return qca8k_mdio_register(priv);
1041 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
1046 /* SoC specific settings for ipq8064.
1047 * If more device require this consider adding
1048 * a dedicated binding.
1050 if (of_machine_is_compatible("qcom,ipq8064"))
1051 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
1053 /* SoC specific settings for ipq8065 */
1054 if (of_machine_is_compatible("qcom,ipq8065"))
1055 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
1058 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
1059 QCA8K_MAC_PWR_RGMII0_1_8V |
1060 QCA8K_MAC_PWR_RGMII1_1_8V,
1067 static int qca8k_find_cpu_port(struct dsa_switch *ds)
1069 struct qca8k_priv *priv = ds->priv;
1071 /* Find the connected cpu port. Valid port are 0 or 6 */
1072 if (dsa_is_cpu_port(ds, 0))
1075 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
1077 if (dsa_is_cpu_port(ds, 6))
1084 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
1086 const struct qca8k_match_data *data = priv->info;
1087 struct device_node *node = priv->dev->of_node;
1091 /* QCA8327 require to set to the correct mode.
1092 * His bigger brother QCA8328 have the 172 pin layout.
1093 * Should be applied by default but we set this just to make sure.
1095 if (priv->switch_id == QCA8K_ID_QCA8327) {
1096 /* Set the correct package of 148 pin for QCA8327 */
1097 if (data->reduced_package)
1098 val |= QCA8327_PWS_PACKAGE148_EN;
1100 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1106 if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1107 val |= QCA8K_PWS_POWER_ON_SEL;
1109 if (of_property_read_bool(node, "qca,led-open-drain")) {
1110 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1111 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1115 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1118 return qca8k_rmw(priv, QCA8K_REG_PWS,
1119 QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1124 qca8k_parse_port_config(struct qca8k_priv *priv)
1126 int port, cpu_port_index = -1, ret;
1127 struct device_node *port_dn;
1128 phy_interface_t mode;
1129 struct dsa_port *dp;
1132 /* We have 2 CPU port. Check them */
1133 for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1134 /* Skip every other port */
1135 if (port != 0 && port != 6)
1138 dp = dsa_to_port(priv->ds, port);
1142 if (!of_device_is_available(port_dn))
1145 ret = of_get_phy_mode(port_dn, &mode);
1150 case PHY_INTERFACE_MODE_RGMII:
1151 case PHY_INTERFACE_MODE_RGMII_ID:
1152 case PHY_INTERFACE_MODE_RGMII_TXID:
1153 case PHY_INTERFACE_MODE_RGMII_RXID:
1154 case PHY_INTERFACE_MODE_SGMII:
1157 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1158 /* Switch regs accept value in ns, convert ps to ns */
1159 delay = delay / 1000;
1160 else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1161 mode == PHY_INTERFACE_MODE_RGMII_TXID)
1164 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1165 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1169 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1173 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1174 /* Switch regs accept value in ns, convert ps to ns */
1175 delay = delay / 1000;
1176 else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1177 mode == PHY_INTERFACE_MODE_RGMII_RXID)
1180 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1181 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1185 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1187 /* Skip sgmii parsing for rgmii* mode */
1188 if (mode == PHY_INTERFACE_MODE_RGMII ||
1189 mode == PHY_INTERFACE_MODE_RGMII_ID ||
1190 mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1191 mode == PHY_INTERFACE_MODE_RGMII_RXID)
1194 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1195 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1197 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1198 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1200 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1201 priv->ports_config.sgmii_enable_pll = true;
1203 if (priv->switch_id == QCA8K_ID_QCA8327) {
1204 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1205 priv->ports_config.sgmii_enable_pll = false;
1208 if (priv->switch_revision < 2)
1209 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1222 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1228 /* Delay can be declared in 3 different way.
1229 * Mode to rgmii and internal-delay standard binding defined
1230 * rgmii-id or rgmii-tx/rx phy mode set.
1231 * The parse logic set a delay different than 0 only when one
1232 * of the 3 different way is used. In all other case delay is
1233 * not enabled. With ID or TX/RXID delay is enabled and set
1234 * to the default and recommended value.
1236 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1237 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1239 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1240 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1243 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1244 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1246 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1247 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1250 /* Set RGMII delay based on the selected values */
1251 ret = qca8k_rmw(priv, reg,
1252 QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1253 QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1254 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1255 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1258 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1259 cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1262 static struct phylink_pcs *
1263 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
1264 phy_interface_t interface)
1266 struct qca8k_priv *priv = ds->priv;
1267 struct phylink_pcs *pcs = NULL;
1269 switch (interface) {
1270 case PHY_INTERFACE_MODE_SGMII:
1271 case PHY_INTERFACE_MODE_1000BASEX:
1274 pcs = &priv->pcs_port_0.pcs;
1278 pcs = &priv->pcs_port_6.pcs;
1291 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1292 const struct phylink_link_state *state)
1294 struct qca8k_priv *priv = ds->priv;
1299 case 0: /* 1st CPU port */
1300 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1301 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1302 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1303 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1304 state->interface != PHY_INTERFACE_MODE_SGMII)
1307 reg = QCA8K_REG_PORT0_PAD_CTRL;
1308 cpu_port_index = QCA8K_CPU_PORT0;
1315 /* Internal PHY, nothing to do */
1317 case 6: /* 2nd CPU port / external PHY */
1318 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1319 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1320 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1321 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1322 state->interface != PHY_INTERFACE_MODE_SGMII &&
1323 state->interface != PHY_INTERFACE_MODE_1000BASEX)
1326 reg = QCA8K_REG_PORT6_PAD_CTRL;
1327 cpu_port_index = QCA8K_CPU_PORT6;
1330 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1334 if (port != 6 && phylink_autoneg_inband(mode)) {
1335 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1340 switch (state->interface) {
1341 case PHY_INTERFACE_MODE_RGMII:
1342 case PHY_INTERFACE_MODE_RGMII_ID:
1343 case PHY_INTERFACE_MODE_RGMII_TXID:
1344 case PHY_INTERFACE_MODE_RGMII_RXID:
1345 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1347 /* Configure rgmii delay */
1348 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1350 /* QCA8337 requires to set rgmii rx delay for all ports.
1351 * This is enabled through PORT5_PAD_CTRL for all ports,
1352 * rather than individual port registers.
1354 if (priv->switch_id == QCA8K_ID_QCA8337)
1355 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1356 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1358 case PHY_INTERFACE_MODE_SGMII:
1359 case PHY_INTERFACE_MODE_1000BASEX:
1360 /* Enable SGMII on the port */
1361 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1364 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1365 phy_modes(state->interface), port);
1370 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port,
1371 struct phylink_config *config)
1374 case 0: /* 1st CPU port */
1375 phy_interface_set_rgmii(config->supported_interfaces);
1376 __set_bit(PHY_INTERFACE_MODE_SGMII,
1377 config->supported_interfaces);
1386 __set_bit(PHY_INTERFACE_MODE_GMII,
1387 config->supported_interfaces);
1388 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1389 config->supported_interfaces);
1392 case 6: /* 2nd CPU port / external PHY */
1393 phy_interface_set_rgmii(config->supported_interfaces);
1394 __set_bit(PHY_INTERFACE_MODE_SGMII,
1395 config->supported_interfaces);
1396 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1397 config->supported_interfaces);
1401 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1402 MAC_10 | MAC_100 | MAC_1000FD;
1406 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1407 phy_interface_t interface)
1409 struct qca8k_priv *priv = ds->priv;
1411 qca8k_port_set_status(priv, port, 0);
1415 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1416 phy_interface_t interface, struct phy_device *phydev,
1417 int speed, int duplex, bool tx_pause, bool rx_pause)
1419 struct qca8k_priv *priv = ds->priv;
1422 if (phylink_autoneg_inband(mode)) {
1423 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1427 reg = QCA8K_PORT_STATUS_SPEED_10;
1430 reg = QCA8K_PORT_STATUS_SPEED_100;
1433 reg = QCA8K_PORT_STATUS_SPEED_1000;
1436 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1440 if (duplex == DUPLEX_FULL)
1441 reg |= QCA8K_PORT_STATUS_DUPLEX;
1443 if (rx_pause || dsa_is_cpu_port(ds, port))
1444 reg |= QCA8K_PORT_STATUS_RXFLOW;
1446 if (tx_pause || dsa_is_cpu_port(ds, port))
1447 reg |= QCA8K_PORT_STATUS_TXFLOW;
1450 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1452 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1455 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
1457 return container_of(pcs, struct qca8k_pcs, pcs);
1460 static void qca8k_pcs_get_state(struct phylink_pcs *pcs,
1461 struct phylink_link_state *state)
1463 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1464 int port = pcs_to_qca8k_pcs(pcs)->port;
1468 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
1470 state->link = false;
1474 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1475 state->an_complete = state->link;
1476 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1479 switch (reg & QCA8K_PORT_STATUS_SPEED) {
1480 case QCA8K_PORT_STATUS_SPEED_10:
1481 state->speed = SPEED_10;
1483 case QCA8K_PORT_STATUS_SPEED_100:
1484 state->speed = SPEED_100;
1486 case QCA8K_PORT_STATUS_SPEED_1000:
1487 state->speed = SPEED_1000;
1490 state->speed = SPEED_UNKNOWN;
1494 if (reg & QCA8K_PORT_STATUS_RXFLOW)
1495 state->pause |= MLO_PAUSE_RX;
1496 if (reg & QCA8K_PORT_STATUS_TXFLOW)
1497 state->pause |= MLO_PAUSE_TX;
1500 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
1501 phy_interface_t interface,
1502 const unsigned long *advertising,
1503 bool permit_pause_to_mac)
1505 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1506 int cpu_port_index, ret, port;
1509 port = pcs_to_qca8k_pcs(pcs)->port;
1512 reg = QCA8K_REG_PORT0_PAD_CTRL;
1513 cpu_port_index = QCA8K_CPU_PORT0;
1517 reg = QCA8K_REG_PORT6_PAD_CTRL;
1518 cpu_port_index = QCA8K_CPU_PORT6;
1526 /* Enable/disable SerDes auto-negotiation as necessary */
1527 val = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ?
1528 0 : QCA8K_PWS_SERDES_AEN_DIS;
1530 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8K_PWS_SERDES_AEN_DIS, val);
1534 /* Configure the SGMII parameters */
1535 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1539 val |= QCA8K_SGMII_EN_SD;
1541 if (priv->ports_config.sgmii_enable_pll)
1542 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1545 if (dsa_is_cpu_port(priv->ds, port)) {
1546 /* CPU port, we're talking to the CPU MAC, be a PHY */
1547 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1548 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1549 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1550 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1551 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1552 } else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1553 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1554 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1557 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1559 /* From original code is reported port instability as SGMII also
1560 * require delay set. Apply advised values here or take them from DT.
1562 if (interface == PHY_INTERFACE_MODE_SGMII)
1563 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1564 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1565 * falling edge is set writing in the PORT0 PAD reg
1567 if (priv->switch_id == QCA8K_ID_QCA8327 ||
1568 priv->switch_id == QCA8K_ID_QCA8337)
1569 reg = QCA8K_REG_PORT0_PAD_CTRL;
1573 /* SGMII Clock phase configuration */
1574 if (priv->ports_config.sgmii_rx_clk_falling_edge)
1575 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1577 if (priv->ports_config.sgmii_tx_clk_falling_edge)
1578 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1581 ret = qca8k_rmw(priv, reg,
1582 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1583 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1589 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs)
1593 static const struct phylink_pcs_ops qca8k_pcs_ops = {
1594 .pcs_get_state = qca8k_pcs_get_state,
1595 .pcs_config = qca8k_pcs_config,
1596 .pcs_an_restart = qca8k_pcs_an_restart,
1599 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs,
1602 qpcs->pcs.ops = &qca8k_pcs_ops;
1603 qpcs->pcs.neg_mode = true;
1605 /* We don't have interrupts for link changes, so we need to poll */
1606 qpcs->pcs.poll = true;
1611 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
1613 struct qca8k_mib_eth_data *mib_eth_data;
1614 struct qca8k_priv *priv = ds->priv;
1615 const struct qca8k_mib_desc *mib;
1616 struct mib_ethhdr *mib_ethhdr;
1621 mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
1622 mib_eth_data = &priv->mib_eth_data;
1624 /* The switch autocast every port. Ignore other packet and
1625 * parse only the requested one.
1627 port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
1628 if (port != mib_eth_data->req_port)
1631 data2 = (__le32 *)skb->data;
1633 for (i = 0; i < priv->info->mib_count; i++) {
1634 mib = &ar8327_mib[i];
1636 /* First 3 mib are present in the skb head */
1638 mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i);
1642 /* Some mib are 64 bit wide */
1644 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2);
1646 mib_eth_data->data[i] = get_unaligned_le32(data2);
1652 /* Complete on receiving all the mib packet */
1653 if (refcount_dec_and_test(&mib_eth_data->port_parsed))
1654 complete(&mib_eth_data->rw_done);
1658 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
1660 struct dsa_port *dp = dsa_to_port(ds, port);
1661 struct qca8k_mib_eth_data *mib_eth_data;
1662 struct qca8k_priv *priv = ds->priv;
1665 mib_eth_data = &priv->mib_eth_data;
1667 mutex_lock(&mib_eth_data->mutex);
1669 reinit_completion(&mib_eth_data->rw_done);
1671 mib_eth_data->req_port = dp->index;
1672 mib_eth_data->data = data;
1673 refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
1675 mutex_lock(&priv->reg_mutex);
1677 /* Send mib autocast request */
1678 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
1679 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
1680 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
1683 mutex_unlock(&priv->reg_mutex);
1688 ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
1691 mutex_unlock(&mib_eth_data->mutex);
1696 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1698 struct qca8k_priv *priv = ds->priv;
1700 /* Communicate to the phy internal driver the switch revision.
1701 * Based on the switch revision different values needs to be
1702 * set to the dbg and mmd reg on the phy.
1703 * The first 2 bit are used to communicate the switch revision
1704 * to the phy driver.
1706 if (port > 0 && port < 6)
1707 return priv->switch_revision;
1712 static enum dsa_tag_protocol
1713 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1714 enum dsa_tag_protocol mp)
1716 return DSA_TAG_PROTO_QCA;
1720 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
1723 struct dsa_port *dp = master->dsa_ptr;
1724 struct qca8k_priv *priv = ds->priv;
1726 /* Ethernet MIB/MDIO is only supported for CPU port 0 */
1730 mutex_lock(&priv->mgmt_eth_data.mutex);
1731 mutex_lock(&priv->mib_eth_data.mutex);
1733 priv->mgmt_master = operational ? (struct net_device *)master : NULL;
1735 mutex_unlock(&priv->mib_eth_data.mutex);
1736 mutex_unlock(&priv->mgmt_eth_data.mutex);
1739 static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
1740 enum dsa_tag_protocol proto)
1742 struct qca_tagger_data *tagger_data;
1745 case DSA_TAG_PROTO_QCA:
1746 tagger_data = ds->tagger_data;
1748 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
1749 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
1759 static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port)
1764 /* The 2 CPU port and port 5 requires some different
1765 * priority than any other ports.
1770 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1771 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1772 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1773 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1774 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1775 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1776 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1779 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1780 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1781 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1782 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1783 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1785 regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask);
1787 mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1788 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1789 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1790 QCA8K_PORT_HOL_CTRL1_WRED_EN;
1791 regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port),
1792 QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1793 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1794 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1795 QCA8K_PORT_HOL_CTRL1_WRED_EN,
1800 qca8k_setup(struct dsa_switch *ds)
1802 struct qca8k_priv *priv = ds->priv;
1803 struct dsa_port *dp;
1807 cpu_port = qca8k_find_cpu_port(ds);
1809 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1813 /* Parse CPU port config to be later used in phy_link mac_config */
1814 ret = qca8k_parse_port_config(priv);
1818 ret = qca8k_setup_mdio_bus(priv);
1822 ret = qca8k_setup_of_pws_reg(priv);
1826 ret = qca8k_setup_mac_pwr_sel(priv);
1830 ret = qca8k_setup_led_ctrl(priv);
1834 qca8k_setup_pcs(priv, &priv->pcs_port_0, 0);
1835 qca8k_setup_pcs(priv, &priv->pcs_port_6, 6);
1837 /* Make sure MAC06 is disabled */
1838 ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1839 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1841 dev_err(priv->dev, "failed disabling MAC06 exchange");
1845 /* Enable CPU Port */
1846 ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1847 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1849 dev_err(priv->dev, "failed enabling CPU port");
1853 /* Enable MIB counters */
1854 ret = qca8k_mib_init(priv);
1856 dev_warn(priv->dev, "mib init failed");
1858 /* Initial setup of all ports */
1859 dsa_switch_for_each_port(dp, ds) {
1860 /* Disable forwarding by default on all ports */
1861 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(dp->index),
1862 QCA8K_PORT_LOOKUP_MEMBER, 0);
1867 /* Disable MAC by default on all user ports */
1868 dsa_switch_for_each_user_port(dp, ds)
1869 qca8k_port_set_status(priv, dp->index, 0);
1871 /* Enable QCA header mode on all cpu ports */
1872 dsa_switch_for_each_cpu_port(dp, ds) {
1873 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(dp->index),
1874 FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1875 FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1877 dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index);
1882 /* Forward all unknown frames to CPU port for Linux processing
1883 * Notice that in multi-cpu config only one port should be set
1884 * for igmp, unknown, multicast and broadcast packet
1886 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1887 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1888 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1889 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1890 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1894 /* CPU port gets connected to all user ports of the switch */
1895 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),
1896 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1900 /* Setup connection between CPU port & user ports
1901 * Individual user ports get connected to CPU port only
1903 dsa_switch_for_each_user_port(dp, ds) {
1904 u8 port = dp->index;
1906 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1907 QCA8K_PORT_LOOKUP_MEMBER,
1912 ret = regmap_clear_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
1913 QCA8K_PORT_LOOKUP_LEARN);
1917 /* For port based vlans to work we need to set the
1918 * default egress vid
1920 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1921 QCA8K_EGREES_VLAN_PORT_MASK(port),
1922 QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
1926 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1927 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1928 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1933 /* The port 5 of the qca8337 have some problem in flood condition. The
1934 * original legacy driver had some specific buffer and priority settings
1935 * for the different port suggested by the QCA switch team. Add this
1936 * missing settings to improve switch stability under load condition.
1937 * This problem is limited to qca8337 and other qca8k switch are not affected.
1939 if (priv->switch_id == QCA8K_ID_QCA8337)
1940 dsa_switch_for_each_available_port(dp, ds)
1941 qca8k_setup_hol_fixup(priv, dp->index);
1943 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1944 if (priv->switch_id == QCA8K_ID_QCA8327) {
1945 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1946 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1947 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1948 QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1949 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1953 /* Setup our port MTUs to match power on defaults */
1954 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1956 dev_warn(priv->dev, "failed setting MTU settings");
1958 /* Flush the FDB table */
1959 qca8k_fdb_flush(priv);
1961 /* Set min a max ageing value supported */
1962 ds->ageing_time_min = 7000;
1963 ds->ageing_time_max = 458745000;
1965 /* Set max number of LAGs supported */
1966 ds->num_lag_ids = QCA8K_NUM_LAGS;
1971 static const struct dsa_switch_ops qca8k_switch_ops = {
1972 .get_tag_protocol = qca8k_get_tag_protocol,
1973 .setup = qca8k_setup,
1974 .get_strings = qca8k_get_strings,
1975 .get_ethtool_stats = qca8k_get_ethtool_stats,
1976 .get_sset_count = qca8k_get_sset_count,
1977 .set_ageing_time = qca8k_set_ageing_time,
1978 .get_mac_eee = qca8k_get_mac_eee,
1979 .set_mac_eee = qca8k_set_mac_eee,
1980 .port_enable = qca8k_port_enable,
1981 .port_disable = qca8k_port_disable,
1982 .port_change_mtu = qca8k_port_change_mtu,
1983 .port_max_mtu = qca8k_port_max_mtu,
1984 .port_stp_state_set = qca8k_port_stp_state_set,
1985 .port_pre_bridge_flags = qca8k_port_pre_bridge_flags,
1986 .port_bridge_flags = qca8k_port_bridge_flags,
1987 .port_bridge_join = qca8k_port_bridge_join,
1988 .port_bridge_leave = qca8k_port_bridge_leave,
1989 .port_fast_age = qca8k_port_fast_age,
1990 .port_fdb_add = qca8k_port_fdb_add,
1991 .port_fdb_del = qca8k_port_fdb_del,
1992 .port_fdb_dump = qca8k_port_fdb_dump,
1993 .port_mdb_add = qca8k_port_mdb_add,
1994 .port_mdb_del = qca8k_port_mdb_del,
1995 .port_mirror_add = qca8k_port_mirror_add,
1996 .port_mirror_del = qca8k_port_mirror_del,
1997 .port_vlan_filtering = qca8k_port_vlan_filtering,
1998 .port_vlan_add = qca8k_port_vlan_add,
1999 .port_vlan_del = qca8k_port_vlan_del,
2000 .phylink_get_caps = qca8k_phylink_get_caps,
2001 .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs,
2002 .phylink_mac_config = qca8k_phylink_mac_config,
2003 .phylink_mac_link_down = qca8k_phylink_mac_link_down,
2004 .phylink_mac_link_up = qca8k_phylink_mac_link_up,
2005 .get_phy_flags = qca8k_get_phy_flags,
2006 .port_lag_join = qca8k_port_lag_join,
2007 .port_lag_leave = qca8k_port_lag_leave,
2008 .master_state_change = qca8k_master_change,
2009 .connect_tag_protocol = qca8k_connect_tag_protocol,
2013 qca8k_sw_probe(struct mdio_device *mdiodev)
2015 struct qca8k_priv *priv;
2018 /* allocate the private data struct so that we can probe the switches
2021 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2025 priv->bus = mdiodev->bus;
2026 priv->dev = &mdiodev->dev;
2027 priv->info = of_device_get_match_data(priv->dev);
2029 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2031 if (IS_ERR(priv->reset_gpio))
2032 return PTR_ERR(priv->reset_gpio);
2034 if (priv->reset_gpio) {
2035 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2036 /* The active low duration must be greater than 10 ms
2037 * and checkpatch.pl wants 20 ms.
2040 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2043 /* Start by setting up the register mapping */
2044 priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
2045 &qca8k_regmap_config);
2046 if (IS_ERR(priv->regmap)) {
2047 dev_err(priv->dev, "regmap initialization failed");
2048 return PTR_ERR(priv->regmap);
2051 priv->mdio_cache.page = 0xffff;
2053 /* Check the detected switch id */
2054 ret = qca8k_read_switch_id(priv);
2058 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2062 mutex_init(&priv->mgmt_eth_data.mutex);
2063 init_completion(&priv->mgmt_eth_data.rw_done);
2065 mutex_init(&priv->mib_eth_data.mutex);
2066 init_completion(&priv->mib_eth_data.rw_done);
2068 priv->ds->dev = &mdiodev->dev;
2069 priv->ds->num_ports = QCA8K_NUM_PORTS;
2070 priv->ds->priv = priv;
2071 priv->ds->ops = &qca8k_switch_ops;
2072 mutex_init(&priv->reg_mutex);
2073 dev_set_drvdata(&mdiodev->dev, priv);
2075 return dsa_register_switch(priv->ds);
2079 qca8k_sw_remove(struct mdio_device *mdiodev)
2081 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2087 for (i = 0; i < QCA8K_NUM_PORTS; i++)
2088 qca8k_port_set_status(priv, i, 0);
2090 dsa_unregister_switch(priv->ds);
2093 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2095 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2100 dsa_switch_shutdown(priv->ds);
2102 dev_set_drvdata(&mdiodev->dev, NULL);
2105 #ifdef CONFIG_PM_SLEEP
2107 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2111 for (port = 0; port < QCA8K_NUM_PORTS; port++) {
2112 /* Do not enable on resume if the port was
2115 if (!(priv->port_enabled_map & BIT(port)))
2118 qca8k_port_set_status(priv, port, enable);
2122 static int qca8k_suspend(struct device *dev)
2124 struct qca8k_priv *priv = dev_get_drvdata(dev);
2126 qca8k_set_pm(priv, 0);
2128 return dsa_switch_suspend(priv->ds);
2131 static int qca8k_resume(struct device *dev)
2133 struct qca8k_priv *priv = dev_get_drvdata(dev);
2135 qca8k_set_pm(priv, 1);
2137 return dsa_switch_resume(priv->ds);
2139 #endif /* CONFIG_PM_SLEEP */
2141 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2142 qca8k_suspend, qca8k_resume);
2144 static const struct qca8k_info_ops qca8xxx_ops = {
2145 .autocast_mib = qca8k_get_ethtool_stats_eth,
2148 static const struct qca8k_match_data qca8327 = {
2149 .id = QCA8K_ID_QCA8327,
2150 .reduced_package = true,
2151 .mib_count = QCA8K_QCA832X_MIB_COUNT,
2152 .ops = &qca8xxx_ops,
2155 static const struct qca8k_match_data qca8328 = {
2156 .id = QCA8K_ID_QCA8327,
2157 .mib_count = QCA8K_QCA832X_MIB_COUNT,
2158 .ops = &qca8xxx_ops,
2161 static const struct qca8k_match_data qca833x = {
2162 .id = QCA8K_ID_QCA8337,
2163 .mib_count = QCA8K_QCA833X_MIB_COUNT,
2164 .ops = &qca8xxx_ops,
2167 static const struct of_device_id qca8k_of_match[] = {
2168 { .compatible = "qca,qca8327", .data = &qca8327 },
2169 { .compatible = "qca,qca8328", .data = &qca8328 },
2170 { .compatible = "qca,qca8334", .data = &qca833x },
2171 { .compatible = "qca,qca8337", .data = &qca833x },
2175 static struct mdio_driver qca8kmdio_driver = {
2176 .probe = qca8k_sw_probe,
2177 .remove = qca8k_sw_remove,
2178 .shutdown = qca8k_sw_shutdown,
2181 .of_match_table = qca8k_of_match,
2182 .pm = &qca8k_pm_ops,
2186 mdio_module_driver(qca8kmdio_driver);
2188 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
2189 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2190 MODULE_LICENSE("GPL v2");
2191 MODULE_ALIAS("platform:qca8k");