drivers/net/dsa/qca/qca8k-8xxx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/bitfield.h>
  13 #include <linux/regmap.h>
  14 #include <net/dsa.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/mdio.h>
  19 #include <linux/phylink.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/dsa/tag_qca.h>
  23
  24 #include "qca8k.h"
  25 #include "qca8k_leds.h"
  26
  27 static void
  28 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  29 {
  30         regaddr >>= 1;
  31         *r1 = regaddr & 0x1e;
  32
  33         regaddr >>= 5;
  34         *r2 = regaddr & 0x7;
  35
  36         regaddr >>= 3;
  37         *page = regaddr & 0x3ff;
  38 }
  39
  40 static int
  41 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  42 {
  43         int ret;
  44         u16 lo;
  45
  46         lo = val & 0xffff;
  47         ret = bus->write(bus, phy_id, regnum, lo);
  48         if (ret < 0)
  49                 dev_err_ratelimited(&bus->dev,
  50                                     "failed to write qca8k 32bit lo register\n");
  51
  52         return ret;
  53 }
  54
  55 static int
  56 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  57 {
  58         int ret;
  59         u16 hi;
  60
  61         hi = (u16)(val >> 16);
  62         ret = bus->write(bus, phy_id, regnum, hi);
  63         if (ret < 0)
  64                 dev_err_ratelimited(&bus->dev,
  65                                     "failed to write qca8k 32bit hi register\n");
  66
  67         return ret;
  68 }
  69
  70 static int
  71 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  72 {
  73         int ret;
  74
  75         ret = bus->read(bus, phy_id, regnum);
  76         if (ret < 0)
  77                 goto err;
  78
  79         *val = ret & 0xffff;
  80         return 0;
  81
  82 err:
  83         dev_err_ratelimited(&bus->dev,
  84                             "failed to read qca8k 32bit lo register\n");
  85         *val = 0;
  86
  87         return ret;
  88 }
  89
  90 static int
  91 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  92 {
  93         int ret;
  94
  95         ret = bus->read(bus, phy_id, regnum);
  96         if (ret < 0)
  97                 goto err;
  98
  99         *val = ret << 16;
 100         return 0;
 101
 102 err:
 103         dev_err_ratelimited(&bus->dev,
 104                             "failed to read qca8k 32bit hi register\n");
 105         *val = 0;
 106
 107         return ret;
 108 }
 109
 110 static int
 111 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 112 {
 113         u32 hi, lo;
 114         int ret;
 115
 116         *val = 0;
 117
 118         ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
 119         if (ret < 0)
 120                 goto err;
 121
 122         ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
 123         if (ret < 0)
 124                 goto err;
 125
 126         *val = lo | hi;
 127
 128 err:
 129         return ret;
 130 }
 131
 132 static void
 133 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 134 {
 135         if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
 136                 return;
 137
 138         qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
 139 }
 140
 141 static int
 142 qca8k_set_page(struct qca8k_priv *priv, u16 page)
 143 {
 144         u16 *cached_page = &priv->mdio_cache.page;
 145         struct mii_bus *bus = priv->bus;
 146         int ret;
 147
 148         if (page == *cached_page)
 149                 return 0;
 150
 151         ret = bus->write(bus, 0x18, 0, page);
 152         if (ret < 0) {
 153                 dev_err_ratelimited(&bus->dev,
 154                                     "failed to set qca8k page\n");
 155                 return ret;
 156         }
 157
 158         *cached_page = page;
 159         usleep_range(1000, 2000);
 160         return 0;
 161 }
 162
 163 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 164 {
 165         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 166         struct qca8k_priv *priv = ds->priv;
 167         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 168         u32 command;
 169         u8 len, cmd;
 170         int i;
 171
 172         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
 173         mgmt_eth_data = &priv->mgmt_eth_data;
 174
 175         command = get_unaligned_le32(&mgmt_ethhdr->command);
 176         cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
 177
 178         len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
 179         /* Special case for len of 15 as this is the max value for len and needs to
 180          * be increased before converting it from word to dword.
 181          */
 182         if (len == 15)
 183                 len++;
 184
 185         /* We can ignore odd value, we always round up them in the alloc function. */
 186         len *= sizeof(u16);
 187
 188         /* Make sure the seq match the requested packet */
 189         if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
 190                 mgmt_eth_data->ack = true;
 191
 192         if (cmd == MDIO_READ) {
 193                 u32 *val = mgmt_eth_data->data;
 194
 195                 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data);
 196
 197                 /* Get the rest of the 12 byte of data.
 198                  * The read/write function will extract the requested data.
 199                  */
 200                 if (len > QCA_HDR_MGMT_DATA1_LEN) {
 201                         __le32 *data2 = (__le32 *)skb->data;
 202                         int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 203                                              len - QCA_HDR_MGMT_DATA1_LEN);
 204
 205                         val++;
 206
 207                         for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 208                                 *val = get_unaligned_le32(data2);
 209                                 val++;
 210                                 data2++;
 211                         }
 212                 }
 213         }
 214
 215         complete(&mgmt_eth_data->rw_done);
 216 }
 217
 218 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
 219                                                int priority, unsigned int len)
 220 {
 221         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 222         unsigned int real_len;
 223         struct sk_buff *skb;
 224         __le32 *data2;
 225         u32 command;
 226         u16 hdr;
 227         int i;
 228
 229         skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
 230         if (!skb)
 231                 return NULL;
 232
 233         /* Hdr mgmt length value is in step of word size.
 234          * As an example to process 4 byte of data the correct length to set is 2.
 235          * To process 8 byte 4, 12 byte 6, 16 byte 8...
 236          *
 237          * Odd values will always return the next size on the ack packet.
 238          * (length of 3 (6 byte) will always return 8 bytes of data)
 239          *
 240          * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
 241          * of data.
 242          *
 243          * To correctly calculate the length we devide the requested len by word and
 244          * round up.
 245          * On the ack function we can skip the odd check as we already handle the
 246          * case here.
 247          */
 248         real_len = DIV_ROUND_UP(len, sizeof(u16));
 249
 250         /* We check if the result len is odd and we round up another time to
 251          * the next size. (length of 3 will be increased to 4 as switch will always
 252          * return 8 bytes)
 253          */
 254         if (real_len % sizeof(u16) != 0)
 255                 real_len++;
 256
 257         /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
 258         if (real_len == 16)
 259                 real_len--;
 260
 261         skb_reset_mac_header(skb);
 262         skb_set_network_header(skb, skb->len);
 263
 264         mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
 265
 266         hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
 267         hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
 268         hdr |= QCA_HDR_XMIT_FROM_CPU;
 269         hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
 270         hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
 271
 272         command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
 273         command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
 274         command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
 275         command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
 276                                            QCA_HDR_MGMT_CHECK_CODE_VAL);
 277
 278         put_unaligned_le32(command, &mgmt_ethhdr->command);
 279
 280         if (cmd == MDIO_WRITE)
 281                 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data);
 282
 283         mgmt_ethhdr->hdr = htons(hdr);
 284
 285         data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
 286         if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) {
 287                 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 288                                      len - QCA_HDR_MGMT_DATA1_LEN);
 289
 290                 val++;
 291
 292                 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 293                         put_unaligned_le32(*val, data2);
 294                         data2++;
 295                         val++;
 296                 }
 297         }
 298
 299         return skb;
 300 }
 301
 302 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
 303 {
 304         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 305         u32 seq;
 306
 307         seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
 308         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
 309         put_unaligned_le32(seq, &mgmt_ethhdr->seq);
 310 }
 311
 312 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 313 {
 314         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 315         struct sk_buff *skb;
 316         bool ack;
 317         int ret;
 318
 319         skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
 320                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 321         if (!skb)
 322                 return -ENOMEM;
 323
 324         mutex_lock(&mgmt_eth_data->mutex);
 325
 326         /* Check mgmt_master if is operational */
 327         if (!priv->mgmt_master) {
 328                 kfree_skb(skb);
 329                 mutex_unlock(&mgmt_eth_data->mutex);
 330                 return -EINVAL;
 331         }
 332
 333         skb->dev = priv->mgmt_master;
 334
 335         reinit_completion(&mgmt_eth_data->rw_done);
 336
 337         /* Increment seq_num and set it in the mdio pkt */
 338         mgmt_eth_data->seq++;
 339         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 340         mgmt_eth_data->ack = false;
 341
 342         dev_queue_xmit(skb);
 343
 344         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 345                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 346
 347         *val = mgmt_eth_data->data[0];
 348         if (len > QCA_HDR_MGMT_DATA1_LEN)
 349                 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
 350
 351         ack = mgmt_eth_data->ack;
 352
 353         mutex_unlock(&mgmt_eth_data->mutex);
 354
 355         if (ret <= 0)
 356                 return -ETIMEDOUT;
 357
 358         if (!ack)
 359                 return -EINVAL;
 360
 361         return 0;
 362 }
 363
 364 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 365 {
 366         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 367         struct sk_buff *skb;
 368         bool ack;
 369         int ret;
 370
 371         skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
 372                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 373         if (!skb)
 374                 return -ENOMEM;
 375
 376         mutex_lock(&mgmt_eth_data->mutex);
 377
 378         /* Check mgmt_master if is operational */
 379         if (!priv->mgmt_master) {
 380                 kfree_skb(skb);
 381                 mutex_unlock(&mgmt_eth_data->mutex);
 382                 return -EINVAL;
 383         }
 384
 385         skb->dev = priv->mgmt_master;
 386
 387         reinit_completion(&mgmt_eth_data->rw_done);
 388
 389         /* Increment seq_num and set it in the mdio pkt */
 390         mgmt_eth_data->seq++;
 391         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 392         mgmt_eth_data->ack = false;
 393
 394         dev_queue_xmit(skb);
 395
 396         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 397                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 398
 399         ack = mgmt_eth_data->ack;
 400
 401         mutex_unlock(&mgmt_eth_data->mutex);
 402
 403         if (ret <= 0)
 404                 return -ETIMEDOUT;
 405
 406         if (!ack)
 407                 return -EINVAL;
 408
 409         return 0;
 410 }
 411
 412 static int
 413 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 414 {
 415         u32 val = 0;
 416         int ret;
 417
 418         ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
 419         if (ret)
 420                 return ret;
 421
 422         val &= ~mask;
 423         val |= write_val;
 424
 425         return qca8k_write_eth(priv, reg, &val, sizeof(val));
 426 }
 427
 428 static int
 429 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)
 430 {
 431         struct mii_bus *bus = priv->bus;
 432         u16 r1, r2, page;
 433         int ret;
 434
 435         qca8k_split_addr(reg, &r1, &r2, &page);
 436
 437         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 438
 439         ret = qca8k_set_page(priv, page);
 440         if (ret < 0)
 441                 goto exit;
 442
 443         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 444
 445 exit:
 446         mutex_unlock(&bus->mdio_lock);
 447         return ret;
 448 }
 449
 450 static int
 451 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)
 452 {
 453         struct mii_bus *bus = priv->bus;
 454         u16 r1, r2, page;
 455         int ret;
 456
 457         qca8k_split_addr(reg, &r1, &r2, &page);
 458
 459         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 460
 461         ret = qca8k_set_page(priv, page);
 462         if (ret < 0)
 463                 goto exit;
 464
 465         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 466
 467 exit:
 468         mutex_unlock(&bus->mdio_lock);
 469         return ret;
 470 }
 471
 472 static int
 473 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,
 474                              uint32_t mask, uint32_t write_val)
 475 {
 476         struct mii_bus *bus = priv->bus;
 477         u16 r1, r2, page;
 478         u32 val;
 479         int ret;
 480
 481         qca8k_split_addr(reg, &r1, &r2, &page);
 482
 483         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 484
 485         ret = qca8k_set_page(priv, page);
 486         if (ret < 0)
 487                 goto exit;
 488
 489         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 490         if (ret < 0)
 491                 goto exit;
 492
 493         val &= ~mask;
 494         val |= write_val;
 495         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 496
 497 exit:
 498         mutex_unlock(&bus->mdio_lock);
 499
 500         return ret;
 501 }
 502
 503 static int
 504 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,
 505                 void *val_buf, size_t val_len)
 506 {
 507         int i, count = val_len / sizeof(u32), ret;
 508         struct qca8k_priv *priv = ctx;
 509         u32 reg = *(u16 *)reg_buf;
 510
 511         if (priv->mgmt_master &&
 512             !qca8k_read_eth(priv, reg, val_buf, val_len))
 513                 return 0;
 514
 515         /* loop count times and increment reg of 4 */
 516         for (i = 0; i < count; i++, reg += sizeof(u32)) {
 517                 ret = qca8k_read_mii(priv, reg, val_buf + i);
 518                 if (ret < 0)
 519                         return ret;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int
 526 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,
 527                         const void *val_buf, size_t val_len)
 528 {
 529         int i, count = val_len / sizeof(u32), ret;
 530         struct qca8k_priv *priv = ctx;
 531         u32 reg = *(u16 *)reg_buf;
 532         u32 *val = (u32 *)val_buf;
 533
 534         if (priv->mgmt_master &&
 535             !qca8k_write_eth(priv, reg, val, val_len))
 536                 return 0;
 537
 538         /* loop count times, increment reg of 4 and increment val ptr to
 539          * the next value
 540          */
 541         for (i = 0; i < count; i++, reg += sizeof(u32), val++) {
 542                 ret = qca8k_write_mii(priv, reg, *val);
 543                 if (ret < 0)
 544                         return ret;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int
 551 qca8k_bulk_write(void *ctx, const void *data, size_t bytes)
 552 {
 553         return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),
 554                                        bytes - sizeof(u16));
 555 }
 556
 557 static int
 558 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
 559 {
 560         struct qca8k_priv *priv = ctx;
 561
 562         if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
 563                 return 0;
 564
 565         return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);
 566 }
 567
 568 static struct regmap_config qca8k_regmap_config = {
 569         .reg_bits = 16,
 570         .val_bits = 32,
 571         .reg_stride = 4,
 572         .max_register = 0x16ac, /* end MIB - Port6 range */
 573         .read = qca8k_bulk_read,
 574         .write = qca8k_bulk_write,
 575         .reg_update_bits = qca8k_regmap_update_bits,
 576         .rd_table = &qca8k_readable_table,
 577         .disable_locking = true, /* Locking is handled by qca8k read/write */
 578         .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
 579         .max_raw_read = 32, /* mgmt eth can read up to 8 registers at time */
 580         /* ATU regs suffer from a bug where some data are not correctly
 581          * written. Disable bulk write to correctly write ATU entry.
 582          */
 583         .use_single_write = true,
 584 };
 585
 586 static int
 587 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
 588                         struct sk_buff *read_skb, u32 *val)
 589 {
 590         struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
 591         bool ack;
 592         int ret;
 593
 594         if (!skb)
 595                 return -ENOMEM;
 596
 597         reinit_completion(&mgmt_eth_data->rw_done);
 598
 599         /* Increment seq_num and set it in the copy pkt */
 600         mgmt_eth_data->seq++;
 601         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 602         mgmt_eth_data->ack = false;
 603
 604         dev_queue_xmit(skb);
 605
 606         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 607                                           QCA8K_ETHERNET_TIMEOUT);
 608
 609         ack = mgmt_eth_data->ack;
 610
 611         if (ret <= 0)
 612                 return -ETIMEDOUT;
 613
 614         if (!ack)
 615                 return -EINVAL;
 616
 617         *val = mgmt_eth_data->data[0];
 618
 619         return 0;
 620 }
 621
 622 static int
 623 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
 624                       int regnum, u16 data)
 625 {
 626         struct sk_buff *write_skb, *clear_skb, *read_skb;
 627         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 628         u32 write_val, clear_val = 0, val;
 629         struct net_device *mgmt_master;
 630         int ret, ret1;
 631         bool ack;
 632
 633         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 634                 return -EINVAL;
 635
 636         mgmt_eth_data = &priv->mgmt_eth_data;
 637
 638         write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 639                     QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 640                     QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 641
 642         if (read) {
 643                 write_val |= QCA8K_MDIO_MASTER_READ;
 644         } else {
 645                 write_val |= QCA8K_MDIO_MASTER_WRITE;
 646                 write_val |= QCA8K_MDIO_MASTER_DATA(data);
 647         }
 648
 649         /* Prealloc all the needed skb before the lock */
 650         write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
 651                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
 652         if (!write_skb)
 653                 return -ENOMEM;
 654
 655         clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 656                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 657         if (!clear_skb) {
 658                 ret = -ENOMEM;
 659                 goto err_clear_skb;
 660         }
 661
 662         read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 663                                            QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 664         if (!read_skb) {
 665                 ret = -ENOMEM;
 666                 goto err_read_skb;
 667         }
 668
 669         /* It seems that accessing the switch's internal PHYs via management
 670          * packets still uses the MDIO bus within the switch internally, and
 671          * these accesses can conflict with external MDIO accesses to other
 672          * devices on the MDIO bus.
 673          * We therefore need to lock the MDIO bus onto which the switch is
 674          * connected.
 675          */
 676         mutex_lock(&priv->bus->mdio_lock);
 677
 678         /* Actually start the request:
 679          * 1. Send mdio master packet
 680          * 2. Busy Wait for mdio master command
 681          * 3. Get the data if we are reading
 682          * 4. Reset the mdio master (even with error)
 683          */
 684         mutex_lock(&mgmt_eth_data->mutex);
 685
 686         /* Check if mgmt_master is operational */
 687         mgmt_master = priv->mgmt_master;
 688         if (!mgmt_master) {
 689                 mutex_unlock(&mgmt_eth_data->mutex);
 690                 mutex_unlock(&priv->bus->mdio_lock);
 691                 ret = -EINVAL;
 692                 goto err_mgmt_master;
 693         }
 694
 695         read_skb->dev = mgmt_master;
 696         clear_skb->dev = mgmt_master;
 697         write_skb->dev = mgmt_master;
 698
 699         reinit_completion(&mgmt_eth_data->rw_done);
 700
 701         /* Increment seq_num and set it in the write pkt */
 702         mgmt_eth_data->seq++;
 703         qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
 704         mgmt_eth_data->ack = false;
 705
 706         dev_queue_xmit(write_skb);
 707
 708         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 709                                           QCA8K_ETHERNET_TIMEOUT);
 710
 711         ack = mgmt_eth_data->ack;
 712
 713         if (ret <= 0) {
 714                 ret = -ETIMEDOUT;
 715                 kfree_skb(read_skb);
 716                 goto exit;
 717         }
 718
 719         if (!ack) {
 720                 ret = -EINVAL;
 721                 kfree_skb(read_skb);
 722                 goto exit;
 723         }
 724
 725         ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
 726                                 !(val & QCA8K_MDIO_MASTER_BUSY), 0,
 727                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 728                                 mgmt_eth_data, read_skb, &val);
 729
 730         if (ret < 0 && ret1 < 0) {
 731                 ret = ret1;
 732                 goto exit;
 733         }
 734
 735         if (read) {
 736                 reinit_completion(&mgmt_eth_data->rw_done);
 737
 738                 /* Increment seq_num and set it in the read pkt */
 739                 mgmt_eth_data->seq++;
 740                 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
 741                 mgmt_eth_data->ack = false;
 742
 743                 dev_queue_xmit(read_skb);
 744
 745                 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 746                                                   QCA8K_ETHERNET_TIMEOUT);
 747
 748                 ack = mgmt_eth_data->ack;
 749
 750                 if (ret <= 0) {
 751                         ret = -ETIMEDOUT;
 752                         goto exit;
 753                 }
 754
 755                 if (!ack) {
 756                         ret = -EINVAL;
 757                         goto exit;
 758                 }
 759
 760                 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
 761         } else {
 762                 kfree_skb(read_skb);
 763         }
 764 exit:
 765         reinit_completion(&mgmt_eth_data->rw_done);
 766
 767         /* Increment seq_num and set it in the clear pkt */
 768         mgmt_eth_data->seq++;
 769         qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
 770         mgmt_eth_data->ack = false;
 771
 772         dev_queue_xmit(clear_skb);
 773
 774         wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 775                                     QCA8K_ETHERNET_TIMEOUT);
 776
 777         mutex_unlock(&mgmt_eth_data->mutex);
 778         mutex_unlock(&priv->bus->mdio_lock);
 779
 780         return ret;
 781
 782         /* Error handling before lock */
 783 err_mgmt_master:
 784         kfree_skb(read_skb);
 785 err_read_skb:
 786         kfree_skb(clear_skb);
 787 err_clear_skb:
 788         kfree_skb(write_skb);
 789
 790         return ret;
 791 }
 792
 793 static int
 794 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 795 {
 796         u16 r1, r2, page;
 797         u32 val;
 798         int ret, ret1;
 799
 800         qca8k_split_addr(reg, &r1, &r2, &page);
 801
 802         ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
 803                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 804                                 bus, 0x10 | r2, r1 + 1, &val);
 805
 806         /* Check if qca8k_read has failed for a different reason
 807          * before returnting -ETIMEDOUT
 808          */
 809         if (ret < 0 && ret1 < 0)
 810                 return ret1;
 811
 812         return ret;
 813 }
 814
 815 static int
 816 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
 817 {
 818         struct mii_bus *bus = priv->bus;
 819         u16 r1, r2, page;
 820         u32 val;
 821         int ret;
 822
 823         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 824                 return -EINVAL;
 825
 826         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 827               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 828               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 829               QCA8K_MDIO_MASTER_DATA(data);
 830
 831         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 832
 833         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 834
 835         ret = qca8k_set_page(priv, page);
 836         if (ret)
 837                 goto exit;
 838
 839         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 840
 841         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 842                                    QCA8K_MDIO_MASTER_BUSY);
 843
 844 exit:
 845         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 846         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 847
 848         mutex_unlock(&bus->mdio_lock);
 849
 850         return ret;
 851 }
 852
 853 static int
 854 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 855 {
 856         struct mii_bus *bus = priv->bus;
 857         u16 r1, r2, page;
 858         u32 val;
 859         int ret;
 860
 861         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 862                 return -EINVAL;
 863
 864         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 865               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 866               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 867
 868         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 869
 870         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 871
 872         ret = qca8k_set_page(priv, page);
 873         if (ret)
 874                 goto exit;
 875
 876         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
 877
 878         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 879                                    QCA8K_MDIO_MASTER_BUSY);
 880         if (ret)
 881                 goto exit;
 882
 883         ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
 884
 885 exit:
 886         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 887         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 888
 889         mutex_unlock(&bus->mdio_lock);
 890
 891         if (ret >= 0)
 892                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 893
 894         return ret;
 895 }
 896
 897 static int
 898 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
 899 {
 900         struct qca8k_priv *priv = slave_bus->priv;
 901         int ret;
 902
 903         /* Use mdio Ethernet when available, fallback to legacy one on error */
 904         ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
 905         if (!ret)
 906                 return 0;
 907
 908         return qca8k_mdio_write(priv, phy, regnum, data);
 909 }
 910
 911 static int
 912 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
 913 {
 914         struct qca8k_priv *priv = slave_bus->priv;
 915         int ret;
 916
 917         /* Use mdio Ethernet when available, fallback to legacy one on error */
 918         ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
 919         if (ret >= 0)
 920                 return ret;
 921
 922         ret = qca8k_mdio_read(priv, phy, regnum);
 923
 924         if (ret < 0)
 925                 return 0xffff;
 926
 927         return ret;
 928 }
 929
 930 static int
 931 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
 932 {
 933         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 934
 935         return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
 936 }
 937
 938 static int
 939 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
 940 {
 941         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 942
 943         return qca8k_internal_mdio_read(slave_bus, port, regnum);
 944 }
 945
 946 static int
 947 qca8k_mdio_register(struct qca8k_priv *priv)
 948 {
 949         struct dsa_switch *ds = priv->ds;
 950         struct device_node *mdio;
 951         struct mii_bus *bus;
 952
 953         bus = devm_mdiobus_alloc(ds->dev);
 954         if (!bus)
 955                 return -ENOMEM;
 956
 957         bus->priv = (void *)priv;
 958         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
 959                  ds->dst->index, ds->index);
 960         bus->parent = ds->dev;
 961         bus->phy_mask = ~ds->phys_mii_mask;
 962         ds->slave_mii_bus = bus;
 963
 964         /* Check if the devicetree declare the port:phy mapping */
 965         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 966         if (of_device_is_available(mdio)) {
 967                 bus->name = "qca8k slave mii";
 968                 bus->read = qca8k_internal_mdio_read;
 969                 bus->write = qca8k_internal_mdio_write;
 970                 return devm_of_mdiobus_register(priv->dev, bus, mdio);
 971         }
 972
 973         /* If a mapping can't be found the legacy mapping is used,
 974          * using the qca8k_port_to_phy function
 975          */
 976         bus->name = "qca8k-legacy slave mii";
 977         bus->read = qca8k_legacy_mdio_read;
 978         bus->write = qca8k_legacy_mdio_write;
 979         return devm_mdiobus_register(priv->dev, bus);
 980 }
 981
 982 static int
 983 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 984 {
 985         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 986         struct device_node *ports, *port;
 987         phy_interface_t mode;
 988         int err;
 989
 990         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 991         if (!ports)
 992                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 993
 994         if (!ports)
 995                 return -EINVAL;
 996
 997         for_each_available_child_of_node(ports, port) {
 998                 err = of_property_read_u32(port, "reg", &reg);
 999                 if (err) {
1000                         of_node_put(port);
1001                         of_node_put(ports);
1002                         return err;
1003                 }
1004
1005                 if (!dsa_is_user_port(priv->ds, reg))
1006                         continue;
1007
1008                 of_get_phy_mode(port, &mode);
1009
1010                 if (of_property_read_bool(port, "phy-handle") &&
1011                     mode != PHY_INTERFACE_MODE_INTERNAL)
1012                         external_mdio_mask |= BIT(reg);
1013                 else
1014                         internal_mdio_mask |= BIT(reg);
1015         }
1016
1017         of_node_put(ports);
1018         if (!external_mdio_mask && !internal_mdio_mask) {
1019                 dev_err(priv->dev, "no PHYs are defined.\n");
1020                 return -EINVAL;
1021         }
1022
1023         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
1024          * the MDIO_MASTER register also _disconnects_ the external MDC
1025          * passthrough to the internal PHYs. It's not possible to use both
1026          * configurations at the same time!
1027          *
1028          * Because this came up during the review process:
1029          * If the external mdio-bus driver is capable magically disabling
1030          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
1031          * accessors for the time being, it would be possible to pull this
1032          * off.
1033          */
1034         if (!!external_mdio_mask && !!internal_mdio_mask) {
1035                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
1036                 return -EINVAL;
1037         }
1038
1039         if (external_mdio_mask) {
1040                 /* Make sure to disable the internal mdio bus in cases
1041                  * a dt-overlay and driver reload changed the configuration
1042                  */
1043
1044                 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
1045                                          QCA8K_MDIO_MASTER_EN);
1046         }
1047
1048         return qca8k_mdio_register(priv);
1049 }
1050
1051 static int
1052 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
1053 {
1054         u32 mask = 0;
1055         int ret = 0;
1056
1057         /* SoC specific settings for ipq8064.
1058          * If more device require this consider adding
1059          * a dedicated binding.
1060          */
1061         if (of_machine_is_compatible("qcom,ipq8064"))
1062                 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
1063
1064         /* SoC specific settings for ipq8065 */
1065         if (of_machine_is_compatible("qcom,ipq8065"))
1066                 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
1067
1068         if (mask) {
1069                 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
1070                                 QCA8K_MAC_PWR_RGMII0_1_8V |
1071                                 QCA8K_MAC_PWR_RGMII1_1_8V,
1072                                 mask);
1073         }
1074
1075         return ret;
1076 }
1077
1078 static int qca8k_find_cpu_port(struct dsa_switch *ds)
1079 {
1080         struct qca8k_priv *priv = ds->priv;
1081
1082         /* Find the connected cpu port. Valid port are 0 or 6 */
1083         if (dsa_is_cpu_port(ds, 0))
1084                 return 0;
1085
1086         dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
1087
1088         if (dsa_is_cpu_port(ds, 6))
1089                 return 6;
1090
1091         return -EINVAL;
1092 }
1093
1094 static int
1095 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
1096 {
1097         const struct qca8k_match_data *data = priv->info;
1098         struct device_node *node = priv->dev->of_node;
1099         u32 val = 0;
1100         int ret;
1101
1102         /* QCA8327 require to set to the correct mode.
1103          * His bigger brother QCA8328 have the 172 pin layout.
1104          * Should be applied by default but we set this just to make sure.
1105          */
1106         if (priv->switch_id == QCA8K_ID_QCA8327) {
1107                 /* Set the correct package of 148 pin for QCA8327 */
1108                 if (data->reduced_package)
1109                         val |= QCA8327_PWS_PACKAGE148_EN;
1110
1111                 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1112                                 val);
1113                 if (ret)
1114                         return ret;
1115         }
1116
1117         if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1118                 val |= QCA8K_PWS_POWER_ON_SEL;
1119
1120         if (of_property_read_bool(node, "qca,led-open-drain")) {
1121                 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1122                         dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1123                         return -EINVAL;
1124                 }
1125
1126                 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1127         }
1128
1129         return qca8k_rmw(priv, QCA8K_REG_PWS,
1130                         QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1131                         val);
1132 }
1133
1134 static int
1135 qca8k_parse_port_config(struct qca8k_priv *priv)
1136 {
1137         int port, cpu_port_index = -1, ret;
1138         struct device_node *port_dn;
1139         phy_interface_t mode;
1140         struct dsa_port *dp;
1141         u32 delay;
1142
1143         /* We have 2 CPU port. Check them */
1144         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1145                 /* Skip every other port */
1146                 if (port != 0 && port != 6)
1147                         continue;
1148
1149                 dp = dsa_to_port(priv->ds, port);
1150                 port_dn = dp->dn;
1151                 cpu_port_index++;
1152
1153                 if (!of_device_is_available(port_dn))
1154                         continue;
1155
1156                 ret = of_get_phy_mode(port_dn, &mode);
1157                 if (ret)
1158                         continue;
1159
1160                 switch (mode) {
1161                 case PHY_INTERFACE_MODE_RGMII:
1162                 case PHY_INTERFACE_MODE_RGMII_ID:
1163                 case PHY_INTERFACE_MODE_RGMII_TXID:
1164                 case PHY_INTERFACE_MODE_RGMII_RXID:
1165                 case PHY_INTERFACE_MODE_SGMII:
1166                         delay = 0;
1167
1168                         if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1169                                 /* Switch regs accept value in ns, convert ps to ns */
1170                                 delay = delay / 1000;
1171                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1172                                  mode == PHY_INTERFACE_MODE_RGMII_TXID)
1173                                 delay = 1;
1174
1175                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1176                                 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1177                                 delay = 3;
1178                         }
1179
1180                         priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1181
1182                         delay = 0;
1183
1184                         if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1185                                 /* Switch regs accept value in ns, convert ps to ns */
1186                                 delay = delay / 1000;
1187                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1188                                  mode == PHY_INTERFACE_MODE_RGMII_RXID)
1189                                 delay = 2;
1190
1191                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1192                                 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1193                                 delay = 3;
1194                         }
1195
1196                         priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1197
1198                         /* Skip sgmii parsing for rgmii* mode */
1199                         if (mode == PHY_INTERFACE_MODE_RGMII ||
1200                             mode == PHY_INTERFACE_MODE_RGMII_ID ||
1201                             mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1202                             mode == PHY_INTERFACE_MODE_RGMII_RXID)
1203                                 break;
1204
1205                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1206                                 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1207
1208                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1209                                 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1210
1211                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1212                                 priv->ports_config.sgmii_enable_pll = true;
1213
1214                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
1215                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1216                                         priv->ports_config.sgmii_enable_pll = false;
1217                                 }
1218
1219                                 if (priv->switch_revision < 2)
1220                                         dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1221                         }
1222
1223                         break;
1224                 default:
1225                         continue;
1226                 }
1227         }
1228
1229         return 0;
1230 }
1231
1232 static void
1233 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1234                                       u32 reg)
1235 {
1236         u32 delay, val = 0;
1237         int ret;
1238
1239         /* Delay can be declared in 3 different way.
1240          * Mode to rgmii and internal-delay standard binding defined
1241          * rgmii-id or rgmii-tx/rx phy mode set.
1242          * The parse logic set a delay different than 0 only when one
1243          * of the 3 different way is used. In all other case delay is
1244          * not enabled. With ID or TX/RXID delay is enabled and set
1245          * to the default and recommended value.
1246          */
1247         if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1248                 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1249
1250                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1251                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1252         }
1253
1254         if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1255                 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1256
1257                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1258                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1259         }
1260
1261         /* Set RGMII delay based on the selected values */
1262         ret = qca8k_rmw(priv, reg,
1263                         QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1264                         QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1265                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1266                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1267                         val);
1268         if (ret)
1269                 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1270                         cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1271 }
1272
1273 static struct phylink_pcs *
1274 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
1275                              phy_interface_t interface)
1276 {
1277         struct qca8k_priv *priv = ds->priv;
1278         struct phylink_pcs *pcs = NULL;
1279
1280         switch (interface) {
1281         case PHY_INTERFACE_MODE_SGMII:
1282         case PHY_INTERFACE_MODE_1000BASEX:
1283                 switch (port) {
1284                 case 0:
1285                         pcs = &priv->pcs_port_0.pcs;
1286                         break;
1287
1288                 case 6:
1289                         pcs = &priv->pcs_port_6.pcs;
1290                         break;
1291                 }
1292                 break;
1293
1294         default:
1295                 break;
1296         }
1297
1298         return pcs;
1299 }
1300
1301 static void
1302 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1303                          const struct phylink_link_state *state)
1304 {
1305         struct qca8k_priv *priv = ds->priv;
1306         int cpu_port_index;
1307         u32 reg;
1308
1309         switch (port) {
1310         case 0: /* 1st CPU port */
1311                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1312                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1313                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1314                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1315                     state->interface != PHY_INTERFACE_MODE_SGMII)
1316                         return;
1317
1318                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1319                 cpu_port_index = QCA8K_CPU_PORT0;
1320                 break;
1321         case 1:
1322         case 2:
1323         case 3:
1324         case 4:
1325         case 5:
1326                 /* Internal PHY, nothing to do */
1327                 return;
1328         case 6: /* 2nd CPU port / external PHY */
1329                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1330                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1331                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1332                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1333                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1334                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1335                         return;
1336
1337                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1338                 cpu_port_index = QCA8K_CPU_PORT6;
1339                 break;
1340         default:
1341                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1342                 return;
1343         }
1344
1345         if (port != 6 && phylink_autoneg_inband(mode)) {
1346                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1347                         __func__);
1348                 return;
1349         }
1350
1351         switch (state->interface) {
1352         case PHY_INTERFACE_MODE_RGMII:
1353         case PHY_INTERFACE_MODE_RGMII_ID:
1354         case PHY_INTERFACE_MODE_RGMII_TXID:
1355         case PHY_INTERFACE_MODE_RGMII_RXID:
1356                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1357
1358                 /* Configure rgmii delay */
1359                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1360
1361                 /* QCA8337 requires to set rgmii rx delay for all ports.
1362                  * This is enabled through PORT5_PAD_CTRL for all ports,
1363                  * rather than individual port registers.
1364                  */
1365                 if (priv->switch_id == QCA8K_ID_QCA8337)
1366                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1367                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1368                 break;
1369         case PHY_INTERFACE_MODE_SGMII:
1370         case PHY_INTERFACE_MODE_1000BASEX:
1371                 /* Enable SGMII on the port */
1372                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1373                 break;
1374         default:
1375                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1376                         phy_modes(state->interface), port);
1377                 return;
1378         }
1379 }
1380
1381 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port,
1382                                    struct phylink_config *config)
1383 {
1384         switch (port) {
1385         case 0: /* 1st CPU port */
1386                 phy_interface_set_rgmii(config->supported_interfaces);
1387                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1388                           config->supported_interfaces);
1389                 break;
1390
1391         case 1:
1392         case 2:
1393         case 3:
1394         case 4:
1395         case 5:
1396                 /* Internal PHY */
1397                 __set_bit(PHY_INTERFACE_MODE_GMII,
1398                           config->supported_interfaces);
1399                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1400                           config->supported_interfaces);
1401                 break;
1402
1403         case 6: /* 2nd CPU port / external PHY */
1404                 phy_interface_set_rgmii(config->supported_interfaces);
1405                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1406                           config->supported_interfaces);
1407                 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1408                           config->supported_interfaces);
1409                 break;
1410         }
1411
1412         config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1413                 MAC_10 | MAC_100 | MAC_1000FD;
1414 }
1415
1416 static void
1417 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1418                             phy_interface_t interface)
1419 {
1420         struct qca8k_priv *priv = ds->priv;
1421
1422         qca8k_port_set_status(priv, port, 0);
1423 }
1424
1425 static void
1426 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1427                           phy_interface_t interface, struct phy_device *phydev,
1428                           int speed, int duplex, bool tx_pause, bool rx_pause)
1429 {
1430         struct qca8k_priv *priv = ds->priv;
1431         u32 reg;
1432
1433         if (phylink_autoneg_inband(mode)) {
1434                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1435         } else {
1436                 switch (speed) {
1437                 case SPEED_10:
1438                         reg = QCA8K_PORT_STATUS_SPEED_10;
1439                         break;
1440                 case SPEED_100:
1441                         reg = QCA8K_PORT_STATUS_SPEED_100;
1442                         break;
1443                 case SPEED_1000:
1444                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1445                         break;
1446                 default:
1447                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1448                         break;
1449                 }
1450
1451                 if (duplex == DUPLEX_FULL)
1452                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1453
1454                 if (rx_pause || dsa_is_cpu_port(ds, port))
1455                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1456
1457                 if (tx_pause || dsa_is_cpu_port(ds, port))
1458                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1459         }
1460
1461         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1462
1463         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1464 }
1465
1466 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
1467 {
1468         return container_of(pcs, struct qca8k_pcs, pcs);
1469 }
1470
1471 static void qca8k_pcs_get_state(struct phylink_pcs *pcs,
1472                                 struct phylink_link_state *state)
1473 {
1474         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1475         int port = pcs_to_qca8k_pcs(pcs)->port;
1476         u32 reg;
1477         int ret;
1478
1479         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1480         if (ret < 0) {
1481                 state->link = false;
1482                 return;
1483         }
1484
1485         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1486         state->an_complete = state->link;
1487         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1488                                                            DUPLEX_HALF;
1489
1490         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1491         case QCA8K_PORT_STATUS_SPEED_10:
1492                 state->speed = SPEED_10;
1493                 break;
1494         case QCA8K_PORT_STATUS_SPEED_100:
1495                 state->speed = SPEED_100;
1496                 break;
1497         case QCA8K_PORT_STATUS_SPEED_1000:
1498                 state->speed = SPEED_1000;
1499                 break;
1500         default:
1501                 state->speed = SPEED_UNKNOWN;
1502                 break;
1503         }
1504
1505         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1506                 state->pause |= MLO_PAUSE_RX;
1507         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1508                 state->pause |= MLO_PAUSE_TX;
1509 }
1510
1511 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
1512                             phy_interface_t interface,
1513                             const unsigned long *advertising,
1514                             bool permit_pause_to_mac)
1515 {
1516         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1517         int cpu_port_index, ret, port;
1518         u32 reg, val;
1519
1520         port = pcs_to_qca8k_pcs(pcs)->port;
1521         switch (port) {
1522         case 0:
1523                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1524                 cpu_port_index = QCA8K_CPU_PORT0;
1525                 break;
1526
1527         case 6:
1528                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1529                 cpu_port_index = QCA8K_CPU_PORT6;
1530                 break;
1531
1532         default:
1533                 WARN_ON(1);
1534                 return -EINVAL;
1535         }
1536
1537         /* Enable/disable SerDes auto-negotiation as necessary */
1538         val = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ?
1539                 0 : QCA8K_PWS_SERDES_AEN_DIS;
1540
1541         ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8K_PWS_SERDES_AEN_DIS, val);
1542         if (ret)
1543                 return ret;
1544
1545         /* Configure the SGMII parameters */
1546         ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1547         if (ret)
1548                 return ret;
1549
1550         val |= QCA8K_SGMII_EN_SD;
1551
1552         if (priv->ports_config.sgmii_enable_pll)
1553                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1554                        QCA8K_SGMII_EN_TX;
1555
1556         if (dsa_is_cpu_port(priv->ds, port)) {
1557                 /* CPU port, we're talking to the CPU MAC, be a PHY */
1558                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1559                 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1560         } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1561                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1562                 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1563         } else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1564                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1565                 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1566         }
1567
1568         qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1569
1570         /* From original code is reported port instability as SGMII also
1571          * require delay set. Apply advised values here or take them from DT.
1572          */
1573         if (interface == PHY_INTERFACE_MODE_SGMII)
1574                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1575         /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1576          * falling edge is set writing in the PORT0 PAD reg
1577          */
1578         if (priv->switch_id == QCA8K_ID_QCA8327 ||
1579             priv->switch_id == QCA8K_ID_QCA8337)
1580                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1581
1582         val = 0;
1583
1584         /* SGMII Clock phase configuration */
1585         if (priv->ports_config.sgmii_rx_clk_falling_edge)
1586                 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1587
1588         if (priv->ports_config.sgmii_tx_clk_falling_edge)
1589                 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1590
1591         if (val)
1592                 ret = qca8k_rmw(priv, reg,
1593                                 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1594                                 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1595                                 val);
1596
1597         return 0;
1598 }
1599
1600 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs)
1601 {
1602 }
1603
1604 static const struct phylink_pcs_ops qca8k_pcs_ops = {
1605         .pcs_get_state = qca8k_pcs_get_state,
1606         .pcs_config = qca8k_pcs_config,
1607         .pcs_an_restart = qca8k_pcs_an_restart,
1608 };
1609
1610 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs,
1611                             int port)
1612 {
1613         qpcs->pcs.ops = &qca8k_pcs_ops;
1614         qpcs->pcs.neg_mode = true;
1615
1616         /* We don't have interrupts for link changes, so we need to poll */
1617         qpcs->pcs.poll = true;
1618         qpcs->priv = priv;
1619         qpcs->port = port;
1620 }
1621
1622 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
1623 {
1624         struct qca8k_mib_eth_data *mib_eth_data;
1625         struct qca8k_priv *priv = ds->priv;
1626         const struct qca8k_mib_desc *mib;
1627         struct mib_ethhdr *mib_ethhdr;
1628         __le32 *data2;
1629         u8 port;
1630         int i;
1631
1632         mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
1633         mib_eth_data = &priv->mib_eth_data;
1634
1635         /* The switch autocast every port. Ignore other packet and
1636          * parse only the requested one.
1637          */
1638         port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
1639         if (port != mib_eth_data->req_port)
1640                 goto exit;
1641
1642         data2 = (__le32 *)skb->data;
1643
1644         for (i = 0; i < priv->info->mib_count; i++) {
1645                 mib = &ar8327_mib[i];
1646
1647                 /* First 3 mib are present in the skb head */
1648                 if (i < 3) {
1649                         mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i);
1650                         continue;
1651                 }
1652
1653                 /* Some mib are 64 bit wide */
1654                 if (mib->size == 2)
1655                         mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2);
1656                 else
1657                         mib_eth_data->data[i] = get_unaligned_le32(data2);
1658
1659                 data2 += mib->size;
1660         }
1661
1662 exit:
1663         /* Complete on receiving all the mib packet */
1664         if (refcount_dec_and_test(&mib_eth_data->port_parsed))
1665                 complete(&mib_eth_data->rw_done);
1666 }
1667
1668 static int
1669 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
1670 {
1671         struct dsa_port *dp = dsa_to_port(ds, port);
1672         struct qca8k_mib_eth_data *mib_eth_data;
1673         struct qca8k_priv *priv = ds->priv;
1674         int ret;
1675
1676         mib_eth_data = &priv->mib_eth_data;
1677
1678         mutex_lock(&mib_eth_data->mutex);
1679
1680         reinit_completion(&mib_eth_data->rw_done);
1681
1682         mib_eth_data->req_port = dp->index;
1683         mib_eth_data->data = data;
1684         refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
1685
1686         mutex_lock(&priv->reg_mutex);
1687
1688         /* Send mib autocast request */
1689         ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
1690                                  QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
1691                                  FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
1692                                  QCA8K_MIB_BUSY);
1693
1694         mutex_unlock(&priv->reg_mutex);
1695
1696         if (ret)
1697                 goto exit;
1698
1699         ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
1700
1701 exit:
1702         mutex_unlock(&mib_eth_data->mutex);
1703
1704         return ret;
1705 }
1706
1707 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1708 {
1709         struct qca8k_priv *priv = ds->priv;
1710
1711         /* Communicate to the phy internal driver the switch revision.
1712          * Based on the switch revision different values needs to be
1713          * set to the dbg and mmd reg on the phy.
1714          * The first 2 bit are used to communicate the switch revision
1715          * to the phy driver.
1716          */
1717         if (port > 0 && port < 6)
1718                 return priv->switch_revision;
1719
1720         return 0;
1721 }
1722
1723 static enum dsa_tag_protocol
1724 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1725                        enum dsa_tag_protocol mp)
1726 {
1727         return DSA_TAG_PROTO_QCA;
1728 }
1729
1730 static void
1731 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
1732                     bool operational)
1733 {
1734         struct dsa_port *dp = master->dsa_ptr;
1735         struct qca8k_priv *priv = ds->priv;
1736
1737         /* Ethernet MIB/MDIO is only supported for CPU port 0 */
1738         if (dp->index != 0)
1739                 return;
1740
1741         mutex_lock(&priv->mgmt_eth_data.mutex);
1742         mutex_lock(&priv->mib_eth_data.mutex);
1743
1744         priv->mgmt_master = operational ? (struct net_device *)master : NULL;
1745
1746         mutex_unlock(&priv->mib_eth_data.mutex);
1747         mutex_unlock(&priv->mgmt_eth_data.mutex);
1748 }
1749
1750 static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
1751                                       enum dsa_tag_protocol proto)
1752 {
1753         struct qca_tagger_data *tagger_data;
1754
1755         switch (proto) {
1756         case DSA_TAG_PROTO_QCA:
1757                 tagger_data = ds->tagger_data;
1758
1759                 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
1760                 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
1761
1762                 break;
1763         default:
1764                 return -EOPNOTSUPP;
1765         }
1766
1767         return 0;
1768 }
1769
1770 static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port)
1771 {
1772         u32 mask;
1773
1774         switch (port) {
1775         /* The 2 CPU port and port 5 requires some different
1776          * priority than any other ports.
1777          */
1778         case 0:
1779         case 5:
1780         case 6:
1781                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1782                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1783                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1784                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1785                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1786                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1787                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1788                 break;
1789         default:
1790                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1791                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1792                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1793                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1794                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1795         }
1796         regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask);
1797
1798         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1799                QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1800                QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1801                QCA8K_PORT_HOL_CTRL1_WRED_EN;
1802         regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port),
1803                            QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1804                            QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1805                            QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1806                            QCA8K_PORT_HOL_CTRL1_WRED_EN,
1807                            mask);
1808 }
1809
1810 static int
1811 qca8k_setup(struct dsa_switch *ds)
1812 {
1813         struct qca8k_priv *priv = ds->priv;
1814         struct dsa_port *dp;
1815         int cpu_port, ret;
1816         u32 mask;
1817
1818         cpu_port = qca8k_find_cpu_port(ds);
1819         if (cpu_port < 0) {
1820                 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1821                 return cpu_port;
1822         }
1823
1824         /* Parse CPU port config to be later used in phy_link mac_config */
1825         ret = qca8k_parse_port_config(priv);
1826         if (ret)
1827                 return ret;
1828
1829         ret = qca8k_setup_mdio_bus(priv);
1830         if (ret)
1831                 return ret;
1832
1833         ret = qca8k_setup_of_pws_reg(priv);
1834         if (ret)
1835                 return ret;
1836
1837         ret = qca8k_setup_mac_pwr_sel(priv);
1838         if (ret)
1839                 return ret;
1840
1841         ret = qca8k_setup_led_ctrl(priv);
1842         if (ret)
1843                 return ret;
1844
1845         qca8k_setup_pcs(priv, &priv->pcs_port_0, 0);
1846         qca8k_setup_pcs(priv, &priv->pcs_port_6, 6);
1847
1848         /* Make sure MAC06 is disabled */
1849         ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1850                                 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1851         if (ret) {
1852                 dev_err(priv->dev, "failed disabling MAC06 exchange");
1853                 return ret;
1854         }
1855
1856         /* Enable CPU Port */
1857         ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1858                               QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1859         if (ret) {
1860                 dev_err(priv->dev, "failed enabling CPU port");
1861                 return ret;
1862         }
1863
1864         /* Enable MIB counters */
1865         ret = qca8k_mib_init(priv);
1866         if (ret)
1867                 dev_warn(priv->dev, "mib init failed");
1868
1869         /* Initial setup of all ports */
1870         dsa_switch_for_each_port(dp, ds) {
1871                 /* Disable forwarding by default on all ports */
1872                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(dp->index),
1873                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
1874                 if (ret)
1875                         return ret;
1876         }
1877
1878         /* Disable MAC by default on all user ports */
1879         dsa_switch_for_each_user_port(dp, ds)
1880                 qca8k_port_set_status(priv, dp->index, 0);
1881
1882         /* Enable QCA header mode on all cpu ports */
1883         dsa_switch_for_each_cpu_port(dp, ds) {
1884                 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(dp->index),
1885                                   FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1886                                   FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1887                 if (ret) {
1888                         dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index);
1889                         return ret;
1890                 }
1891         }
1892
1893         /* Forward all unknown frames to CPU port for Linux processing
1894          * Notice that in multi-cpu config only one port should be set
1895          * for igmp, unknown, multicast and broadcast packet
1896          */
1897         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1898                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1899                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1900                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1901                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1902         if (ret)
1903                 return ret;
1904
1905         /* CPU port gets connected to all user ports of the switch */
1906         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),
1907                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1908         if (ret)
1909                 return ret;
1910
1911         /* Setup connection between CPU port & user ports
1912          * Individual user ports get connected to CPU port only
1913          */
1914         dsa_switch_for_each_user_port(dp, ds) {
1915                 u8 port = dp->index;
1916
1917                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1918                                 QCA8K_PORT_LOOKUP_MEMBER,
1919                                 BIT(cpu_port));
1920                 if (ret)
1921                         return ret;
1922
1923                 ret = regmap_clear_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
1924                                         QCA8K_PORT_LOOKUP_LEARN);
1925                 if (ret)
1926                         return ret;
1927
1928                 /* For port based vlans to work we need to set the
1929                  * default egress vid
1930                  */
1931                 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1932                                 QCA8K_EGREES_VLAN_PORT_MASK(port),
1933                                 QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
1934                 if (ret)
1935                         return ret;
1936
1937                 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1938                                   QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1939                                   QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1940                 if (ret)
1941                         return ret;
1942         }
1943
1944         /* The port 5 of the qca8337 have some problem in flood condition. The
1945          * original legacy driver had some specific buffer and priority settings
1946          * for the different port suggested by the QCA switch team. Add this
1947          * missing settings to improve switch stability under load condition.
1948          * This problem is limited to qca8337 and other qca8k switch are not affected.
1949          */
1950         if (priv->switch_id == QCA8K_ID_QCA8337)
1951                 dsa_switch_for_each_available_port(dp, ds)
1952                         qca8k_setup_hol_fixup(priv, dp->index);
1953
1954         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1955         if (priv->switch_id == QCA8K_ID_QCA8327) {
1956                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1957                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1958                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1959                           QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1960                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1961                           mask);
1962         }
1963
1964         /* Setup our port MTUs to match power on defaults */
1965         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1966         if (ret)
1967                 dev_warn(priv->dev, "failed setting MTU settings");
1968
1969         /* Flush the FDB table */
1970         qca8k_fdb_flush(priv);
1971
1972         /* Set min a max ageing value supported */
1973         ds->ageing_time_min = 7000;
1974         ds->ageing_time_max = 458745000;
1975
1976         /* Set max number of LAGs supported */
1977         ds->num_lag_ids = QCA8K_NUM_LAGS;
1978
1979         return 0;
1980 }
1981
1982 static const struct dsa_switch_ops qca8k_switch_ops = {
1983         .get_tag_protocol       = qca8k_get_tag_protocol,
1984         .setup                  = qca8k_setup,
1985         .get_strings            = qca8k_get_strings,
1986         .get_ethtool_stats      = qca8k_get_ethtool_stats,
1987         .get_sset_count         = qca8k_get_sset_count,
1988         .set_ageing_time        = qca8k_set_ageing_time,
1989         .get_mac_eee            = qca8k_get_mac_eee,
1990         .set_mac_eee            = qca8k_set_mac_eee,
1991         .port_enable            = qca8k_port_enable,
1992         .port_disable           = qca8k_port_disable,
1993         .port_change_mtu        = qca8k_port_change_mtu,
1994         .port_max_mtu           = qca8k_port_max_mtu,
1995         .port_stp_state_set     = qca8k_port_stp_state_set,
1996         .port_pre_bridge_flags  = qca8k_port_pre_bridge_flags,
1997         .port_bridge_flags      = qca8k_port_bridge_flags,
1998         .port_bridge_join       = qca8k_port_bridge_join,
1999         .port_bridge_leave      = qca8k_port_bridge_leave,
2000         .port_fast_age          = qca8k_port_fast_age,
2001         .port_fdb_add           = qca8k_port_fdb_add,
2002         .port_fdb_del           = qca8k_port_fdb_del,
2003         .port_fdb_dump          = qca8k_port_fdb_dump,
2004         .port_mdb_add           = qca8k_port_mdb_add,
2005         .port_mdb_del           = qca8k_port_mdb_del,
2006         .port_mirror_add        = qca8k_port_mirror_add,
2007         .port_mirror_del        = qca8k_port_mirror_del,
2008         .port_vlan_filtering    = qca8k_port_vlan_filtering,
2009         .port_vlan_add          = qca8k_port_vlan_add,
2010         .port_vlan_del          = qca8k_port_vlan_del,
2011         .phylink_get_caps       = qca8k_phylink_get_caps,
2012         .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs,
2013         .phylink_mac_config     = qca8k_phylink_mac_config,
2014         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
2015         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
2016         .get_phy_flags          = qca8k_get_phy_flags,
2017         .port_lag_join          = qca8k_port_lag_join,
2018         .port_lag_leave         = qca8k_port_lag_leave,
2019         .master_state_change    = qca8k_master_change,
2020         .connect_tag_protocol   = qca8k_connect_tag_protocol,
2021 };
2022
2023 static int
2024 qca8k_sw_probe(struct mdio_device *mdiodev)
2025 {
2026         struct qca8k_priv *priv;
2027         int ret;
2028
2029         /* allocate the private data struct so that we can probe the switches
2030          * ID register
2031          */
2032         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2033         if (!priv)
2034                 return -ENOMEM;
2035
2036         priv->bus = mdiodev->bus;
2037         priv->dev = &mdiodev->dev;
2038         priv->info = of_device_get_match_data(priv->dev);
2039
2040         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2041                                                    GPIOD_ASIS);
2042         if (IS_ERR(priv->reset_gpio))
2043                 return PTR_ERR(priv->reset_gpio);
2044
2045         if (priv->reset_gpio) {
2046                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2047                 /* The active low duration must be greater than 10 ms
2048                  * and checkpatch.pl wants 20 ms.
2049                  */
2050                 msleep(20);
2051                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2052         }
2053
2054         /* Start by setting up the register mapping */
2055         priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
2056                                         &qca8k_regmap_config);
2057         if (IS_ERR(priv->regmap)) {
2058                 dev_err(priv->dev, "regmap initialization failed");
2059                 return PTR_ERR(priv->regmap);
2060         }
2061
2062         priv->mdio_cache.page = 0xffff;
2063
2064         /* Check the detected switch id */
2065         ret = qca8k_read_switch_id(priv);
2066         if (ret)
2067                 return ret;
2068
2069         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2070         if (!priv->ds)
2071                 return -ENOMEM;
2072
2073         mutex_init(&priv->mgmt_eth_data.mutex);
2074         init_completion(&priv->mgmt_eth_data.rw_done);
2075
2076         mutex_init(&priv->mib_eth_data.mutex);
2077         init_completion(&priv->mib_eth_data.rw_done);
2078
2079         priv->ds->dev = &mdiodev->dev;
2080         priv->ds->num_ports = QCA8K_NUM_PORTS;
2081         priv->ds->priv = priv;
2082         priv->ds->ops = &qca8k_switch_ops;
2083         mutex_init(&priv->reg_mutex);
2084         dev_set_drvdata(&mdiodev->dev, priv);
2085
2086         return dsa_register_switch(priv->ds);
2087 }
2088
2089 static void
2090 qca8k_sw_remove(struct mdio_device *mdiodev)
2091 {
2092         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2093         int i;
2094
2095         if (!priv)
2096                 return;
2097
2098         for (i = 0; i < QCA8K_NUM_PORTS; i++)
2099                 qca8k_port_set_status(priv, i, 0);
2100
2101         dsa_unregister_switch(priv->ds);
2102 }
2103
2104 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2105 {
2106         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2107
2108         if (!priv)
2109                 return;
2110
2111         dsa_switch_shutdown(priv->ds);
2112
2113         dev_set_drvdata(&mdiodev->dev, NULL);
2114 }
2115
2116 #ifdef CONFIG_PM_SLEEP
2117 static void
2118 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2119 {
2120         int port;
2121
2122         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
2123                 /* Do not enable on resume if the port was
2124                  * disabled before.
2125                  */
2126                 if (!(priv->port_enabled_map & BIT(port)))
2127                         continue;
2128
2129                 qca8k_port_set_status(priv, port, enable);
2130         }
2131 }
2132
2133 static int qca8k_suspend(struct device *dev)
2134 {
2135         struct qca8k_priv *priv = dev_get_drvdata(dev);
2136
2137         qca8k_set_pm(priv, 0);
2138
2139         return dsa_switch_suspend(priv->ds);
2140 }
2141
2142 static int qca8k_resume(struct device *dev)
2143 {
2144         struct qca8k_priv *priv = dev_get_drvdata(dev);
2145
2146         qca8k_set_pm(priv, 1);
2147
2148         return dsa_switch_resume(priv->ds);
2149 }
2150 #endif /* CONFIG_PM_SLEEP */
2151
2152 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2153                          qca8k_suspend, qca8k_resume);
2154
2155 static const struct qca8k_info_ops qca8xxx_ops = {
2156         .autocast_mib = qca8k_get_ethtool_stats_eth,
2157 };
2158
2159 static const struct qca8k_match_data qca8327 = {
2160         .id = QCA8K_ID_QCA8327,
2161         .reduced_package = true,
2162         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2163         .ops = &qca8xxx_ops,
2164 };
2165
2166 static const struct qca8k_match_data qca8328 = {
2167         .id = QCA8K_ID_QCA8327,
2168         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2169         .ops = &qca8xxx_ops,
2170 };
2171
2172 static const struct qca8k_match_data qca833x = {
2173         .id = QCA8K_ID_QCA8337,
2174         .mib_count = QCA8K_QCA833X_MIB_COUNT,
2175         .ops = &qca8xxx_ops,
2176 };
2177
2178 static const struct of_device_id qca8k_of_match[] = {
2179         { .compatible = "qca,qca8327", .data = &qca8327 },
2180         { .compatible = "qca,qca8328", .data = &qca8328 },
2181         { .compatible = "qca,qca8334", .data = &qca833x },
2182         { .compatible = "qca,qca8337", .data = &qca833x },
2183         { /* sentinel */ },
2184 };
2185
2186 static struct mdio_driver qca8kmdio_driver = {
2187         .probe  = qca8k_sw_probe,
2188         .remove = qca8k_sw_remove,
2189         .shutdown = qca8k_sw_shutdown,
2190         .mdiodrv.driver = {
2191                 .name = "qca8k",
2192                 .of_match_table = qca8k_of_match,
2193                 .pm = &qca8k_pm_ops,
2194         },
2195 };
2196
2197 mdio_module_driver(qca8kmdio_driver);
2198
2199 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
2200 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2201 MODULE_LICENSE("GPL v2");
2202 MODULE_ALIAS("platform:qca8k");