drivers/net/dsa/qca/qca8k-8xxx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/bitfield.h>
  13 #include <linux/regmap.h>
  14 #include <net/dsa.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/mdio.h>
  19 #include <linux/phylink.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/dsa/tag_qca.h>
  23
  24 #include "qca8k.h"
  25 #include "qca8k_leds.h"
  26
  27 static void
  28 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  29 {
  30         regaddr >>= 1;
  31         *r1 = regaddr & 0x1e;
  32
  33         regaddr >>= 5;
  34         *r2 = regaddr & 0x7;
  35
  36         regaddr >>= 3;
  37         *page = regaddr & 0x3ff;
  38 }
  39
  40 static int
  41 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  42 {
  43         int ret;
  44         u16 lo;
  45
  46         lo = val & 0xffff;
  47         ret = bus->write(bus, phy_id, regnum, lo);
  48         if (ret < 0)
  49                 dev_err_ratelimited(&bus->dev,
  50                                     "failed to write qca8k 32bit lo register\n");
  51
  52         return ret;
  53 }
  54
  55 static int
  56 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  57 {
  58         int ret;
  59         u16 hi;
  60
  61         hi = (u16)(val >> 16);
  62         ret = bus->write(bus, phy_id, regnum, hi);
  63         if (ret < 0)
  64                 dev_err_ratelimited(&bus->dev,
  65                                     "failed to write qca8k 32bit hi register\n");
  66
  67         return ret;
  68 }
  69
  70 static int
  71 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  72 {
  73         int ret;
  74
  75         ret = bus->read(bus, phy_id, regnum);
  76         if (ret < 0)
  77                 goto err;
  78
  79         *val = ret & 0xffff;
  80         return 0;
  81
  82 err:
  83         dev_err_ratelimited(&bus->dev,
  84                             "failed to read qca8k 32bit lo register\n");
  85         *val = 0;
  86
  87         return ret;
  88 }
  89
  90 static int
  91 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  92 {
  93         int ret;
  94
  95         ret = bus->read(bus, phy_id, regnum);
  96         if (ret < 0)
  97                 goto err;
  98
  99         *val = ret << 16;
 100         return 0;
 101
 102 err:
 103         dev_err_ratelimited(&bus->dev,
 104                             "failed to read qca8k 32bit hi register\n");
 105         *val = 0;
 106
 107         return ret;
 108 }
 109
 110 static int
 111 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 112 {
 113         u32 hi, lo;
 114         int ret;
 115
 116         *val = 0;
 117
 118         ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
 119         if (ret < 0)
 120                 goto err;
 121
 122         ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
 123         if (ret < 0)
 124                 goto err;
 125
 126         *val = lo | hi;
 127
 128 err:
 129         return ret;
 130 }
 131
 132 static void
 133 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 134 {
 135         if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
 136                 return;
 137
 138         qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
 139 }
 140
 141 static int
 142 qca8k_set_page(struct qca8k_priv *priv, u16 page)
 143 {
 144         u16 *cached_page = &priv->mdio_cache.page;
 145         struct mii_bus *bus = priv->bus;
 146         int ret;
 147
 148         if (page == *cached_page)
 149                 return 0;
 150
 151         ret = bus->write(bus, 0x18, 0, page);
 152         if (ret < 0) {
 153                 dev_err_ratelimited(&bus->dev,
 154                                     "failed to set qca8k page\n");
 155                 return ret;
 156         }
 157
 158         *cached_page = page;
 159         usleep_range(1000, 2000);
 160         return 0;
 161 }
 162
 163 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 164 {
 165         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 166         struct qca8k_priv *priv = ds->priv;
 167         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 168         u32 command;
 169         u8 len, cmd;
 170         int i;
 171
 172         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
 173         mgmt_eth_data = &priv->mgmt_eth_data;
 174
 175         command = get_unaligned_le32(&mgmt_ethhdr->command);
 176         cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
 177
 178         len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
 179         /* Special case for len of 15 as this is the max value for len and needs to
 180          * be increased before converting it from word to dword.
 181          */
 182         if (len == 15)
 183                 len++;
 184
 185         /* We can ignore odd value, we always round up them in the alloc function. */
 186         len *= sizeof(u16);
 187
 188         /* Make sure the seq match the requested packet */
 189         if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
 190                 mgmt_eth_data->ack = true;
 191
 192         if (cmd == MDIO_READ) {
 193                 u32 *val = mgmt_eth_data->data;
 194
 195                 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data);
 196
 197                 /* Get the rest of the 12 byte of data.
 198                  * The read/write function will extract the requested data.
 199                  */
 200                 if (len > QCA_HDR_MGMT_DATA1_LEN) {
 201                         __le32 *data2 = (__le32 *)skb->data;
 202                         int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 203                                              len - QCA_HDR_MGMT_DATA1_LEN);
 204
 205                         val++;
 206
 207                         for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 208                                 *val = get_unaligned_le32(data2);
 209                                 val++;
 210                                 data2++;
 211                         }
 212                 }
 213         }
 214
 215         complete(&mgmt_eth_data->rw_done);
 216 }
 217
 218 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
 219                                                int priority, unsigned int len)
 220 {
 221         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 222         unsigned int real_len;
 223         struct sk_buff *skb;
 224         __le32 *data2;
 225         u32 command;
 226         u16 hdr;
 227         int i;
 228
 229         skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
 230         if (!skb)
 231                 return NULL;
 232
 233         /* Hdr mgmt length value is in step of word size.
 234          * As an example to process 4 byte of data the correct length to set is 2.
 235          * To process 8 byte 4, 12 byte 6, 16 byte 8...
 236          *
 237          * Odd values will always return the next size on the ack packet.
 238          * (length of 3 (6 byte) will always return 8 bytes of data)
 239          *
 240          * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
 241          * of data.
 242          *
 243          * To correctly calculate the length we devide the requested len by word and
 244          * round up.
 245          * On the ack function we can skip the odd check as we already handle the
 246          * case here.
 247          */
 248         real_len = DIV_ROUND_UP(len, sizeof(u16));
 249
 250         /* We check if the result len is odd and we round up another time to
 251          * the next size. (length of 3 will be increased to 4 as switch will always
 252          * return 8 bytes)
 253          */
 254         if (real_len % sizeof(u16) != 0)
 255                 real_len++;
 256
 257         /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
 258         if (real_len == 16)
 259                 real_len--;
 260
 261         skb_reset_mac_header(skb);
 262         skb_set_network_header(skb, skb->len);
 263
 264         mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
 265
 266         hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
 267         hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
 268         hdr |= QCA_HDR_XMIT_FROM_CPU;
 269         hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
 270         hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
 271
 272         command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
 273         command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
 274         command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
 275         command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
 276                                            QCA_HDR_MGMT_CHECK_CODE_VAL);
 277
 278         put_unaligned_le32(command, &mgmt_ethhdr->command);
 279
 280         if (cmd == MDIO_WRITE)
 281                 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data);
 282
 283         mgmt_ethhdr->hdr = htons(hdr);
 284
 285         data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
 286         if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) {
 287                 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 288                                      len - QCA_HDR_MGMT_DATA1_LEN);
 289
 290                 val++;
 291
 292                 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 293                         put_unaligned_le32(*val, data2);
 294                         data2++;
 295                         val++;
 296                 }
 297         }
 298
 299         return skb;
 300 }
 301
 302 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
 303 {
 304         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 305         u32 seq;
 306
 307         seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
 308         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
 309         put_unaligned_le32(seq, &mgmt_ethhdr->seq);
 310 }
 311
 312 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 313 {
 314         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 315         struct sk_buff *skb;
 316         bool ack;
 317         int ret;
 318
 319         skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
 320                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 321         if (!skb)
 322                 return -ENOMEM;
 323
 324         mutex_lock(&mgmt_eth_data->mutex);
 325
 326         /* Check mgmt_master if is operational */
 327         if (!priv->mgmt_master) {
 328                 kfree_skb(skb);
 329                 mutex_unlock(&mgmt_eth_data->mutex);
 330                 return -EINVAL;
 331         }
 332
 333         skb->dev = priv->mgmt_master;
 334
 335         reinit_completion(&mgmt_eth_data->rw_done);
 336
 337         /* Increment seq_num and set it in the mdio pkt */
 338         mgmt_eth_data->seq++;
 339         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 340         mgmt_eth_data->ack = false;
 341
 342         dev_queue_xmit(skb);
 343
 344         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 345                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 346
 347         *val = mgmt_eth_data->data[0];
 348         if (len > QCA_HDR_MGMT_DATA1_LEN)
 349                 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
 350
 351         ack = mgmt_eth_data->ack;
 352
 353         mutex_unlock(&mgmt_eth_data->mutex);
 354
 355         if (ret <= 0)
 356                 return -ETIMEDOUT;
 357
 358         if (!ack)
 359                 return -EINVAL;
 360
 361         return 0;
 362 }
 363
 364 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 365 {
 366         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 367         struct sk_buff *skb;
 368         bool ack;
 369         int ret;
 370
 371         skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
 372                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 373         if (!skb)
 374                 return -ENOMEM;
 375
 376         mutex_lock(&mgmt_eth_data->mutex);
 377
 378         /* Check mgmt_master if is operational */
 379         if (!priv->mgmt_master) {
 380                 kfree_skb(skb);
 381                 mutex_unlock(&mgmt_eth_data->mutex);
 382                 return -EINVAL;
 383         }
 384
 385         skb->dev = priv->mgmt_master;
 386
 387         reinit_completion(&mgmt_eth_data->rw_done);
 388
 389         /* Increment seq_num and set it in the mdio pkt */
 390         mgmt_eth_data->seq++;
 391         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 392         mgmt_eth_data->ack = false;
 393
 394         dev_queue_xmit(skb);
 395
 396         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 397                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 398
 399         ack = mgmt_eth_data->ack;
 400
 401         mutex_unlock(&mgmt_eth_data->mutex);
 402
 403         if (ret <= 0)
 404                 return -ETIMEDOUT;
 405
 406         if (!ack)
 407                 return -EINVAL;
 408
 409         return 0;
 410 }
 411
 412 static int
 413 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 414 {
 415         u32 val = 0;
 416         int ret;
 417
 418         ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
 419         if (ret)
 420                 return ret;
 421
 422         val &= ~mask;
 423         val |= write_val;
 424
 425         return qca8k_write_eth(priv, reg, &val, sizeof(val));
 426 }
 427
 428 static int
 429 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)
 430 {
 431         struct mii_bus *bus = priv->bus;
 432         u16 r1, r2, page;
 433         int ret;
 434
 435         qca8k_split_addr(reg, &r1, &r2, &page);
 436
 437         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 438
 439         ret = qca8k_set_page(priv, page);
 440         if (ret < 0)
 441                 goto exit;
 442
 443         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 444
 445 exit:
 446         mutex_unlock(&bus->mdio_lock);
 447         return ret;
 448 }
 449
 450 static int
 451 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)
 452 {
 453         struct mii_bus *bus = priv->bus;
 454         u16 r1, r2, page;
 455         int ret;
 456
 457         qca8k_split_addr(reg, &r1, &r2, &page);
 458
 459         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 460
 461         ret = qca8k_set_page(priv, page);
 462         if (ret < 0)
 463                 goto exit;
 464
 465         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 466
 467 exit:
 468         mutex_unlock(&bus->mdio_lock);
 469         return ret;
 470 }
 471
 472 static int
 473 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,
 474                              uint32_t mask, uint32_t write_val)
 475 {
 476         struct mii_bus *bus = priv->bus;
 477         u16 r1, r2, page;
 478         u32 val;
 479         int ret;
 480
 481         qca8k_split_addr(reg, &r1, &r2, &page);
 482
 483         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 484
 485         ret = qca8k_set_page(priv, page);
 486         if (ret < 0)
 487                 goto exit;
 488
 489         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 490         if (ret < 0)
 491                 goto exit;
 492
 493         val &= ~mask;
 494         val |= write_val;
 495         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 496
 497 exit:
 498         mutex_unlock(&bus->mdio_lock);
 499
 500         return ret;
 501 }
 502
 503 static int
 504 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,
 505                 void *val_buf, size_t val_len)
 506 {
 507         int i, count = val_len / sizeof(u32), ret;
 508         u32 reg = *(u32 *)reg_buf & U16_MAX;
 509         struct qca8k_priv *priv = ctx;
 510
 511         if (priv->mgmt_master &&
 512             !qca8k_read_eth(priv, reg, val_buf, val_len))
 513                 return 0;
 514
 515         /* loop count times and increment reg of 4 */
 516         for (i = 0; i < count; i++, reg += sizeof(u32)) {
 517                 ret = qca8k_read_mii(priv, reg, val_buf + i);
 518                 if (ret < 0)
 519                         return ret;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int
 526 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,
 527                         const void *val_buf, size_t val_len)
 528 {
 529         int i, count = val_len / sizeof(u32), ret;
 530         u32 reg = *(u32 *)reg_buf & U16_MAX;
 531         struct qca8k_priv *priv = ctx;
 532         u32 *val = (u32 *)val_buf;
 533
 534         if (priv->mgmt_master &&
 535             !qca8k_write_eth(priv, reg, val, val_len))
 536                 return 0;
 537
 538         /* loop count times, increment reg of 4 and increment val ptr to
 539          * the next value
 540          */
 541         for (i = 0; i < count; i++, reg += sizeof(u32), val++) {
 542                 ret = qca8k_write_mii(priv, reg, *val);
 543                 if (ret < 0)
 544                         return ret;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int
 551 qca8k_bulk_write(void *ctx, const void *data, size_t bytes)
 552 {
 553         return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),
 554                                        bytes - sizeof(u16));
 555 }
 556
 557 static int
 558 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
 559 {
 560         struct qca8k_priv *priv = ctx;
 561
 562         if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
 563                 return 0;
 564
 565         return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);
 566 }
 567
 568 static struct regmap_config qca8k_regmap_config = {
 569         .reg_bits = 16,
 570         .val_bits = 32,
 571         .reg_stride = 4,
 572         .max_register = 0x16ac, /* end MIB - Port6 range */
 573         .read = qca8k_bulk_read,
 574         .write = qca8k_bulk_write,
 575         .reg_update_bits = qca8k_regmap_update_bits,
 576         .rd_table = &qca8k_readable_table,
 577         .disable_locking = true, /* Locking is handled by qca8k read/write */
 578         .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
 579         .max_raw_read = 32, /* mgmt eth can read/write up to 8 registers at time */
 580         .max_raw_write = 32,
 581 };
 582
 583 static int
 584 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
 585                         struct sk_buff *read_skb, u32 *val)
 586 {
 587         struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
 588         bool ack;
 589         int ret;
 590
 591         if (!skb)
 592                 return -ENOMEM;
 593
 594         reinit_completion(&mgmt_eth_data->rw_done);
 595
 596         /* Increment seq_num and set it in the copy pkt */
 597         mgmt_eth_data->seq++;
 598         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 599         mgmt_eth_data->ack = false;
 600
 601         dev_queue_xmit(skb);
 602
 603         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 604                                           QCA8K_ETHERNET_TIMEOUT);
 605
 606         ack = mgmt_eth_data->ack;
 607
 608         if (ret <= 0)
 609                 return -ETIMEDOUT;
 610
 611         if (!ack)
 612                 return -EINVAL;
 613
 614         *val = mgmt_eth_data->data[0];
 615
 616         return 0;
 617 }
 618
 619 static int
 620 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
 621                       int regnum, u16 data)
 622 {
 623         struct sk_buff *write_skb, *clear_skb, *read_skb;
 624         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 625         u32 write_val, clear_val = 0, val;
 626         struct net_device *mgmt_master;
 627         int ret, ret1;
 628         bool ack;
 629
 630         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 631                 return -EINVAL;
 632
 633         mgmt_eth_data = &priv->mgmt_eth_data;
 634
 635         write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 636                     QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 637                     QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 638
 639         if (read) {
 640                 write_val |= QCA8K_MDIO_MASTER_READ;
 641         } else {
 642                 write_val |= QCA8K_MDIO_MASTER_WRITE;
 643                 write_val |= QCA8K_MDIO_MASTER_DATA(data);
 644         }
 645
 646         /* Prealloc all the needed skb before the lock */
 647         write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
 648                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
 649         if (!write_skb)
 650                 return -ENOMEM;
 651
 652         clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 653                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 654         if (!clear_skb) {
 655                 ret = -ENOMEM;
 656                 goto err_clear_skb;
 657         }
 658
 659         read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 660                                            QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 661         if (!read_skb) {
 662                 ret = -ENOMEM;
 663                 goto err_read_skb;
 664         }
 665
 666         /* Actually start the request:
 667          * 1. Send mdio master packet
 668          * 2. Busy Wait for mdio master command
 669          * 3. Get the data if we are reading
 670          * 4. Reset the mdio master (even with error)
 671          */
 672         mutex_lock(&mgmt_eth_data->mutex);
 673
 674         /* Check if mgmt_master is operational */
 675         mgmt_master = priv->mgmt_master;
 676         if (!mgmt_master) {
 677                 mutex_unlock(&mgmt_eth_data->mutex);
 678                 ret = -EINVAL;
 679                 goto err_mgmt_master;
 680         }
 681
 682         read_skb->dev = mgmt_master;
 683         clear_skb->dev = mgmt_master;
 684         write_skb->dev = mgmt_master;
 685
 686         reinit_completion(&mgmt_eth_data->rw_done);
 687
 688         /* Increment seq_num and set it in the write pkt */
 689         mgmt_eth_data->seq++;
 690         qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
 691         mgmt_eth_data->ack = false;
 692
 693         dev_queue_xmit(write_skb);
 694
 695         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 696                                           QCA8K_ETHERNET_TIMEOUT);
 697
 698         ack = mgmt_eth_data->ack;
 699
 700         if (ret <= 0) {
 701                 ret = -ETIMEDOUT;
 702                 kfree_skb(read_skb);
 703                 goto exit;
 704         }
 705
 706         if (!ack) {
 707                 ret = -EINVAL;
 708                 kfree_skb(read_skb);
 709                 goto exit;
 710         }
 711
 712         ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
 713                                 !(val & QCA8K_MDIO_MASTER_BUSY), 0,
 714                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 715                                 mgmt_eth_data, read_skb, &val);
 716
 717         if (ret < 0 && ret1 < 0) {
 718                 ret = ret1;
 719                 goto exit;
 720         }
 721
 722         if (read) {
 723                 reinit_completion(&mgmt_eth_data->rw_done);
 724
 725                 /* Increment seq_num and set it in the read pkt */
 726                 mgmt_eth_data->seq++;
 727                 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
 728                 mgmt_eth_data->ack = false;
 729
 730                 dev_queue_xmit(read_skb);
 731
 732                 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 733                                                   QCA8K_ETHERNET_TIMEOUT);
 734
 735                 ack = mgmt_eth_data->ack;
 736
 737                 if (ret <= 0) {
 738                         ret = -ETIMEDOUT;
 739                         goto exit;
 740                 }
 741
 742                 if (!ack) {
 743                         ret = -EINVAL;
 744                         goto exit;
 745                 }
 746
 747                 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
 748         } else {
 749                 kfree_skb(read_skb);
 750         }
 751 exit:
 752         reinit_completion(&mgmt_eth_data->rw_done);
 753
 754         /* Increment seq_num and set it in the clear pkt */
 755         mgmt_eth_data->seq++;
 756         qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
 757         mgmt_eth_data->ack = false;
 758
 759         dev_queue_xmit(clear_skb);
 760
 761         wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 762                                     QCA8K_ETHERNET_TIMEOUT);
 763
 764         mutex_unlock(&mgmt_eth_data->mutex);
 765
 766         return ret;
 767
 768         /* Error handling before lock */
 769 err_mgmt_master:
 770         kfree_skb(read_skb);
 771 err_read_skb:
 772         kfree_skb(clear_skb);
 773 err_clear_skb:
 774         kfree_skb(write_skb);
 775
 776         return ret;
 777 }
 778
 779 static int
 780 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 781 {
 782         u16 r1, r2, page;
 783         u32 val;
 784         int ret, ret1;
 785
 786         qca8k_split_addr(reg, &r1, &r2, &page);
 787
 788         ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
 789                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 790                                 bus, 0x10 | r2, r1 + 1, &val);
 791
 792         /* Check if qca8k_read has failed for a different reason
 793          * before returnting -ETIMEDOUT
 794          */
 795         if (ret < 0 && ret1 < 0)
 796                 return ret1;
 797
 798         return ret;
 799 }
 800
 801 static int
 802 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
 803 {
 804         struct mii_bus *bus = priv->bus;
 805         u16 r1, r2, page;
 806         u32 val;
 807         int ret;
 808
 809         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 810                 return -EINVAL;
 811
 812         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 813               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 814               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 815               QCA8K_MDIO_MASTER_DATA(data);
 816
 817         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 818
 819         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 820
 821         ret = qca8k_set_page(priv, page);
 822         if (ret)
 823                 goto exit;
 824
 825         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 826
 827         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 828                                    QCA8K_MDIO_MASTER_BUSY);
 829
 830 exit:
 831         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 832         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 833
 834         mutex_unlock(&bus->mdio_lock);
 835
 836         return ret;
 837 }
 838
 839 static int
 840 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 841 {
 842         struct mii_bus *bus = priv->bus;
 843         u16 r1, r2, page;
 844         u32 val;
 845         int ret;
 846
 847         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 848                 return -EINVAL;
 849
 850         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 851               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 852               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 853
 854         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 855
 856         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 857
 858         ret = qca8k_set_page(priv, page);
 859         if (ret)
 860                 goto exit;
 861
 862         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
 863
 864         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 865                                    QCA8K_MDIO_MASTER_BUSY);
 866         if (ret)
 867                 goto exit;
 868
 869         ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
 870
 871 exit:
 872         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 873         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 874
 875         mutex_unlock(&bus->mdio_lock);
 876
 877         if (ret >= 0)
 878                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 879
 880         return ret;
 881 }
 882
 883 static int
 884 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
 885 {
 886         struct qca8k_priv *priv = slave_bus->priv;
 887         int ret;
 888
 889         /* Use mdio Ethernet when available, fallback to legacy one on error */
 890         ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
 891         if (!ret)
 892                 return 0;
 893
 894         return qca8k_mdio_write(priv, phy, regnum, data);
 895 }
 896
 897 static int
 898 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
 899 {
 900         struct qca8k_priv *priv = slave_bus->priv;
 901         int ret;
 902
 903         /* Use mdio Ethernet when available, fallback to legacy one on error */
 904         ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
 905         if (ret >= 0)
 906                 return ret;
 907
 908         ret = qca8k_mdio_read(priv, phy, regnum);
 909
 910         if (ret < 0)
 911                 return 0xffff;
 912
 913         return ret;
 914 }
 915
 916 static int
 917 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
 918 {
 919         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 920
 921         return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
 922 }
 923
 924 static int
 925 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
 926 {
 927         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 928
 929         return qca8k_internal_mdio_read(slave_bus, port, regnum);
 930 }
 931
 932 static int
 933 qca8k_mdio_register(struct qca8k_priv *priv)
 934 {
 935         struct dsa_switch *ds = priv->ds;
 936         struct device_node *mdio;
 937         struct mii_bus *bus;
 938
 939         bus = devm_mdiobus_alloc(ds->dev);
 940         if (!bus)
 941                 return -ENOMEM;
 942
 943         bus->priv = (void *)priv;
 944         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
 945                  ds->dst->index, ds->index);
 946         bus->parent = ds->dev;
 947         bus->phy_mask = ~ds->phys_mii_mask;
 948         ds->slave_mii_bus = bus;
 949
 950         /* Check if the devicetree declare the port:phy mapping */
 951         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 952         if (of_device_is_available(mdio)) {
 953                 bus->name = "qca8k slave mii";
 954                 bus->read = qca8k_internal_mdio_read;
 955                 bus->write = qca8k_internal_mdio_write;
 956                 return devm_of_mdiobus_register(priv->dev, bus, mdio);
 957         }
 958
 959         /* If a mapping can't be found the legacy mapping is used,
 960          * using the qca8k_port_to_phy function
 961          */
 962         bus->name = "qca8k-legacy slave mii";
 963         bus->read = qca8k_legacy_mdio_read;
 964         bus->write = qca8k_legacy_mdio_write;
 965         return devm_mdiobus_register(priv->dev, bus);
 966 }
 967
 968 static int
 969 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 970 {
 971         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 972         struct device_node *ports, *port;
 973         phy_interface_t mode;
 974         int err;
 975
 976         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 977         if (!ports)
 978                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 979
 980         if (!ports)
 981                 return -EINVAL;
 982
 983         for_each_available_child_of_node(ports, port) {
 984                 err = of_property_read_u32(port, "reg", &reg);
 985                 if (err) {
 986                         of_node_put(port);
 987                         of_node_put(ports);
 988                         return err;
 989                 }
 990
 991                 if (!dsa_is_user_port(priv->ds, reg))
 992                         continue;
 993
 994                 of_get_phy_mode(port, &mode);
 995
 996                 if (of_property_read_bool(port, "phy-handle") &&
 997                     mode != PHY_INTERFACE_MODE_INTERNAL)
 998                         external_mdio_mask |= BIT(reg);
 999                 else
1000                         internal_mdio_mask |= BIT(reg);
1001         }
1002
1003         of_node_put(ports);
1004         if (!external_mdio_mask && !internal_mdio_mask) {
1005                 dev_err(priv->dev, "no PHYs are defined.\n");
1006                 return -EINVAL;
1007         }
1008
1009         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
1010          * the MDIO_MASTER register also _disconnects_ the external MDC
1011          * passthrough to the internal PHYs. It's not possible to use both
1012          * configurations at the same time!
1013          *
1014          * Because this came up during the review process:
1015          * If the external mdio-bus driver is capable magically disabling
1016          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
1017          * accessors for the time being, it would be possible to pull this
1018          * off.
1019          */
1020         if (!!external_mdio_mask && !!internal_mdio_mask) {
1021                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
1022                 return -EINVAL;
1023         }
1024
1025         if (external_mdio_mask) {
1026                 /* Make sure to disable the internal mdio bus in cases
1027                  * a dt-overlay and driver reload changed the configuration
1028                  */
1029
1030                 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
1031                                          QCA8K_MDIO_MASTER_EN);
1032         }
1033
1034         return qca8k_mdio_register(priv);
1035 }
1036
1037 static int
1038 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
1039 {
1040         u32 mask = 0;
1041         int ret = 0;
1042
1043         /* SoC specific settings for ipq8064.
1044          * If more device require this consider adding
1045          * a dedicated binding.
1046          */
1047         if (of_machine_is_compatible("qcom,ipq8064"))
1048                 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
1049
1050         /* SoC specific settings for ipq8065 */
1051         if (of_machine_is_compatible("qcom,ipq8065"))
1052                 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
1053
1054         if (mask) {
1055                 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
1056                                 QCA8K_MAC_PWR_RGMII0_1_8V |
1057                                 QCA8K_MAC_PWR_RGMII1_1_8V,
1058                                 mask);
1059         }
1060
1061         return ret;
1062 }
1063
1064 static int qca8k_find_cpu_port(struct dsa_switch *ds)
1065 {
1066         struct qca8k_priv *priv = ds->priv;
1067
1068         /* Find the connected cpu port. Valid port are 0 or 6 */
1069         if (dsa_is_cpu_port(ds, 0))
1070                 return 0;
1071
1072         dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
1073
1074         if (dsa_is_cpu_port(ds, 6))
1075                 return 6;
1076
1077         return -EINVAL;
1078 }
1079
1080 static int
1081 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
1082 {
1083         const struct qca8k_match_data *data = priv->info;
1084         struct device_node *node = priv->dev->of_node;
1085         u32 val = 0;
1086         int ret;
1087
1088         /* QCA8327 require to set to the correct mode.
1089          * His bigger brother QCA8328 have the 172 pin layout.
1090          * Should be applied by default but we set this just to make sure.
1091          */
1092         if (priv->switch_id == QCA8K_ID_QCA8327) {
1093                 /* Set the correct package of 148 pin for QCA8327 */
1094                 if (data->reduced_package)
1095                         val |= QCA8327_PWS_PACKAGE148_EN;
1096
1097                 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1098                                 val);
1099                 if (ret)
1100                         return ret;
1101         }
1102
1103         if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1104                 val |= QCA8K_PWS_POWER_ON_SEL;
1105
1106         if (of_property_read_bool(node, "qca,led-open-drain")) {
1107                 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1108                         dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1109                         return -EINVAL;
1110                 }
1111
1112                 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1113         }
1114
1115         return qca8k_rmw(priv, QCA8K_REG_PWS,
1116                         QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1117                         val);
1118 }
1119
1120 static int
1121 qca8k_parse_port_config(struct qca8k_priv *priv)
1122 {
1123         int port, cpu_port_index = -1, ret;
1124         struct device_node *port_dn;
1125         phy_interface_t mode;
1126         struct dsa_port *dp;
1127         u32 delay;
1128
1129         /* We have 2 CPU port. Check them */
1130         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1131                 /* Skip every other port */
1132                 if (port != 0 && port != 6)
1133                         continue;
1134
1135                 dp = dsa_to_port(priv->ds, port);
1136                 port_dn = dp->dn;
1137                 cpu_port_index++;
1138
1139                 if (!of_device_is_available(port_dn))
1140                         continue;
1141
1142                 ret = of_get_phy_mode(port_dn, &mode);
1143                 if (ret)
1144                         continue;
1145
1146                 switch (mode) {
1147                 case PHY_INTERFACE_MODE_RGMII:
1148                 case PHY_INTERFACE_MODE_RGMII_ID:
1149                 case PHY_INTERFACE_MODE_RGMII_TXID:
1150                 case PHY_INTERFACE_MODE_RGMII_RXID:
1151                 case PHY_INTERFACE_MODE_SGMII:
1152                         delay = 0;
1153
1154                         if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1155                                 /* Switch regs accept value in ns, convert ps to ns */
1156                                 delay = delay / 1000;
1157                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1158                                  mode == PHY_INTERFACE_MODE_RGMII_TXID)
1159                                 delay = 1;
1160
1161                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1162                                 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1163                                 delay = 3;
1164                         }
1165
1166                         priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1167
1168                         delay = 0;
1169
1170                         if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1171                                 /* Switch regs accept value in ns, convert ps to ns */
1172                                 delay = delay / 1000;
1173                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1174                                  mode == PHY_INTERFACE_MODE_RGMII_RXID)
1175                                 delay = 2;
1176
1177                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1178                                 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1179                                 delay = 3;
1180                         }
1181
1182                         priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1183
1184                         /* Skip sgmii parsing for rgmii* mode */
1185                         if (mode == PHY_INTERFACE_MODE_RGMII ||
1186                             mode == PHY_INTERFACE_MODE_RGMII_ID ||
1187                             mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1188                             mode == PHY_INTERFACE_MODE_RGMII_RXID)
1189                                 break;
1190
1191                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1192                                 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1193
1194                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1195                                 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1196
1197                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1198                                 priv->ports_config.sgmii_enable_pll = true;
1199
1200                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
1201                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1202                                         priv->ports_config.sgmii_enable_pll = false;
1203                                 }
1204
1205                                 if (priv->switch_revision < 2)
1206                                         dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1207                         }
1208
1209                         break;
1210                 default:
1211                         continue;
1212                 }
1213         }
1214
1215         return 0;
1216 }
1217
1218 static void
1219 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1220                                       u32 reg)
1221 {
1222         u32 delay, val = 0;
1223         int ret;
1224
1225         /* Delay can be declared in 3 different way.
1226          * Mode to rgmii and internal-delay standard binding defined
1227          * rgmii-id or rgmii-tx/rx phy mode set.
1228          * The parse logic set a delay different than 0 only when one
1229          * of the 3 different way is used. In all other case delay is
1230          * not enabled. With ID or TX/RXID delay is enabled and set
1231          * to the default and recommended value.
1232          */
1233         if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1234                 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1235
1236                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1237                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1238         }
1239
1240         if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1241                 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1242
1243                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1244                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1245         }
1246
1247         /* Set RGMII delay based on the selected values */
1248         ret = qca8k_rmw(priv, reg,
1249                         QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1250                         QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1251                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1252                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1253                         val);
1254         if (ret)
1255                 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1256                         cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1257 }
1258
1259 static struct phylink_pcs *
1260 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
1261                              phy_interface_t interface)
1262 {
1263         struct qca8k_priv *priv = ds->priv;
1264         struct phylink_pcs *pcs = NULL;
1265
1266         switch (interface) {
1267         case PHY_INTERFACE_MODE_SGMII:
1268         case PHY_INTERFACE_MODE_1000BASEX:
1269                 switch (port) {
1270                 case 0:
1271                         pcs = &priv->pcs_port_0.pcs;
1272                         break;
1273
1274                 case 6:
1275                         pcs = &priv->pcs_port_6.pcs;
1276                         break;
1277                 }
1278                 break;
1279
1280         default:
1281                 break;
1282         }
1283
1284         return pcs;
1285 }
1286
1287 static void
1288 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1289                          const struct phylink_link_state *state)
1290 {
1291         struct qca8k_priv *priv = ds->priv;
1292         int cpu_port_index;
1293         u32 reg;
1294
1295         switch (port) {
1296         case 0: /* 1st CPU port */
1297                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1298                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1299                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1300                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1301                     state->interface != PHY_INTERFACE_MODE_SGMII)
1302                         return;
1303
1304                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1305                 cpu_port_index = QCA8K_CPU_PORT0;
1306                 break;
1307         case 1:
1308         case 2:
1309         case 3:
1310         case 4:
1311         case 5:
1312                 /* Internal PHY, nothing to do */
1313                 return;
1314         case 6: /* 2nd CPU port / external PHY */
1315                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1316                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1317                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1318                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1319                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1320                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1321                         return;
1322
1323                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1324                 cpu_port_index = QCA8K_CPU_PORT6;
1325                 break;
1326         default:
1327                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1328                 return;
1329         }
1330
1331         if (port != 6 && phylink_autoneg_inband(mode)) {
1332                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1333                         __func__);
1334                 return;
1335         }
1336
1337         switch (state->interface) {
1338         case PHY_INTERFACE_MODE_RGMII:
1339         case PHY_INTERFACE_MODE_RGMII_ID:
1340         case PHY_INTERFACE_MODE_RGMII_TXID:
1341         case PHY_INTERFACE_MODE_RGMII_RXID:
1342                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1343
1344                 /* Configure rgmii delay */
1345                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1346
1347                 /* QCA8337 requires to set rgmii rx delay for all ports.
1348                  * This is enabled through PORT5_PAD_CTRL for all ports,
1349                  * rather than individual port registers.
1350                  */
1351                 if (priv->switch_id == QCA8K_ID_QCA8337)
1352                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1353                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1354                 break;
1355         case PHY_INTERFACE_MODE_SGMII:
1356         case PHY_INTERFACE_MODE_1000BASEX:
1357                 /* Enable SGMII on the port */
1358                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1359                 break;
1360         default:
1361                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1362                         phy_modes(state->interface), port);
1363                 return;
1364         }
1365 }
1366
1367 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port,
1368                                    struct phylink_config *config)
1369 {
1370         switch (port) {
1371         case 0: /* 1st CPU port */
1372                 phy_interface_set_rgmii(config->supported_interfaces);
1373                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1374                           config->supported_interfaces);
1375                 break;
1376
1377         case 1:
1378         case 2:
1379         case 3:
1380         case 4:
1381         case 5:
1382                 /* Internal PHY */
1383                 __set_bit(PHY_INTERFACE_MODE_GMII,
1384                           config->supported_interfaces);
1385                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1386                           config->supported_interfaces);
1387                 break;
1388
1389         case 6: /* 2nd CPU port / external PHY */
1390                 phy_interface_set_rgmii(config->supported_interfaces);
1391                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1392                           config->supported_interfaces);
1393                 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1394                           config->supported_interfaces);
1395                 break;
1396         }
1397
1398         config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1399                 MAC_10 | MAC_100 | MAC_1000FD;
1400
1401         config->legacy_pre_march2020 = false;
1402 }
1403
1404 static void
1405 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1406                             phy_interface_t interface)
1407 {
1408         struct qca8k_priv *priv = ds->priv;
1409
1410         qca8k_port_set_status(priv, port, 0);
1411 }
1412
1413 static void
1414 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1415                           phy_interface_t interface, struct phy_device *phydev,
1416                           int speed, int duplex, bool tx_pause, bool rx_pause)
1417 {
1418         struct qca8k_priv *priv = ds->priv;
1419         u32 reg;
1420
1421         if (phylink_autoneg_inband(mode)) {
1422                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1423         } else {
1424                 switch (speed) {
1425                 case SPEED_10:
1426                         reg = QCA8K_PORT_STATUS_SPEED_10;
1427                         break;
1428                 case SPEED_100:
1429                         reg = QCA8K_PORT_STATUS_SPEED_100;
1430                         break;
1431                 case SPEED_1000:
1432                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1433                         break;
1434                 default:
1435                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1436                         break;
1437                 }
1438
1439                 if (duplex == DUPLEX_FULL)
1440                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1441
1442                 if (rx_pause || dsa_is_cpu_port(ds, port))
1443                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1444
1445                 if (tx_pause || dsa_is_cpu_port(ds, port))
1446                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1447         }
1448
1449         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1450
1451         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1452 }
1453
1454 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
1455 {
1456         return container_of(pcs, struct qca8k_pcs, pcs);
1457 }
1458
1459 static void qca8k_pcs_get_state(struct phylink_pcs *pcs,
1460                                 struct phylink_link_state *state)
1461 {
1462         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1463         int port = pcs_to_qca8k_pcs(pcs)->port;
1464         u32 reg;
1465         int ret;
1466
1467         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1468         if (ret < 0) {
1469                 state->link = false;
1470                 return;
1471         }
1472
1473         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1474         state->an_complete = state->link;
1475         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1476                                                            DUPLEX_HALF;
1477
1478         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1479         case QCA8K_PORT_STATUS_SPEED_10:
1480                 state->speed = SPEED_10;
1481                 break;
1482         case QCA8K_PORT_STATUS_SPEED_100:
1483                 state->speed = SPEED_100;
1484                 break;
1485         case QCA8K_PORT_STATUS_SPEED_1000:
1486                 state->speed = SPEED_1000;
1487                 break;
1488         default:
1489                 state->speed = SPEED_UNKNOWN;
1490                 break;
1491         }
1492
1493         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1494                 state->pause |= MLO_PAUSE_RX;
1495         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1496                 state->pause |= MLO_PAUSE_TX;
1497 }
1498
1499 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
1500                             phy_interface_t interface,
1501                             const unsigned long *advertising,
1502                             bool permit_pause_to_mac)
1503 {
1504         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1505         int cpu_port_index, ret, port;
1506         u32 reg, val;
1507
1508         port = pcs_to_qca8k_pcs(pcs)->port;
1509         switch (port) {
1510         case 0:
1511                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1512                 cpu_port_index = QCA8K_CPU_PORT0;
1513                 break;
1514
1515         case 6:
1516                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1517                 cpu_port_index = QCA8K_CPU_PORT6;
1518                 break;
1519
1520         default:
1521                 WARN_ON(1);
1522                 return -EINVAL;
1523         }
1524
1525         /* Enable/disable SerDes auto-negotiation as necessary */
1526         val = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ?
1527                 0 : QCA8K_PWS_SERDES_AEN_DIS;
1528
1529         ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8K_PWS_SERDES_AEN_DIS, val);
1530         if (ret)
1531                 return ret;
1532
1533         /* Configure the SGMII parameters */
1534         ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1535         if (ret)
1536                 return ret;
1537
1538         val |= QCA8K_SGMII_EN_SD;
1539
1540         if (priv->ports_config.sgmii_enable_pll)
1541                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1542                        QCA8K_SGMII_EN_TX;
1543
1544         if (dsa_is_cpu_port(priv->ds, port)) {
1545                 /* CPU port, we're talking to the CPU MAC, be a PHY */
1546                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1547                 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1548         } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1549                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1550                 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1551         } else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1552                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1553                 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1554         }
1555
1556         qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1557
1558         /* From original code is reported port instability as SGMII also
1559          * require delay set. Apply advised values here or take them from DT.
1560          */
1561         if (interface == PHY_INTERFACE_MODE_SGMII)
1562                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1563         /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1564          * falling edge is set writing in the PORT0 PAD reg
1565          */
1566         if (priv->switch_id == QCA8K_ID_QCA8327 ||
1567             priv->switch_id == QCA8K_ID_QCA8337)
1568                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1569
1570         val = 0;
1571
1572         /* SGMII Clock phase configuration */
1573         if (priv->ports_config.sgmii_rx_clk_falling_edge)
1574                 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1575
1576         if (priv->ports_config.sgmii_tx_clk_falling_edge)
1577                 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1578
1579         if (val)
1580                 ret = qca8k_rmw(priv, reg,
1581                                 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1582                                 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1583                                 val);
1584
1585         return 0;
1586 }
1587
1588 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs)
1589 {
1590 }
1591
1592 static const struct phylink_pcs_ops qca8k_pcs_ops = {
1593         .pcs_get_state = qca8k_pcs_get_state,
1594         .pcs_config = qca8k_pcs_config,
1595         .pcs_an_restart = qca8k_pcs_an_restart,
1596 };
1597
1598 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs,
1599                             int port)
1600 {
1601         qpcs->pcs.ops = &qca8k_pcs_ops;
1602         qpcs->pcs.neg_mode = true;
1603
1604         /* We don't have interrupts for link changes, so we need to poll */
1605         qpcs->pcs.poll = true;
1606         qpcs->priv = priv;
1607         qpcs->port = port;
1608 }
1609
1610 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
1611 {
1612         struct qca8k_mib_eth_data *mib_eth_data;
1613         struct qca8k_priv *priv = ds->priv;
1614         const struct qca8k_mib_desc *mib;
1615         struct mib_ethhdr *mib_ethhdr;
1616         __le32 *data2;
1617         u8 port;
1618         int i;
1619
1620         mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
1621         mib_eth_data = &priv->mib_eth_data;
1622
1623         /* The switch autocast every port. Ignore other packet and
1624          * parse only the requested one.
1625          */
1626         port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
1627         if (port != mib_eth_data->req_port)
1628                 goto exit;
1629
1630         data2 = (__le32 *)skb->data;
1631
1632         for (i = 0; i < priv->info->mib_count; i++) {
1633                 mib = &ar8327_mib[i];
1634
1635                 /* First 3 mib are present in the skb head */
1636                 if (i < 3) {
1637                         mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i);
1638                         continue;
1639                 }
1640
1641                 /* Some mib are 64 bit wide */
1642                 if (mib->size == 2)
1643                         mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2);
1644                 else
1645                         mib_eth_data->data[i] = get_unaligned_le32(data2);
1646
1647                 data2 += mib->size;
1648         }
1649
1650 exit:
1651         /* Complete on receiving all the mib packet */
1652         if (refcount_dec_and_test(&mib_eth_data->port_parsed))
1653                 complete(&mib_eth_data->rw_done);
1654 }
1655
1656 static int
1657 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
1658 {
1659         struct dsa_port *dp = dsa_to_port(ds, port);
1660         struct qca8k_mib_eth_data *mib_eth_data;
1661         struct qca8k_priv *priv = ds->priv;
1662         int ret;
1663
1664         mib_eth_data = &priv->mib_eth_data;
1665
1666         mutex_lock(&mib_eth_data->mutex);
1667
1668         reinit_completion(&mib_eth_data->rw_done);
1669
1670         mib_eth_data->req_port = dp->index;
1671         mib_eth_data->data = data;
1672         refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
1673
1674         mutex_lock(&priv->reg_mutex);
1675
1676         /* Send mib autocast request */
1677         ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
1678                                  QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
1679                                  FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
1680                                  QCA8K_MIB_BUSY);
1681
1682         mutex_unlock(&priv->reg_mutex);
1683
1684         if (ret)
1685                 goto exit;
1686
1687         ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
1688
1689 exit:
1690         mutex_unlock(&mib_eth_data->mutex);
1691
1692         return ret;
1693 }
1694
1695 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1696 {
1697         struct qca8k_priv *priv = ds->priv;
1698
1699         /* Communicate to the phy internal driver the switch revision.
1700          * Based on the switch revision different values needs to be
1701          * set to the dbg and mmd reg on the phy.
1702          * The first 2 bit are used to communicate the switch revision
1703          * to the phy driver.
1704          */
1705         if (port > 0 && port < 6)
1706                 return priv->switch_revision;
1707
1708         return 0;
1709 }
1710
1711 static enum dsa_tag_protocol
1712 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1713                        enum dsa_tag_protocol mp)
1714 {
1715         return DSA_TAG_PROTO_QCA;
1716 }
1717
1718 static void
1719 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
1720                     bool operational)
1721 {
1722         struct dsa_port *dp = master->dsa_ptr;
1723         struct qca8k_priv *priv = ds->priv;
1724
1725         /* Ethernet MIB/MDIO is only supported for CPU port 0 */
1726         if (dp->index != 0)
1727                 return;
1728
1729         mutex_lock(&priv->mgmt_eth_data.mutex);
1730         mutex_lock(&priv->mib_eth_data.mutex);
1731
1732         priv->mgmt_master = operational ? (struct net_device *)master : NULL;
1733
1734         mutex_unlock(&priv->mib_eth_data.mutex);
1735         mutex_unlock(&priv->mgmt_eth_data.mutex);
1736 }
1737
1738 static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
1739                                       enum dsa_tag_protocol proto)
1740 {
1741         struct qca_tagger_data *tagger_data;
1742
1743         switch (proto) {
1744         case DSA_TAG_PROTO_QCA:
1745                 tagger_data = ds->tagger_data;
1746
1747                 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
1748                 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
1749
1750                 break;
1751         default:
1752                 return -EOPNOTSUPP;
1753         }
1754
1755         return 0;
1756 }
1757
1758 static int
1759 qca8k_setup(struct dsa_switch *ds)
1760 {
1761         struct qca8k_priv *priv = ds->priv;
1762         int cpu_port, ret, i;
1763         u32 mask;
1764
1765         cpu_port = qca8k_find_cpu_port(ds);
1766         if (cpu_port < 0) {
1767                 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1768                 return cpu_port;
1769         }
1770
1771         /* Parse CPU port config to be later used in phy_link mac_config */
1772         ret = qca8k_parse_port_config(priv);
1773         if (ret)
1774                 return ret;
1775
1776         ret = qca8k_setup_mdio_bus(priv);
1777         if (ret)
1778                 return ret;
1779
1780         ret = qca8k_setup_of_pws_reg(priv);
1781         if (ret)
1782                 return ret;
1783
1784         ret = qca8k_setup_mac_pwr_sel(priv);
1785         if (ret)
1786                 return ret;
1787
1788         ret = qca8k_setup_led_ctrl(priv);
1789         if (ret)
1790                 return ret;
1791
1792         qca8k_setup_pcs(priv, &priv->pcs_port_0, 0);
1793         qca8k_setup_pcs(priv, &priv->pcs_port_6, 6);
1794
1795         /* Make sure MAC06 is disabled */
1796         ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1797                                 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1798         if (ret) {
1799                 dev_err(priv->dev, "failed disabling MAC06 exchange");
1800                 return ret;
1801         }
1802
1803         /* Enable CPU Port */
1804         ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1805                               QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1806         if (ret) {
1807                 dev_err(priv->dev, "failed enabling CPU port");
1808                 return ret;
1809         }
1810
1811         /* Enable MIB counters */
1812         ret = qca8k_mib_init(priv);
1813         if (ret)
1814                 dev_warn(priv->dev, "mib init failed");
1815
1816         /* Initial setup of all ports */
1817         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1818                 /* Disable forwarding by default on all ports */
1819                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1820                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
1821                 if (ret)
1822                         return ret;
1823
1824                 /* Enable QCA header mode on all cpu ports */
1825                 if (dsa_is_cpu_port(ds, i)) {
1826                         ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1827                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1828                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1829                         if (ret) {
1830                                 dev_err(priv->dev, "failed enabling QCA header mode");
1831                                 return ret;
1832                         }
1833                 }
1834
1835                 /* Disable MAC by default on all user ports */
1836                 if (dsa_is_user_port(ds, i))
1837                         qca8k_port_set_status(priv, i, 0);
1838         }
1839
1840         /* Forward all unknown frames to CPU port for Linux processing
1841          * Notice that in multi-cpu config only one port should be set
1842          * for igmp, unknown, multicast and broadcast packet
1843          */
1844         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1845                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1846                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1847                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1848                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1849         if (ret)
1850                 return ret;
1851
1852         /* Setup connection between CPU port & user ports
1853          * Configure specific switch configuration for ports
1854          */
1855         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1856                 /* CPU port gets connected to all user ports of the switch */
1857                 if (dsa_is_cpu_port(ds, i)) {
1858                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1859                                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1860                         if (ret)
1861                                 return ret;
1862                 }
1863
1864                 /* Individual user ports get connected to CPU port only */
1865                 if (dsa_is_user_port(ds, i)) {
1866                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1867                                         QCA8K_PORT_LOOKUP_MEMBER,
1868                                         BIT(cpu_port));
1869                         if (ret)
1870                                 return ret;
1871
1872                         /* Enable ARP Auto-learning by default */
1873                         ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
1874                                               QCA8K_PORT_LOOKUP_LEARN);
1875                         if (ret)
1876                                 return ret;
1877
1878                         /* For port based vlans to work we need to set the
1879                          * default egress vid
1880                          */
1881                         ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1882                                         QCA8K_EGREES_VLAN_PORT_MASK(i),
1883                                         QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
1884                         if (ret)
1885                                 return ret;
1886
1887                         ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1888                                           QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1889                                           QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1890                         if (ret)
1891                                 return ret;
1892                 }
1893
1894                 /* The port 5 of the qca8337 have some problem in flood condition. The
1895                  * original legacy driver had some specific buffer and priority settings
1896                  * for the different port suggested by the QCA switch team. Add this
1897                  * missing settings to improve switch stability under load condition.
1898                  * This problem is limited to qca8337 and other qca8k switch are not affected.
1899                  */
1900                 if (priv->switch_id == QCA8K_ID_QCA8337) {
1901                         switch (i) {
1902                         /* The 2 CPU port and port 5 requires some different
1903                          * priority than any other ports.
1904                          */
1905                         case 0:
1906                         case 5:
1907                         case 6:
1908                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1909                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1910                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1911                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1912                                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1913                                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1914                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1915                                 break;
1916                         default:
1917                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1918                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1919                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1920                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1921                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1922                         }
1923                         qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1924
1925                         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1926                         QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1927                         QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1928                         QCA8K_PORT_HOL_CTRL1_WRED_EN;
1929                         qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1930                                   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1931                                   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1932                                   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1933                                   QCA8K_PORT_HOL_CTRL1_WRED_EN,
1934                                   mask);
1935                 }
1936         }
1937
1938         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1939         if (priv->switch_id == QCA8K_ID_QCA8327) {
1940                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1941                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1942                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1943                           QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1944                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1945                           mask);
1946         }
1947
1948         /* Setup our port MTUs to match power on defaults */
1949         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1950         if (ret)
1951                 dev_warn(priv->dev, "failed setting MTU settings");
1952
1953         /* Flush the FDB table */
1954         qca8k_fdb_flush(priv);
1955
1956         /* Set min a max ageing value supported */
1957         ds->ageing_time_min = 7000;
1958         ds->ageing_time_max = 458745000;
1959
1960         /* Set max number of LAGs supported */
1961         ds->num_lag_ids = QCA8K_NUM_LAGS;
1962
1963         return 0;
1964 }
1965
1966 static const struct dsa_switch_ops qca8k_switch_ops = {
1967         .get_tag_protocol       = qca8k_get_tag_protocol,
1968         .setup                  = qca8k_setup,
1969         .get_strings            = qca8k_get_strings,
1970         .get_ethtool_stats      = qca8k_get_ethtool_stats,
1971         .get_sset_count         = qca8k_get_sset_count,
1972         .set_ageing_time        = qca8k_set_ageing_time,
1973         .get_mac_eee            = qca8k_get_mac_eee,
1974         .set_mac_eee            = qca8k_set_mac_eee,
1975         .port_enable            = qca8k_port_enable,
1976         .port_disable           = qca8k_port_disable,
1977         .port_change_mtu        = qca8k_port_change_mtu,
1978         .port_max_mtu           = qca8k_port_max_mtu,
1979         .port_stp_state_set     = qca8k_port_stp_state_set,
1980         .port_bridge_join       = qca8k_port_bridge_join,
1981         .port_bridge_leave      = qca8k_port_bridge_leave,
1982         .port_fast_age          = qca8k_port_fast_age,
1983         .port_fdb_add           = qca8k_port_fdb_add,
1984         .port_fdb_del           = qca8k_port_fdb_del,
1985         .port_fdb_dump          = qca8k_port_fdb_dump,
1986         .port_mdb_add           = qca8k_port_mdb_add,
1987         .port_mdb_del           = qca8k_port_mdb_del,
1988         .port_mirror_add        = qca8k_port_mirror_add,
1989         .port_mirror_del        = qca8k_port_mirror_del,
1990         .port_vlan_filtering    = qca8k_port_vlan_filtering,
1991         .port_vlan_add          = qca8k_port_vlan_add,
1992         .port_vlan_del          = qca8k_port_vlan_del,
1993         .phylink_get_caps       = qca8k_phylink_get_caps,
1994         .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs,
1995         .phylink_mac_config     = qca8k_phylink_mac_config,
1996         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
1997         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
1998         .get_phy_flags          = qca8k_get_phy_flags,
1999         .port_lag_join          = qca8k_port_lag_join,
2000         .port_lag_leave         = qca8k_port_lag_leave,
2001         .master_state_change    = qca8k_master_change,
2002         .connect_tag_protocol   = qca8k_connect_tag_protocol,
2003 };
2004
2005 static int
2006 qca8k_sw_probe(struct mdio_device *mdiodev)
2007 {
2008         struct qca8k_priv *priv;
2009         int ret;
2010
2011         /* allocate the private data struct so that we can probe the switches
2012          * ID register
2013          */
2014         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2015         if (!priv)
2016                 return -ENOMEM;
2017
2018         priv->bus = mdiodev->bus;
2019         priv->dev = &mdiodev->dev;
2020         priv->info = of_device_get_match_data(priv->dev);
2021
2022         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2023                                                    GPIOD_ASIS);
2024         if (IS_ERR(priv->reset_gpio))
2025                 return PTR_ERR(priv->reset_gpio);
2026
2027         if (priv->reset_gpio) {
2028                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2029                 /* The active low duration must be greater than 10 ms
2030                  * and checkpatch.pl wants 20 ms.
2031                  */
2032                 msleep(20);
2033                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2034         }
2035
2036         /* Start by setting up the register mapping */
2037         priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
2038                                         &qca8k_regmap_config);
2039         if (IS_ERR(priv->regmap)) {
2040                 dev_err(priv->dev, "regmap initialization failed");
2041                 return PTR_ERR(priv->regmap);
2042         }
2043
2044         priv->mdio_cache.page = 0xffff;
2045
2046         /* Check the detected switch id */
2047         ret = qca8k_read_switch_id(priv);
2048         if (ret)
2049                 return ret;
2050
2051         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2052         if (!priv->ds)
2053                 return -ENOMEM;
2054
2055         mutex_init(&priv->mgmt_eth_data.mutex);
2056         init_completion(&priv->mgmt_eth_data.rw_done);
2057
2058         mutex_init(&priv->mib_eth_data.mutex);
2059         init_completion(&priv->mib_eth_data.rw_done);
2060
2061         priv->ds->dev = &mdiodev->dev;
2062         priv->ds->num_ports = QCA8K_NUM_PORTS;
2063         priv->ds->priv = priv;
2064         priv->ds->ops = &qca8k_switch_ops;
2065         mutex_init(&priv->reg_mutex);
2066         dev_set_drvdata(&mdiodev->dev, priv);
2067
2068         return dsa_register_switch(priv->ds);
2069 }
2070
2071 static void
2072 qca8k_sw_remove(struct mdio_device *mdiodev)
2073 {
2074         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2075         int i;
2076
2077         if (!priv)
2078                 return;
2079
2080         for (i = 0; i < QCA8K_NUM_PORTS; i++)
2081                 qca8k_port_set_status(priv, i, 0);
2082
2083         dsa_unregister_switch(priv->ds);
2084 }
2085
2086 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2087 {
2088         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2089
2090         if (!priv)
2091                 return;
2092
2093         dsa_switch_shutdown(priv->ds);
2094
2095         dev_set_drvdata(&mdiodev->dev, NULL);
2096 }
2097
2098 #ifdef CONFIG_PM_SLEEP
2099 static void
2100 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2101 {
2102         int port;
2103
2104         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
2105                 /* Do not enable on resume if the port was
2106                  * disabled before.
2107                  */
2108                 if (!(priv->port_enabled_map & BIT(port)))
2109                         continue;
2110
2111                 qca8k_port_set_status(priv, port, enable);
2112         }
2113 }
2114
2115 static int qca8k_suspend(struct device *dev)
2116 {
2117         struct qca8k_priv *priv = dev_get_drvdata(dev);
2118
2119         qca8k_set_pm(priv, 0);
2120
2121         return dsa_switch_suspend(priv->ds);
2122 }
2123
2124 static int qca8k_resume(struct device *dev)
2125 {
2126         struct qca8k_priv *priv = dev_get_drvdata(dev);
2127
2128         qca8k_set_pm(priv, 1);
2129
2130         return dsa_switch_resume(priv->ds);
2131 }
2132 #endif /* CONFIG_PM_SLEEP */
2133
2134 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2135                          qca8k_suspend, qca8k_resume);
2136
2137 static const struct qca8k_info_ops qca8xxx_ops = {
2138         .autocast_mib = qca8k_get_ethtool_stats_eth,
2139 };
2140
2141 static const struct qca8k_match_data qca8327 = {
2142         .id = QCA8K_ID_QCA8327,
2143         .reduced_package = true,
2144         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2145         .ops = &qca8xxx_ops,
2146 };
2147
2148 static const struct qca8k_match_data qca8328 = {
2149         .id = QCA8K_ID_QCA8327,
2150         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2151         .ops = &qca8xxx_ops,
2152 };
2153
2154 static const struct qca8k_match_data qca833x = {
2155         .id = QCA8K_ID_QCA8337,
2156         .mib_count = QCA8K_QCA833X_MIB_COUNT,
2157         .ops = &qca8xxx_ops,
2158 };
2159
2160 static const struct of_device_id qca8k_of_match[] = {
2161         { .compatible = "qca,qca8327", .data = &qca8327 },
2162         { .compatible = "qca,qca8328", .data = &qca8328 },
2163         { .compatible = "qca,qca8334", .data = &qca833x },
2164         { .compatible = "qca,qca8337", .data = &qca833x },
2165         { /* sentinel */ },
2166 };
2167
2168 static struct mdio_driver qca8kmdio_driver = {
2169         .probe  = qca8k_sw_probe,
2170         .remove = qca8k_sw_remove,
2171         .shutdown = qca8k_sw_shutdown,
2172         .mdiodrv.driver = {
2173                 .name = "qca8k",
2174                 .of_match_table = qca8k_of_match,
2175                 .pm = &qca8k_pm_ops,
2176         },
2177 };
2178
2179 mdio_module_driver(qca8kmdio_driver);
2180
2181 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
2182 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2183 MODULE_LICENSE("GPL v2");
2184 MODULE_ALIAS("platform:qca8k");