1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
12 * | MAC2-|----RMII--------| PHY1 |-o P1
15 * | MAC3-|----RMII--------| PHY2 |-o P2
18 * | MAC4-|----RMII--------| PHY3 |-o P3
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on
28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be
29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled.
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this
33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register
39 * set and not related to switch internal registers.
42 #include <linux/bitfield.h>
43 #include <linux/module.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_mdio.h>
46 #include <linux/regmap.h>
47 #include <linux/reset.h>
50 #define AR9331_SW_NAME "ar9331_switch"
51 #define AR9331_SW_PORTS 6
53 /* dummy reg to change page */
54 #define AR9331_SW_REG_PAGE 0x40000
56 /* Global Interrupt */
57 #define AR9331_SW_REG_GINT 0x10
58 #define AR9331_SW_REG_GINT_MASK 0x14
59 #define AR9331_SW_GINT_PHY_INT BIT(2)
61 #define AR9331_SW_REG_FLOOD_MASK 0x2c
62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30
65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
67 #define AR9331_SW_REG_MDIO_CTRL 0x98
68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
78 * If not set, mac can be config by software.
80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
82 /* LINK_EN - If set, MAC is configured from PHY link status.
83 * If not set, MAC should be configured by software.
85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2
93 #define AR9331_SW_PORT_STATUS_SPEED_100 1
94 #define AR9331_SW_PORT_STATUS_SPEED_10 0
96 #define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
99 #define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
104 #define AR9331_SW_REG_PORT_CTRL(_port) (0x104 + (_port) * 0x100)
105 #define AR9331_SW_PORT_CTRL_HEAD_EN BIT(11)
106 #define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0)
107 #define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED 0
108 #define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING 1
109 #define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING 2
110 #define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING 3
111 #define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD 4
113 #define AR9331_SW_REG_PORT_VLAN(_port) (0x108 + (_port) * 0x100)
114 #define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30)
115 #define AR9331_SW_8021Q_MODE_SECURE 3
116 #define AR9331_SW_8021Q_MODE_CHECK 2
117 #define AR9331_SW_8021Q_MODE_FALLBACK 1
118 #define AR9331_SW_8021Q_MODE_NONE 0
119 #define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16)
122 #define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100))
125 * ------------------------------------------------------------------------
126 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
128 * real | start | OP | PhyAddr | Reg Addr | TA |
129 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA |
132 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
136 * ------------------------------------------------------------------------
138 * ------------------------------------------------------------------------
139 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
140 * real | start | OP | PhyAddr | Reg Addr | TA |
141 * atheros| start | OP | 2'b11 | 8'b0 | TA |
143 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
145 * atheros| | Page [9:0] |
147 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be
148 * written to bits[9:0] of mdio data register.
150 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
152 /* ------------------------------------------------------------------------
153 * Normal register access mode
154 * ------------------------------------------------------------------------
155 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
156 * real | start | OP | PhyAddr | Reg Addr | TA |
157 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA |
159 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
162 * ------------------------------------------------------------------------
164 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
165 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
167 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
168 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3
169 #define AR9331_SW_MDIO_PHY_MODE_REG 2
170 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
171 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
173 /* Empirical determined values */
174 #define AR9331_SW_MDIO_POLL_SLEEP_US 1
175 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
177 /* The interval should be small enough to avoid overflow of 32bit MIBs */
179 * FIXME: until we can read MIBs from stats64 call directly (i.e. sleep
180 * there), we have to poll stats more frequently then it is actually needed.
181 * For overflow protection, normally, 100 sec interval should have been OK.
183 #define STATS_INTERVAL_JIFFIES (3 * HZ)
185 struct ar9331_sw_stats_raw {
186 u32 rxbroad; /* 0x00 */
187 u32 rxpause; /* 0x04 */
188 u32 rxmulti; /* 0x08 */
189 u32 rxfcserr; /* 0x0c */
190 u32 rxalignerr; /* 0x10 */
191 u32 rxrunt; /* 0x14 */
192 u32 rxfragment; /* 0x18 */
193 u32 rx64byte; /* 0x1c */
194 u32 rx128byte; /* 0x20 */
195 u32 rx256byte; /* 0x24 */
196 u32 rx512byte; /* 0x28 */
197 u32 rx1024byte; /* 0x2c */
198 u32 rx1518byte; /* 0x30 */
199 u32 rxmaxbyte; /* 0x34 */
200 u32 rxtoolong; /* 0x38 */
201 u32 rxgoodbyte; /* 0x3c */
203 u32 rxbadbyte; /* 0x44 */
205 u32 rxoverflow; /* 0x4c */
206 u32 filtered; /* 0x50 */
207 u32 txbroad; /* 0x54 */
208 u32 txpause; /* 0x58 */
209 u32 txmulti; /* 0x5c */
210 u32 txunderrun; /* 0x60 */
211 u32 tx64byte; /* 0x64 */
212 u32 tx128byte; /* 0x68 */
213 u32 tx256byte; /* 0x6c */
214 u32 tx512byte; /* 0x70 */
215 u32 tx1024byte; /* 0x74 */
216 u32 tx1518byte; /* 0x78 */
217 u32 txmaxbyte; /* 0x7c */
218 u32 txoversize; /* 0x80 */
219 u32 txbyte; /* 0x84 */
221 u32 txcollision; /* 0x8c */
222 u32 txabortcol; /* 0x90 */
223 u32 txmulticol; /* 0x94 */
224 u32 txsinglecol; /* 0x98 */
225 u32 txexcdefer; /* 0x9c */
226 u32 txdefer; /* 0xa0 */
227 u32 txlatecol; /* 0xa4 */
230 struct ar9331_sw_port {
232 struct delayed_work mib_read;
233 struct rtnl_link_stats64 stats;
234 struct spinlock stats_lock;
237 struct ar9331_sw_priv {
239 struct dsa_switch ds;
240 struct dsa_switch_ops ops;
241 struct irq_domain *irqdomain;
243 struct mutex lock_irq;
244 struct mii_bus *mbus; /* mdio master */
245 struct mii_bus *sbus; /* mdio slave */
246 struct regmap *regmap;
247 struct reset_control *sw_reset;
248 struct ar9331_sw_port port[AR9331_SW_PORTS];
251 static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
253 struct ar9331_sw_port *p = port - port->idx;
255 return (struct ar9331_sw_priv *)((void *)p -
256 offsetof(struct ar9331_sw_priv, port));
259 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
260 * If some kind of optimization is used, the request should be repeated.
262 static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
266 ret = reset_control_assert(priv->sw_reset);
270 /* AR9331 doc do not provide any information about proper reset
271 * sequence. The AR8136 (the closes switch to the AR9331) doc says:
272 * reset duration should be greater than 10ms. So, let's use this value
275 usleep_range(10000, 15000);
276 ret = reset_control_deassert(priv->sw_reset);
279 /* There is no information on how long should we wait after reset.
280 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load
281 * status. AR9331 has no EEPROM support.
282 * For now, do not wait. In case AR8136 will be needed, the after
283 * reset delay can be added as well.
288 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
292 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
295 struct ar9331_sw_priv *priv = mbus->priv;
296 struct regmap *regmap = priv->regmap;
300 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
301 AR9331_SW_MDIO_CTRL_BUSY |
302 AR9331_SW_MDIO_CTRL_MASTER_EN |
303 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
304 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
305 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
309 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
310 !(val & AR9331_SW_MDIO_CTRL_BUSY),
311 AR9331_SW_MDIO_POLL_SLEEP_US,
312 AR9331_SW_MDIO_POLL_TIMEOUT_US);
318 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
322 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
324 struct ar9331_sw_priv *priv = mbus->priv;
325 struct regmap *regmap = priv->regmap;
329 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
330 AR9331_SW_MDIO_CTRL_BUSY |
331 AR9331_SW_MDIO_CTRL_MASTER_EN |
332 AR9331_SW_MDIO_CTRL_CMD_READ |
333 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
334 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
338 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
339 !(val & AR9331_SW_MDIO_CTRL_BUSY),
340 AR9331_SW_MDIO_POLL_SLEEP_US,
341 AR9331_SW_MDIO_POLL_TIMEOUT_US);
345 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
349 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
352 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
356 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
358 struct device *dev = priv->dev;
359 struct mii_bus *mbus;
360 struct device_node *np, *mnp;
365 mbus = devm_mdiobus_alloc(dev);
369 mbus->name = np->full_name;
370 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
372 mbus->read = ar9331_sw_mbus_read;
373 mbus->write = ar9331_sw_mbus_write;
377 mnp = of_get_child_by_name(np, "mdio");
381 ret = of_mdiobus_register(mbus, mnp);
391 static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
393 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
394 struct regmap *regmap = priv->regmap;
395 u32 port_mask, port_ctrl, val;
398 /* Generate default port settings */
399 port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE,
400 AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD);
402 if (dsa_is_cpu_port(ds, port)) {
403 /* CPU port should be allowed to communicate with all user
406 port_mask = dsa_user_ports(ds);
407 /* Enable Atheros header on CPU port. This will allow us
408 * communicate with each port separately
410 port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN;
411 } else if (dsa_is_user_port(ds, port)) {
412 /* User ports should communicate only with the CPU port.
414 port_mask = BIT(dsa_upstream_port(ds, port));
416 /* Other ports do not need to communicate at all */
420 val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE,
421 AR9331_SW_8021Q_MODE_NONE) |
422 FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask);
424 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
428 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
434 dev_err(priv->dev, "%s: error: %i\n", __func__, ret);
439 static int ar9331_sw_setup(struct dsa_switch *ds)
441 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
442 struct regmap *regmap = priv->regmap;
445 ret = ar9331_sw_reset(priv);
449 /* Reset will set proper defaults. CPU - Port0 will be enabled and
450 * configured. All other ports (ports 1 - 5) are disabled
452 ret = ar9331_sw_mbus_init(priv);
456 /* Do not drop broadcast frames */
457 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
458 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
459 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
463 /* Set max frame size to the maximum supported value */
464 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
465 AR9331_SW_GLOBAL_CTRL_MFS_M,
466 AR9331_SW_GLOBAL_CTRL_MFS_M);
470 for (i = 0; i < ds->num_ports; i++) {
471 ret = ar9331_sw_setup_port(ds, i);
476 ds->configure_vlan_while_not_filtering = false;
480 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
484 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
486 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
487 struct regmap *regmap = priv->regmap;
490 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
492 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
495 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
497 enum dsa_tag_protocol m)
499 return DSA_TAG_PROTO_AR9331;
502 static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port,
503 unsigned long *supported,
504 struct phylink_link_state *state)
506 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
510 if (state->interface != PHY_INTERFACE_MODE_GMII)
513 phylink_set(mask, 1000baseT_Full);
514 phylink_set(mask, 1000baseT_Half);
521 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
525 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
526 dev_err(ds->dev, "Unsupported port: %i\n", port);
530 phylink_set_port_modes(mask);
531 phylink_set(mask, Pause);
532 phylink_set(mask, Asym_Pause);
534 phylink_set(mask, 10baseT_Half);
535 phylink_set(mask, 10baseT_Full);
536 phylink_set(mask, 100baseT_Half);
537 phylink_set(mask, 100baseT_Full);
539 bitmap_and(supported, supported, mask,
540 __ETHTOOL_LINK_MODE_MASK_NBITS);
541 bitmap_and(state->advertising, state->advertising, mask,
542 __ETHTOOL_LINK_MODE_MASK_NBITS);
547 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
548 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n",
549 state->interface, port);
552 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
554 const struct phylink_link_state *state)
556 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
557 struct regmap *regmap = priv->regmap;
560 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
561 AR9331_SW_PORT_STATUS_LINK_EN |
562 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
564 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
567 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
569 phy_interface_t interface)
571 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
572 struct ar9331_sw_port *p = &priv->port[port];
573 struct regmap *regmap = priv->regmap;
576 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
577 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
579 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
581 cancel_delayed_work_sync(&p->mib_read);
584 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
586 phy_interface_t interface,
587 struct phy_device *phydev,
588 int speed, int duplex,
589 bool tx_pause, bool rx_pause)
591 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
592 struct ar9331_sw_port *p = &priv->port[port];
593 struct regmap *regmap = priv->regmap;
597 schedule_delayed_work(&p->mib_read, 0);
599 val = AR9331_SW_PORT_STATUS_MAC_MASK;
602 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
605 val |= AR9331_SW_PORT_STATUS_SPEED_100;
608 val |= AR9331_SW_PORT_STATUS_SPEED_10;
615 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
618 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
621 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
623 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
624 AR9331_SW_PORT_STATUS_MAC_MASK |
625 AR9331_SW_PORT_STATUS_LINK_MASK,
628 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
631 static void ar9331_read_stats(struct ar9331_sw_port *port)
633 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
634 struct rtnl_link_stats64 *stats = &port->stats;
635 struct ar9331_sw_stats_raw raw;
638 /* Do the slowest part first, to avoid needless locking for long time */
639 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
640 &raw, sizeof(raw) / sizeof(u32));
642 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
645 /* All MIB counters are cleared automatically on read */
647 spin_lock(&port->stats_lock);
649 stats->rx_bytes += raw.rxgoodbyte;
650 stats->tx_bytes += raw.txbyte;
652 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
653 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
654 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
655 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
657 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
658 stats->rx_crc_errors += raw.rxfcserr;
659 stats->rx_frame_errors += raw.rxalignerr;
660 stats->rx_missed_errors += raw.rxoverflow;
661 stats->rx_dropped += raw.filtered;
662 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
663 raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
665 stats->tx_window_errors += raw.txlatecol;
666 stats->tx_fifo_errors += raw.txunderrun;
667 stats->tx_aborted_errors += raw.txabortcol;
668 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
671 stats->multicast += raw.rxmulti;
672 stats->collisions += raw.txcollision;
674 spin_unlock(&port->stats_lock);
677 static void ar9331_do_stats_poll(struct work_struct *work)
679 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
682 ar9331_read_stats(port);
684 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
687 static void ar9331_get_stats64(struct dsa_switch *ds, int port,
688 struct rtnl_link_stats64 *s)
690 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
691 struct ar9331_sw_port *p = &priv->port[port];
693 spin_lock(&p->stats_lock);
694 memcpy(s, &p->stats, sizeof(*s));
695 spin_unlock(&p->stats_lock);
698 static const struct dsa_switch_ops ar9331_sw_ops = {
699 .get_tag_protocol = ar9331_sw_get_tag_protocol,
700 .setup = ar9331_sw_setup,
701 .port_disable = ar9331_sw_port_disable,
702 .phylink_validate = ar9331_sw_phylink_validate,
703 .phylink_mac_config = ar9331_sw_phylink_mac_config,
704 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
705 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
706 .get_stats64 = ar9331_get_stats64,
709 static irqreturn_t ar9331_sw_irq(int irq, void *data)
711 struct ar9331_sw_priv *priv = data;
712 struct regmap *regmap = priv->regmap;
716 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
718 dev_err(priv->dev, "can't read interrupt status\n");
725 if (stat & AR9331_SW_GINT_PHY_INT) {
728 child_irq = irq_find_mapping(priv->irqdomain, 0);
729 handle_nested_irq(child_irq);
732 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
734 dev_err(priv->dev, "can't write interrupt status\n");
741 static void ar9331_sw_mask_irq(struct irq_data *d)
743 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
748 static void ar9331_sw_unmask_irq(struct irq_data *d)
750 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
752 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
755 static void ar9331_sw_irq_bus_lock(struct irq_data *d)
757 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
759 mutex_lock(&priv->lock_irq);
762 static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
764 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
765 struct regmap *regmap = priv->regmap;
768 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
769 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
771 dev_err(priv->dev, "failed to change IRQ mask\n");
773 mutex_unlock(&priv->lock_irq);
776 static struct irq_chip ar9331_sw_irq_chip = {
777 .name = AR9331_SW_NAME,
778 .irq_mask = ar9331_sw_mask_irq,
779 .irq_unmask = ar9331_sw_unmask_irq,
780 .irq_bus_lock = ar9331_sw_irq_bus_lock,
781 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
784 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
785 irq_hw_number_t hwirq)
787 irq_set_chip_data(irq, domain->host_data);
788 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
789 irq_set_nested_thread(irq, 1);
790 irq_set_noprobe(irq);
795 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
797 irq_set_nested_thread(irq, 0);
798 irq_set_chip_and_handler(irq, NULL, NULL);
799 irq_set_chip_data(irq, NULL);
802 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
803 .map = ar9331_sw_irq_map,
804 .unmap = ar9331_sw_irq_unmap,
805 .xlate = irq_domain_xlate_onecell,
808 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
810 struct device_node *np = priv->dev->of_node;
811 struct device *dev = priv->dev;
814 irq = of_irq_get(np, 0);
816 dev_err(dev, "failed to get parent IRQ\n");
817 return irq ? irq : -EINVAL;
820 mutex_init(&priv->lock_irq);
821 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
822 IRQF_ONESHOT, AR9331_SW_NAME, priv);
824 dev_err(dev, "unable to request irq: %d\n", ret);
828 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
830 if (!priv->irqdomain) {
831 dev_err(dev, "failed to create IRQ domain\n");
835 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
840 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
844 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
845 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
846 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
848 return mdiobus_write(sbus, p, r, val);
851 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
855 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
856 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
857 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
859 return mdiobus_read(sbus, p, r);
862 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
863 void *val_buf, size_t val_len)
865 struct ar9331_sw_priv *priv = ctx;
866 struct mii_bus *sbus = priv->sbus;
867 u32 reg = *(u32 *)reg_buf;
870 if (reg == AR9331_SW_REG_PAGE) {
871 /* We cannot read the page selector register from hardware and
872 * we cache its value in regmap. Return all bits set here,
873 * that regmap will always write the page on first use.
875 *(u32 *)val_buf = GENMASK(9, 0);
879 ret = __ar9331_mdio_read(sbus, reg);
883 *(u32 *)val_buf = ret;
884 ret = __ar9331_mdio_read(sbus, reg + 2);
888 *(u32 *)val_buf |= ret << 16;
892 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
896 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
898 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
899 struct mii_bus *sbus = priv->sbus;
902 if (reg == AR9331_SW_REG_PAGE) {
903 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
911 /* In case of this switch we work with 32bit registers on top of 16bit
912 * bus. Some registers (for example access to forwarding database) have
913 * trigger bit on the first 16bit half of request, the result and
914 * configuration of request in the second half.
915 * To make it work properly, we should do the second part of transfer
916 * before the first one is done.
918 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
923 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
930 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
934 static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
936 u32 reg = *(u32 *)data;
937 u32 val = *((u32 *)data + 1);
939 return ar9331_mdio_write(context, reg, val);
942 static const struct regmap_range ar9331_valid_regs[] = {
943 regmap_reg_range(0x0, 0x0),
944 regmap_reg_range(0x10, 0x14),
945 regmap_reg_range(0x20, 0x24),
946 regmap_reg_range(0x2c, 0x30),
947 regmap_reg_range(0x40, 0x44),
948 regmap_reg_range(0x50, 0x78),
949 regmap_reg_range(0x80, 0x98),
951 regmap_reg_range(0x100, 0x120),
952 regmap_reg_range(0x200, 0x220),
953 regmap_reg_range(0x300, 0x320),
954 regmap_reg_range(0x400, 0x420),
955 regmap_reg_range(0x500, 0x520),
956 regmap_reg_range(0x600, 0x620),
958 regmap_reg_range(0x20000, 0x200a4),
959 regmap_reg_range(0x20100, 0x201a4),
960 regmap_reg_range(0x20200, 0x202a4),
961 regmap_reg_range(0x20300, 0x203a4),
962 regmap_reg_range(0x20400, 0x204a4),
963 regmap_reg_range(0x20500, 0x205a4),
965 /* dummy page selector reg */
966 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
969 static const struct regmap_range ar9331_nonvolatile_regs[] = {
970 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
973 static const struct regmap_range_cfg ar9331_regmap_range[] = {
975 .selector_reg = AR9331_SW_REG_PAGE,
976 .selector_mask = GENMASK(9, 0),
983 .range_max = AR9331_SW_REG_PAGE - 4,
987 static const struct regmap_access_table ar9331_register_set = {
988 .yes_ranges = ar9331_valid_regs,
989 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
992 static const struct regmap_access_table ar9331_volatile_set = {
993 .no_ranges = ar9331_nonvolatile_regs,
994 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
997 static const struct regmap_config ar9331_mdio_regmap_config = {
1001 .max_register = AR9331_SW_REG_PAGE,
1003 .ranges = ar9331_regmap_range,
1004 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
1006 .volatile_table = &ar9331_volatile_set,
1007 .wr_table = &ar9331_register_set,
1008 .rd_table = &ar9331_register_set,
1010 .cache_type = REGCACHE_RBTREE,
1013 static struct regmap_bus ar9331_sw_bus = {
1014 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
1015 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1016 .read = ar9331_mdio_read,
1017 .write = ar9331_sw_bus_write,
1022 static int ar9331_sw_probe(struct mdio_device *mdiodev)
1024 struct ar9331_sw_priv *priv;
1025 struct dsa_switch *ds;
1028 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1032 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
1033 &ar9331_mdio_regmap_config);
1034 if (IS_ERR(priv->regmap)) {
1035 ret = PTR_ERR(priv->regmap);
1036 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
1040 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
1041 if (IS_ERR(priv->sw_reset)) {
1042 dev_err(&mdiodev->dev, "missing switch reset\n");
1043 return PTR_ERR(priv->sw_reset);
1046 priv->sbus = mdiodev->bus;
1047 priv->dev = &mdiodev->dev;
1049 ret = ar9331_sw_irq_init(priv);
1054 ds->dev = &mdiodev->dev;
1055 ds->num_ports = AR9331_SW_PORTS;
1057 priv->ops = ar9331_sw_ops;
1058 ds->ops = &priv->ops;
1059 dev_set_drvdata(&mdiodev->dev, priv);
1061 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1062 struct ar9331_sw_port *port = &priv->port[i];
1065 spin_lock_init(&port->stats_lock);
1066 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1069 ret = dsa_register_switch(ds);
1071 goto err_remove_irq;
1076 irq_domain_remove(priv->irqdomain);
1081 static void ar9331_sw_remove(struct mdio_device *mdiodev)
1083 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1086 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1087 struct ar9331_sw_port *port = &priv->port[i];
1089 cancel_delayed_work_sync(&port->mib_read);
1092 irq_domain_remove(priv->irqdomain);
1093 mdiobus_unregister(priv->mbus);
1094 dsa_unregister_switch(&priv->ds);
1096 reset_control_assert(priv->sw_reset);
1099 static const struct of_device_id ar9331_sw_of_match[] = {
1100 { .compatible = "qca,ar9331-switch" },
1104 static struct mdio_driver ar9331_sw_mdio_driver = {
1105 .probe = ar9331_sw_probe,
1106 .remove = ar9331_sw_remove,
1108 .name = AR9331_SW_NAME,
1109 .of_match_table = ar9331_sw_of_match,
1113 mdio_module_driver(ar9331_sw_mdio_driver);
1115 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1116 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1117 MODULE_LICENSE("GPL v2");