drivers/net/dsa/ocelot/felix_vsc9959.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright 2017 Microsemi Corporation
   3  * Copyright 2018-2019 NXP
   4  */
   5 #include <linux/fsl/enetc_mdio.h>
   6 #include <soc/mscc/ocelot_qsys.h>
   7 #include <soc/mscc/ocelot_vcap.h>
   8 #include <soc/mscc/ocelot_ana.h>
   9 #include <soc/mscc/ocelot_ptp.h>
  10 #include <soc/mscc/ocelot_sys.h>
  11 #include <net/tc_act/tc_gate.h>
  12 #include <soc/mscc/ocelot.h>
  13 #include <linux/dsa/ocelot.h>
  14 #include <linux/pcs-lynx.h>
  15 #include <net/pkt_sched.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/mdio.h>
  18 #include <linux/pci.h>
  19 #include <linux/time.h>
  20 #include "felix.h"
  21
  22 #define VSC9959_NUM_PORTS               6
  23
  24 #define VSC9959_TAS_GCL_ENTRY_MAX       63
  25 #define VSC9959_VCAP_POLICER_BASE       63
  26 #define VSC9959_VCAP_POLICER_MAX        383
  27 #define VSC9959_SWITCH_PCI_BAR          4
  28 #define VSC9959_IMDIO_PCI_BAR           0
  29
  30 #define VSC9959_PORT_MODE_SERDES        (OCELOT_PORT_MODE_SGMII | \
  31                                          OCELOT_PORT_MODE_QSGMII | \
  32                                          OCELOT_PORT_MODE_1000BASEX | \
  33                                          OCELOT_PORT_MODE_2500BASEX | \
  34                                          OCELOT_PORT_MODE_USXGMII)
  35
  36 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
  37         VSC9959_PORT_MODE_SERDES,
  38         VSC9959_PORT_MODE_SERDES,
  39         VSC9959_PORT_MODE_SERDES,
  40         VSC9959_PORT_MODE_SERDES,
  41         OCELOT_PORT_MODE_INTERNAL,
  42         OCELOT_PORT_MODE_INTERNAL,
  43 };
  44
  45 static const u32 vsc9959_ana_regmap[] = {
  46         REG(ANA_ADVLEARN,                       0x0089a0),
  47         REG(ANA_VLANMASK,                       0x0089a4),
  48         REG_RESERVED(ANA_PORT_B_DOMAIN),
  49         REG(ANA_ANAGEFIL,                       0x0089ac),
  50         REG(ANA_ANEVENTS,                       0x0089b0),
  51         REG(ANA_STORMLIMIT_BURST,               0x0089b4),
  52         REG(ANA_STORMLIMIT_CFG,                 0x0089b8),
  53         REG(ANA_ISOLATED_PORTS,                 0x0089c8),
  54         REG(ANA_COMMUNITY_PORTS,                0x0089cc),
  55         REG(ANA_AUTOAGE,                        0x0089d0),
  56         REG(ANA_MACTOPTIONS,                    0x0089d4),
  57         REG(ANA_LEARNDISC,                      0x0089d8),
  58         REG(ANA_AGENCTRL,                       0x0089dc),
  59         REG(ANA_MIRRORPORTS,                    0x0089e0),
  60         REG(ANA_EMIRRORPORTS,                   0x0089e4),
  61         REG(ANA_FLOODING,                       0x0089e8),
  62         REG(ANA_FLOODING_IPMC,                  0x008a08),
  63         REG(ANA_SFLOW_CFG,                      0x008a0c),
  64         REG(ANA_PORT_MODE,                      0x008a28),
  65         REG(ANA_CUT_THRU_CFG,                   0x008a48),
  66         REG(ANA_PGID_PGID,                      0x008400),
  67         REG(ANA_TABLES_ANMOVED,                 0x007f1c),
  68         REG(ANA_TABLES_MACHDATA,                0x007f20),
  69         REG(ANA_TABLES_MACLDATA,                0x007f24),
  70         REG(ANA_TABLES_STREAMDATA,              0x007f28),
  71         REG(ANA_TABLES_MACACCESS,               0x007f2c),
  72         REG(ANA_TABLES_MACTINDX,                0x007f30),
  73         REG(ANA_TABLES_VLANACCESS,              0x007f34),
  74         REG(ANA_TABLES_VLANTIDX,                0x007f38),
  75         REG(ANA_TABLES_ISDXACCESS,              0x007f3c),
  76         REG(ANA_TABLES_ISDXTIDX,                0x007f40),
  77         REG(ANA_TABLES_ENTRYLIM,                0x007f00),
  78         REG(ANA_TABLES_PTP_ID_HIGH,             0x007f44),
  79         REG(ANA_TABLES_PTP_ID_LOW,              0x007f48),
  80         REG(ANA_TABLES_STREAMACCESS,            0x007f4c),
  81         REG(ANA_TABLES_STREAMTIDX,              0x007f50),
  82         REG(ANA_TABLES_SEQ_HISTORY,             0x007f54),
  83         REG(ANA_TABLES_SEQ_MASK,                0x007f58),
  84         REG(ANA_TABLES_SFID_MASK,               0x007f5c),
  85         REG(ANA_TABLES_SFIDACCESS,              0x007f60),
  86         REG(ANA_TABLES_SFIDTIDX,                0x007f64),
  87         REG(ANA_MSTI_STATE,                     0x008600),
  88         REG(ANA_OAM_UPM_LM_CNT,                 0x008000),
  89         REG(ANA_SG_ACCESS_CTRL,                 0x008a64),
  90         REG(ANA_SG_CONFIG_REG_1,                0x007fb0),
  91         REG(ANA_SG_CONFIG_REG_2,                0x007fb4),
  92         REG(ANA_SG_CONFIG_REG_3,                0x007fb8),
  93         REG(ANA_SG_CONFIG_REG_4,                0x007fbc),
  94         REG(ANA_SG_CONFIG_REG_5,                0x007fc0),
  95         REG(ANA_SG_GCL_GS_CONFIG,               0x007f80),
  96         REG(ANA_SG_GCL_TI_CONFIG,               0x007f90),
  97         REG(ANA_SG_STATUS_REG_1,                0x008980),
  98         REG(ANA_SG_STATUS_REG_2,                0x008984),
  99         REG(ANA_SG_STATUS_REG_3,                0x008988),
 100         REG(ANA_PORT_VLAN_CFG,                  0x007800),
 101         REG(ANA_PORT_DROP_CFG,                  0x007804),
 102         REG(ANA_PORT_QOS_CFG,                   0x007808),
 103         REG(ANA_PORT_VCAP_CFG,                  0x00780c),
 104         REG(ANA_PORT_VCAP_S1_KEY_CFG,           0x007810),
 105         REG(ANA_PORT_VCAP_S2_CFG,               0x00781c),
 106         REG(ANA_PORT_PCP_DEI_MAP,               0x007820),
 107         REG(ANA_PORT_CPU_FWD_CFG,               0x007860),
 108         REG(ANA_PORT_CPU_FWD_BPDU_CFG,          0x007864),
 109         REG(ANA_PORT_CPU_FWD_GARP_CFG,          0x007868),
 110         REG(ANA_PORT_CPU_FWD_CCM_CFG,           0x00786c),
 111         REG(ANA_PORT_PORT_CFG,                  0x007870),
 112         REG(ANA_PORT_POL_CFG,                   0x007874),
 113         REG(ANA_PORT_PTP_CFG,                   0x007878),
 114         REG(ANA_PORT_PTP_DLY1_CFG,              0x00787c),
 115         REG(ANA_PORT_PTP_DLY2_CFG,              0x007880),
 116         REG(ANA_PORT_SFID_CFG,                  0x007884),
 117         REG(ANA_PFC_PFC_CFG,                    0x008800),
 118         REG_RESERVED(ANA_PFC_PFC_TIMER),
 119         REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
 120         REG_RESERVED(ANA_IPT_IPT),
 121         REG_RESERVED(ANA_PPT_PPT),
 122         REG_RESERVED(ANA_FID_MAP_FID_MAP),
 123         REG(ANA_AGGR_CFG,                       0x008a68),
 124         REG(ANA_CPUQ_CFG,                       0x008a6c),
 125         REG_RESERVED(ANA_CPUQ_CFG2),
 126         REG(ANA_CPUQ_8021_CFG,                  0x008a74),
 127         REG(ANA_DSCP_CFG,                       0x008ab4),
 128         REG(ANA_DSCP_REWR_CFG,                  0x008bb4),
 129         REG(ANA_VCAP_RNG_TYPE_CFG,              0x008bf4),
 130         REG(ANA_VCAP_RNG_VAL_CFG,               0x008c14),
 131         REG_RESERVED(ANA_VRAP_CFG),
 132         REG_RESERVED(ANA_VRAP_HDR_DATA),
 133         REG_RESERVED(ANA_VRAP_HDR_MASK),
 134         REG(ANA_DISCARD_CFG,                    0x008c40),
 135         REG(ANA_FID_CFG,                        0x008c44),
 136         REG(ANA_POL_PIR_CFG,                    0x004000),
 137         REG(ANA_POL_CIR_CFG,                    0x004004),
 138         REG(ANA_POL_MODE_CFG,                   0x004008),
 139         REG(ANA_POL_PIR_STATE,                  0x00400c),
 140         REG(ANA_POL_CIR_STATE,                  0x004010),
 141         REG_RESERVED(ANA_POL_STATE),
 142         REG(ANA_POL_FLOWC,                      0x008c48),
 143         REG(ANA_POL_HYST,                       0x008cb4),
 144         REG_RESERVED(ANA_POL_MISC_CFG),
 145 };
 146
 147 static const u32 vsc9959_qs_regmap[] = {
 148         REG(QS_XTR_GRP_CFG,                     0x000000),
 149         REG(QS_XTR_RD,                          0x000008),
 150         REG(QS_XTR_FRM_PRUNING,                 0x000010),
 151         REG(QS_XTR_FLUSH,                       0x000018),
 152         REG(QS_XTR_DATA_PRESENT,                0x00001c),
 153         REG(QS_XTR_CFG,                         0x000020),
 154         REG(QS_INJ_GRP_CFG,                     0x000024),
 155         REG(QS_INJ_WR,                          0x00002c),
 156         REG(QS_INJ_CTRL,                        0x000034),
 157         REG(QS_INJ_STATUS,                      0x00003c),
 158         REG(QS_INJ_ERR,                         0x000040),
 159         REG_RESERVED(QS_INH_DBG),
 160 };
 161
 162 static const u32 vsc9959_vcap_regmap[] = {
 163         /* VCAP_CORE_CFG */
 164         REG(VCAP_CORE_UPDATE_CTRL,              0x000000),
 165         REG(VCAP_CORE_MV_CFG,                   0x000004),
 166         /* VCAP_CORE_CACHE */
 167         REG(VCAP_CACHE_ENTRY_DAT,               0x000008),
 168         REG(VCAP_CACHE_MASK_DAT,                0x000108),
 169         REG(VCAP_CACHE_ACTION_DAT,              0x000208),
 170         REG(VCAP_CACHE_CNT_DAT,                 0x000308),
 171         REG(VCAP_CACHE_TG_DAT,                  0x000388),
 172         /* VCAP_CONST */
 173         REG(VCAP_CONST_VCAP_VER,                0x000398),
 174         REG(VCAP_CONST_ENTRY_WIDTH,             0x00039c),
 175         REG(VCAP_CONST_ENTRY_CNT,               0x0003a0),
 176         REG(VCAP_CONST_ENTRY_SWCNT,             0x0003a4),
 177         REG(VCAP_CONST_ENTRY_TG_WIDTH,          0x0003a8),
 178         REG(VCAP_CONST_ACTION_DEF_CNT,          0x0003ac),
 179         REG(VCAP_CONST_ACTION_WIDTH,            0x0003b0),
 180         REG(VCAP_CONST_CNT_WIDTH,               0x0003b4),
 181         REG(VCAP_CONST_CORE_CNT,                0x0003b8),
 182         REG(VCAP_CONST_IF_CNT,                  0x0003bc),
 183 };
 184
 185 static const u32 vsc9959_qsys_regmap[] = {
 186         REG(QSYS_PORT_MODE,                     0x00f460),
 187         REG(QSYS_SWITCH_PORT_MODE,              0x00f480),
 188         REG(QSYS_STAT_CNT_CFG,                  0x00f49c),
 189         REG(QSYS_EEE_CFG,                       0x00f4a0),
 190         REG(QSYS_EEE_THRES,                     0x00f4b8),
 191         REG(QSYS_IGR_NO_SHARING,                0x00f4bc),
 192         REG(QSYS_EGR_NO_SHARING,                0x00f4c0),
 193         REG(QSYS_SW_STATUS,                     0x00f4c4),
 194         REG(QSYS_EXT_CPU_CFG,                   0x00f4e0),
 195         REG_RESERVED(QSYS_PAD_CFG),
 196         REG(QSYS_CPU_GROUP_MAP,                 0x00f4e8),
 197         REG_RESERVED(QSYS_QMAP),
 198         REG_RESERVED(QSYS_ISDX_SGRP),
 199         REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
 200         REG(QSYS_TFRM_MISC,                     0x00f50c),
 201         REG(QSYS_TFRM_PORT_DLY,                 0x00f510),
 202         REG(QSYS_TFRM_TIMER_CFG_1,              0x00f514),
 203         REG(QSYS_TFRM_TIMER_CFG_2,              0x00f518),
 204         REG(QSYS_TFRM_TIMER_CFG_3,              0x00f51c),
 205         REG(QSYS_TFRM_TIMER_CFG_4,              0x00f520),
 206         REG(QSYS_TFRM_TIMER_CFG_5,              0x00f524),
 207         REG(QSYS_TFRM_TIMER_CFG_6,              0x00f528),
 208         REG(QSYS_TFRM_TIMER_CFG_7,              0x00f52c),
 209         REG(QSYS_TFRM_TIMER_CFG_8,              0x00f530),
 210         REG(QSYS_RED_PROFILE,                   0x00f534),
 211         REG(QSYS_RES_QOS_MODE,                  0x00f574),
 212         REG(QSYS_RES_CFG,                       0x00c000),
 213         REG(QSYS_RES_STAT,                      0x00c004),
 214         REG(QSYS_EGR_DROP_MODE,                 0x00f578),
 215         REG(QSYS_EQ_CTRL,                       0x00f57c),
 216         REG_RESERVED(QSYS_EVENTS_CORE),
 217         REG(QSYS_QMAXSDU_CFG_0,                 0x00f584),
 218         REG(QSYS_QMAXSDU_CFG_1,                 0x00f5a0),
 219         REG(QSYS_QMAXSDU_CFG_2,                 0x00f5bc),
 220         REG(QSYS_QMAXSDU_CFG_3,                 0x00f5d8),
 221         REG(QSYS_QMAXSDU_CFG_4,                 0x00f5f4),
 222         REG(QSYS_QMAXSDU_CFG_5,                 0x00f610),
 223         REG(QSYS_QMAXSDU_CFG_6,                 0x00f62c),
 224         REG(QSYS_QMAXSDU_CFG_7,                 0x00f648),
 225         REG(QSYS_PREEMPTION_CFG,                0x00f664),
 226         REG(QSYS_CIR_CFG,                       0x000000),
 227         REG(QSYS_EIR_CFG,                       0x000004),
 228         REG(QSYS_SE_CFG,                        0x000008),
 229         REG(QSYS_SE_DWRR_CFG,                   0x00000c),
 230         REG_RESERVED(QSYS_SE_CONNECT),
 231         REG(QSYS_SE_DLB_SENSE,                  0x000040),
 232         REG(QSYS_CIR_STATE,                     0x000044),
 233         REG(QSYS_EIR_STATE,                     0x000048),
 234         REG_RESERVED(QSYS_SE_STATE),
 235         REG(QSYS_HSCH_MISC_CFG,                 0x00f67c),
 236         REG(QSYS_TAG_CONFIG,                    0x00f680),
 237         REG(QSYS_TAS_PARAM_CFG_CTRL,            0x00f698),
 238         REG(QSYS_PORT_MAX_SDU,                  0x00f69c),
 239         REG(QSYS_PARAM_CFG_REG_1,               0x00f440),
 240         REG(QSYS_PARAM_CFG_REG_2,               0x00f444),
 241         REG(QSYS_PARAM_CFG_REG_3,               0x00f448),
 242         REG(QSYS_PARAM_CFG_REG_4,               0x00f44c),
 243         REG(QSYS_PARAM_CFG_REG_5,               0x00f450),
 244         REG(QSYS_GCL_CFG_REG_1,                 0x00f454),
 245         REG(QSYS_GCL_CFG_REG_2,                 0x00f458),
 246         REG(QSYS_PARAM_STATUS_REG_1,            0x00f400),
 247         REG(QSYS_PARAM_STATUS_REG_2,            0x00f404),
 248         REG(QSYS_PARAM_STATUS_REG_3,            0x00f408),
 249         REG(QSYS_PARAM_STATUS_REG_4,            0x00f40c),
 250         REG(QSYS_PARAM_STATUS_REG_5,            0x00f410),
 251         REG(QSYS_PARAM_STATUS_REG_6,            0x00f414),
 252         REG(QSYS_PARAM_STATUS_REG_7,            0x00f418),
 253         REG(QSYS_PARAM_STATUS_REG_8,            0x00f41c),
 254         REG(QSYS_PARAM_STATUS_REG_9,            0x00f420),
 255         REG(QSYS_GCL_STATUS_REG_1,              0x00f424),
 256         REG(QSYS_GCL_STATUS_REG_2,              0x00f428),
 257 };
 258
 259 static const u32 vsc9959_rew_regmap[] = {
 260         REG(REW_PORT_VLAN_CFG,                  0x000000),
 261         REG(REW_TAG_CFG,                        0x000004),
 262         REG(REW_PORT_CFG,                       0x000008),
 263         REG(REW_DSCP_CFG,                       0x00000c),
 264         REG(REW_PCP_DEI_QOS_MAP_CFG,            0x000010),
 265         REG(REW_PTP_CFG,                        0x000050),
 266         REG(REW_PTP_DLY1_CFG,                   0x000054),
 267         REG(REW_RED_TAG_CFG,                    0x000058),
 268         REG(REW_DSCP_REMAP_DP1_CFG,             0x000410),
 269         REG(REW_DSCP_REMAP_CFG,                 0x000510),
 270         REG_RESERVED(REW_STAT_CFG),
 271         REG_RESERVED(REW_REW_STICKY),
 272         REG_RESERVED(REW_PPT),
 273 };
 274
 275 static const u32 vsc9959_sys_regmap[] = {
 276         REG(SYS_COUNT_RX_OCTETS,                0x000000),
 277         REG(SYS_COUNT_RX_MULTICAST,             0x000008),
 278         REG(SYS_COUNT_RX_SHORTS,                0x000010),
 279         REG(SYS_COUNT_RX_FRAGMENTS,             0x000014),
 280         REG(SYS_COUNT_RX_JABBERS,               0x000018),
 281         REG(SYS_COUNT_RX_64,                    0x000024),
 282         REG(SYS_COUNT_RX_65_127,                0x000028),
 283         REG(SYS_COUNT_RX_128_255,               0x00002c),
 284         REG(SYS_COUNT_RX_256_1023,              0x000030),
 285         REG(SYS_COUNT_RX_1024_1526,             0x000034),
 286         REG(SYS_COUNT_RX_1527_MAX,              0x000038),
 287         REG(SYS_COUNT_RX_LONGS,                 0x000044),
 288         REG(SYS_COUNT_TX_OCTETS,                0x000200),
 289         REG(SYS_COUNT_TX_COLLISION,             0x000210),
 290         REG(SYS_COUNT_TX_DROPS,                 0x000214),
 291         REG(SYS_COUNT_TX_64,                    0x00021c),
 292         REG(SYS_COUNT_TX_65_127,                0x000220),
 293         REG(SYS_COUNT_TX_128_511,               0x000224),
 294         REG(SYS_COUNT_TX_512_1023,              0x000228),
 295         REG(SYS_COUNT_TX_1024_1526,             0x00022c),
 296         REG(SYS_COUNT_TX_1527_MAX,              0x000230),
 297         REG(SYS_COUNT_TX_AGING,                 0x000278),
 298         REG(SYS_RESET_CFG,                      0x000e00),
 299         REG(SYS_SR_ETYPE_CFG,                   0x000e04),
 300         REG(SYS_VLAN_ETYPE_CFG,                 0x000e08),
 301         REG(SYS_PORT_MODE,                      0x000e0c),
 302         REG(SYS_FRONT_PORT_MODE,                0x000e2c),
 303         REG(SYS_FRM_AGING,                      0x000e44),
 304         REG(SYS_STAT_CFG,                       0x000e48),
 305         REG(SYS_SW_STATUS,                      0x000e4c),
 306         REG_RESERVED(SYS_MISC_CFG),
 307         REG(SYS_REW_MAC_HIGH_CFG,               0x000e6c),
 308         REG(SYS_REW_MAC_LOW_CFG,                0x000e84),
 309         REG(SYS_TIMESTAMP_OFFSET,               0x000e9c),
 310         REG(SYS_PAUSE_CFG,                      0x000ea0),
 311         REG(SYS_PAUSE_TOT_CFG,                  0x000ebc),
 312         REG(SYS_ATOP,                           0x000ec0),
 313         REG(SYS_ATOP_TOT_CFG,                   0x000edc),
 314         REG(SYS_MAC_FC_CFG,                     0x000ee0),
 315         REG(SYS_MMGT,                           0x000ef8),
 316         REG_RESERVED(SYS_MMGT_FAST),
 317         REG_RESERVED(SYS_EVENTS_DIF),
 318         REG_RESERVED(SYS_EVENTS_CORE),
 319         REG(SYS_CNT,                            0x000000),
 320         REG(SYS_PTP_STATUS,                     0x000f14),
 321         REG(SYS_PTP_TXSTAMP,                    0x000f18),
 322         REG(SYS_PTP_NXT,                        0x000f1c),
 323         REG(SYS_PTP_CFG,                        0x000f20),
 324         REG(SYS_RAM_INIT,                       0x000f24),
 325         REG_RESERVED(SYS_CM_ADDR),
 326         REG_RESERVED(SYS_CM_DATA_WR),
 327         REG_RESERVED(SYS_CM_DATA_RD),
 328         REG_RESERVED(SYS_CM_OP),
 329         REG_RESERVED(SYS_CM_DATA),
 330 };
 331
 332 static const u32 vsc9959_ptp_regmap[] = {
 333         REG(PTP_PIN_CFG,                        0x000000),
 334         REG(PTP_PIN_TOD_SEC_MSB,                0x000004),
 335         REG(PTP_PIN_TOD_SEC_LSB,                0x000008),
 336         REG(PTP_PIN_TOD_NSEC,                   0x00000c),
 337         REG(PTP_PIN_WF_HIGH_PERIOD,             0x000014),
 338         REG(PTP_PIN_WF_LOW_PERIOD,              0x000018),
 339         REG(PTP_CFG_MISC,                       0x0000a0),
 340         REG(PTP_CLK_CFG_ADJ_CFG,                0x0000a4),
 341         REG(PTP_CLK_CFG_ADJ_FREQ,               0x0000a8),
 342 };
 343
 344 static const u32 vsc9959_gcb_regmap[] = {
 345         REG(GCB_SOFT_RST,                       0x000004),
 346 };
 347
 348 static const u32 vsc9959_dev_gmii_regmap[] = {
 349         REG(DEV_CLOCK_CFG,                      0x0),
 350         REG(DEV_PORT_MISC,                      0x4),
 351         REG(DEV_EVENTS,                         0x8),
 352         REG(DEV_EEE_CFG,                        0xc),
 353         REG(DEV_RX_PATH_DELAY,                  0x10),
 354         REG(DEV_TX_PATH_DELAY,                  0x14),
 355         REG(DEV_PTP_PREDICT_CFG,                0x18),
 356         REG(DEV_MAC_ENA_CFG,                    0x1c),
 357         REG(DEV_MAC_MODE_CFG,                   0x20),
 358         REG(DEV_MAC_MAXLEN_CFG,                 0x24),
 359         REG(DEV_MAC_TAGS_CFG,                   0x28),
 360         REG(DEV_MAC_ADV_CHK_CFG,                0x2c),
 361         REG(DEV_MAC_IFG_CFG,                    0x30),
 362         REG(DEV_MAC_HDX_CFG,                    0x34),
 363         REG(DEV_MAC_DBG_CFG,                    0x38),
 364         REG(DEV_MAC_FC_MAC_LOW_CFG,             0x3c),
 365         REG(DEV_MAC_FC_MAC_HIGH_CFG,            0x40),
 366         REG(DEV_MAC_STICKY,                     0x44),
 367         REG_RESERVED(PCS1G_CFG),
 368         REG_RESERVED(PCS1G_MODE_CFG),
 369         REG_RESERVED(PCS1G_SD_CFG),
 370         REG_RESERVED(PCS1G_ANEG_CFG),
 371         REG_RESERVED(PCS1G_ANEG_NP_CFG),
 372         REG_RESERVED(PCS1G_LB_CFG),
 373         REG_RESERVED(PCS1G_DBG_CFG),
 374         REG_RESERVED(PCS1G_CDET_CFG),
 375         REG_RESERVED(PCS1G_ANEG_STATUS),
 376         REG_RESERVED(PCS1G_ANEG_NP_STATUS),
 377         REG_RESERVED(PCS1G_LINK_STATUS),
 378         REG_RESERVED(PCS1G_LINK_DOWN_CNT),
 379         REG_RESERVED(PCS1G_STICKY),
 380         REG_RESERVED(PCS1G_DEBUG_STATUS),
 381         REG_RESERVED(PCS1G_LPI_CFG),
 382         REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
 383         REG_RESERVED(PCS1G_LPI_STATUS),
 384         REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
 385         REG_RESERVED(PCS1G_TSTPAT_STATUS),
 386         REG_RESERVED(DEV_PCS_FX100_CFG),
 387         REG_RESERVED(DEV_PCS_FX100_STATUS),
 388 };
 389
 390 static const u32 *vsc9959_regmap[TARGET_MAX] = {
 391         [ANA]   = vsc9959_ana_regmap,
 392         [QS]    = vsc9959_qs_regmap,
 393         [QSYS]  = vsc9959_qsys_regmap,
 394         [REW]   = vsc9959_rew_regmap,
 395         [SYS]   = vsc9959_sys_regmap,
 396         [S0]    = vsc9959_vcap_regmap,
 397         [S1]    = vsc9959_vcap_regmap,
 398         [S2]    = vsc9959_vcap_regmap,
 399         [PTP]   = vsc9959_ptp_regmap,
 400         [GCB]   = vsc9959_gcb_regmap,
 401         [DEV_GMII] = vsc9959_dev_gmii_regmap,
 402 };
 403
 404 /* Addresses are relative to the PCI device's base address */
 405 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
 406         [ANA] = {
 407                 .start  = 0x0280000,
 408                 .end    = 0x028ffff,
 409                 .name   = "ana",
 410         },
 411         [QS] = {
 412                 .start  = 0x0080000,
 413                 .end    = 0x00800ff,
 414                 .name   = "qs",
 415         },
 416         [QSYS] = {
 417                 .start  = 0x0200000,
 418                 .end    = 0x021ffff,
 419                 .name   = "qsys",
 420         },
 421         [REW] = {
 422                 .start  = 0x0030000,
 423                 .end    = 0x003ffff,
 424                 .name   = "rew",
 425         },
 426         [SYS] = {
 427                 .start  = 0x0010000,
 428                 .end    = 0x001ffff,
 429                 .name   = "sys",
 430         },
 431         [S0] = {
 432                 .start  = 0x0040000,
 433                 .end    = 0x00403ff,
 434                 .name   = "s0",
 435         },
 436         [S1] = {
 437                 .start  = 0x0050000,
 438                 .end    = 0x00503ff,
 439                 .name   = "s1",
 440         },
 441         [S2] = {
 442                 .start  = 0x0060000,
 443                 .end    = 0x00603ff,
 444                 .name   = "s2",
 445         },
 446         [PTP] = {
 447                 .start  = 0x0090000,
 448                 .end    = 0x00900cb,
 449                 .name   = "ptp",
 450         },
 451         [GCB] = {
 452                 .start  = 0x0070000,
 453                 .end    = 0x00701ff,
 454                 .name   = "devcpu_gcb",
 455         },
 456 };
 457
 458 static const struct resource vsc9959_port_io_res[] = {
 459         {
 460                 .start  = 0x0100000,
 461                 .end    = 0x010ffff,
 462                 .name   = "port0",
 463         },
 464         {
 465                 .start  = 0x0110000,
 466                 .end    = 0x011ffff,
 467                 .name   = "port1",
 468         },
 469         {
 470                 .start  = 0x0120000,
 471                 .end    = 0x012ffff,
 472                 .name   = "port2",
 473         },
 474         {
 475                 .start  = 0x0130000,
 476                 .end    = 0x013ffff,
 477                 .name   = "port3",
 478         },
 479         {
 480                 .start  = 0x0140000,
 481                 .end    = 0x014ffff,
 482                 .name   = "port4",
 483         },
 484         {
 485                 .start  = 0x0150000,
 486                 .end    = 0x015ffff,
 487                 .name   = "port5",
 488         },
 489 };
 490
 491 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
 492  * SGMII/QSGMII MAC PCS can be found.
 493  */
 494 static const struct resource vsc9959_imdio_res = {
 495         .start          = 0x8030,
 496         .end            = 0x8040,
 497         .name           = "imdio",
 498 };
 499
 500 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
 501         [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
 502         [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
 503         [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
 504         [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
 505         [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
 506         [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
 507         [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
 508         [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
 509         [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
 510         [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
 511         [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
 512         [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
 513         [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
 514         [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
 515         [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
 516         [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
 517         [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
 518         [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
 519         [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
 520         [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
 521         [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
 522         [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
 523         [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
 524         [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
 525         [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
 526         [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
 527         [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
 528         [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
 529         [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
 530         [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
 531         [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
 532         [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
 533         [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
 534         /* Replicated per number of ports (7), register size 4 per port */
 535         [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
 536         [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
 537         [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
 538         [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
 539         [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
 540         [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
 541         [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
 542         [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
 543         [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
 544         [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
 545         [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
 546         [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
 547         [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
 548 };
 549
 550 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
 551         { .offset = 0x00,       .name = "rx_octets", },
 552         { .offset = 0x01,       .name = "rx_unicast", },
 553         { .offset = 0x02,       .name = "rx_multicast", },
 554         { .offset = 0x03,       .name = "rx_broadcast", },
 555         { .offset = 0x04,       .name = "rx_shorts", },
 556         { .offset = 0x05,       .name = "rx_fragments", },
 557         { .offset = 0x06,       .name = "rx_jabbers", },
 558         { .offset = 0x07,       .name = "rx_crc_align_errs", },
 559         { .offset = 0x08,       .name = "rx_sym_errs", },
 560         { .offset = 0x09,       .name = "rx_frames_below_65_octets", },
 561         { .offset = 0x0A,       .name = "rx_frames_65_to_127_octets", },
 562         { .offset = 0x0B,       .name = "rx_frames_128_to_255_octets", },
 563         { .offset = 0x0C,       .name = "rx_frames_256_to_511_octets", },
 564         { .offset = 0x0D,       .name = "rx_frames_512_to_1023_octets", },
 565         { .offset = 0x0E,       .name = "rx_frames_1024_to_1526_octets", },
 566         { .offset = 0x0F,       .name = "rx_frames_over_1526_octets", },
 567         { .offset = 0x10,       .name = "rx_pause", },
 568         { .offset = 0x11,       .name = "rx_control", },
 569         { .offset = 0x12,       .name = "rx_longs", },
 570         { .offset = 0x13,       .name = "rx_classified_drops", },
 571         { .offset = 0x14,       .name = "rx_red_prio_0", },
 572         { .offset = 0x15,       .name = "rx_red_prio_1", },
 573         { .offset = 0x16,       .name = "rx_red_prio_2", },
 574         { .offset = 0x17,       .name = "rx_red_prio_3", },
 575         { .offset = 0x18,       .name = "rx_red_prio_4", },
 576         { .offset = 0x19,       .name = "rx_red_prio_5", },
 577         { .offset = 0x1A,       .name = "rx_red_prio_6", },
 578         { .offset = 0x1B,       .name = "rx_red_prio_7", },
 579         { .offset = 0x1C,       .name = "rx_yellow_prio_0", },
 580         { .offset = 0x1D,       .name = "rx_yellow_prio_1", },
 581         { .offset = 0x1E,       .name = "rx_yellow_prio_2", },
 582         { .offset = 0x1F,       .name = "rx_yellow_prio_3", },
 583         { .offset = 0x20,       .name = "rx_yellow_prio_4", },
 584         { .offset = 0x21,       .name = "rx_yellow_prio_5", },
 585         { .offset = 0x22,       .name = "rx_yellow_prio_6", },
 586         { .offset = 0x23,       .name = "rx_yellow_prio_7", },
 587         { .offset = 0x24,       .name = "rx_green_prio_0", },
 588         { .offset = 0x25,       .name = "rx_green_prio_1", },
 589         { .offset = 0x26,       .name = "rx_green_prio_2", },
 590         { .offset = 0x27,       .name = "rx_green_prio_3", },
 591         { .offset = 0x28,       .name = "rx_green_prio_4", },
 592         { .offset = 0x29,       .name = "rx_green_prio_5", },
 593         { .offset = 0x2A,       .name = "rx_green_prio_6", },
 594         { .offset = 0x2B,       .name = "rx_green_prio_7", },
 595         { .offset = 0x80,       .name = "tx_octets", },
 596         { .offset = 0x81,       .name = "tx_unicast", },
 597         { .offset = 0x82,       .name = "tx_multicast", },
 598         { .offset = 0x83,       .name = "tx_broadcast", },
 599         { .offset = 0x84,       .name = "tx_collision", },
 600         { .offset = 0x85,       .name = "tx_drops", },
 601         { .offset = 0x86,       .name = "tx_pause", },
 602         { .offset = 0x87,       .name = "tx_frames_below_65_octets", },
 603         { .offset = 0x88,       .name = "tx_frames_65_to_127_octets", },
 604         { .offset = 0x89,       .name = "tx_frames_128_255_octets", },
 605         { .offset = 0x8B,       .name = "tx_frames_256_511_octets", },
 606         { .offset = 0x8C,       .name = "tx_frames_1024_1526_octets", },
 607         { .offset = 0x8D,       .name = "tx_frames_over_1526_octets", },
 608         { .offset = 0x8E,       .name = "tx_yellow_prio_0", },
 609         { .offset = 0x8F,       .name = "tx_yellow_prio_1", },
 610         { .offset = 0x90,       .name = "tx_yellow_prio_2", },
 611         { .offset = 0x91,       .name = "tx_yellow_prio_3", },
 612         { .offset = 0x92,       .name = "tx_yellow_prio_4", },
 613         { .offset = 0x93,       .name = "tx_yellow_prio_5", },
 614         { .offset = 0x94,       .name = "tx_yellow_prio_6", },
 615         { .offset = 0x95,       .name = "tx_yellow_prio_7", },
 616         { .offset = 0x96,       .name = "tx_green_prio_0", },
 617         { .offset = 0x97,       .name = "tx_green_prio_1", },
 618         { .offset = 0x98,       .name = "tx_green_prio_2", },
 619         { .offset = 0x99,       .name = "tx_green_prio_3", },
 620         { .offset = 0x9A,       .name = "tx_green_prio_4", },
 621         { .offset = 0x9B,       .name = "tx_green_prio_5", },
 622         { .offset = 0x9C,       .name = "tx_green_prio_6", },
 623         { .offset = 0x9D,       .name = "tx_green_prio_7", },
 624         { .offset = 0x9E,       .name = "tx_aged", },
 625         { .offset = 0x100,      .name = "drop_local", },
 626         { .offset = 0x101,      .name = "drop_tail", },
 627         { .offset = 0x102,      .name = "drop_yellow_prio_0", },
 628         { .offset = 0x103,      .name = "drop_yellow_prio_1", },
 629         { .offset = 0x104,      .name = "drop_yellow_prio_2", },
 630         { .offset = 0x105,      .name = "drop_yellow_prio_3", },
 631         { .offset = 0x106,      .name = "drop_yellow_prio_4", },
 632         { .offset = 0x107,      .name = "drop_yellow_prio_5", },
 633         { .offset = 0x108,      .name = "drop_yellow_prio_6", },
 634         { .offset = 0x109,      .name = "drop_yellow_prio_7", },
 635         { .offset = 0x10A,      .name = "drop_green_prio_0", },
 636         { .offset = 0x10B,      .name = "drop_green_prio_1", },
 637         { .offset = 0x10C,      .name = "drop_green_prio_2", },
 638         { .offset = 0x10D,      .name = "drop_green_prio_3", },
 639         { .offset = 0x10E,      .name = "drop_green_prio_4", },
 640         { .offset = 0x10F,      .name = "drop_green_prio_5", },
 641         { .offset = 0x110,      .name = "drop_green_prio_6", },
 642         { .offset = 0x111,      .name = "drop_green_prio_7", },
 643         OCELOT_STAT_END
 644 };
 645
 646 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
 647         [VCAP_ES0_EGR_PORT]                     = {  0,  3},
 648         [VCAP_ES0_IGR_PORT]                     = {  3,  3},
 649         [VCAP_ES0_RSV]                          = {  6,  2},
 650         [VCAP_ES0_L2_MC]                        = {  8,  1},
 651         [VCAP_ES0_L2_BC]                        = {  9,  1},
 652         [VCAP_ES0_VID]                          = { 10, 12},
 653         [VCAP_ES0_DP]                           = { 22,  1},
 654         [VCAP_ES0_PCP]                          = { 23,  3},
 655 };
 656
 657 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
 658         [VCAP_ES0_ACT_PUSH_OUTER_TAG]           = {  0,  2},
 659         [VCAP_ES0_ACT_PUSH_INNER_TAG]           = {  2,  1},
 660         [VCAP_ES0_ACT_TAG_A_TPID_SEL]           = {  3,  2},
 661         [VCAP_ES0_ACT_TAG_A_VID_SEL]            = {  5,  1},
 662         [VCAP_ES0_ACT_TAG_A_PCP_SEL]            = {  6,  2},
 663         [VCAP_ES0_ACT_TAG_A_DEI_SEL]            = {  8,  2},
 664         [VCAP_ES0_ACT_TAG_B_TPID_SEL]           = { 10,  2},
 665         [VCAP_ES0_ACT_TAG_B_VID_SEL]            = { 12,  1},
 666         [VCAP_ES0_ACT_TAG_B_PCP_SEL]            = { 13,  2},
 667         [VCAP_ES0_ACT_TAG_B_DEI_SEL]            = { 15,  2},
 668         [VCAP_ES0_ACT_VID_A_VAL]                = { 17, 12},
 669         [VCAP_ES0_ACT_PCP_A_VAL]                = { 29,  3},
 670         [VCAP_ES0_ACT_DEI_A_VAL]                = { 32,  1},
 671         [VCAP_ES0_ACT_VID_B_VAL]                = { 33, 12},
 672         [VCAP_ES0_ACT_PCP_B_VAL]                = { 45,  3},
 673         [VCAP_ES0_ACT_DEI_B_VAL]                = { 48,  1},
 674         [VCAP_ES0_ACT_RSV]                      = { 49, 23},
 675         [VCAP_ES0_ACT_HIT_STICKY]               = { 72,  1},
 676 };
 677
 678 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
 679         [VCAP_IS1_HK_TYPE]                      = {  0,   1},
 680         [VCAP_IS1_HK_LOOKUP]                    = {  1,   2},
 681         [VCAP_IS1_HK_IGR_PORT_MASK]             = {  3,   7},
 682         [VCAP_IS1_HK_RSV]                       = { 10,   9},
 683         [VCAP_IS1_HK_OAM_Y1731]                 = { 19,   1},
 684         [VCAP_IS1_HK_L2_MC]                     = { 20,   1},
 685         [VCAP_IS1_HK_L2_BC]                     = { 21,   1},
 686         [VCAP_IS1_HK_IP_MC]                     = { 22,   1},
 687         [VCAP_IS1_HK_VLAN_TAGGED]               = { 23,   1},
 688         [VCAP_IS1_HK_VLAN_DBL_TAGGED]           = { 24,   1},
 689         [VCAP_IS1_HK_TPID]                      = { 25,   1},
 690         [VCAP_IS1_HK_VID]                       = { 26,  12},
 691         [VCAP_IS1_HK_DEI]                       = { 38,   1},
 692         [VCAP_IS1_HK_PCP]                       = { 39,   3},
 693         /* Specific Fields for IS1 Half Key S1_NORMAL */
 694         [VCAP_IS1_HK_L2_SMAC]                   = { 42,  48},
 695         [VCAP_IS1_HK_ETYPE_LEN]                 = { 90,   1},
 696         [VCAP_IS1_HK_ETYPE]                     = { 91,  16},
 697         [VCAP_IS1_HK_IP_SNAP]                   = {107,   1},
 698         [VCAP_IS1_HK_IP4]                       = {108,   1},
 699         /* Layer-3 Information */
 700         [VCAP_IS1_HK_L3_FRAGMENT]               = {109,   1},
 701         [VCAP_IS1_HK_L3_FRAG_OFS_GT0]           = {110,   1},
 702         [VCAP_IS1_HK_L3_OPTIONS]                = {111,   1},
 703         [VCAP_IS1_HK_L3_DSCP]                   = {112,   6},
 704         [VCAP_IS1_HK_L3_IP4_SIP]                = {118,  32},
 705         /* Layer-4 Information */
 706         [VCAP_IS1_HK_TCP_UDP]                   = {150,   1},
 707         [VCAP_IS1_HK_TCP]                       = {151,   1},
 708         [VCAP_IS1_HK_L4_SPORT]                  = {152,  16},
 709         [VCAP_IS1_HK_L4_RNG]                    = {168,   8},
 710         /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
 711         [VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
 712         [VCAP_IS1_HK_IP4_INNER_VID]             = { 43,  12},
 713         [VCAP_IS1_HK_IP4_INNER_DEI]             = { 55,   1},
 714         [VCAP_IS1_HK_IP4_INNER_PCP]             = { 56,   3},
 715         [VCAP_IS1_HK_IP4_IP4]                   = { 59,   1},
 716         [VCAP_IS1_HK_IP4_L3_FRAGMENT]           = { 60,   1},
 717         [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]       = { 61,   1},
 718         [VCAP_IS1_HK_IP4_L3_OPTIONS]            = { 62,   1},
 719         [VCAP_IS1_HK_IP4_L3_DSCP]               = { 63,   6},
 720         [VCAP_IS1_HK_IP4_L3_IP4_DIP]            = { 69,  32},
 721         [VCAP_IS1_HK_IP4_L3_IP4_SIP]            = {101,  32},
 722         [VCAP_IS1_HK_IP4_L3_PROTO]              = {133,   8},
 723         [VCAP_IS1_HK_IP4_TCP_UDP]               = {141,   1},
 724         [VCAP_IS1_HK_IP4_TCP]                   = {142,   1},
 725         [VCAP_IS1_HK_IP4_L4_RNG]                = {143,   8},
 726         [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = {151,  32},
 727 };
 728
 729 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
 730         [VCAP_IS1_ACT_DSCP_ENA]                 = {  0,  1},
 731         [VCAP_IS1_ACT_DSCP_VAL]                 = {  1,  6},
 732         [VCAP_IS1_ACT_QOS_ENA]                  = {  7,  1},
 733         [VCAP_IS1_ACT_QOS_VAL]                  = {  8,  3},
 734         [VCAP_IS1_ACT_DP_ENA]                   = { 11,  1},
 735         [VCAP_IS1_ACT_DP_VAL]                   = { 12,  1},
 736         [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]        = { 13,  8},
 737         [VCAP_IS1_ACT_PAG_VAL]                  = { 21,  8},
 738         [VCAP_IS1_ACT_RSV]                      = { 29,  9},
 739         /* The fields below are incorrectly shifted by 2 in the manual */
 740         [VCAP_IS1_ACT_VID_REPLACE_ENA]          = { 38,  1},
 741         [VCAP_IS1_ACT_VID_ADD_VAL]              = { 39, 12},
 742         [VCAP_IS1_ACT_FID_SEL]                  = { 51,  2},
 743         [VCAP_IS1_ACT_FID_VAL]                  = { 53, 13},
 744         [VCAP_IS1_ACT_PCP_DEI_ENA]              = { 66,  1},
 745         [VCAP_IS1_ACT_PCP_VAL]                  = { 67,  3},
 746         [VCAP_IS1_ACT_DEI_VAL]                  = { 70,  1},
 747         [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]         = { 71,  1},
 748         [VCAP_IS1_ACT_VLAN_POP_CNT]             = { 72,  2},
 749         [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]      = { 74,  4},
 750         [VCAP_IS1_ACT_HIT_STICKY]               = { 78,  1},
 751 };
 752
 753 static struct vcap_field vsc9959_vcap_is2_keys[] = {
 754         /* Common: 41 bits */
 755         [VCAP_IS2_TYPE]                         = {  0,   4},
 756         [VCAP_IS2_HK_FIRST]                     = {  4,   1},
 757         [VCAP_IS2_HK_PAG]                       = {  5,   8},
 758         [VCAP_IS2_HK_IGR_PORT_MASK]             = { 13,   7},
 759         [VCAP_IS2_HK_RSV2]                      = { 20,   1},
 760         [VCAP_IS2_HK_HOST_MATCH]                = { 21,   1},
 761         [VCAP_IS2_HK_L2_MC]                     = { 22,   1},
 762         [VCAP_IS2_HK_L2_BC]                     = { 23,   1},
 763         [VCAP_IS2_HK_VLAN_TAGGED]               = { 24,   1},
 764         [VCAP_IS2_HK_VID]                       = { 25,  12},
 765         [VCAP_IS2_HK_DEI]                       = { 37,   1},
 766         [VCAP_IS2_HK_PCP]                       = { 38,   3},
 767         /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
 768         [VCAP_IS2_HK_L2_DMAC]                   = { 41,  48},
 769         [VCAP_IS2_HK_L2_SMAC]                   = { 89,  48},
 770         /* MAC_ETYPE (TYPE=000) */
 771         [VCAP_IS2_HK_MAC_ETYPE_ETYPE]           = {137,  16},
 772         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]     = {153,  16},
 773         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]     = {169,   8},
 774         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]     = {177,   3},
 775         /* MAC_LLC (TYPE=001) */
 776         [VCAP_IS2_HK_MAC_LLC_L2_LLC]            = {137,  40},
 777         /* MAC_SNAP (TYPE=010) */
 778         [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]          = {137,  40},
 779         /* MAC_ARP (TYPE=011) */
 780         [VCAP_IS2_HK_MAC_ARP_SMAC]              = { 41,  48},
 781         [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]     = { 89,   1},
 782         [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 90,   1},
 783         [VCAP_IS2_HK_MAC_ARP_LEN_OK]            = { 91,   1},
 784         [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]      = { 92,   1},
 785         [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]      = { 93,   1},
 786         [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 94,   1},
 787         [VCAP_IS2_HK_MAC_ARP_OPCODE]            = { 95,   2},
 788         [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]        = { 97,  32},
 789         [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]        = {129,  32},
 790         [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]        = {161,   1},
 791         /* IP4_TCP_UDP / IP4_OTHER common */
 792         [VCAP_IS2_HK_IP4]                       = { 41,   1},
 793         [VCAP_IS2_HK_L3_FRAGMENT]               = { 42,   1},
 794         [VCAP_IS2_HK_L3_FRAG_OFS_GT0]           = { 43,   1},
 795         [VCAP_IS2_HK_L3_OPTIONS]                = { 44,   1},
 796         [VCAP_IS2_HK_IP4_L3_TTL_GT0]            = { 45,   1},
 797         [VCAP_IS2_HK_L3_TOS]                    = { 46,   8},
 798         [VCAP_IS2_HK_L3_IP4_DIP]                = { 54,  32},
 799         [VCAP_IS2_HK_L3_IP4_SIP]                = { 86,  32},
 800         [VCAP_IS2_HK_DIP_EQ_SIP]                = {118,   1},
 801         /* IP4_TCP_UDP (TYPE=100) */
 802         [VCAP_IS2_HK_TCP]                       = {119,   1},
 803         [VCAP_IS2_HK_L4_DPORT]                  = {120,  16},
 804         [VCAP_IS2_HK_L4_SPORT]                  = {136,  16},
 805         [VCAP_IS2_HK_L4_RNG]                    = {152,   8},
 806         [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]         = {160,   1},
 807         [VCAP_IS2_HK_L4_SEQUENCE_EQ0]           = {161,   1},
 808         [VCAP_IS2_HK_L4_FIN]                    = {162,   1},
 809         [VCAP_IS2_HK_L4_SYN]                    = {163,   1},
 810         [VCAP_IS2_HK_L4_RST]                    = {164,   1},
 811         [VCAP_IS2_HK_L4_PSH]                    = {165,   1},
 812         [VCAP_IS2_HK_L4_ACK]                    = {166,   1},
 813         [VCAP_IS2_HK_L4_URG]                    = {167,   1},
 814         [VCAP_IS2_HK_L4_1588_DOM]               = {168,   8},
 815         [VCAP_IS2_HK_L4_1588_VER]               = {176,   4},
 816         /* IP4_OTHER (TYPE=101) */
 817         [VCAP_IS2_HK_IP4_L3_PROTO]              = {119,   8},
 818         [VCAP_IS2_HK_L3_PAYLOAD]                = {127,  56},
 819         /* IP6_STD (TYPE=110) */
 820         [VCAP_IS2_HK_IP6_L3_TTL_GT0]            = { 41,   1},
 821         [VCAP_IS2_HK_L3_IP6_SIP]                = { 42, 128},
 822         [VCAP_IS2_HK_IP6_L3_PROTO]              = {170,   8},
 823         /* OAM (TYPE=111) */
 824         [VCAP_IS2_HK_OAM_MEL_FLAGS]             = {137,   7},
 825         [VCAP_IS2_HK_OAM_VER]                   = {144,   5},
 826         [VCAP_IS2_HK_OAM_OPCODE]                = {149,   8},
 827         [VCAP_IS2_HK_OAM_FLAGS]                 = {157,   8},
 828         [VCAP_IS2_HK_OAM_MEPID]                 = {165,  16},
 829         [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]          = {181,   1},
 830         [VCAP_IS2_HK_OAM_IS_Y1731]              = {182,   1},
 831 };
 832
 833 static struct vcap_field vsc9959_vcap_is2_actions[] = {
 834         [VCAP_IS2_ACT_HIT_ME_ONCE]              = {  0,  1},
 835         [VCAP_IS2_ACT_CPU_COPY_ENA]             = {  1,  1},
 836         [VCAP_IS2_ACT_CPU_QU_NUM]               = {  2,  3},
 837         [VCAP_IS2_ACT_MASK_MODE]                = {  5,  2},
 838         [VCAP_IS2_ACT_MIRROR_ENA]               = {  7,  1},
 839         [VCAP_IS2_ACT_LRN_DIS]                  = {  8,  1},
 840         [VCAP_IS2_ACT_POLICE_ENA]               = {  9,  1},
 841         [VCAP_IS2_ACT_POLICE_IDX]               = { 10,  9},
 842         [VCAP_IS2_ACT_POLICE_VCAP_ONLY]         = { 19,  1},
 843         [VCAP_IS2_ACT_PORT_MASK]                = { 20,  6},
 844         [VCAP_IS2_ACT_REW_OP]                   = { 26,  9},
 845         [VCAP_IS2_ACT_SMAC_REPLACE_ENA]         = { 35,  1},
 846         [VCAP_IS2_ACT_RSV]                      = { 36,  2},
 847         [VCAP_IS2_ACT_ACL_ID]                   = { 38,  6},
 848         [VCAP_IS2_ACT_HIT_CNT]                  = { 44, 32},
 849 };
 850
 851 static struct vcap_props vsc9959_vcap_props[] = {
 852         [VCAP_ES0] = {
 853                 .action_type_width = 0,
 854                 .action_table = {
 855                         [ES0_ACTION_TYPE_NORMAL] = {
 856                                 .width = 72, /* HIT_STICKY not included */
 857                                 .count = 1,
 858                         },
 859                 },
 860                 .target = S0,
 861                 .keys = vsc9959_vcap_es0_keys,
 862                 .actions = vsc9959_vcap_es0_actions,
 863         },
 864         [VCAP_IS1] = {
 865                 .action_type_width = 0,
 866                 .action_table = {
 867                         [IS1_ACTION_TYPE_NORMAL] = {
 868                                 .width = 78, /* HIT_STICKY not included */
 869                                 .count = 4,
 870                         },
 871                 },
 872                 .target = S1,
 873                 .keys = vsc9959_vcap_is1_keys,
 874                 .actions = vsc9959_vcap_is1_actions,
 875         },
 876         [VCAP_IS2] = {
 877                 .action_type_width = 1,
 878                 .action_table = {
 879                         [IS2_ACTION_TYPE_NORMAL] = {
 880                                 .width = 44,
 881                                 .count = 2
 882                         },
 883                         [IS2_ACTION_TYPE_SMAC_SIP] = {
 884                                 .width = 6,
 885                                 .count = 4
 886                         },
 887                 },
 888                 .target = S2,
 889                 .keys = vsc9959_vcap_is2_keys,
 890                 .actions = vsc9959_vcap_is2_actions,
 891         },
 892 };
 893
 894 static const struct ptp_clock_info vsc9959_ptp_caps = {
 895         .owner          = THIS_MODULE,
 896         .name           = "felix ptp",
 897         .max_adj        = 0x7fffffff,
 898         .n_alarm        = 0,
 899         .n_ext_ts       = 0,
 900         .n_per_out      = OCELOT_PTP_PINS_NUM,
 901         .n_pins         = OCELOT_PTP_PINS_NUM,
 902         .pps            = 0,
 903         .gettime64      = ocelot_ptp_gettime64,
 904         .settime64      = ocelot_ptp_settime64,
 905         .adjtime        = ocelot_ptp_adjtime,
 906         .adjfine        = ocelot_ptp_adjfine,
 907         .verify         = ocelot_ptp_verify,
 908         .enable         = ocelot_ptp_enable,
 909 };
 910
 911 #define VSC9959_INIT_TIMEOUT                    50000
 912 #define VSC9959_GCB_RST_SLEEP                   100
 913 #define VSC9959_SYS_RAMINIT_SLEEP               80
 914
 915 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
 916 {
 917         int val;
 918
 919         ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
 920
 921         return val;
 922 }
 923
 924 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
 925 {
 926         return ocelot_read(ocelot, SYS_RAM_INIT);
 927 }
 928
 929 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
 930  * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
 931  */
 932 static int vsc9959_reset(struct ocelot *ocelot)
 933 {
 934         int val, err;
 935
 936         /* soft-reset the switch core */
 937         ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
 938
 939         err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
 940                                  VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
 941         if (err) {
 942                 dev_err(ocelot->dev, "timeout: switch core reset\n");
 943                 return err;
 944         }
 945
 946         /* initialize switch mem ~40us */
 947         ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
 948         err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
 949                                  VSC9959_SYS_RAMINIT_SLEEP,
 950                                  VSC9959_INIT_TIMEOUT);
 951         if (err) {
 952                 dev_err(ocelot->dev, "timeout: switch sram init\n");
 953                 return err;
 954         }
 955
 956         /* enable switch core */
 957         ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
 958
 959         return 0;
 960 }
 961
 962 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
 963                                      unsigned long *supported,
 964                                      struct phylink_link_state *state)
 965 {
 966         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 967
 968         phylink_set_port_modes(mask);
 969         phylink_set(mask, Autoneg);
 970         phylink_set(mask, Pause);
 971         phylink_set(mask, Asym_Pause);
 972         phylink_set(mask, 10baseT_Half);
 973         phylink_set(mask, 10baseT_Full);
 974         phylink_set(mask, 100baseT_Half);
 975         phylink_set(mask, 100baseT_Full);
 976         phylink_set(mask, 1000baseT_Half);
 977         phylink_set(mask, 1000baseT_Full);
 978         phylink_set(mask, 1000baseX_Full);
 979
 980         if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
 981             state->interface == PHY_INTERFACE_MODE_2500BASEX ||
 982             state->interface == PHY_INTERFACE_MODE_USXGMII) {
 983                 phylink_set(mask, 2500baseT_Full);
 984                 phylink_set(mask, 2500baseX_Full);
 985         }
 986
 987         linkmode_and(supported, supported, mask);
 988         linkmode_and(state->advertising, state->advertising, mask);
 989 }
 990
 991 /* Watermark encode
 992  * Bit 8:   Unit; 0:1, 1:16
 993  * Bit 7-0: Value to be multiplied with unit
 994  */
 995 static u16 vsc9959_wm_enc(u16 value)
 996 {
 997         WARN_ON(value >= 16 * BIT(8));
 998
 999         if (value >= BIT(8))
1000                 return BIT(8) | (value / 16);
1001
1002         return value;
1003 }
1004
1005 static u16 vsc9959_wm_dec(u16 wm)
1006 {
1007         WARN_ON(wm & ~GENMASK(8, 0));
1008
1009         if (wm & BIT(8))
1010                 return (wm & GENMASK(7, 0)) * 16;
1011
1012         return wm;
1013 }
1014
1015 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1016 {
1017         *inuse = (val & GENMASK(23, 12)) >> 12;
1018         *maxuse = val & GENMASK(11, 0);
1019 }
1020
1021 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1022 {
1023         struct felix *felix = ocelot_to_felix(ocelot);
1024         struct enetc_mdio_priv *mdio_priv;
1025         struct device *dev = ocelot->dev;
1026         void __iomem *imdio_regs;
1027         struct resource res;
1028         struct enetc_hw *hw;
1029         struct mii_bus *bus;
1030         int port;
1031         int rc;
1032
1033         felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1034                                   sizeof(struct phylink_pcs *),
1035                                   GFP_KERNEL);
1036         if (!felix->pcs) {
1037                 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1038                 return -ENOMEM;
1039         }
1040
1041         memcpy(&res, felix->info->imdio_res, sizeof(res));
1042         res.flags = IORESOURCE_MEM;
1043         res.start += felix->imdio_base;
1044         res.end += felix->imdio_base;
1045
1046         imdio_regs = devm_ioremap_resource(dev, &res);
1047         if (IS_ERR(imdio_regs))
1048                 return PTR_ERR(imdio_regs);
1049
1050         hw = enetc_hw_alloc(dev, imdio_regs);
1051         if (IS_ERR(hw)) {
1052                 dev_err(dev, "failed to allocate ENETC HW structure\n");
1053                 return PTR_ERR(hw);
1054         }
1055
1056         bus = mdiobus_alloc_size(sizeof(*mdio_priv));
1057         if (!bus)
1058                 return -ENOMEM;
1059
1060         bus->name = "VSC9959 internal MDIO bus";
1061         bus->read = enetc_mdio_read;
1062         bus->write = enetc_mdio_write;
1063         bus->parent = dev;
1064         mdio_priv = bus->priv;
1065         mdio_priv->hw = hw;
1066         /* This gets added to imdio_regs, which already maps addresses
1067          * starting with the proper offset.
1068          */
1069         mdio_priv->mdio_base = 0;
1070         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1071
1072         /* Needed in order to initialize the bus mutex lock */
1073         rc = mdiobus_register(bus);
1074         if (rc < 0) {
1075                 dev_err(dev, "failed to register MDIO bus\n");
1076                 mdiobus_free(bus);
1077                 return rc;
1078         }
1079
1080         felix->imdio = bus;
1081
1082         for (port = 0; port < felix->info->num_ports; port++) {
1083                 struct ocelot_port *ocelot_port = ocelot->ports[port];
1084                 struct phylink_pcs *phylink_pcs;
1085                 struct mdio_device *mdio_device;
1086
1087                 if (dsa_is_unused_port(felix->ds, port))
1088                         continue;
1089
1090                 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1091                         continue;
1092
1093                 mdio_device = mdio_device_create(felix->imdio, port);
1094                 if (IS_ERR(mdio_device))
1095                         continue;
1096
1097                 phylink_pcs = lynx_pcs_create(mdio_device);
1098                 if (!phylink_pcs) {
1099                         mdio_device_free(mdio_device);
1100                         continue;
1101                 }
1102
1103                 felix->pcs[port] = phylink_pcs;
1104
1105                 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1106         }
1107
1108         return 0;
1109 }
1110
1111 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1112 {
1113         struct felix *felix = ocelot_to_felix(ocelot);
1114         int port;
1115
1116         for (port = 0; port < ocelot->num_phys_ports; port++) {
1117                 struct phylink_pcs *phylink_pcs = felix->pcs[port];
1118                 struct mdio_device *mdio_device;
1119
1120                 if (!phylink_pcs)
1121                         continue;
1122
1123                 mdio_device = lynx_get_mdio_device(phylink_pcs);
1124                 mdio_device_free(mdio_device);
1125                 lynx_pcs_destroy(phylink_pcs);
1126         }
1127         mdiobus_unregister(felix->imdio);
1128         mdiobus_free(felix->imdio);
1129 }
1130
1131 /* Extract shortest continuous gate open intervals in ns for each traffic class
1132  * of a cyclic tc-taprio schedule. If a gate is always open, the duration is
1133  * considered U64_MAX. If the gate is always closed, it is considered 0.
1134  */
1135 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio,
1136                                          u64 min_gate_len[OCELOT_NUM_TC])
1137 {
1138         struct tc_taprio_sched_entry *entry;
1139         u64 gate_len[OCELOT_NUM_TC];
1140         u8 gates_ever_opened = 0;
1141         int tc, i, n;
1142
1143         /* Initialize arrays */
1144         for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1145                 min_gate_len[tc] = U64_MAX;
1146                 gate_len[tc] = 0;
1147         }
1148
1149         /* If we don't have taprio, consider all gates as permanently open */
1150         if (!taprio)
1151                 return;
1152
1153         n = taprio->num_entries;
1154
1155         /* Walk through the gate list twice to determine the length
1156          * of consecutively open gates for a traffic class, including
1157          * open gates that wrap around. We are just interested in the
1158          * minimum window size, and this doesn't change what the
1159          * minimum is (if the gate never closes, min_gate_len will
1160          * remain U64_MAX).
1161          */
1162         for (i = 0; i < 2 * n; i++) {
1163                 entry = &taprio->entries[i % n];
1164
1165                 for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1166                         if (entry->gate_mask & BIT(tc)) {
1167                                 gate_len[tc] += entry->interval;
1168                                 gates_ever_opened |= BIT(tc);
1169                         } else {
1170                                 /* Gate closes now, record a potential new
1171                                  * minimum and reinitialize length
1172                                  */
1173                                 if (min_gate_len[tc] > gate_len[tc] &&
1174                                     gate_len[tc])
1175                                         min_gate_len[tc] = gate_len[tc];
1176                                 gate_len[tc] = 0;
1177                         }
1178                 }
1179         }
1180
1181         /* min_gate_len[tc] actually tracks minimum *open* gate time, so for
1182          * permanently closed gates, min_gate_len[tc] will still be U64_MAX.
1183          * Therefore they are currently indistinguishable from permanently
1184          * open gates. Overwrite the gate len with 0 when we know they're
1185          * actually permanently closed, i.e. after the loop above.
1186          */
1187         for (tc = 0; tc < OCELOT_NUM_TC; tc++)
1188                 if (!(gates_ever_opened & BIT(tc)))
1189                         min_gate_len[tc] = 0;
1190 }
1191
1192 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the
1193  * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU
1194  * values (the default value is 1518). Also, for traffic class windows smaller
1195  * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame
1196  * dropping, such that these won't hang the port, as they will never be sent.
1197  */
1198 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port)
1199 {
1200         struct ocelot_port *ocelot_port = ocelot->ports[port];
1201         u64 min_gate_len[OCELOT_NUM_TC];
1202         int speed, picos_per_byte;
1203         u64 needed_bit_time_ps;
1204         u32 val, maxlen;
1205         u8 tas_speed;
1206         int tc;
1207
1208         lockdep_assert_held(&ocelot->tas_lock);
1209
1210         val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1211         tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val);
1212
1213         switch (tas_speed) {
1214         case OCELOT_SPEED_10:
1215                 speed = SPEED_10;
1216                 break;
1217         case OCELOT_SPEED_100:
1218                 speed = SPEED_100;
1219                 break;
1220         case OCELOT_SPEED_1000:
1221                 speed = SPEED_1000;
1222                 break;
1223         case OCELOT_SPEED_2500:
1224                 speed = SPEED_2500;
1225                 break;
1226         default:
1227                 return;
1228         }
1229
1230         picos_per_byte = (USEC_PER_SEC * 8) / speed;
1231
1232         val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG);
1233         /* MAXLEN_CFG accounts automatically for VLAN. We need to include it
1234          * manually in the bit time calculation, plus the preamble and SFD.
1235          */
1236         maxlen = val + 2 * VLAN_HLEN;
1237         /* Consider the standard Ethernet overhead of 8 octets preamble+SFD,
1238          * 4 octets FCS, 12 octets IFG.
1239          */
1240         needed_bit_time_ps = (maxlen + 24) * picos_per_byte;
1241
1242         dev_dbg(ocelot->dev,
1243                 "port %d: max frame size %d needs %llu ps at speed %d\n",
1244                 port, maxlen, needed_bit_time_ps, speed);
1245
1246         vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len);
1247
1248         for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1249                 u32 max_sdu;
1250
1251                 if (min_gate_len[tc] == U64_MAX /* Gate always open */ ||
1252                     min_gate_len[tc] * PSEC_PER_NSEC > needed_bit_time_ps) {
1253                         /* Setting QMAXSDU_CFG to 0 disables oversized frame
1254                          * dropping.
1255                          */
1256                         max_sdu = 0;
1257                         dev_dbg(ocelot->dev,
1258                                 "port %d tc %d min gate len %llu"
1259                                 ", sending all frames\n",
1260                                 port, tc, min_gate_len[tc]);
1261                 } else {
1262                         /* If traffic class doesn't support a full MTU sized
1263                          * frame, make sure to enable oversize frame dropping
1264                          * for frames larger than the smallest that would fit.
1265                          */
1266                         max_sdu = div_u64(min_gate_len[tc] * PSEC_PER_NSEC,
1267                                           picos_per_byte);
1268                         /* A TC gate may be completely closed, which is a
1269                          * special case where all packets are oversized.
1270                          * Any limit smaller than 64 octets accomplishes this
1271                          */
1272                         if (!max_sdu)
1273                                 max_sdu = 1;
1274                         /* Take L1 overhead into account, but just don't allow
1275                          * max_sdu to go negative or to 0. Here we use 20
1276                          * because QSYS_MAXSDU_CFG_* already counts the 4 FCS
1277                          * octets as part of packet size.
1278                          */
1279                         if (max_sdu > 20)
1280                                 max_sdu -= 20;
1281                         dev_info(ocelot->dev,
1282                                  "port %d tc %d min gate length %llu"
1283                                  " ns not enough for max frame size %d at %d"
1284                                  " Mbps, dropping frames over %d"
1285                                  " octets including FCS\n",
1286                                  port, tc, min_gate_len[tc], maxlen, speed,
1287                                  max_sdu);
1288                 }
1289
1290                 /* ocelot_write_rix is a macro that concatenates
1291                  * QSYS_MAXSDU_CFG_* with _RSZ, so we need to spell out
1292                  * the writes to each traffic class
1293                  */
1294                 switch (tc) {
1295                 case 0:
1296                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0,
1297                                          port);
1298                         break;
1299                 case 1:
1300                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1,
1301                                          port);
1302                         break;
1303                 case 2:
1304                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2,
1305                                          port);
1306                         break;
1307                 case 3:
1308                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3,
1309                                          port);
1310                         break;
1311                 case 4:
1312                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4,
1313                                          port);
1314                         break;
1315                 case 5:
1316                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5,
1317                                          port);
1318                         break;
1319                 case 6:
1320                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6,
1321                                          port);
1322                         break;
1323                 case 7:
1324                         ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7,
1325                                          port);
1326                         break;
1327                 }
1328         }
1329
1330         ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port);
1331 }
1332
1333 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1334                                     u32 speed)
1335 {
1336         struct ocelot_port *ocelot_port = ocelot->ports[port];
1337         u8 tas_speed;
1338
1339         switch (speed) {
1340         case SPEED_10:
1341                 tas_speed = OCELOT_SPEED_10;
1342                 break;
1343         case SPEED_100:
1344                 tas_speed = OCELOT_SPEED_100;
1345                 break;
1346         case SPEED_1000:
1347                 tas_speed = OCELOT_SPEED_1000;
1348                 break;
1349         case SPEED_2500:
1350                 tas_speed = OCELOT_SPEED_2500;
1351                 break;
1352         default:
1353                 tas_speed = OCELOT_SPEED_1000;
1354                 break;
1355         }
1356
1357         ocelot_rmw_rix(ocelot,
1358                        QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1359                        QSYS_TAG_CONFIG_LINK_SPEED_M,
1360                        QSYS_TAG_CONFIG, port);
1361
1362         mutex_lock(&ocelot->tas_lock);
1363
1364         if (ocelot_port->taprio)
1365                 vsc9959_tas_guard_bands_update(ocelot, port);
1366
1367         mutex_unlock(&ocelot->tas_lock);
1368 }
1369
1370 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1371                                   u64 cycle_time,
1372                                   struct timespec64 *new_base_ts)
1373 {
1374         struct timespec64 ts;
1375         ktime_t new_base_time;
1376         ktime_t current_time;
1377
1378         ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1379         current_time = timespec64_to_ktime(ts);
1380         new_base_time = base_time;
1381
1382         if (base_time < current_time) {
1383                 u64 nr_of_cycles = current_time - base_time;
1384
1385                 do_div(nr_of_cycles, cycle_time);
1386                 new_base_time += cycle_time * (nr_of_cycles + 1);
1387         }
1388
1389         *new_base_ts = ktime_to_timespec64(new_base_time);
1390 }
1391
1392 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1393 {
1394         return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1395 }
1396
1397 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1398                                 struct tc_taprio_sched_entry *entry)
1399 {
1400         ocelot_write(ocelot,
1401                      QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1402                      QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1403                      QSYS_GCL_CFG_REG_1);
1404         ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1405 }
1406
1407 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1408                                     struct tc_taprio_qopt_offload *taprio)
1409 {
1410         struct ocelot_port *ocelot_port = ocelot->ports[port];
1411         struct timespec64 base_ts;
1412         int ret, i;
1413         u32 val;
1414
1415         mutex_lock(&ocelot->tas_lock);
1416
1417         if (!taprio->enable) {
1418                 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1419                                QSYS_TAG_CONFIG, port);
1420
1421                 taprio_offload_free(ocelot_port->taprio);
1422                 ocelot_port->taprio = NULL;
1423
1424                 vsc9959_tas_guard_bands_update(ocelot, port);
1425
1426                 mutex_unlock(&ocelot->tas_lock);
1427                 return 0;
1428         }
1429
1430         if (taprio->cycle_time > NSEC_PER_SEC ||
1431             taprio->cycle_time_extension >= NSEC_PER_SEC) {
1432                 ret = -EINVAL;
1433                 goto err;
1434         }
1435
1436         if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) {
1437                 ret = -ERANGE;
1438                 goto err;
1439         }
1440
1441         /* Enable guard band. The switch will schedule frames without taking
1442          * their length into account. Thus we'll always need to enable the
1443          * guard band which reserves the time of a maximum sized frame at the
1444          * end of the time window.
1445          *
1446          * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1447          * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1448          * operate on the port number.
1449          */
1450         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1451                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1452                    QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1453                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1454                    QSYS_TAS_PARAM_CFG_CTRL);
1455
1456         /* Hardware errata -  Admin config could not be overwritten if
1457          * config is pending, need reset the TAS module
1458          */
1459         val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1460         if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1461                 ret = -EBUSY;
1462                 goto err;
1463         }
1464
1465         ocelot_rmw_rix(ocelot,
1466                        QSYS_TAG_CONFIG_ENABLE |
1467                        QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1468                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1469                        QSYS_TAG_CONFIG_ENABLE |
1470                        QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1471                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1472                        QSYS_TAG_CONFIG, port);
1473
1474         vsc9959_new_base_time(ocelot, taprio->base_time,
1475                               taprio->cycle_time, &base_ts);
1476         ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1477         ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1478         val = upper_32_bits(base_ts.tv_sec);
1479         ocelot_write(ocelot,
1480                      QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1481                      QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1482                      QSYS_PARAM_CFG_REG_3);
1483         ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1484         ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1485
1486         for (i = 0; i < taprio->num_entries; i++)
1487                 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1488
1489         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1490                    QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1491                    QSYS_TAS_PARAM_CFG_CTRL);
1492
1493         ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1494                                  !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1495                                  10, 100000);
1496         if (ret)
1497                 goto err;
1498
1499         ocelot_port->taprio = taprio_offload_get(taprio);
1500         vsc9959_tas_guard_bands_update(ocelot, port);
1501
1502 err:
1503         mutex_unlock(&ocelot->tas_lock);
1504
1505         return ret;
1506 }
1507
1508 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot)
1509 {
1510         struct tc_taprio_qopt_offload *taprio;
1511         struct ocelot_port *ocelot_port;
1512         struct timespec64 base_ts;
1513         int port;
1514         u32 val;
1515
1516         mutex_lock(&ocelot->tas_lock);
1517
1518         for (port = 0; port < ocelot->num_phys_ports; port++) {
1519                 ocelot_port = ocelot->ports[port];
1520                 taprio = ocelot_port->taprio;
1521                 if (!taprio)
1522                         continue;
1523
1524                 ocelot_rmw(ocelot,
1525                            QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port),
1526                            QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M,
1527                            QSYS_TAS_PARAM_CFG_CTRL);
1528
1529                 /* Disable time-aware shaper */
1530                 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1531                                QSYS_TAG_CONFIG, port);
1532
1533                 vsc9959_new_base_time(ocelot, taprio->base_time,
1534                                       taprio->cycle_time, &base_ts);
1535
1536                 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1537                 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec),
1538                              QSYS_PARAM_CFG_REG_2);
1539                 val = upper_32_bits(base_ts.tv_sec);
1540                 ocelot_rmw(ocelot,
1541                            QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val),
1542                            QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M,
1543                            QSYS_PARAM_CFG_REG_3);
1544
1545                 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1546                            QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1547                            QSYS_TAS_PARAM_CFG_CTRL);
1548
1549                 /* Re-enable time-aware shaper */
1550                 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE,
1551                                QSYS_TAG_CONFIG_ENABLE,
1552                                QSYS_TAG_CONFIG, port);
1553         }
1554         mutex_unlock(&ocelot->tas_lock);
1555 }
1556
1557 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1558                                     struct tc_cbs_qopt_offload *cbs_qopt)
1559 {
1560         struct ocelot *ocelot = ds->priv;
1561         int port_ix = port * 8 + cbs_qopt->queue;
1562         u32 rate, burst;
1563
1564         if (cbs_qopt->queue >= ds->num_tx_queues)
1565                 return -EINVAL;
1566
1567         if (!cbs_qopt->enable) {
1568                 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1569                                  QSYS_CIR_CFG_CIR_BURST(0),
1570                                  QSYS_CIR_CFG, port_ix);
1571
1572                 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1573                                QSYS_SE_CFG, port_ix);
1574
1575                 return 0;
1576         }
1577
1578         /* Rate unit is 100 kbps */
1579         rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1580         /* Avoid using zero rate */
1581         rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1582         /* Burst unit is 4kB */
1583         burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1584         /* Avoid using zero burst size */
1585         burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1586         ocelot_write_gix(ocelot,
1587                          QSYS_CIR_CFG_CIR_RATE(rate) |
1588                          QSYS_CIR_CFG_CIR_BURST(burst),
1589                          QSYS_CIR_CFG,
1590                          port_ix);
1591
1592         ocelot_rmw_gix(ocelot,
1593                        QSYS_SE_CFG_SE_FRM_MODE(0) |
1594                        QSYS_SE_CFG_SE_AVB_ENA,
1595                        QSYS_SE_CFG_SE_AVB_ENA |
1596                        QSYS_SE_CFG_SE_FRM_MODE_M,
1597                        QSYS_SE_CFG,
1598                        port_ix);
1599
1600         return 0;
1601 }
1602
1603 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1604                                  enum tc_setup_type type,
1605                                  void *type_data)
1606 {
1607         struct ocelot *ocelot = ds->priv;
1608
1609         switch (type) {
1610         case TC_SETUP_QDISC_TAPRIO:
1611                 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1612         case TC_SETUP_QDISC_CBS:
1613                 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1614         default:
1615                 return -EOPNOTSUPP;
1616         }
1617 }
1618
1619 #define VSC9959_PSFP_SFID_MAX                   175
1620 #define VSC9959_PSFP_GATE_ID_MAX                183
1621 #define VSC9959_PSFP_POLICER_BASE               63
1622 #define VSC9959_PSFP_POLICER_MAX                383
1623 #define VSC9959_PSFP_GATE_LIST_NUM              4
1624 #define VSC9959_PSFP_GATE_CYCLETIME_MIN         5000
1625
1626 struct felix_stream {
1627         struct list_head list;
1628         unsigned long id;
1629         bool dummy;
1630         int ports;
1631         int port;
1632         u8 dmac[ETH_ALEN];
1633         u16 vid;
1634         s8 prio;
1635         u8 sfid_valid;
1636         u8 ssid_valid;
1637         u32 sfid;
1638         u32 ssid;
1639 };
1640
1641 struct felix_stream_filter {
1642         struct list_head list;
1643         refcount_t refcount;
1644         u32 index;
1645         u8 enable;
1646         int portmask;
1647         u8 sg_valid;
1648         u32 sgid;
1649         u8 fm_valid;
1650         u32 fmid;
1651         u8 prio_valid;
1652         u8 prio;
1653         u32 maxsdu;
1654 };
1655
1656 struct felix_stream_filter_counters {
1657         u32 match;
1658         u32 not_pass_gate;
1659         u32 not_pass_sdu;
1660         u32 red;
1661 };
1662
1663 struct felix_stream_gate {
1664         u32 index;
1665         u8 enable;
1666         u8 ipv_valid;
1667         u8 init_ipv;
1668         u64 basetime;
1669         u64 cycletime;
1670         u64 cycletime_ext;
1671         u32 num_entries;
1672         struct action_gate_entry entries[];
1673 };
1674
1675 struct felix_stream_gate_entry {
1676         struct list_head list;
1677         refcount_t refcount;
1678         u32 index;
1679 };
1680
1681 static int vsc9959_stream_identify(struct flow_cls_offload *f,
1682                                    struct felix_stream *stream)
1683 {
1684         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1685         struct flow_dissector *dissector = rule->match.dissector;
1686
1687         if (dissector->used_keys &
1688             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1689               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1690               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1691               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
1692                 return -EOPNOTSUPP;
1693
1694         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1695                 struct flow_match_eth_addrs match;
1696
1697                 flow_rule_match_eth_addrs(rule, &match);
1698                 ether_addr_copy(stream->dmac, match.key->dst);
1699                 if (!is_zero_ether_addr(match.mask->src))
1700                         return -EOPNOTSUPP;
1701         } else {
1702                 return -EOPNOTSUPP;
1703         }
1704
1705         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1706                 struct flow_match_vlan match;
1707
1708                 flow_rule_match_vlan(rule, &match);
1709                 if (match.mask->vlan_priority)
1710                         stream->prio = match.key->vlan_priority;
1711                 else
1712                         stream->prio = -1;
1713
1714                 if (!match.mask->vlan_id)
1715                         return -EOPNOTSUPP;
1716                 stream->vid = match.key->vlan_id;
1717         } else {
1718                 return -EOPNOTSUPP;
1719         }
1720
1721         stream->id = f->cookie;
1722
1723         return 0;
1724 }
1725
1726 static int vsc9959_mact_stream_set(struct ocelot *ocelot,
1727                                    struct felix_stream *stream,
1728                                    struct netlink_ext_ack *extack)
1729 {
1730         enum macaccess_entry_type type;
1731         int ret, sfid, ssid;
1732         u32 vid, dst_idx;
1733         u8 mac[ETH_ALEN];
1734
1735         ether_addr_copy(mac, stream->dmac);
1736         vid = stream->vid;
1737
1738         /* Stream identification desn't support to add a stream with non
1739          * existent MAC (The MAC entry has not been learned in MAC table).
1740          */
1741         ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
1742         if (ret) {
1743                 if (extack)
1744                         NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
1745                 return -EOPNOTSUPP;
1746         }
1747
1748         if ((stream->sfid_valid || stream->ssid_valid) &&
1749             type == ENTRYTYPE_NORMAL)
1750                 type = ENTRYTYPE_LOCKED;
1751
1752         sfid = stream->sfid_valid ? stream->sfid : -1;
1753         ssid = stream->ssid_valid ? stream->ssid : -1;
1754
1755         ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
1756                                            sfid, ssid);
1757
1758         return ret;
1759 }
1760
1761 static struct felix_stream *
1762 vsc9959_stream_table_lookup(struct list_head *stream_list,
1763                             struct felix_stream *stream)
1764 {
1765         struct felix_stream *tmp;
1766
1767         list_for_each_entry(tmp, stream_list, list)
1768                 if (ether_addr_equal(tmp->dmac, stream->dmac) &&
1769                     tmp->vid == stream->vid)
1770                         return tmp;
1771
1772         return NULL;
1773 }
1774
1775 static int vsc9959_stream_table_add(struct ocelot *ocelot,
1776                                     struct list_head *stream_list,
1777                                     struct felix_stream *stream,
1778                                     struct netlink_ext_ack *extack)
1779 {
1780         struct felix_stream *stream_entry;
1781         int ret;
1782
1783         stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
1784         if (!stream_entry)
1785                 return -ENOMEM;
1786
1787         if (!stream->dummy) {
1788                 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
1789                 if (ret) {
1790                         kfree(stream_entry);
1791                         return ret;
1792                 }
1793         }
1794
1795         list_add_tail(&stream_entry->list, stream_list);
1796
1797         return 0;
1798 }
1799
1800 static struct felix_stream *
1801 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
1802 {
1803         struct felix_stream *tmp;
1804
1805         list_for_each_entry(tmp, stream_list, list)
1806                 if (tmp->id == id)
1807                         return tmp;
1808
1809         return NULL;
1810 }
1811
1812 static void vsc9959_stream_table_del(struct ocelot *ocelot,
1813                                      struct felix_stream *stream)
1814 {
1815         if (!stream->dummy)
1816                 vsc9959_mact_stream_set(ocelot, stream, NULL);
1817
1818         list_del(&stream->list);
1819         kfree(stream);
1820 }
1821
1822 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
1823 {
1824         return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
1825 }
1826
1827 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
1828                                 struct felix_stream_filter *sfi)
1829 {
1830         u32 val;
1831
1832         if (sfi->index > VSC9959_PSFP_SFID_MAX)
1833                 return -EINVAL;
1834
1835         if (!sfi->enable) {
1836                 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1837                              ANA_TABLES_SFIDTIDX);
1838
1839                 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
1840                 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
1841
1842                 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1843                                           (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1844                                           10, 100000);
1845         }
1846
1847         if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
1848             sfi->fmid > VSC9959_PSFP_POLICER_MAX)
1849                 return -EINVAL;
1850
1851         ocelot_write(ocelot,
1852                      (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
1853                      ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
1854                      (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
1855                      ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
1856                      ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1857                      ANA_TABLES_SFIDTIDX);
1858
1859         ocelot_write(ocelot,
1860                      (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
1861                      ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
1862                      ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
1863                      ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1864                      ANA_TABLES_SFIDACCESS);
1865
1866         return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1867                                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1868                                   10, 100000);
1869 }
1870
1871 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1872 {
1873         u32 val;
1874
1875         ocelot_rmw(ocelot,
1876                    ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1877                    ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1878                    ANA_TABLES_SFIDTIDX);
1879
1880         ocelot_write(ocelot,
1881                      ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1882                      ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1883                      ANA_TABLES_SFID_MASK);
1884
1885         ocelot_rmw(ocelot,
1886                    ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1887                    ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1888                    ANA_TABLES_SFIDACCESS);
1889
1890         return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1891                                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1892                                   10, 100000);
1893 }
1894
1895 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1896                                      struct felix_stream_filter *sfi,
1897                                      struct list_head *pos)
1898 {
1899         struct felix_stream_filter *sfi_entry;
1900         int ret;
1901
1902         sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
1903         if (!sfi_entry)
1904                 return -ENOMEM;
1905
1906         refcount_set(&sfi_entry->refcount, 1);
1907
1908         ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
1909         if (ret) {
1910                 kfree(sfi_entry);
1911                 return ret;
1912         }
1913
1914         vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1915
1916         list_add(&sfi_entry->list, pos);
1917
1918         return 0;
1919 }
1920
1921 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1922                                       struct felix_stream_filter *sfi)
1923 {
1924         struct list_head *pos, *q, *last;
1925         struct felix_stream_filter *tmp;
1926         struct ocelot_psfp_list *psfp;
1927         u32 insert = 0;
1928
1929         psfp = &ocelot->psfp;
1930         last = &psfp->sfi_list;
1931
1932         list_for_each_safe(pos, q, &psfp->sfi_list) {
1933                 tmp = list_entry(pos, struct felix_stream_filter, list);
1934                 if (sfi->sg_valid == tmp->sg_valid &&
1935                     sfi->fm_valid == tmp->fm_valid &&
1936                     sfi->portmask == tmp->portmask &&
1937                     tmp->sgid == sfi->sgid &&
1938                     tmp->fmid == sfi->fmid) {
1939                         sfi->index = tmp->index;
1940                         refcount_inc(&tmp->refcount);
1941                         return 0;
1942                 }
1943                 /* Make sure that the index is increasing in order. */
1944                 if (tmp->index == insert) {
1945                         last = pos;
1946                         insert++;
1947                 }
1948         }
1949         sfi->index = insert;
1950
1951         return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1952 }
1953
1954 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
1955                                        struct felix_stream_filter *sfi,
1956                                        struct felix_stream_filter *sfi2)
1957 {
1958         struct felix_stream_filter *tmp;
1959         struct list_head *pos, *q, *last;
1960         struct ocelot_psfp_list *psfp;
1961         u32 insert = 0;
1962         int ret;
1963
1964         psfp = &ocelot->psfp;
1965         last = &psfp->sfi_list;
1966
1967         list_for_each_safe(pos, q, &psfp->sfi_list) {
1968                 tmp = list_entry(pos, struct felix_stream_filter, list);
1969                 /* Make sure that the index is increasing in order. */
1970                 if (tmp->index >= insert + 2)
1971                         break;
1972
1973                 insert = tmp->index + 1;
1974                 last = pos;
1975         }
1976         sfi->index = insert;
1977
1978         ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1979         if (ret)
1980                 return ret;
1981
1982         sfi2->index = insert + 1;
1983
1984         return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
1985 }
1986
1987 static struct felix_stream_filter *
1988 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
1989 {
1990         struct felix_stream_filter *tmp;
1991
1992         list_for_each_entry(tmp, sfi_list, list)
1993                 if (tmp->index == index)
1994                         return tmp;
1995
1996         return NULL;
1997 }
1998
1999 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
2000 {
2001         struct felix_stream_filter *tmp, *n;
2002         struct ocelot_psfp_list *psfp;
2003         u8 z;
2004
2005         psfp = &ocelot->psfp;
2006
2007         list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
2008                 if (tmp->index == index) {
2009                         z = refcount_dec_and_test(&tmp->refcount);
2010                         if (z) {
2011                                 tmp->enable = 0;
2012                                 vsc9959_psfp_sfi_set(ocelot, tmp);
2013                                 list_del(&tmp->list);
2014                                 kfree(tmp);
2015                         }
2016                         break;
2017                 }
2018 }
2019
2020 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
2021                                     struct felix_stream_gate *sgi)
2022 {
2023         sgi->index = entry->hw_index;
2024         sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
2025         sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
2026         sgi->basetime = entry->gate.basetime;
2027         sgi->cycletime = entry->gate.cycletime;
2028         sgi->num_entries = entry->gate.num_entries;
2029         sgi->enable = 1;
2030
2031         memcpy(sgi->entries, entry->gate.entries,
2032                entry->gate.num_entries * sizeof(struct action_gate_entry));
2033 }
2034
2035 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
2036 {
2037         return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
2038 }
2039
2040 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
2041                                 struct felix_stream_gate *sgi)
2042 {
2043         struct action_gate_entry *e;
2044         struct timespec64 base_ts;
2045         u32 interval_sum = 0;
2046         u32 val;
2047         int i;
2048
2049         if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
2050                 return -EINVAL;
2051
2052         ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
2053                      ANA_SG_ACCESS_CTRL);
2054
2055         if (!sgi->enable) {
2056                 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
2057                            ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2058                            ANA_SG_CONFIG_REG_3_GATE_ENABLE,
2059                            ANA_SG_CONFIG_REG_3);
2060
2061                 return 0;
2062         }
2063
2064         if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
2065             sgi->cycletime > NSEC_PER_SEC)
2066                 return -EINVAL;
2067
2068         if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
2069                 return -EINVAL;
2070
2071         vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
2072         ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
2073         val = lower_32_bits(base_ts.tv_sec);
2074         ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
2075
2076         val = upper_32_bits(base_ts.tv_sec);
2077         ocelot_write(ocelot,
2078                      (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
2079                      ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
2080                      ANA_SG_CONFIG_REG_3_GATE_ENABLE |
2081                      ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
2082                      ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2083                      ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
2084                      ANA_SG_CONFIG_REG_3);
2085
2086         ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
2087
2088         e = sgi->entries;
2089         for (i = 0; i < sgi->num_entries; i++) {
2090                 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
2091
2092                 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
2093                                  (e[i].gate_state ?
2094                                   ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
2095                                  ANA_SG_GCL_GS_CONFIG, i);
2096
2097                 interval_sum += e[i].interval;
2098                 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
2099         }
2100
2101         ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2102                    ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2103                    ANA_SG_ACCESS_CTRL);
2104
2105         return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
2106                                   (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
2107                                   10, 100000);
2108 }
2109
2110 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
2111                                       struct felix_stream_gate *sgi)
2112 {
2113         struct felix_stream_gate_entry *tmp;
2114         struct ocelot_psfp_list *psfp;
2115         int ret;
2116
2117         psfp = &ocelot->psfp;
2118
2119         list_for_each_entry(tmp, &psfp->sgi_list, list)
2120                 if (tmp->index == sgi->index) {
2121                         refcount_inc(&tmp->refcount);
2122                         return 0;
2123                 }
2124
2125         tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2126         if (!tmp)
2127                 return -ENOMEM;
2128
2129         ret = vsc9959_psfp_sgi_set(ocelot, sgi);
2130         if (ret) {
2131                 kfree(tmp);
2132                 return ret;
2133         }
2134
2135         tmp->index = sgi->index;
2136         refcount_set(&tmp->refcount, 1);
2137         list_add_tail(&tmp->list, &psfp->sgi_list);
2138
2139         return 0;
2140 }
2141
2142 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
2143                                        u32 index)
2144 {
2145         struct felix_stream_gate_entry *tmp, *n;
2146         struct felix_stream_gate sgi = {0};
2147         struct ocelot_psfp_list *psfp;
2148         u8 z;
2149
2150         psfp = &ocelot->psfp;
2151
2152         list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
2153                 if (tmp->index == index) {
2154                         z = refcount_dec_and_test(&tmp->refcount);
2155                         if (z) {
2156                                 sgi.index = index;
2157                                 sgi.enable = 0;
2158                                 vsc9959_psfp_sgi_set(ocelot, &sgi);
2159                                 list_del(&tmp->list);
2160                                 kfree(tmp);
2161                         }
2162                         break;
2163                 }
2164 }
2165
2166 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
2167                                       struct felix_stream_filter_counters *counters)
2168 {
2169         mutex_lock(&ocelot->stats_lock);
2170
2171         ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
2172                    SYS_STAT_CFG_STAT_VIEW_M,
2173                    SYS_STAT_CFG);
2174
2175         counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200);
2176         counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201);
2177         counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202);
2178         counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203);
2179
2180         /* Clear the PSFP counter. */
2181         ocelot_write(ocelot,
2182                      SYS_STAT_CFG_STAT_VIEW(index) |
2183                      SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
2184                      SYS_STAT_CFG);
2185
2186         mutex_unlock(&ocelot->stats_lock);
2187 }
2188
2189 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
2190                                    struct flow_cls_offload *f)
2191 {
2192         struct netlink_ext_ack *extack = f->common.extack;
2193         struct felix_stream_filter old_sfi, *sfi_entry;
2194         struct felix_stream_filter sfi = {0};
2195         const struct flow_action_entry *a;
2196         struct felix_stream *stream_entry;
2197         struct felix_stream stream = {0};
2198         struct felix_stream_gate *sgi;
2199         struct ocelot_psfp_list *psfp;
2200         struct ocelot_policer pol;
2201         int ret, i, size;
2202         u64 rate, burst;
2203         u32 index;
2204
2205         psfp = &ocelot->psfp;
2206
2207         ret = vsc9959_stream_identify(f, &stream);
2208         if (ret) {
2209                 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
2210                 return ret;
2211         }
2212
2213         flow_action_for_each(i, a, &f->rule->action) {
2214                 switch (a->id) {
2215                 case FLOW_ACTION_GATE:
2216                         size = struct_size(sgi, entries, a->gate.num_entries);
2217                         sgi = kzalloc(size, GFP_KERNEL);
2218                         if (!sgi) {
2219                                 ret = -ENOMEM;
2220                                 goto err;
2221                         }
2222                         vsc9959_psfp_parse_gate(a, sgi);
2223                         ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
2224                         if (ret) {
2225                                 kfree(sgi);
2226                                 goto err;
2227                         }
2228                         sfi.sg_valid = 1;
2229                         sfi.sgid = sgi->index;
2230                         kfree(sgi);
2231                         break;
2232                 case FLOW_ACTION_POLICE:
2233                         index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
2234                         if (index > VSC9959_PSFP_POLICER_MAX) {
2235                                 ret = -EINVAL;
2236                                 goto err;
2237                         }
2238
2239                         rate = a->police.rate_bytes_ps;
2240                         burst = rate * PSCHED_NS2TICKS(a->police.burst);
2241                         pol = (struct ocelot_policer) {
2242                                 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
2243                                 .rate = div_u64(rate, 1000) * 8,
2244                         };
2245                         ret = ocelot_vcap_policer_add(ocelot, index, &pol);
2246                         if (ret)
2247                                 goto err;
2248
2249                         sfi.fm_valid = 1;
2250                         sfi.fmid = index;
2251                         sfi.maxsdu = a->police.mtu;
2252                         break;
2253                 default:
2254                         return -EOPNOTSUPP;
2255                 }
2256         }
2257
2258         stream.ports = BIT(port);
2259         stream.port = port;
2260
2261         sfi.portmask = stream.ports;
2262         sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
2263         sfi.prio = (sfi.prio_valid ? stream.prio : 0);
2264         sfi.enable = 1;
2265
2266         /* Check if stream is set. */
2267         stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
2268         if (stream_entry) {
2269                 if (stream_entry->ports & BIT(port)) {
2270                         NL_SET_ERR_MSG_MOD(extack,
2271                                            "The stream is added on this port");
2272                         ret = -EEXIST;
2273                         goto err;
2274                 }
2275
2276                 if (stream_entry->ports != BIT(stream_entry->port)) {
2277                         NL_SET_ERR_MSG_MOD(extack,
2278                                            "The stream is added on two ports");
2279                         ret = -EEXIST;
2280                         goto err;
2281                 }
2282
2283                 stream_entry->ports |= BIT(port);
2284                 stream.ports = stream_entry->ports;
2285
2286                 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2287                                                        stream_entry->sfid);
2288                 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2289
2290                 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2291
2292                 old_sfi.portmask = stream_entry->ports;
2293                 sfi.portmask = stream.ports;
2294
2295                 if (stream_entry->port > port) {
2296                         ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2297                                                           &old_sfi);
2298                         stream_entry->dummy = true;
2299                 } else {
2300                         ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2301                                                           &sfi);
2302                         stream.dummy = true;
2303                 }
2304                 if (ret)
2305                         goto err;
2306
2307                 stream_entry->sfid = old_sfi.index;
2308         } else {
2309                 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2310                 if (ret)
2311                         goto err;
2312         }
2313
2314         stream.sfid = sfi.index;
2315         stream.sfid_valid = 1;
2316         ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2317                                        &stream, extack);
2318         if (ret) {
2319                 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2320                 goto err;
2321         }
2322
2323         return 0;
2324
2325 err:
2326         if (sfi.sg_valid)
2327                 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2328
2329         if (sfi.fm_valid)
2330                 ocelot_vcap_policer_del(ocelot, sfi.fmid);
2331
2332         return ret;
2333 }
2334
2335 static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2336                                    struct flow_cls_offload *f)
2337 {
2338         struct felix_stream *stream, tmp, *stream_entry;
2339         static struct felix_stream_filter *sfi;
2340         struct ocelot_psfp_list *psfp;
2341
2342         psfp = &ocelot->psfp;
2343
2344         stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2345         if (!stream)
2346                 return -ENOMEM;
2347
2348         sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2349         if (!sfi)
2350                 return -ENOMEM;
2351
2352         if (sfi->sg_valid)
2353                 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2354
2355         if (sfi->fm_valid)
2356                 ocelot_vcap_policer_del(ocelot, sfi->fmid);
2357
2358         vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2359
2360         memcpy(&tmp, stream, sizeof(tmp));
2361
2362         stream->sfid_valid = 0;
2363         vsc9959_stream_table_del(ocelot, stream);
2364
2365         stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2366         if (stream_entry) {
2367                 stream_entry->ports = BIT(stream_entry->port);
2368                 if (stream_entry->dummy) {
2369                         stream_entry->dummy = false;
2370                         vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2371                 }
2372                 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2373                                           stream_entry->ports);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2380                                   struct flow_cls_offload *f,
2381                                   struct flow_stats *stats)
2382 {
2383         struct felix_stream_filter_counters counters;
2384         struct ocelot_psfp_list *psfp;
2385         struct felix_stream *stream;
2386
2387         psfp = &ocelot->psfp;
2388         stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2389         if (!stream)
2390                 return -ENOMEM;
2391
2392         vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters);
2393
2394         stats->pkts = counters.match;
2395         stats->drops = counters.not_pass_gate + counters.not_pass_sdu +
2396                        counters.red;
2397
2398         return 0;
2399 }
2400
2401 static void vsc9959_psfp_init(struct ocelot *ocelot)
2402 {
2403         struct ocelot_psfp_list *psfp = &ocelot->psfp;
2404
2405         INIT_LIST_HEAD(&psfp->stream_list);
2406         INIT_LIST_HEAD(&psfp->sfi_list);
2407         INIT_LIST_HEAD(&psfp->sgi_list);
2408 }
2409
2410 /* When using cut-through forwarding and the egress port runs at a higher data
2411  * rate than the ingress port, the packet currently under transmission would
2412  * suffer an underrun since it would be transmitted faster than it is received.
2413  * The Felix switch implementation of cut-through forwarding does not check in
2414  * hardware whether this condition is satisfied or not, so we must restrict the
2415  * list of ports that have cut-through forwarding enabled on egress to only be
2416  * the ports operating at the lowest link speed within their respective
2417  * forwarding domain.
2418  */
2419 static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2420 {
2421         struct felix *felix = ocelot_to_felix(ocelot);
2422         struct dsa_switch *ds = felix->ds;
2423         int port, other_port;
2424
2425         lockdep_assert_held(&ocelot->fwd_domain_lock);
2426
2427         for (port = 0; port < ocelot->num_phys_ports; port++) {
2428                 struct ocelot_port *ocelot_port = ocelot->ports[port];
2429                 int min_speed = ocelot_port->speed;
2430                 unsigned long mask = 0;
2431                 u32 tmp, val = 0;
2432
2433                 /* Disable cut-through on ports that are down */
2434                 if (ocelot_port->speed <= 0)
2435                         goto set;
2436
2437                 if (dsa_is_cpu_port(ds, port)) {
2438                         /* Ocelot switches forward from the NPI port towards
2439                          * any port, regardless of it being in the NPI port's
2440                          * forwarding domain or not.
2441                          */
2442                         mask = dsa_user_ports(ds);
2443                 } else {
2444                         mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2445                         mask &= ~BIT(port);
2446                         if (ocelot->npi >= 0)
2447                                 mask |= BIT(ocelot->npi);
2448                         else
2449                                 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
2450                                                                                 port);
2451                 }
2452
2453                 /* Calculate the minimum link speed, among the ports that are
2454                  * up, of this source port's forwarding domain.
2455                  */
2456                 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2457                         struct ocelot_port *other_ocelot_port;
2458
2459                         other_ocelot_port = ocelot->ports[other_port];
2460                         if (other_ocelot_port->speed <= 0)
2461                                 continue;
2462
2463                         if (min_speed > other_ocelot_port->speed)
2464                                 min_speed = other_ocelot_port->speed;
2465                 }
2466
2467                 /* Enable cut-through forwarding for all traffic classes. */
2468                 if (ocelot_port->speed == min_speed)
2469                         val = GENMASK(7, 0);
2470
2471 set:
2472                 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2473                 if (tmp == val)
2474                         continue;
2475
2476                 dev_dbg(ocelot->dev,
2477                         "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n",
2478                         port, mask, ocelot_port->speed, min_speed,
2479                         val ? "enabling" : "disabling");
2480
2481                 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2482         }
2483 }
2484
2485 static const struct ocelot_ops vsc9959_ops = {
2486         .reset                  = vsc9959_reset,
2487         .wm_enc                 = vsc9959_wm_enc,
2488         .wm_dec                 = vsc9959_wm_dec,
2489         .wm_stat                = vsc9959_wm_stat,
2490         .port_to_netdev         = felix_port_to_netdev,
2491         .netdev_to_port         = felix_netdev_to_port,
2492         .psfp_init              = vsc9959_psfp_init,
2493         .psfp_filter_add        = vsc9959_psfp_filter_add,
2494         .psfp_filter_del        = vsc9959_psfp_filter_del,
2495         .psfp_stats_get         = vsc9959_psfp_stats_get,
2496         .cut_through_fwd        = vsc9959_cut_through_fwd,
2497         .tas_clock_adjust       = vsc9959_tas_clock_adjust,
2498 };
2499
2500 static const struct felix_info felix_info_vsc9959 = {
2501         .target_io_res          = vsc9959_target_io_res,
2502         .port_io_res            = vsc9959_port_io_res,
2503         .imdio_res              = &vsc9959_imdio_res,
2504         .regfields              = vsc9959_regfields,
2505         .map                    = vsc9959_regmap,
2506         .ops                    = &vsc9959_ops,
2507         .stats_layout           = vsc9959_stats_layout,
2508         .vcap                   = vsc9959_vcap_props,
2509         .vcap_pol_base          = VSC9959_VCAP_POLICER_BASE,
2510         .vcap_pol_max           = VSC9959_VCAP_POLICER_MAX,
2511         .vcap_pol_base2         = 0,
2512         .vcap_pol_max2          = 0,
2513         .num_mact_rows          = 2048,
2514         .num_ports              = VSC9959_NUM_PORTS,
2515         .num_tx_queues          = OCELOT_NUM_TC,
2516         .quirk_no_xtr_irq       = true,
2517         .ptp_caps               = &vsc9959_ptp_caps,
2518         .mdio_bus_alloc         = vsc9959_mdio_bus_alloc,
2519         .mdio_bus_free          = vsc9959_mdio_bus_free,
2520         .phylink_validate       = vsc9959_phylink_validate,
2521         .port_modes             = vsc9959_port_modes,
2522         .port_setup_tc          = vsc9959_port_setup_tc,
2523         .port_sched_speed_set   = vsc9959_sched_speed_set,
2524         .tas_guard_bands_update = vsc9959_tas_guard_bands_update,
2525         .init_regmap            = ocelot_regmap_init,
2526 };
2527
2528 static irqreturn_t felix_irq_handler(int irq, void *data)
2529 {
2530         struct ocelot *ocelot = (struct ocelot *)data;
2531
2532         /* The INTB interrupt is used for both PTP TX timestamp interrupt
2533          * and preemption status change interrupt on each port.
2534          *
2535          * - Get txtstamp if have
2536          * - TODO: handle preemption. Without handling it, driver may get
2537          *   interrupt storm.
2538          */
2539
2540         ocelot_get_txtstamp(ocelot);
2541
2542         return IRQ_HANDLED;
2543 }
2544
2545 static int felix_pci_probe(struct pci_dev *pdev,
2546                            const struct pci_device_id *id)
2547 {
2548         struct dsa_switch *ds;
2549         struct ocelot *ocelot;
2550         struct felix *felix;
2551         int err;
2552
2553         if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2554                 dev_info(&pdev->dev, "device is disabled, skipping\n");
2555                 return -ENODEV;
2556         }
2557
2558         err = pci_enable_device(pdev);
2559         if (err) {
2560                 dev_err(&pdev->dev, "device enable failed\n");
2561                 goto err_pci_enable;
2562         }
2563
2564         felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2565         if (!felix) {
2566                 err = -ENOMEM;
2567                 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2568                 goto err_alloc_felix;
2569         }
2570
2571         pci_set_drvdata(pdev, felix);
2572         ocelot = &felix->ocelot;
2573         ocelot->dev = &pdev->dev;
2574         ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2575         felix->info = &felix_info_vsc9959;
2576         felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2577         felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
2578
2579         pci_set_master(pdev);
2580
2581         err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2582                                         &felix_irq_handler, IRQF_ONESHOT,
2583                                         "felix-intb", ocelot);
2584         if (err) {
2585                 dev_err(&pdev->dev, "Failed to request irq\n");
2586                 goto err_alloc_irq;
2587         }
2588
2589         ocelot->ptp = 1;
2590
2591         ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
2592         if (!ds) {
2593                 err = -ENOMEM;
2594                 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
2595                 goto err_alloc_ds;
2596         }
2597
2598         ds->dev = &pdev->dev;
2599         ds->num_ports = felix->info->num_ports;
2600         ds->num_tx_queues = felix->info->num_tx_queues;
2601         ds->ops = &felix_switch_ops;
2602         ds->priv = ocelot;
2603         felix->ds = ds;
2604         felix->tag_proto = DSA_TAG_PROTO_OCELOT;
2605
2606         err = dsa_register_switch(ds);
2607         if (err) {
2608                 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n");
2609                 goto err_register_ds;
2610         }
2611
2612         return 0;
2613
2614 err_register_ds:
2615         kfree(ds);
2616 err_alloc_ds:
2617 err_alloc_irq:
2618         kfree(felix);
2619 err_alloc_felix:
2620         pci_disable_device(pdev);
2621 err_pci_enable:
2622         return err;
2623 }
2624
2625 static void felix_pci_remove(struct pci_dev *pdev)
2626 {
2627         struct felix *felix = pci_get_drvdata(pdev);
2628
2629         if (!felix)
2630                 return;
2631
2632         dsa_unregister_switch(felix->ds);
2633
2634         kfree(felix->ds);
2635         kfree(felix);
2636
2637         pci_disable_device(pdev);
2638
2639         pci_set_drvdata(pdev, NULL);
2640 }
2641
2642 static void felix_pci_shutdown(struct pci_dev *pdev)
2643 {
2644         struct felix *felix = pci_get_drvdata(pdev);
2645
2646         if (!felix)
2647                 return;
2648
2649         dsa_switch_shutdown(felix->ds);
2650
2651         pci_set_drvdata(pdev, NULL);
2652 }
2653
2654 static struct pci_device_id felix_ids[] = {
2655         {
2656                 /* NXP LS1028A */
2657                 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2658         },
2659         { 0, }
2660 };
2661 MODULE_DEVICE_TABLE(pci, felix_ids);
2662
2663 static struct pci_driver felix_vsc9959_pci_driver = {
2664         .name           = "mscc_felix",
2665         .id_table       = felix_ids,
2666         .probe          = felix_pci_probe,
2667         .remove         = felix_pci_remove,
2668         .shutdown       = felix_pci_shutdown,
2669 };
2670 module_pci_driver(felix_vsc9959_pci_driver);
2671
2672 MODULE_DESCRIPTION("Felix Switch driver");
2673 MODULE_LICENSE("GPL v2");