1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Port Registers support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 #include <linux/bitfield.h>
12 #include <linux/if_bridge.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
23 int addr = chip->info->port_base_addr + port;
25 return mv88e6xxx_read(chip, addr, reg, val);
28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
31 int addr = chip->info->port_base_addr + port;
33 return mv88e6xxx_write(chip, addr, reg, val);
36 /* Offset 0x00: MAC (or PCS or Physical) Status Register
38 * For most devices, this is read only. However the 6185 has the MyPause
41 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
47 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
52 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
54 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
56 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
59 /* Offset 0x01: MAC (or PCS or Physical) Control Register
61 * Link, Duplex and Flow Control have one force bit, one value bit.
63 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
64 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
65 * Newer chips need a ForcedSpd bit 13 set to consider the value.
68 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
74 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
78 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
79 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
82 case PHY_INTERFACE_MODE_RGMII_RXID:
83 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
85 case PHY_INTERFACE_MODE_RGMII_TXID:
86 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
88 case PHY_INTERFACE_MODE_RGMII_ID:
89 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
90 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
92 case PHY_INTERFACE_MODE_RGMII:
98 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
102 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
103 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
104 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
109 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
110 phy_interface_t mode)
115 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
118 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
119 phy_interface_t mode)
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
127 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
132 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
136 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
137 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
140 case LINK_FORCED_DOWN:
141 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
144 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
145 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
148 /* normal link detection */
154 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
158 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
159 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
160 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
165 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
167 const struct mv88e6xxx_ops *ops = chip->info->ops;
172 link = LINK_FORCED_UP;
174 link = LINK_FORCED_DOWN;
176 if (ops->port_set_link)
177 err = ops->port_set_link(chip, port, link);
182 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
184 const struct mv88e6xxx_ops *ops = chip->info->ops;
188 if (mode == MLO_AN_INBAND)
189 link = LINK_UNFORCED;
191 link = LINK_FORCED_UP;
193 link = LINK_FORCED_DOWN;
195 if (ops->port_set_link)
196 err = ops->port_set_link(chip, port, link);
201 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
202 int port, int speed, bool alt_bit,
203 bool force_bit, int duplex)
210 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
213 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
217 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
218 MV88E6390_PORT_MAC_CTL_ALTSPEED;
220 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
223 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
227 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
228 MV88E6390_PORT_MAC_CTL_ALTSPEED;
230 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
233 /* all bits set, fall through... */
235 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
243 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
246 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
247 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
249 case DUPLEX_UNFORCED:
250 /* normal duplex detection */
256 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
260 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
261 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
262 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
265 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
267 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
268 if (speed != SPEED_UNFORCED)
269 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
273 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
278 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
280 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
281 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
282 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
283 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
288 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
289 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
290 int speed, int duplex)
292 if (speed == SPEED_MAX)
298 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
299 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
303 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
304 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
305 int speed, int duplex)
307 if (speed == SPEED_MAX)
310 if (speed == 200 || speed > 1000)
313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
317 /* Support 10, 100 Mbps (e.g. 88E6250 family) */
318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
319 int speed, int duplex)
321 if (speed == SPEED_MAX)
327 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
331 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
332 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
333 int speed, int duplex)
335 if (speed == SPEED_MAX)
336 speed = port < 5 ? 1000 : 2500;
341 if (speed == 200 && port != 0)
344 if (speed == 2500 && port < 5)
347 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
351 phy_interface_t mv88e6341_port_max_speed_mode(int port)
354 return PHY_INTERFACE_MODE_2500BASEX;
356 return PHY_INTERFACE_MODE_NA;
359 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
360 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
361 int speed, int duplex)
363 if (speed == SPEED_MAX)
369 if (speed == 200 && port < 5)
372 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
376 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
377 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
378 int speed, int duplex)
380 if (speed == SPEED_MAX)
381 speed = port < 9 ? 1000 : 2500;
386 if (speed == 200 && port != 0)
389 if (speed == 2500 && port < 9)
392 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
396 phy_interface_t mv88e6390_port_max_speed_mode(int port)
398 if (port == 9 || port == 10)
399 return PHY_INTERFACE_MODE_2500BASEX;
401 return PHY_INTERFACE_MODE_NA;
404 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
405 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
406 int speed, int duplex)
408 if (speed == SPEED_MAX)
409 speed = port < 9 ? 1000 : 10000;
411 if (speed == 200 && port != 0)
414 if (speed >= 2500 && port < 9)
417 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
421 phy_interface_t mv88e6390x_port_max_speed_mode(int port)
423 if (port == 9 || port == 10)
424 return PHY_INTERFACE_MODE_XAUI;
426 return PHY_INTERFACE_MODE_NA;
429 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
430 phy_interface_t mode, bool force)
437 /* Default to a slow mode, so freeing up SERDES interfaces for
438 * other ports which might use them for SFPs.
440 if (mode == PHY_INTERFACE_MODE_NA)
441 mode = PHY_INTERFACE_MODE_1000BASEX;
444 case PHY_INTERFACE_MODE_1000BASEX:
445 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
447 case PHY_INTERFACE_MODE_SGMII:
448 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
450 case PHY_INTERFACE_MODE_2500BASEX:
451 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
453 case PHY_INTERFACE_MODE_XGMII:
454 case PHY_INTERFACE_MODE_XAUI:
455 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
457 case PHY_INTERFACE_MODE_RXAUI:
458 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
464 /* cmode doesn't change, nothing to do for us unless forced */
465 if (cmode == chip->ports[port].cmode && !force)
468 lane = mv88e6xxx_serdes_get_lane(chip, port);
470 if (chip->ports[port].serdes_irq) {
471 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
476 err = mv88e6xxx_serdes_power_down(chip, port, lane);
481 chip->ports[port].cmode = 0;
484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
488 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
491 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
495 chip->ports[port].cmode = cmode;
497 lane = mv88e6xxx_serdes_get_lane(chip, port);
501 err = mv88e6xxx_serdes_power_up(chip, port, lane);
505 if (chip->ports[port].serdes_irq) {
506 err = mv88e6xxx_serdes_irq_enable(chip, port, lane);
515 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
516 phy_interface_t mode)
518 if (port != 9 && port != 10)
521 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
524 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
525 phy_interface_t mode)
527 if (port != 9 && port != 10)
531 case PHY_INTERFACE_MODE_NA:
533 case PHY_INTERFACE_MODE_XGMII:
534 case PHY_INTERFACE_MODE_XAUI:
535 case PHY_INTERFACE_MODE_RXAUI:
541 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
544 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
553 addr = chip->info->port_base_addr + port;
555 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
559 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
560 MV88E6341_PORT_RESERVED_1A_SGMII_AN;
562 if ((reg & bits) == bits)
566 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
569 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
570 phy_interface_t mode)
578 case PHY_INTERFACE_MODE_NA:
580 case PHY_INTERFACE_MODE_XGMII:
581 case PHY_INTERFACE_MODE_XAUI:
582 case PHY_INTERFACE_MODE_RXAUI:
588 err = mv88e6341_port_set_cmode_writable(chip, port);
592 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
595 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
600 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
604 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
609 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
614 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
618 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
623 /* Offset 0x02: Jamming Control
625 * Do not limit the period of time that this port can be paused for by
626 * the remote end or the period of time that this port can pause the
629 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
632 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
636 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
641 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
642 MV88E6390_PORT_FLOW_CTL_UPDATE |
643 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
647 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
648 MV88E6390_PORT_FLOW_CTL_UPDATE |
649 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
652 /* Offset 0x04: Port Control Register */
654 static const char * const mv88e6xxx_port_state_names[] = {
655 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
656 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
657 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
658 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
661 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
666 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
670 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
673 case BR_STATE_DISABLED:
674 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
676 case BR_STATE_BLOCKING:
677 case BR_STATE_LISTENING:
678 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
680 case BR_STATE_LEARNING:
681 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
683 case BR_STATE_FORWARDING:
684 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
692 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
696 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
697 mv88e6xxx_port_state_names[state]);
702 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
703 enum mv88e6xxx_egress_mode mode)
708 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
712 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
715 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
716 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
718 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
719 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
721 case MV88E6XXX_EGRESS_MODE_TAGGED:
722 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
724 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
725 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
731 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
734 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
735 enum mv88e6xxx_frame_mode mode)
740 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
744 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
747 case MV88E6XXX_FRAME_MODE_NORMAL:
748 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
750 case MV88E6XXX_FRAME_MODE_DSA:
751 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
757 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
760 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
761 enum mv88e6xxx_frame_mode mode)
766 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
770 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
773 case MV88E6XXX_FRAME_MODE_NORMAL:
774 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
776 case MV88E6XXX_FRAME_MODE_DSA:
777 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
779 case MV88E6XXX_FRAME_MODE_PROVIDER:
780 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
782 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
783 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
789 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
792 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
793 int port, bool unicast)
798 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
803 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
805 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
807 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
810 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
816 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
821 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
823 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
825 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
828 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
834 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
839 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
841 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
843 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
846 /* Offset 0x05: Port Control 1 */
848 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
854 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
859 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
861 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
863 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
866 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
872 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
876 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
879 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
880 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
882 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
884 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
887 /* Offset 0x06: Port Based VLAN Map */
889 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
891 const u16 mask = mv88e6xxx_port_mask(chip);
895 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
902 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
906 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
911 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
913 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
917 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
922 *fid = (reg & 0xf000) >> 12;
924 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
926 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
931 *fid |= (reg & upper_mask) << 4;
937 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
939 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
943 if (fid >= mv88e6xxx_num_databases(chip))
946 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
947 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
952 reg |= (fid & 0x000f) << 12;
954 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
958 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
960 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
966 reg |= (fid >> 4) & upper_mask;
968 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
974 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
979 /* Offset 0x07: Default Port VLAN ID & Priority */
981 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
986 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
991 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
996 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1001 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1006 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1007 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1009 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1014 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1019 /* Offset 0x08: Port Control 2 Register */
1021 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1022 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1023 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1024 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1025 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1028 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1029 int port, bool multicast)
1034 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1039 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1041 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1043 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1046 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1052 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1056 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1057 reg |= upstream_port;
1059 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1062 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1063 enum mv88e6xxx_egress_direction direction,
1071 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1075 switch (direction) {
1076 case MV88E6XXX_EGRESS_DIR_INGRESS:
1077 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1078 mirror_port = &chip->ports[port].mirror_ingress;
1080 case MV88E6XXX_EGRESS_DIR_EGRESS:
1081 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1082 mirror_port = &chip->ports[port].mirror_egress;
1092 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1094 *mirror_port = mirror;
1099 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1105 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1109 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1110 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1112 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1116 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1117 mv88e6xxx_port_8021q_mode_names[mode]);
1122 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
1127 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1131 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1133 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1136 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1142 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1146 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1149 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1150 else if (size <= 2048)
1151 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1152 else if (size <= 10240)
1153 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1157 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1160 /* Offset 0x09: Port Rate Control */
1162 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1164 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1168 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1170 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1174 /* Offset 0x0C: Port ATU Control */
1176 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1178 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1181 /* Offset 0x0D: (Priority) Override Register */
1183 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1185 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1188 /* Offset 0x0f: Port Ether type */
1190 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1193 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1196 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1197 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1200 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1204 /* Use a direct priority mapping for all IEEE tagged frames */
1205 err = mv88e6xxx_port_write(chip, port,
1206 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1211 return mv88e6xxx_port_write(chip, port,
1212 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1216 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1217 int port, u16 table, u8 ptr, u16 data)
1221 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1222 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1223 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1225 return mv88e6xxx_port_write(chip, port,
1226 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1229 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1234 for (i = 0; i <= 7; i++) {
1235 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1236 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1241 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1242 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1246 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1247 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1251 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1252 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1260 /* Offset 0x0E: Policy Control Register */
1262 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1263 enum mv88e6xxx_policy_mapping mapping,
1264 enum mv88e6xxx_policy_action action)
1271 case MV88E6XXX_POLICY_MAPPING_DA:
1272 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1273 mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1275 case MV88E6XXX_POLICY_MAPPING_SA:
1276 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1277 mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1279 case MV88E6XXX_POLICY_MAPPING_VTU:
1280 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1281 mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1283 case MV88E6XXX_POLICY_MAPPING_ETYPE:
1284 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1285 mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1287 case MV88E6XXX_POLICY_MAPPING_PPPOE:
1288 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1289 mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1291 case MV88E6XXX_POLICY_MAPPING_VBAS:
1292 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1293 mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1295 case MV88E6XXX_POLICY_MAPPING_OPT82:
1296 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1297 mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1299 case MV88E6XXX_POLICY_MAPPING_UDP:
1300 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1301 mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1308 case MV88E6XXX_POLICY_ACTION_NORMAL:
1309 val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1311 case MV88E6XXX_POLICY_ACTION_MIRROR:
1312 val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1314 case MV88E6XXX_POLICY_ACTION_TRAP:
1315 val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1317 case MV88E6XXX_POLICY_ACTION_DISCARD:
1318 val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1324 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1329 reg |= (val << shift) & mask;
1331 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);