1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Global (1) Registers support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 #include <linux/bitfield.h>
16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
18 int addr = chip->info->global1_addr;
20 return mv88e6xxx_read(chip, addr, reg, val);
23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
25 int addr = chip->info->global1_addr;
27 return mv88e6xxx_write(chip, addr, reg, val);
30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
44 /* Offset 0x00: Switch Global Status Register */
46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
78 void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
80 const unsigned long timeout = jiffies + 1 * HZ;
84 /* Wait up to 1 second for the switch to finish reading the
87 while (time_before(jiffies, timeout)) {
88 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
90 dev_err(chip->dev, "Error reading status");
94 /* If the switch is still resetting, it may not
95 * respond on the bus, and so MDIO read returns
96 * 0xffff. Differentiate between that, and waiting for
97 * the EEPROM to be done by bit 0 being set.
100 val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE))
103 usleep_range(1000, 2000);
106 dev_err(chip->dev, "Timeout waiting for EEPROM done");
109 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
110 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
111 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
113 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
118 reg = (addr[0] << 8) | addr[1];
119 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
123 reg = (addr[2] << 8) | addr[3];
124 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
128 reg = (addr[4] << 8) | addr[5];
129 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
136 /* Offset 0x04: Switch Global Control Register */
138 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
143 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
144 * the PPU, including re-doing PHY detection and initialization
146 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
150 val |= MV88E6XXX_G1_CTL1_SW_RESET;
151 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
153 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
157 err = mv88e6xxx_g1_wait_init_ready(chip);
161 return mv88e6185_g1_wait_ppu_polling(chip);
164 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
169 /* Set the SWReset bit 15 */
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
174 val |= MV88E6XXX_G1_CTL1_SW_RESET;
176 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
180 return mv88e6xxx_g1_wait_init_ready(chip);
183 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
187 err = mv88e6250_g1_reset(chip);
191 return mv88e6352_g1_wait_ppu_polling(chip);
194 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
199 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
203 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
205 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
209 return mv88e6185_g1_wait_ppu_polling(chip);
212 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
217 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
221 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
223 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
227 return mv88e6185_g1_wait_ppu_disabled(chip);
230 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
235 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
239 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
242 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
244 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
247 /* Offset 0x10: IP-PRI Mapping Register 0
248 * Offset 0x11: IP-PRI Mapping Register 1
249 * Offset 0x12: IP-PRI Mapping Register 2
250 * Offset 0x13: IP-PRI Mapping Register 3
251 * Offset 0x14: IP-PRI Mapping Register 4
252 * Offset 0x15: IP-PRI Mapping Register 5
253 * Offset 0x16: IP-PRI Mapping Register 6
254 * Offset 0x17: IP-PRI Mapping Register 7
257 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
261 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
262 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
266 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
270 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
274 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
278 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
282 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
286 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
290 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
297 /* Offset 0x18: IEEE-PRI Register */
299 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
301 /* Reset the IEEE Tag priorities to defaults */
302 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
305 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
307 /* Reset the IEEE Tag priorities to defaults */
308 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
311 /* Offset 0x1a: Monitor Control */
312 /* Offset 0x1a: Monitor & MGMT Control on some devices */
314 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
315 enum mv88e6xxx_egress_direction direction,
322 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
327 case MV88E6XXX_EGRESS_DIR_INGRESS:
328 dest_port_chip = &chip->ingress_dest_port;
329 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
331 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
333 case MV88E6XXX_EGRESS_DIR_EGRESS:
334 dest_port_chip = &chip->egress_dest_port;
335 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
337 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
343 err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
345 *dest_port_chip = port;
350 /* Older generations also call this the ARP destination. It has been
351 * generalized in more modern devices such that more than ARP can
354 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
359 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
363 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
364 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
366 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
369 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
370 u16 pointer, u8 data)
374 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
376 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
379 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
380 enum mv88e6xxx_egress_direction direction,
388 case MV88E6XXX_EGRESS_DIR_INGRESS:
389 dest_port_chip = &chip->ingress_dest_port;
390 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
392 case MV88E6XXX_EGRESS_DIR_EGRESS:
393 dest_port_chip = &chip->egress_dest_port;
394 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
400 err = mv88e6390_g1_monitor_write(chip, ptr, port);
402 *dest_port_chip = port;
407 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
409 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
411 /* Use the default high priority for management frames sent to
414 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
416 return mv88e6390_g1_monitor_write(chip, ptr, port);
419 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
424 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
425 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
426 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
430 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
431 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
432 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
436 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
437 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
438 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
442 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
443 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
444 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
451 /* Offset 0x1c: Global Control 2 */
453 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
459 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
466 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
469 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
471 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
473 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
476 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
478 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
479 MV88E6085_G1_CTL2_RM_ENABLE, 0);
482 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
484 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
485 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
488 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
490 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
491 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
494 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
496 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
497 MV88E6390_G1_CTL2_HIST_MODE_RX |
498 MV88E6390_G1_CTL2_HIST_MODE_TX);
501 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
503 return mv88e6xxx_g1_ctl2_mask(chip,
504 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
508 /* Offset 0x1d: Statistics Operation 2 */
510 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
512 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
514 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
517 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
522 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
526 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
528 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
533 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
537 /* Snapshot the hardware statistics counters for this port. */
538 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
539 MV88E6XXX_G1_STATS_OP_BUSY |
540 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
541 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
545 /* Wait for the snapshotting to complete. */
546 return mv88e6xxx_g1_stats_wait(chip);
549 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
551 port = (port + 1) << 5;
553 return mv88e6xxx_g1_stats_snapshot(chip, port);
556 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
560 port = (port + 1) << 5;
562 /* Snapshot the hardware statistics counters for this port. */
563 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
564 MV88E6XXX_G1_STATS_OP_BUSY |
565 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
569 /* Wait for the snapshotting to complete. */
570 return mv88e6xxx_g1_stats_wait(chip);
573 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
581 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
582 MV88E6XXX_G1_STATS_OP_BUSY |
583 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
587 err = mv88e6xxx_g1_stats_wait(chip);
591 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
597 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
604 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
609 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
613 /* Keep the histogram mode bits */
614 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
615 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
617 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
621 /* Wait for the flush to complete. */
622 return mv88e6xxx_g1_stats_wait(chip);