1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
5 * Copyright (c) 2008 Marvell Semiconductor
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
21 #define MV88E6XXX_N_FID 4096
23 /* PVT limits for 4-bit port and 5-bit switch */
24 #define MV88E6XXX_MAX_PVT_SWITCHES 32
25 #define MV88E6XXX_MAX_PVT_PORTS 16
27 #define MV88E6XXX_MAX_GPIO 16
29 enum mv88e6xxx_egress_mode {
30 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 MV88E6XXX_EGRESS_MODE_TAGGED,
33 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
36 enum mv88e6xxx_egress_direction {
37 MV88E6XXX_EGRESS_DIR_INGRESS,
38 MV88E6XXX_EGRESS_DIR_EGRESS,
41 enum mv88e6xxx_frame_mode {
42 MV88E6XXX_FRAME_MODE_NORMAL,
43 MV88E6XXX_FRAME_MODE_DSA,
44 MV88E6XXX_FRAME_MODE_PROVIDER,
45 MV88E6XXX_FRAME_MODE_ETHERTYPE,
48 /* List of supported models */
49 enum mv88e6xxx_model {
83 enum mv88e6xxx_family {
84 MV88E6XXX_FAMILY_NONE,
85 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
86 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
87 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
88 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
89 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
90 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
91 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
92 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
93 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
94 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
95 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
96 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
101 struct mv88e6xxx_info {
102 enum mv88e6xxx_family family;
105 unsigned int num_databases;
106 unsigned int num_macs;
107 unsigned int num_ports;
108 unsigned int num_internal_phys;
109 unsigned int num_gpio;
110 unsigned int max_vid;
111 unsigned int port_base_addr;
112 unsigned int phy_base_addr;
113 unsigned int global1_addr;
114 unsigned int global2_addr;
115 unsigned int age_time_coeff;
116 unsigned int g1_irqs;
117 unsigned int g2_irqs;
120 /* Mark certain ports as invalid. This is required for example for the
121 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
122 * ports 2-4 are not routet to pins.
124 unsigned int invalid_port_mask;
125 /* Multi-chip Addressing Mode.
126 * Some chips respond to only 2 registers of its own SMI device address
127 * when it is non-zero, and use indirect access to internal registers.
130 /* Dual-chip Addressing Mode
131 * Some chips respond to only half of the 32 SMI addresses,
132 * allowing two to coexist on the same SMI interface.
136 enum dsa_tag_protocol tag_protocol;
138 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
139 * operation. 0 means that the ATU Move operation is not supported.
141 u8 atu_move_port_mask;
142 const struct mv88e6xxx_ops *ops;
148 struct mv88e6xxx_atu_entry {
155 struct mv88e6xxx_vtu_entry {
160 u8 member[DSA_MAX_PORTS];
161 u8 state[DSA_MAX_PORTS];
164 struct mv88e6xxx_bus_ops;
165 struct mv88e6xxx_irq_ops;
166 struct mv88e6xxx_gpio_ops;
167 struct mv88e6xxx_avb_ops;
168 struct mv88e6xxx_ptp_ops;
170 struct mv88e6xxx_irq {
172 struct irq_chip chip;
173 struct irq_domain *domain;
177 /* state flags for mv88e6xxx_port_hwtstamp::state */
179 MV88E6XXX_HWTSTAMP_ENABLED,
180 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
183 struct mv88e6xxx_port_hwtstamp {
187 /* Timestamping state */
190 /* Resources for receive timestamping */
191 struct sk_buff_head rx_queue;
192 struct sk_buff_head rx_queue2;
194 /* Resources for transmit timestamping */
195 unsigned long tx_tstamp_start;
196 struct sk_buff *tx_skb;
199 /* Current timestamp configuration */
200 struct hwtstamp_config tstamp_config;
203 enum mv88e6xxx_policy_mapping {
204 MV88E6XXX_POLICY_MAPPING_DA,
205 MV88E6XXX_POLICY_MAPPING_SA,
206 MV88E6XXX_POLICY_MAPPING_VTU,
207 MV88E6XXX_POLICY_MAPPING_ETYPE,
208 MV88E6XXX_POLICY_MAPPING_PPPOE,
209 MV88E6XXX_POLICY_MAPPING_VBAS,
210 MV88E6XXX_POLICY_MAPPING_OPT82,
211 MV88E6XXX_POLICY_MAPPING_UDP,
214 enum mv88e6xxx_policy_action {
215 MV88E6XXX_POLICY_ACTION_NORMAL,
216 MV88E6XXX_POLICY_ACTION_MIRROR,
217 MV88E6XXX_POLICY_ACTION_TRAP,
218 MV88E6XXX_POLICY_ACTION_DISCARD,
221 struct mv88e6xxx_policy {
222 enum mv88e6xxx_policy_mapping mapping;
223 enum mv88e6xxx_policy_action action;
224 struct ethtool_rx_flow_spec fs;
230 struct mv88e6xxx_port {
231 struct mv88e6xxx_chip *chip;
234 u64 atu_member_violation;
235 u64 atu_miss_violation;
236 u64 atu_full_violation;
237 u64 vtu_member_violation;
238 u64 vtu_miss_violation;
239 phy_interface_t interface;
243 unsigned int serdes_irq;
244 char serdes_irq_name[64];
245 struct devlink_region *region;
248 enum mv88e6xxx_region_id {
249 MV88E6XXX_REGION_GLOBAL1 = 0,
250 MV88E6XXX_REGION_GLOBAL2,
251 MV88E6XXX_REGION_ATU,
252 MV88E6XXX_REGION_VTU,
254 _MV88E6XXX_REGION_MAX,
257 struct mv88e6xxx_region_priv {
258 enum mv88e6xxx_region_id id;
261 struct mv88e6xxx_chip {
262 const struct mv88e6xxx_info *info;
264 /* The dsa_switch this private structure is related to */
265 struct dsa_switch *ds;
267 /* The device this structure is associated to */
270 /* This mutex protects the access to the switch registers */
271 struct mutex reg_lock;
273 /* The MII bus and the address on the bus that is used to
274 * communication with the switch
276 const struct mv88e6xxx_bus_ops *smi_ops;
280 /* Handles automatic disabling and re-enabling of the PHY
283 const struct mv88e6xxx_bus_ops *phy_ops;
284 struct mutex ppu_mutex;
286 struct work_struct ppu_work;
287 struct timer_list ppu_timer;
289 /* This mutex serialises access to the statistics unit.
290 * Hold this mutex over snapshot + dump sequences.
292 struct mutex stats_mutex;
294 /* A switch may have a GPIO line tied to its reset pin. Parse
295 * this from the device tree, and use it before performing
298 struct gpio_desc *reset;
300 /* set to size of eeprom if supported by the switch */
303 /* List of mdio busses */
304 struct list_head mdios;
306 /* Policy Control List IDs and rules */
309 /* There can be two interrupt controllers, which are chained
310 * off a GPIO as interrupt source
312 struct mv88e6xxx_irq g1_irq;
313 struct mv88e6xxx_irq g2_irq;
317 char device_irq_name[64];
319 char watchdog_irq_name[64];
322 char atu_prob_irq_name[64];
324 char vtu_prob_irq_name[64];
325 struct kthread_worker *kworker;
326 struct kthread_delayed_work irq_poll_work;
331 /* This cyclecounter abstracts the switch PTP time.
332 * reg_lock must be held for any operation that read()s.
334 struct cyclecounter tstamp_cc;
335 struct timecounter tstamp_tc;
336 struct delayed_work overflow_work;
338 struct ptp_clock *ptp_clock;
339 struct ptp_clock_info ptp_clock_info;
340 struct delayed_work tai_event_work;
341 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
346 /* Current ingress and egress monitor ports */
347 int egress_dest_port;
348 int ingress_dest_port;
350 /* Per-port timestamping resources. */
351 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
353 /* Array of port structures. */
354 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
356 /* devlink regions */
357 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
360 struct mv88e6xxx_bus_ops {
361 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
362 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
365 struct mv88e6xxx_mdio_bus {
367 struct mv88e6xxx_chip *chip;
368 struct list_head list;
372 struct mv88e6xxx_ops {
373 /* Switch Setup Errata, called early in the switch setup to
374 * allow any errata actions to be performed
376 int (*setup_errata)(struct mv88e6xxx_chip *chip);
378 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
379 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
381 /* Ingress Rate Limit unit (IRL) operations */
382 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
384 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
385 struct ethtool_eeprom *eeprom, u8 *data);
386 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
387 struct ethtool_eeprom *eeprom, u8 *data);
389 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
391 int (*phy_read)(struct mv88e6xxx_chip *chip,
393 int addr, int reg, u16 *val);
394 int (*phy_write)(struct mv88e6xxx_chip *chip,
396 int addr, int reg, u16 val);
398 /* Priority Override Table operations */
399 int (*pot_clear)(struct mv88e6xxx_chip *chip);
401 /* PHY Polling Unit (PPU) operations */
402 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
403 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
405 /* Switch Software Reset */
406 int (*reset)(struct mv88e6xxx_chip *chip);
408 /* RGMII Receive/Transmit Timing Control
409 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
411 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
412 phy_interface_t mode);
414 #define LINK_FORCED_DOWN 0
415 #define LINK_FORCED_UP 1
416 #define LINK_UNFORCED -2
418 /* Port's MAC link state
419 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
420 * or LINK_UNFORCED for normal link detection.
422 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
424 /* Synchronise the port link state with that of the SERDES
426 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
431 /* Enable/disable sending Pause */
432 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
435 #define SPEED_MAX INT_MAX
436 #define SPEED_UNFORCED -2
437 #define DUPLEX_UNFORCED -2
439 /* Port's MAC speed (in Mbps) and MAC duplex mode
441 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
442 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
444 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
445 * or DUPLEX_UNFORCED for normal duplex detection.
447 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
448 int speed, int duplex);
450 /* What interface mode should be used for maximum speed? */
451 phy_interface_t (*port_max_speed_mode)(int port);
453 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
455 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
456 enum mv88e6xxx_policy_mapping mapping,
457 enum mv88e6xxx_policy_action action);
459 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
460 enum mv88e6xxx_frame_mode mode);
461 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
463 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
465 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
467 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
470 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
471 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
473 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
474 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
475 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
477 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
478 * Some chips allow this to be configured on specific ports.
480 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
481 phy_interface_t mode);
482 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
484 /* Some devices have a per port register indicating what is
485 * the upstream port this port should forward to.
487 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
490 /* Snapshot the statistics for a port. The statistics can then
491 * be read back a leisure but still with a consistent view.
493 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
495 /* Set the histogram mode for statistics, when the control registers
496 * are separated out of the STATS_OP register.
498 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
500 /* Return the number of strings describing statistics */
501 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
502 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
503 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
505 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
506 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
507 enum mv88e6xxx_egress_direction direction,
510 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
511 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
513 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
515 const struct mv88e6xxx_irq_ops *watchdog_ops;
517 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
519 /* Power on/off a SERDES interface */
520 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
523 /* SERDES lane mapping */
524 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
526 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
527 int lane, struct phylink_link_state *state);
528 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
529 int lane, unsigned int mode,
530 phy_interface_t interface,
531 const unsigned long *advertise);
532 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
534 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
535 int lane, int speed, int duplex);
537 /* SERDES interrupt handling */
538 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
540 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
542 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
545 /* Statistics from the SERDES interface */
546 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
547 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
549 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
552 /* SERDES registers for ethtool */
553 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
554 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
557 /* Address Translation Unit operations */
558 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
559 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
561 /* VLAN Translation Unit operations */
562 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
563 struct mv88e6xxx_vtu_entry *entry);
564 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
565 struct mv88e6xxx_vtu_entry *entry);
567 /* GPIO operations */
568 const struct mv88e6xxx_gpio_ops *gpio_ops;
570 /* Interface to the AVB/PTP registers */
571 const struct mv88e6xxx_avb_ops *avb_ops;
573 /* Remote Management Unit operations */
574 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
576 /* Precision Time Protocol operations */
577 const struct mv88e6xxx_ptp_ops *ptp_ops;
580 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
582 struct phylink_link_state *state);
585 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
588 struct mv88e6xxx_irq_ops {
589 /* Action to be performed when the interrupt happens */
590 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
591 /* Setup the hardware to generate the interrupt */
592 int (*irq_setup)(struct mv88e6xxx_chip *chip);
593 /* Reset the hardware to stop generating the interrupt */
594 void (*irq_free)(struct mv88e6xxx_chip *chip);
597 struct mv88e6xxx_gpio_ops {
598 /* Get/set data on GPIO pin */
599 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
600 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
603 /* get/set GPIO direction */
604 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
605 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
608 /* get/set GPIO pin control */
609 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
611 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
615 struct mv88e6xxx_avb_ops {
616 /* Access port-scoped Precision Time Protocol registers */
617 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
619 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
622 /* Access global Precision Time Protocol registers */
623 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
625 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
627 /* Access global Time Application Interface registers */
628 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
630 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
633 struct mv88e6xxx_ptp_ops {
634 u64 (*clock_read)(const struct cyclecounter *cc);
635 int (*ptp_enable)(struct ptp_clock_info *ptp,
636 struct ptp_clock_request *rq, int on);
637 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
638 enum ptp_pin_function func, unsigned int chan);
639 void (*event_work)(struct work_struct *ugly);
640 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
641 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
642 int (*global_enable)(struct mv88e6xxx_chip *chip);
643 int (*global_disable)(struct mv88e6xxx_chip *chip);
655 #define STATS_TYPE_PORT BIT(0)
656 #define STATS_TYPE_BANK0 BIT(1)
657 #define STATS_TYPE_BANK1 BIT(2)
659 struct mv88e6xxx_hw_stat {
660 char string[ETH_GSTRING_LEN];
666 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
668 return chip->info->pvt;
671 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
673 return !!chip->info->global2_addr;
676 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
678 return chip->info->num_databases;
681 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
683 return chip->info->num_macs;
686 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
688 return chip->info->num_ports;
691 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
693 return chip->info->max_vid;
696 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
698 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
701 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
703 return chip->info->num_gpio;
706 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
708 return (chip->info->invalid_port_mask & BIT(port)) != 0;
711 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
712 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
713 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
715 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
717 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
719 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
721 mutex_lock(&chip->reg_lock);
724 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
726 mutex_unlock(&chip->reg_lock);
729 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
731 #endif /* _MV88E6XXX_CHIP_H */