1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
5 * Copyright (c) 2008 Marvell Semiconductor
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
21 #define MV88E6XXX_N_FID 4096
23 /* PVT limits for 4-bit port and 5-bit switch */
24 #define MV88E6XXX_MAX_PVT_SWITCHES 32
25 #define MV88E6XXX_MAX_PVT_PORTS 16
27 #define MV88E6XXX_MAX_GPIO 16
29 enum mv88e6xxx_egress_mode {
30 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 MV88E6XXX_EGRESS_MODE_TAGGED,
33 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
36 enum mv88e6xxx_egress_direction {
37 MV88E6XXX_EGRESS_DIR_INGRESS,
38 MV88E6XXX_EGRESS_DIR_EGRESS,
41 enum mv88e6xxx_frame_mode {
42 MV88E6XXX_FRAME_MODE_NORMAL,
43 MV88E6XXX_FRAME_MODE_DSA,
44 MV88E6XXX_FRAME_MODE_PROVIDER,
45 MV88E6XXX_FRAME_MODE_ETHERTYPE,
48 /* List of supported models */
49 enum mv88e6xxx_model {
80 enum mv88e6xxx_family {
81 MV88E6XXX_FAMILY_NONE,
82 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
83 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
84 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
85 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
86 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
87 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
88 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
89 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
90 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
91 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
92 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
97 struct mv88e6xxx_info {
98 enum mv88e6xxx_family family;
101 unsigned int num_databases;
102 unsigned int num_macs;
103 unsigned int num_ports;
104 unsigned int num_internal_phys;
105 unsigned int num_gpio;
106 unsigned int max_vid;
107 unsigned int port_base_addr;
108 unsigned int phy_base_addr;
109 unsigned int global1_addr;
110 unsigned int global2_addr;
111 unsigned int age_time_coeff;
112 unsigned int g1_irqs;
113 unsigned int g2_irqs;
116 /* Mark certain ports as invalid. This is required for example for the
117 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
118 * ports 2-4 are not routet to pins.
120 unsigned int invalid_port_mask;
121 /* Multi-chip Addressing Mode.
122 * Some chips respond to only 2 registers of its own SMI device address
123 * when it is non-zero, and use indirect access to internal registers.
126 /* Dual-chip Addressing Mode
127 * Some chips respond to only half of the 32 SMI addresses,
128 * allowing two to coexist on the same SMI interface.
132 enum dsa_tag_protocol tag_protocol;
134 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
135 * operation. 0 means that the ATU Move operation is not supported.
137 u8 atu_move_port_mask;
138 const struct mv88e6xxx_ops *ops;
144 struct mv88e6xxx_atu_entry {
151 struct mv88e6xxx_vtu_entry {
156 u8 member[DSA_MAX_PORTS];
157 u8 state[DSA_MAX_PORTS];
160 struct mv88e6xxx_bus_ops;
161 struct mv88e6xxx_irq_ops;
162 struct mv88e6xxx_gpio_ops;
163 struct mv88e6xxx_avb_ops;
164 struct mv88e6xxx_ptp_ops;
166 struct mv88e6xxx_irq {
168 struct irq_chip chip;
169 struct irq_domain *domain;
173 /* state flags for mv88e6xxx_port_hwtstamp::state */
175 MV88E6XXX_HWTSTAMP_ENABLED,
176 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
179 struct mv88e6xxx_port_hwtstamp {
183 /* Timestamping state */
186 /* Resources for receive timestamping */
187 struct sk_buff_head rx_queue;
188 struct sk_buff_head rx_queue2;
190 /* Resources for transmit timestamping */
191 unsigned long tx_tstamp_start;
192 struct sk_buff *tx_skb;
195 /* Current timestamp configuration */
196 struct hwtstamp_config tstamp_config;
199 enum mv88e6xxx_policy_mapping {
200 MV88E6XXX_POLICY_MAPPING_DA,
201 MV88E6XXX_POLICY_MAPPING_SA,
202 MV88E6XXX_POLICY_MAPPING_VTU,
203 MV88E6XXX_POLICY_MAPPING_ETYPE,
204 MV88E6XXX_POLICY_MAPPING_PPPOE,
205 MV88E6XXX_POLICY_MAPPING_VBAS,
206 MV88E6XXX_POLICY_MAPPING_OPT82,
207 MV88E6XXX_POLICY_MAPPING_UDP,
210 enum mv88e6xxx_policy_action {
211 MV88E6XXX_POLICY_ACTION_NORMAL,
212 MV88E6XXX_POLICY_ACTION_MIRROR,
213 MV88E6XXX_POLICY_ACTION_TRAP,
214 MV88E6XXX_POLICY_ACTION_DISCARD,
217 struct mv88e6xxx_policy {
218 enum mv88e6xxx_policy_mapping mapping;
219 enum mv88e6xxx_policy_action action;
220 struct ethtool_rx_flow_spec fs;
226 struct mv88e6xxx_port {
227 struct mv88e6xxx_chip *chip;
230 u64 atu_member_violation;
231 u64 atu_miss_violation;
232 u64 atu_full_violation;
233 u64 vtu_member_violation;
234 u64 vtu_miss_violation;
235 phy_interface_t interface;
239 unsigned int serdes_irq;
240 char serdes_irq_name[64];
241 struct devlink_region *region;
244 enum mv88e6xxx_region_id {
245 MV88E6XXX_REGION_GLOBAL1 = 0,
246 MV88E6XXX_REGION_GLOBAL2,
247 MV88E6XXX_REGION_ATU,
248 MV88E6XXX_REGION_VTU,
250 _MV88E6XXX_REGION_MAX,
253 struct mv88e6xxx_region_priv {
254 enum mv88e6xxx_region_id id;
257 struct mv88e6xxx_chip {
258 const struct mv88e6xxx_info *info;
260 /* The dsa_switch this private structure is related to */
261 struct dsa_switch *ds;
263 /* The device this structure is associated to */
266 /* This mutex protects the access to the switch registers */
267 struct mutex reg_lock;
269 /* The MII bus and the address on the bus that is used to
270 * communication with the switch
272 const struct mv88e6xxx_bus_ops *smi_ops;
276 /* Handles automatic disabling and re-enabling of the PHY
279 const struct mv88e6xxx_bus_ops *phy_ops;
280 struct mutex ppu_mutex;
282 struct work_struct ppu_work;
283 struct timer_list ppu_timer;
285 /* This mutex serialises access to the statistics unit.
286 * Hold this mutex over snapshot + dump sequences.
288 struct mutex stats_mutex;
290 /* A switch may have a GPIO line tied to its reset pin. Parse
291 * this from the device tree, and use it before performing
294 struct gpio_desc *reset;
296 /* set to size of eeprom if supported by the switch */
299 /* List of mdio busses */
300 struct list_head mdios;
302 /* Policy Control List IDs and rules */
305 /* There can be two interrupt controllers, which are chained
306 * off a GPIO as interrupt source
308 struct mv88e6xxx_irq g1_irq;
309 struct mv88e6xxx_irq g2_irq;
313 char device_irq_name[64];
315 char watchdog_irq_name[64];
318 char atu_prob_irq_name[64];
320 char vtu_prob_irq_name[64];
321 struct kthread_worker *kworker;
322 struct kthread_delayed_work irq_poll_work;
327 /* This cyclecounter abstracts the switch PTP time.
328 * reg_lock must be held for any operation that read()s.
330 struct cyclecounter tstamp_cc;
331 struct timecounter tstamp_tc;
332 struct delayed_work overflow_work;
334 struct ptp_clock *ptp_clock;
335 struct ptp_clock_info ptp_clock_info;
336 struct delayed_work tai_event_work;
337 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
342 /* Current ingress and egress monitor ports */
343 int egress_dest_port;
344 int ingress_dest_port;
346 /* Per-port timestamping resources. */
347 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
349 /* Array of port structures. */
350 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
352 /* devlink regions */
353 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
356 struct mv88e6xxx_bus_ops {
357 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
358 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
361 struct mv88e6xxx_mdio_bus {
363 struct mv88e6xxx_chip *chip;
364 struct list_head list;
368 struct mv88e6xxx_ops {
369 /* Switch Setup Errata, called early in the switch setup to
370 * allow any errata actions to be performed
372 int (*setup_errata)(struct mv88e6xxx_chip *chip);
374 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
375 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
377 /* Ingress Rate Limit unit (IRL) operations */
378 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
380 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
383 struct ethtool_eeprom *eeprom, u8 *data);
385 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
387 int (*phy_read)(struct mv88e6xxx_chip *chip,
389 int addr, int reg, u16 *val);
390 int (*phy_write)(struct mv88e6xxx_chip *chip,
392 int addr, int reg, u16 val);
394 /* Priority Override Table operations */
395 int (*pot_clear)(struct mv88e6xxx_chip *chip);
397 /* PHY Polling Unit (PPU) operations */
398 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
399 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
401 /* Switch Software Reset */
402 int (*reset)(struct mv88e6xxx_chip *chip);
404 /* RGMII Receive/Transmit Timing Control
405 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
407 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
408 phy_interface_t mode);
410 #define LINK_FORCED_DOWN 0
411 #define LINK_FORCED_UP 1
412 #define LINK_UNFORCED -2
414 /* Port's MAC link state
415 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
416 * or LINK_UNFORCED for normal link detection.
418 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
420 /* Synchronise the port link state with that of the SERDES
422 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
427 /* Enable/disable sending Pause */
428 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
431 #define SPEED_MAX INT_MAX
432 #define SPEED_UNFORCED -2
433 #define DUPLEX_UNFORCED -2
435 /* Port's MAC speed (in Mbps) and MAC duplex mode
437 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
438 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
440 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
441 * or DUPLEX_UNFORCED for normal duplex detection.
443 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
444 int speed, int duplex);
446 /* What interface mode should be used for maximum speed? */
447 phy_interface_t (*port_max_speed_mode)(int port);
449 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
451 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
452 enum mv88e6xxx_policy_mapping mapping,
453 enum mv88e6xxx_policy_action action);
455 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
456 enum mv88e6xxx_frame_mode mode);
457 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
459 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
461 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
463 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
466 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
467 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
469 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
470 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
471 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
473 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
474 * Some chips allow this to be configured on specific ports.
476 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
477 phy_interface_t mode);
478 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
480 /* Some devices have a per port register indicating what is
481 * the upstream port this port should forward to.
483 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
486 /* Snapshot the statistics for a port. The statistics can then
487 * be read back a leisure but still with a consistent view.
489 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
491 /* Set the histogram mode for statistics, when the control registers
492 * are separated out of the STATS_OP register.
494 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
496 /* Return the number of strings describing statistics */
497 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
498 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
499 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
501 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
502 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
503 enum mv88e6xxx_egress_direction direction,
506 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
507 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
509 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
511 const struct mv88e6xxx_irq_ops *watchdog_ops;
513 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
515 /* Power on/off a SERDES interface */
516 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
519 /* SERDES lane mapping */
520 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
522 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
523 int lane, struct phylink_link_state *state);
524 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
525 int lane, unsigned int mode,
526 phy_interface_t interface,
527 const unsigned long *advertise);
528 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
530 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
531 int lane, int speed, int duplex);
533 /* SERDES interrupt handling */
534 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
536 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
538 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
541 /* Statistics from the SERDES interface */
542 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
543 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
545 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
548 /* SERDES registers for ethtool */
549 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
550 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
553 /* Address Translation Unit operations */
554 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
555 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
557 /* VLAN Translation Unit operations */
558 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
559 struct mv88e6xxx_vtu_entry *entry);
560 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
561 struct mv88e6xxx_vtu_entry *entry);
563 /* GPIO operations */
564 const struct mv88e6xxx_gpio_ops *gpio_ops;
566 /* Interface to the AVB/PTP registers */
567 const struct mv88e6xxx_avb_ops *avb_ops;
569 /* Remote Management Unit operations */
570 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
572 /* Precision Time Protocol operations */
573 const struct mv88e6xxx_ptp_ops *ptp_ops;
576 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
578 struct phylink_link_state *state);
581 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
584 struct mv88e6xxx_irq_ops {
585 /* Action to be performed when the interrupt happens */
586 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
587 /* Setup the hardware to generate the interrupt */
588 int (*irq_setup)(struct mv88e6xxx_chip *chip);
589 /* Reset the hardware to stop generating the interrupt */
590 void (*irq_free)(struct mv88e6xxx_chip *chip);
593 struct mv88e6xxx_gpio_ops {
594 /* Get/set data on GPIO pin */
595 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
596 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
599 /* get/set GPIO direction */
600 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
601 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
604 /* get/set GPIO pin control */
605 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
607 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
611 struct mv88e6xxx_avb_ops {
612 /* Access port-scoped Precision Time Protocol registers */
613 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
615 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
618 /* Access global Precision Time Protocol registers */
619 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
621 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
623 /* Access global Time Application Interface registers */
624 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
626 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
629 struct mv88e6xxx_ptp_ops {
630 u64 (*clock_read)(const struct cyclecounter *cc);
631 int (*ptp_enable)(struct ptp_clock_info *ptp,
632 struct ptp_clock_request *rq, int on);
633 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
634 enum ptp_pin_function func, unsigned int chan);
635 void (*event_work)(struct work_struct *ugly);
636 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
637 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
638 int (*global_enable)(struct mv88e6xxx_chip *chip);
639 int (*global_disable)(struct mv88e6xxx_chip *chip);
651 #define STATS_TYPE_PORT BIT(0)
652 #define STATS_TYPE_BANK0 BIT(1)
653 #define STATS_TYPE_BANK1 BIT(2)
655 struct mv88e6xxx_hw_stat {
656 char string[ETH_GSTRING_LEN];
662 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
664 return chip->info->pvt;
667 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
669 return !!chip->info->global2_addr;
672 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
674 return chip->info->num_databases;
677 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
679 return chip->info->num_macs;
682 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
684 return chip->info->num_ports;
687 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
689 return chip->info->max_vid;
692 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
694 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
697 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
699 return chip->info->num_gpio;
702 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
704 return (chip->info->invalid_port_mask & BIT(port)) != 0;
707 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
708 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
709 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
711 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
713 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
715 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
717 mutex_lock(&chip->reg_lock);
720 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
722 mutex_unlock(&chip->reg_lock);
725 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
727 #endif /* _MV88E6XXX_CHIP_H */