drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 /* Indirect write to single pointer-data register with an Update bit */
 220 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 221                             u16 update)
 222 {
 223         u16 val;
 224         int i, err;
 225
 226         /* Wait until the previous operation is completed */
 227         for (i = 0; i < 16; ++i) {
 228                 err = mv88e6xxx_read(chip, addr, reg, &val);
 229                 if (err)
 230                         return err;
 231
 232                 if (!(val & BIT(15)))
 233                         break;
 234         }
 235
 236         if (i == 16)
 237                 return -ETIMEDOUT;
 238
 239         /* Set the Update bit to trigger a write operation */
 240         val = BIT(15) | update;
 241
 242         return mv88e6xxx_write(chip, addr, reg, val);
 243 }
 244
 245 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 246 {
 247         u16 val;
 248         int err;
 249
 250         err = mv88e6xxx_read(chip, addr, reg, &val);
 251         if (err)
 252                 return err;
 253
 254         return val;
 255 }
 256
 257 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 258                                 int reg, u16 val)
 259 {
 260         return mv88e6xxx_write(chip, addr, reg, val);
 261 }
 262
 263 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
 264                                       int addr, int regnum)
 265 {
 266         if (addr >= 0)
 267                 return _mv88e6xxx_reg_read(chip, addr, regnum);
 268         return 0xffff;
 269 }
 270
 271 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
 272                                        int addr, int regnum, u16 val)
 273 {
 274         if (addr >= 0)
 275                 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
 276         return 0;
 277 }
 278
 279 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 280 {
 281         int ret;
 282         unsigned long timeout;
 283
 284         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 285         if (ret < 0)
 286                 return ret;
 287
 288         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 289                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 290         if (ret)
 291                 return ret;
 292
 293         timeout = jiffies + 1 * HZ;
 294         while (time_before(jiffies, timeout)) {
 295                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 296                 if (ret < 0)
 297                         return ret;
 298
 299                 usleep_range(1000, 2000);
 300                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 301                     GLOBAL_STATUS_PPU_POLLING)
 302                         return 0;
 303         }
 304
 305         return -ETIMEDOUT;
 306 }
 307
 308 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 309 {
 310         int ret, err;
 311         unsigned long timeout;
 312
 313         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 314         if (ret < 0)
 315                 return ret;
 316
 317         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 318                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 319         if (err)
 320                 return err;
 321
 322         timeout = jiffies + 1 * HZ;
 323         while (time_before(jiffies, timeout)) {
 324                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 325                 if (ret < 0)
 326                         return ret;
 327
 328                 usleep_range(1000, 2000);
 329                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 330                     GLOBAL_STATUS_PPU_POLLING)
 331                         return 0;
 332         }
 333
 334         return -ETIMEDOUT;
 335 }
 336
 337 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 338 {
 339         struct mv88e6xxx_chip *chip;
 340
 341         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 342
 343         mutex_lock(&chip->reg_lock);
 344
 345         if (mutex_trylock(&chip->ppu_mutex)) {
 346                 if (mv88e6xxx_ppu_enable(chip) == 0)
 347                         chip->ppu_disabled = 0;
 348                 mutex_unlock(&chip->ppu_mutex);
 349         }
 350
 351         mutex_unlock(&chip->reg_lock);
 352 }
 353
 354 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 355 {
 356         struct mv88e6xxx_chip *chip = (void *)_ps;
 357
 358         schedule_work(&chip->ppu_work);
 359 }
 360
 361 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 362 {
 363         int ret;
 364
 365         mutex_lock(&chip->ppu_mutex);
 366
 367         /* If the PHY polling unit is enabled, disable it so that
 368          * we can access the PHY registers.  If it was already
 369          * disabled, cancel the timer that is going to re-enable
 370          * it.
 371          */
 372         if (!chip->ppu_disabled) {
 373                 ret = mv88e6xxx_ppu_disable(chip);
 374                 if (ret < 0) {
 375                         mutex_unlock(&chip->ppu_mutex);
 376                         return ret;
 377                 }
 378                 chip->ppu_disabled = 1;
 379         } else {
 380                 del_timer(&chip->ppu_timer);
 381                 ret = 0;
 382         }
 383
 384         return ret;
 385 }
 386
 387 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 388 {
 389         /* Schedule a timer to re-enable the PHY polling unit. */
 390         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 391         mutex_unlock(&chip->ppu_mutex);
 392 }
 393
 394 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 395 {
 396         mutex_init(&chip->ppu_mutex);
 397         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 398         init_timer(&chip->ppu_timer);
 399         chip->ppu_timer.data = (unsigned long)chip;
 400         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 401 }
 402
 403 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
 404                                    int regnum)
 405 {
 406         int ret;
 407
 408         ret = mv88e6xxx_ppu_access_get(chip);
 409         if (ret >= 0) {
 410                 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
 411                 mv88e6xxx_ppu_access_put(chip);
 412         }
 413
 414         return ret;
 415 }
 416
 417 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
 418                                     int regnum, u16 val)
 419 {
 420         int ret;
 421
 422         ret = mv88e6xxx_ppu_access_get(chip);
 423         if (ret >= 0) {
 424                 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
 425                 mv88e6xxx_ppu_access_put(chip);
 426         }
 427
 428         return ret;
 429 }
 430
 431 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 432 {
 433         return chip->info->family == MV88E6XXX_FAMILY_6065;
 434 }
 435
 436 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 437 {
 438         return chip->info->family == MV88E6XXX_FAMILY_6095;
 439 }
 440
 441 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 442 {
 443         return chip->info->family == MV88E6XXX_FAMILY_6097;
 444 }
 445
 446 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 447 {
 448         return chip->info->family == MV88E6XXX_FAMILY_6165;
 449 }
 450
 451 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 452 {
 453         return chip->info->family == MV88E6XXX_FAMILY_6185;
 454 }
 455
 456 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 457 {
 458         return chip->info->family == MV88E6XXX_FAMILY_6320;
 459 }
 460
 461 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 462 {
 463         return chip->info->family == MV88E6XXX_FAMILY_6351;
 464 }
 465
 466 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 467 {
 468         return chip->info->family == MV88E6XXX_FAMILY_6352;
 469 }
 470
 471 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 472 {
 473         return chip->info->num_databases;
 474 }
 475
 476 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 477 {
 478         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 479         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 480             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 481                 return true;
 482
 483         return false;
 484 }
 485
 486 /* We expect the switch to perform auto negotiation if there is a real
 487  * phy. However, in the case of a fixed link phy, we force the port
 488  * settings from the fixed link settings.
 489  */
 490 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 491                                   struct phy_device *phydev)
 492 {
 493         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 494         u32 reg;
 495         int ret;
 496
 497         if (!phy_is_pseudo_fixed_link(phydev))
 498                 return;
 499
 500         mutex_lock(&chip->reg_lock);
 501
 502         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 503         if (ret < 0)
 504                 goto out;
 505
 506         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 507                       PORT_PCS_CTRL_FORCE_LINK |
 508                       PORT_PCS_CTRL_DUPLEX_FULL |
 509                       PORT_PCS_CTRL_FORCE_DUPLEX |
 510                       PORT_PCS_CTRL_UNFORCED);
 511
 512         reg |= PORT_PCS_CTRL_FORCE_LINK;
 513         if (phydev->link)
 514                 reg |= PORT_PCS_CTRL_LINK_UP;
 515
 516         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 517                 goto out;
 518
 519         switch (phydev->speed) {
 520         case SPEED_1000:
 521                 reg |= PORT_PCS_CTRL_1000;
 522                 break;
 523         case SPEED_100:
 524                 reg |= PORT_PCS_CTRL_100;
 525                 break;
 526         case SPEED_10:
 527                 reg |= PORT_PCS_CTRL_10;
 528                 break;
 529         default:
 530                 pr_info("Unknown speed");
 531                 goto out;
 532         }
 533
 534         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 535         if (phydev->duplex == DUPLEX_FULL)
 536                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 537
 538         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 539             (port >= chip->info->num_ports - 2)) {
 540                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 541                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 542                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 543                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 544                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 545                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 546                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 547         }
 548         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 549
 550 out:
 551         mutex_unlock(&chip->reg_lock);
 552 }
 553
 554 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 555 {
 556         int ret;
 557         int i;
 558
 559         for (i = 0; i < 10; i++) {
 560                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 561                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 562                         return 0;
 563         }
 564
 565         return -ETIMEDOUT;
 566 }
 567
 568 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 569 {
 570         int ret;
 571
 572         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 573                 port = (port + 1) << 5;
 574
 575         /* Snapshot the hardware statistics counters for this port. */
 576         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 577                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 578                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 579         if (ret < 0)
 580                 return ret;
 581
 582         /* Wait for the snapshotting to complete. */
 583         ret = _mv88e6xxx_stats_wait(chip);
 584         if (ret < 0)
 585                 return ret;
 586
 587         return 0;
 588 }
 589
 590 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 591                                   int stat, u32 *val)
 592 {
 593         u32 _val;
 594         int ret;
 595
 596         *val = 0;
 597
 598         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 599                                    GLOBAL_STATS_OP_READ_CAPTURED |
 600                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 601         if (ret < 0)
 602                 return;
 603
 604         ret = _mv88e6xxx_stats_wait(chip);
 605         if (ret < 0)
 606                 return;
 607
 608         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 609         if (ret < 0)
 610                 return;
 611
 612         _val = ret << 16;
 613
 614         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 615         if (ret < 0)
 616                 return;
 617
 618         *val = _val | ret;
 619 }
 620
 621 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 622         { "in_good_octets",     8, 0x00, BANK0, },
 623         { "in_bad_octets",      4, 0x02, BANK0, },
 624         { "in_unicast",         4, 0x04, BANK0, },
 625         { "in_broadcasts",      4, 0x06, BANK0, },
 626         { "in_multicasts",      4, 0x07, BANK0, },
 627         { "in_pause",           4, 0x16, BANK0, },
 628         { "in_undersize",       4, 0x18, BANK0, },
 629         { "in_fragments",       4, 0x19, BANK0, },
 630         { "in_oversize",        4, 0x1a, BANK0, },
 631         { "in_jabber",          4, 0x1b, BANK0, },
 632         { "in_rx_error",        4, 0x1c, BANK0, },
 633         { "in_fcs_error",       4, 0x1d, BANK0, },
 634         { "out_octets",         8, 0x0e, BANK0, },
 635         { "out_unicast",        4, 0x10, BANK0, },
 636         { "out_broadcasts",     4, 0x13, BANK0, },
 637         { "out_multicasts",     4, 0x12, BANK0, },
 638         { "out_pause",          4, 0x15, BANK0, },
 639         { "excessive",          4, 0x11, BANK0, },
 640         { "collisions",         4, 0x1e, BANK0, },
 641         { "deferred",           4, 0x05, BANK0, },
 642         { "single",             4, 0x14, BANK0, },
 643         { "multiple",           4, 0x17, BANK0, },
 644         { "out_fcs_error",      4, 0x03, BANK0, },
 645         { "late",               4, 0x1f, BANK0, },
 646         { "hist_64bytes",       4, 0x08, BANK0, },
 647         { "hist_65_127bytes",   4, 0x09, BANK0, },
 648         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 649         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 650         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 651         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 652         { "sw_in_discards",     4, 0x10, PORT, },
 653         { "sw_in_filtered",     2, 0x12, PORT, },
 654         { "sw_out_filtered",    2, 0x13, PORT, },
 655         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 656         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 657         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 658         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 659         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 660         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 661         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 662         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 663         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 664         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 665         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 666         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 667         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 668         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 669         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 670         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 671         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 672         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 673         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 674         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 675         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 676         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 677         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 678         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 679         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 680         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 681 };
 682
 683 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 684                                struct mv88e6xxx_hw_stat *stat)
 685 {
 686         switch (stat->type) {
 687         case BANK0:
 688                 return true;
 689         case BANK1:
 690                 return mv88e6xxx_6320_family(chip);
 691         case PORT:
 692                 return mv88e6xxx_6095_family(chip) ||
 693                         mv88e6xxx_6185_family(chip) ||
 694                         mv88e6xxx_6097_family(chip) ||
 695                         mv88e6xxx_6165_family(chip) ||
 696                         mv88e6xxx_6351_family(chip) ||
 697                         mv88e6xxx_6352_family(chip);
 698         }
 699         return false;
 700 }
 701
 702 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 703                                             struct mv88e6xxx_hw_stat *s,
 704                                             int port)
 705 {
 706         u32 low;
 707         u32 high = 0;
 708         int ret;
 709         u64 value;
 710
 711         switch (s->type) {
 712         case PORT:
 713                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 714                 if (ret < 0)
 715                         return UINT64_MAX;
 716
 717                 low = ret;
 718                 if (s->sizeof_stat == 4) {
 719                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 720                                                   s->reg + 1);
 721                         if (ret < 0)
 722                                 return UINT64_MAX;
 723                         high = ret;
 724                 }
 725                 break;
 726         case BANK0:
 727         case BANK1:
 728                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 729                 if (s->sizeof_stat == 8)
 730                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 731         }
 732         value = (((u64)high) << 16) | low;
 733         return value;
 734 }
 735
 736 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 737                                   uint8_t *data)
 738 {
 739         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 740         struct mv88e6xxx_hw_stat *stat;
 741         int i, j;
 742
 743         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 744                 stat = &mv88e6xxx_hw_stats[i];
 745                 if (mv88e6xxx_has_stat(chip, stat)) {
 746                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 747                                ETH_GSTRING_LEN);
 748                         j++;
 749                 }
 750         }
 751 }
 752
 753 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 754 {
 755         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 756         struct mv88e6xxx_hw_stat *stat;
 757         int i, j;
 758
 759         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 760                 stat = &mv88e6xxx_hw_stats[i];
 761                 if (mv88e6xxx_has_stat(chip, stat))
 762                         j++;
 763         }
 764         return j;
 765 }
 766
 767 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 768                                         uint64_t *data)
 769 {
 770         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 771         struct mv88e6xxx_hw_stat *stat;
 772         int ret;
 773         int i, j;
 774
 775         mutex_lock(&chip->reg_lock);
 776
 777         ret = _mv88e6xxx_stats_snapshot(chip, port);
 778         if (ret < 0) {
 779                 mutex_unlock(&chip->reg_lock);
 780                 return;
 781         }
 782         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 783                 stat = &mv88e6xxx_hw_stats[i];
 784                 if (mv88e6xxx_has_stat(chip, stat)) {
 785                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 786                         j++;
 787                 }
 788         }
 789
 790         mutex_unlock(&chip->reg_lock);
 791 }
 792
 793 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 794 {
 795         return 32 * sizeof(u16);
 796 }
 797
 798 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 799                                struct ethtool_regs *regs, void *_p)
 800 {
 801         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 802         u16 *p = _p;
 803         int i;
 804
 805         regs->version = 0;
 806
 807         memset(p, 0xff, 32 * sizeof(u16));
 808
 809         mutex_lock(&chip->reg_lock);
 810
 811         for (i = 0; i < 32; i++) {
 812                 int ret;
 813
 814                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 815                 if (ret >= 0)
 816                         p[i] = ret;
 817         }
 818
 819         mutex_unlock(&chip->reg_lock);
 820 }
 821
 822 static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
 823                            u16 mask)
 824 {
 825         unsigned long timeout = jiffies + HZ / 10;
 826
 827         while (time_before(jiffies, timeout)) {
 828                 int ret;
 829
 830                 ret = _mv88e6xxx_reg_read(chip, reg, offset);
 831                 if (ret < 0)
 832                         return ret;
 833                 if (!(ret & mask))
 834                         return 0;
 835
 836                 usleep_range(1000, 2000);
 837         }
 838         return -ETIMEDOUT;
 839 }
 840
 841 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
 842 {
 843         return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 844                                GLOBAL2_SMI_OP_BUSY);
 845 }
 846
 847 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 848 {
 849         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 850                                GLOBAL_ATU_OP_BUSY);
 851 }
 852
 853 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
 854                                         int addr, int regnum)
 855 {
 856         int ret;
 857
 858         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 859                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
 860                                    regnum);
 861         if (ret < 0)
 862                 return ret;
 863
 864         ret = mv88e6xxx_mdio_wait(chip);
 865         if (ret < 0)
 866                 return ret;
 867
 868         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
 869
 870         return ret;
 871 }
 872
 873 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
 874                                          int addr, int regnum, u16 val)
 875 {
 876         int ret;
 877
 878         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
 879         if (ret < 0)
 880                 return ret;
 881
 882         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 883                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
 884                                    regnum);
 885
 886         return mv88e6xxx_mdio_wait(chip);
 887 }
 888
 889 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 890                              struct ethtool_eee *e)
 891 {
 892         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 893         int reg;
 894
 895         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 896                 return -EOPNOTSUPP;
 897
 898         mutex_lock(&chip->reg_lock);
 899
 900         reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 901         if (reg < 0)
 902                 goto out;
 903
 904         e->eee_enabled = !!(reg & 0x0200);
 905         e->tx_lpi_enabled = !!(reg & 0x0100);
 906
 907         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
 908         if (reg < 0)
 909                 goto out;
 910
 911         e->eee_active = !!(reg & PORT_STATUS_EEE);
 912         reg = 0;
 913
 914 out:
 915         mutex_unlock(&chip->reg_lock);
 916         return reg;
 917 }
 918
 919 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 920                              struct phy_device *phydev, struct ethtool_eee *e)
 921 {
 922         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 923         int reg;
 924         int ret;
 925
 926         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 927                 return -EOPNOTSUPP;
 928
 929         mutex_lock(&chip->reg_lock);
 930
 931         ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 932         if (ret < 0)
 933                 goto out;
 934
 935         reg = ret & ~0x0300;
 936         if (e->eee_enabled)
 937                 reg |= 0x0200;
 938         if (e->tx_lpi_enabled)
 939                 reg |= 0x0100;
 940
 941         ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
 942 out:
 943         mutex_unlock(&chip->reg_lock);
 944
 945         return ret;
 946 }
 947
 948 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 949 {
 950         int ret;
 951
 952         if (mv88e6xxx_has_fid_reg(chip)) {
 953                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 954                                            fid);
 955                 if (ret < 0)
 956                         return ret;
 957         } else if (mv88e6xxx_num_databases(chip) == 256) {
 958                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 959                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 960                 if (ret < 0)
 961                         return ret;
 962
 963                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
 964                                            (ret & 0xfff) |
 965                                            ((fid << 8) & 0xf000));
 966                 if (ret < 0)
 967                         return ret;
 968
 969                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
 970                 cmd |= fid & 0xf;
 971         }
 972
 973         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
 974         if (ret < 0)
 975                 return ret;
 976
 977         return _mv88e6xxx_atu_wait(chip);
 978 }
 979
 980 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
 981                                      struct mv88e6xxx_atu_entry *entry)
 982 {
 983         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
 984
 985         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
 986                 unsigned int mask, shift;
 987
 988                 if (entry->trunk) {
 989                         data |= GLOBAL_ATU_DATA_TRUNK;
 990                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
 991                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
 992                 } else {
 993                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
 994                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
 995                 }
 996
 997                 data |= (entry->portv_trunkid << shift) & mask;
 998         }
 999
1000         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1001 }
1002
1003 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1004                                      struct mv88e6xxx_atu_entry *entry,
1005                                      bool static_too)
1006 {
1007         int op;
1008         int err;
1009
1010         err = _mv88e6xxx_atu_wait(chip);
1011         if (err)
1012                 return err;
1013
1014         err = _mv88e6xxx_atu_data_write(chip, entry);
1015         if (err)
1016                 return err;
1017
1018         if (entry->fid) {
1019                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1020                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1021         } else {
1022                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1023                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1024         }
1025
1026         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1027 }
1028
1029 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1030                                 u16 fid, bool static_too)
1031 {
1032         struct mv88e6xxx_atu_entry entry = {
1033                 .fid = fid,
1034                 .state = 0, /* EntryState bits must be 0 */
1035         };
1036
1037         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1038 }
1039
1040 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1041                                int from_port, int to_port, bool static_too)
1042 {
1043         struct mv88e6xxx_atu_entry entry = {
1044                 .trunk = false,
1045                 .fid = fid,
1046         };
1047
1048         /* EntryState bits must be 0xF */
1049         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1050
1051         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1052         entry.portv_trunkid = (to_port & 0x0f) << 4;
1053         entry.portv_trunkid |= from_port & 0x0f;
1054
1055         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1056 }
1057
1058 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1059                                  int port, bool static_too)
1060 {
1061         /* Destination port 0xF means remove the entries */
1062         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1063 }
1064
1065 static const char * const mv88e6xxx_port_state_names[] = {
1066         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1067         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1068         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1069         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1070 };
1071
1072 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1073                                  u8 state)
1074 {
1075         struct dsa_switch *ds = chip->ds;
1076         int reg, ret = 0;
1077         u8 oldstate;
1078
1079         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1080         if (reg < 0)
1081                 return reg;
1082
1083         oldstate = reg & PORT_CONTROL_STATE_MASK;
1084
1085         if (oldstate != state) {
1086                 /* Flush forwarding database if we're moving a port
1087                  * from Learning or Forwarding state to Disabled or
1088                  * Blocking or Listening state.
1089                  */
1090                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1091                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1092                     (state == PORT_CONTROL_STATE_DISABLED ||
1093                      state == PORT_CONTROL_STATE_BLOCKING)) {
1094                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1095                         if (ret)
1096                                 return ret;
1097                 }
1098
1099                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1100                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1101                                            reg);
1102                 if (ret)
1103                         return ret;
1104
1105                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1106                            mv88e6xxx_port_state_names[state],
1107                            mv88e6xxx_port_state_names[oldstate]);
1108         }
1109
1110         return ret;
1111 }
1112
1113 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1114 {
1115         struct net_device *bridge = chip->ports[port].bridge_dev;
1116         const u16 mask = (1 << chip->info->num_ports) - 1;
1117         struct dsa_switch *ds = chip->ds;
1118         u16 output_ports = 0;
1119         int reg;
1120         int i;
1121
1122         /* allow CPU port or DSA link(s) to send frames to every port */
1123         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1124                 output_ports = mask;
1125         } else {
1126                 for (i = 0; i < chip->info->num_ports; ++i) {
1127                         /* allow sending frames to every group member */
1128                         if (bridge && chip->ports[i].bridge_dev == bridge)
1129                                 output_ports |= BIT(i);
1130
1131                         /* allow sending frames to CPU port and DSA link(s) */
1132                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1133                                 output_ports |= BIT(i);
1134                 }
1135         }
1136
1137         /* prevent frames from going back out of the port they came in on */
1138         output_ports &= ~BIT(port);
1139
1140         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1141         if (reg < 0)
1142                 return reg;
1143
1144         reg &= ~mask;
1145         reg |= output_ports & mask;
1146
1147         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1148 }
1149
1150 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1151                                          u8 state)
1152 {
1153         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1154         int stp_state;
1155         int err;
1156
1157         switch (state) {
1158         case BR_STATE_DISABLED:
1159                 stp_state = PORT_CONTROL_STATE_DISABLED;
1160                 break;
1161         case BR_STATE_BLOCKING:
1162         case BR_STATE_LISTENING:
1163                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1164                 break;
1165         case BR_STATE_LEARNING:
1166                 stp_state = PORT_CONTROL_STATE_LEARNING;
1167                 break;
1168         case BR_STATE_FORWARDING:
1169         default:
1170                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1171                 break;
1172         }
1173
1174         mutex_lock(&chip->reg_lock);
1175         err = _mv88e6xxx_port_state(chip, port, stp_state);
1176         mutex_unlock(&chip->reg_lock);
1177
1178         if (err)
1179                 netdev_err(ds->ports[port].netdev,
1180                            "failed to update state to %s\n",
1181                            mv88e6xxx_port_state_names[stp_state]);
1182 }
1183
1184 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1185                                 u16 *new, u16 *old)
1186 {
1187         struct dsa_switch *ds = chip->ds;
1188         u16 pvid;
1189         int ret;
1190
1191         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1192         if (ret < 0)
1193                 return ret;
1194
1195         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1196
1197         if (new) {
1198                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1199                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1200
1201                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1202                                            PORT_DEFAULT_VLAN, ret);
1203                 if (ret < 0)
1204                         return ret;
1205
1206                 netdev_dbg(ds->ports[port].netdev,
1207                            "DefaultVID %d (was %d)\n", *new, pvid);
1208         }
1209
1210         if (old)
1211                 *old = pvid;
1212
1213         return 0;
1214 }
1215
1216 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1217                                     int port, u16 *pvid)
1218 {
1219         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1220 }
1221
1222 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1223                                     int port, u16 pvid)
1224 {
1225         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1226 }
1227
1228 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1229 {
1230         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1231                                GLOBAL_VTU_OP_BUSY);
1232 }
1233
1234 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1235 {
1236         int ret;
1237
1238         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1239         if (ret < 0)
1240                 return ret;
1241
1242         return _mv88e6xxx_vtu_wait(chip);
1243 }
1244
1245 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1246 {
1247         int ret;
1248
1249         ret = _mv88e6xxx_vtu_wait(chip);
1250         if (ret < 0)
1251                 return ret;
1252
1253         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1254 }
1255
1256 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1257                                         struct mv88e6xxx_vtu_stu_entry *entry,
1258                                         unsigned int nibble_offset)
1259 {
1260         u16 regs[3];
1261         int i;
1262         int ret;
1263
1264         for (i = 0; i < 3; ++i) {
1265                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1266                                           GLOBAL_VTU_DATA_0_3 + i);
1267                 if (ret < 0)
1268                         return ret;
1269
1270                 regs[i] = ret;
1271         }
1272
1273         for (i = 0; i < chip->info->num_ports; ++i) {
1274                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1275                 u16 reg = regs[i / 4];
1276
1277                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1278         }
1279
1280         return 0;
1281 }
1282
1283 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1284                                    struct mv88e6xxx_vtu_stu_entry *entry)
1285 {
1286         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1287 }
1288
1289 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1290                                    struct mv88e6xxx_vtu_stu_entry *entry)
1291 {
1292         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1293 }
1294
1295 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1296                                          struct mv88e6xxx_vtu_stu_entry *entry,
1297                                          unsigned int nibble_offset)
1298 {
1299         u16 regs[3] = { 0 };
1300         int i;
1301         int ret;
1302
1303         for (i = 0; i < chip->info->num_ports; ++i) {
1304                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1305                 u8 data = entry->data[i];
1306
1307                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1308         }
1309
1310         for (i = 0; i < 3; ++i) {
1311                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1312                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1313                 if (ret < 0)
1314                         return ret;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1321                                     struct mv88e6xxx_vtu_stu_entry *entry)
1322 {
1323         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1324 }
1325
1326 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1327                                     struct mv88e6xxx_vtu_stu_entry *entry)
1328 {
1329         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1330 }
1331
1332 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1333 {
1334         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1335                                     vid & GLOBAL_VTU_VID_MASK);
1336 }
1337
1338 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1339                                   struct mv88e6xxx_vtu_stu_entry *entry)
1340 {
1341         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1342         int ret;
1343
1344         ret = _mv88e6xxx_vtu_wait(chip);
1345         if (ret < 0)
1346                 return ret;
1347
1348         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1349         if (ret < 0)
1350                 return ret;
1351
1352         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1353         if (ret < 0)
1354                 return ret;
1355
1356         next.vid = ret & GLOBAL_VTU_VID_MASK;
1357         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1358
1359         if (next.valid) {
1360                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1361                 if (ret < 0)
1362                         return ret;
1363
1364                 if (mv88e6xxx_has_fid_reg(chip)) {
1365                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1366                                                   GLOBAL_VTU_FID);
1367                         if (ret < 0)
1368                                 return ret;
1369
1370                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1371                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1372                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1373                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1374                          */
1375                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1376                                                   GLOBAL_VTU_OP);
1377                         if (ret < 0)
1378                                 return ret;
1379
1380                         next.fid = (ret & 0xf00) >> 4;
1381                         next.fid |= ret & 0xf;
1382                 }
1383
1384                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1385                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1386                                                   GLOBAL_VTU_SID);
1387                         if (ret < 0)
1388                                 return ret;
1389
1390                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1391                 }
1392         }
1393
1394         *entry = next;
1395         return 0;
1396 }
1397
1398 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1399                                     struct switchdev_obj_port_vlan *vlan,
1400                                     int (*cb)(struct switchdev_obj *obj))
1401 {
1402         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1403         struct mv88e6xxx_vtu_stu_entry next;
1404         u16 pvid;
1405         int err;
1406
1407         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1408                 return -EOPNOTSUPP;
1409
1410         mutex_lock(&chip->reg_lock);
1411
1412         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1413         if (err)
1414                 goto unlock;
1415
1416         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1417         if (err)
1418                 goto unlock;
1419
1420         do {
1421                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1422                 if (err)
1423                         break;
1424
1425                 if (!next.valid)
1426                         break;
1427
1428                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1429                         continue;
1430
1431                 /* reinit and dump this VLAN obj */
1432                 vlan->vid_begin = next.vid;
1433                 vlan->vid_end = next.vid;
1434                 vlan->flags = 0;
1435
1436                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1437                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1438
1439                 if (next.vid == pvid)
1440                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1441
1442                 err = cb(&vlan->obj);
1443                 if (err)
1444                         break;
1445         } while (next.vid < GLOBAL_VTU_VID_MASK);
1446
1447 unlock:
1448         mutex_unlock(&chip->reg_lock);
1449
1450         return err;
1451 }
1452
1453 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1454                                     struct mv88e6xxx_vtu_stu_entry *entry)
1455 {
1456         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1457         u16 reg = 0;
1458         int ret;
1459
1460         ret = _mv88e6xxx_vtu_wait(chip);
1461         if (ret < 0)
1462                 return ret;
1463
1464         if (!entry->valid)
1465                 goto loadpurge;
1466
1467         /* Write port member tags */
1468         ret = mv88e6xxx_vtu_data_write(chip, entry);
1469         if (ret < 0)
1470                 return ret;
1471
1472         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1473                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1474                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1475                                            reg);
1476                 if (ret < 0)
1477                         return ret;
1478         }
1479
1480         if (mv88e6xxx_has_fid_reg(chip)) {
1481                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1482                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1483                                            reg);
1484                 if (ret < 0)
1485                         return ret;
1486         } else if (mv88e6xxx_num_databases(chip) == 256) {
1487                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1488                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1489                  */
1490                 op |= (entry->fid & 0xf0) << 8;
1491                 op |= entry->fid & 0xf;
1492         }
1493
1494         reg = GLOBAL_VTU_VID_VALID;
1495 loadpurge:
1496         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1497         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1498         if (ret < 0)
1499                 return ret;
1500
1501         return _mv88e6xxx_vtu_cmd(chip, op);
1502 }
1503
1504 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1505                                   struct mv88e6xxx_vtu_stu_entry *entry)
1506 {
1507         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1508         int ret;
1509
1510         ret = _mv88e6xxx_vtu_wait(chip);
1511         if (ret < 0)
1512                 return ret;
1513
1514         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1515                                    sid & GLOBAL_VTU_SID_MASK);
1516         if (ret < 0)
1517                 return ret;
1518
1519         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1520         if (ret < 0)
1521                 return ret;
1522
1523         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1524         if (ret < 0)
1525                 return ret;
1526
1527         next.sid = ret & GLOBAL_VTU_SID_MASK;
1528
1529         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1530         if (ret < 0)
1531                 return ret;
1532
1533         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1534
1535         if (next.valid) {
1536                 ret = mv88e6xxx_stu_data_read(chip, &next);
1537                 if (ret < 0)
1538                         return ret;
1539         }
1540
1541         *entry = next;
1542         return 0;
1543 }
1544
1545 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1546                                     struct mv88e6xxx_vtu_stu_entry *entry)
1547 {
1548         u16 reg = 0;
1549         int ret;
1550
1551         ret = _mv88e6xxx_vtu_wait(chip);
1552         if (ret < 0)
1553                 return ret;
1554
1555         if (!entry->valid)
1556                 goto loadpurge;
1557
1558         /* Write port states */
1559         ret = mv88e6xxx_stu_data_write(chip, entry);
1560         if (ret < 0)
1561                 return ret;
1562
1563         reg = GLOBAL_VTU_VID_VALID;
1564 loadpurge:
1565         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1566         if (ret < 0)
1567                 return ret;
1568
1569         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1570         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1571         if (ret < 0)
1572                 return ret;
1573
1574         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1575 }
1576
1577 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1578                                u16 *new, u16 *old)
1579 {
1580         struct dsa_switch *ds = chip->ds;
1581         u16 upper_mask;
1582         u16 fid;
1583         int ret;
1584
1585         if (mv88e6xxx_num_databases(chip) == 4096)
1586                 upper_mask = 0xff;
1587         else if (mv88e6xxx_num_databases(chip) == 256)
1588                 upper_mask = 0xf;
1589         else
1590                 return -EOPNOTSUPP;
1591
1592         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1593         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1594         if (ret < 0)
1595                 return ret;
1596
1597         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1598
1599         if (new) {
1600                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1601                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1602
1603                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1604                                            ret);
1605                 if (ret < 0)
1606                         return ret;
1607         }
1608
1609         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1610         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1611         if (ret < 0)
1612                 return ret;
1613
1614         fid |= (ret & upper_mask) << 4;
1615
1616         if (new) {
1617                 ret &= ~upper_mask;
1618                 ret |= (*new >> 4) & upper_mask;
1619
1620                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1621                                            ret);
1622                 if (ret < 0)
1623                         return ret;
1624
1625                 netdev_dbg(ds->ports[port].netdev,
1626                            "FID %d (was %d)\n", *new, fid);
1627         }
1628
1629         if (old)
1630                 *old = fid;
1631
1632         return 0;
1633 }
1634
1635 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1636                                    int port, u16 *fid)
1637 {
1638         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1639 }
1640
1641 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1642                                    int port, u16 fid)
1643 {
1644         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1645 }
1646
1647 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1648 {
1649         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1650         struct mv88e6xxx_vtu_stu_entry vlan;
1651         int i, err;
1652
1653         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1654
1655         /* Set every FID bit used by the (un)bridged ports */
1656         for (i = 0; i < chip->info->num_ports; ++i) {
1657                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1658                 if (err)
1659                         return err;
1660
1661                 set_bit(*fid, fid_bitmap);
1662         }
1663
1664         /* Set every FID bit used by the VLAN entries */
1665         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1666         if (err)
1667                 return err;
1668
1669         do {
1670                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1671                 if (err)
1672                         return err;
1673
1674                 if (!vlan.valid)
1675                         break;
1676
1677                 set_bit(vlan.fid, fid_bitmap);
1678         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1679
1680         /* The reset value 0x000 is used to indicate that multiple address
1681          * databases are not needed. Return the next positive available.
1682          */
1683         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1684         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1685                 return -ENOSPC;
1686
1687         /* Clear the database */
1688         return _mv88e6xxx_atu_flush(chip, *fid, true);
1689 }
1690
1691 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1692                               struct mv88e6xxx_vtu_stu_entry *entry)
1693 {
1694         struct dsa_switch *ds = chip->ds;
1695         struct mv88e6xxx_vtu_stu_entry vlan = {
1696                 .valid = true,
1697                 .vid = vid,
1698         };
1699         int i, err;
1700
1701         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1702         if (err)
1703                 return err;
1704
1705         /* exclude all ports except the CPU and DSA ports */
1706         for (i = 0; i < chip->info->num_ports; ++i)
1707                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1708                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1709                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1710
1711         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1712             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1713                 struct mv88e6xxx_vtu_stu_entry vstp;
1714
1715                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1716                  * implemented, only one STU entry is needed to cover all VTU
1717                  * entries. Thus, validate the SID 0.
1718                  */
1719                 vlan.sid = 0;
1720                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1721                 if (err)
1722                         return err;
1723
1724                 if (vstp.sid != vlan.sid || !vstp.valid) {
1725                         memset(&vstp, 0, sizeof(vstp));
1726                         vstp.valid = true;
1727                         vstp.sid = vlan.sid;
1728
1729                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1730                         if (err)
1731                                 return err;
1732                 }
1733         }
1734
1735         *entry = vlan;
1736         return 0;
1737 }
1738
1739 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1740                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1741 {
1742         int err;
1743
1744         if (!vid)
1745                 return -EINVAL;
1746
1747         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1748         if (err)
1749                 return err;
1750
1751         err = _mv88e6xxx_vtu_getnext(chip, entry);
1752         if (err)
1753                 return err;
1754
1755         if (entry->vid != vid || !entry->valid) {
1756                 if (!creat)
1757                         return -EOPNOTSUPP;
1758                 /* -ENOENT would've been more appropriate, but switchdev expects
1759                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1760                  */
1761
1762                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1763         }
1764
1765         return err;
1766 }
1767
1768 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1769                                         u16 vid_begin, u16 vid_end)
1770 {
1771         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1772         struct mv88e6xxx_vtu_stu_entry vlan;
1773         int i, err;
1774
1775         if (!vid_begin)
1776                 return -EOPNOTSUPP;
1777
1778         mutex_lock(&chip->reg_lock);
1779
1780         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1781         if (err)
1782                 goto unlock;
1783
1784         do {
1785                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1786                 if (err)
1787                         goto unlock;
1788
1789                 if (!vlan.valid)
1790                         break;
1791
1792                 if (vlan.vid > vid_end)
1793                         break;
1794
1795                 for (i = 0; i < chip->info->num_ports; ++i) {
1796                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1797                                 continue;
1798
1799                         if (vlan.data[i] ==
1800                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1801                                 continue;
1802
1803                         if (chip->ports[i].bridge_dev ==
1804                             chip->ports[port].bridge_dev)
1805                                 break; /* same bridge, check next VLAN */
1806
1807                         netdev_warn(ds->ports[port].netdev,
1808                                     "hardware VLAN %d already used by %s\n",
1809                                     vlan.vid,
1810                                     netdev_name(chip->ports[i].bridge_dev));
1811                         err = -EOPNOTSUPP;
1812                         goto unlock;
1813                 }
1814         } while (vlan.vid < vid_end);
1815
1816 unlock:
1817         mutex_unlock(&chip->reg_lock);
1818
1819         return err;
1820 }
1821
1822 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1823         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1824         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1825         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1826         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1827 };
1828
1829 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1830                                          bool vlan_filtering)
1831 {
1832         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1833         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1834                 PORT_CONTROL_2_8021Q_DISABLED;
1835         int ret;
1836
1837         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1838                 return -EOPNOTSUPP;
1839
1840         mutex_lock(&chip->reg_lock);
1841
1842         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1843         if (ret < 0)
1844                 goto unlock;
1845
1846         old = ret & PORT_CONTROL_2_8021Q_MASK;
1847
1848         if (new != old) {
1849                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1850                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1851
1852                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1853                                            ret);
1854                 if (ret < 0)
1855                         goto unlock;
1856
1857                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1858                            mv88e6xxx_port_8021q_mode_names[new],
1859                            mv88e6xxx_port_8021q_mode_names[old]);
1860         }
1861
1862         ret = 0;
1863 unlock:
1864         mutex_unlock(&chip->reg_lock);
1865
1866         return ret;
1867 }
1868
1869 static int
1870 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1871                             const struct switchdev_obj_port_vlan *vlan,
1872                             struct switchdev_trans *trans)
1873 {
1874         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1875         int err;
1876
1877         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1878                 return -EOPNOTSUPP;
1879
1880         /* If the requested port doesn't belong to the same bridge as the VLAN
1881          * members, do not support it (yet) and fallback to software VLAN.
1882          */
1883         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1884                                            vlan->vid_end);
1885         if (err)
1886                 return err;
1887
1888         /* We don't need any dynamic resource from the kernel (yet),
1889          * so skip the prepare phase.
1890          */
1891         return 0;
1892 }
1893
1894 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1895                                     u16 vid, bool untagged)
1896 {
1897         struct mv88e6xxx_vtu_stu_entry vlan;
1898         int err;
1899
1900         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1901         if (err)
1902                 return err;
1903
1904         vlan.data[port] = untagged ?
1905                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1906                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1907
1908         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1909 }
1910
1911 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912                                     const struct switchdev_obj_port_vlan *vlan,
1913                                     struct switchdev_trans *trans)
1914 {
1915         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1916         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1918         u16 vid;
1919
1920         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1921                 return;
1922
1923         mutex_lock(&chip->reg_lock);
1924
1925         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1926                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1927                         netdev_err(ds->ports[port].netdev,
1928                                    "failed to add VLAN %d%c\n",
1929                                    vid, untagged ? 'u' : 't');
1930
1931         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1932                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1933                            vlan->vid_end);
1934
1935         mutex_unlock(&chip->reg_lock);
1936 }
1937
1938 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1939                                     int port, u16 vid)
1940 {
1941         struct dsa_switch *ds = chip->ds;
1942         struct mv88e6xxx_vtu_stu_entry vlan;
1943         int i, err;
1944
1945         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1946         if (err)
1947                 return err;
1948
1949         /* Tell switchdev if this VLAN is handled in software */
1950         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1951                 return -EOPNOTSUPP;
1952
1953         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1954
1955         /* keep the VLAN unless all ports are excluded */
1956         vlan.valid = false;
1957         for (i = 0; i < chip->info->num_ports; ++i) {
1958                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1959                         continue;
1960
1961                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1962                         vlan.valid = true;
1963                         break;
1964                 }
1965         }
1966
1967         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1968         if (err)
1969                 return err;
1970
1971         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1972 }
1973
1974 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1975                                    const struct switchdev_obj_port_vlan *vlan)
1976 {
1977         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1978         u16 pvid, vid;
1979         int err = 0;
1980
1981         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1982                 return -EOPNOTSUPP;
1983
1984         mutex_lock(&chip->reg_lock);
1985
1986         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1987         if (err)
1988                 goto unlock;
1989
1990         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1991                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1992                 if (err)
1993                         goto unlock;
1994
1995                 if (vid == pvid) {
1996                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
1997                         if (err)
1998                                 goto unlock;
1999                 }
2000         }
2001
2002 unlock:
2003         mutex_unlock(&chip->reg_lock);
2004
2005         return err;
2006 }
2007
2008 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2009                                     const unsigned char *addr)
2010 {
2011         int i, ret;
2012
2013         for (i = 0; i < 3; i++) {
2014                 ret = _mv88e6xxx_reg_write(
2015                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2016                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2017                 if (ret < 0)
2018                         return ret;
2019         }
2020
2021         return 0;
2022 }
2023
2024 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2025                                    unsigned char *addr)
2026 {
2027         int i, ret;
2028
2029         for (i = 0; i < 3; i++) {
2030                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2031                                           GLOBAL_ATU_MAC_01 + i);
2032                 if (ret < 0)
2033                         return ret;
2034                 addr[i * 2] = ret >> 8;
2035                 addr[i * 2 + 1] = ret & 0xff;
2036         }
2037
2038         return 0;
2039 }
2040
2041 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2042                                struct mv88e6xxx_atu_entry *entry)
2043 {
2044         int ret;
2045
2046         ret = _mv88e6xxx_atu_wait(chip);
2047         if (ret < 0)
2048                 return ret;
2049
2050         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2051         if (ret < 0)
2052                 return ret;
2053
2054         ret = _mv88e6xxx_atu_data_write(chip, entry);
2055         if (ret < 0)
2056                 return ret;
2057
2058         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2059 }
2060
2061 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2062                                     const unsigned char *addr, u16 vid,
2063                                     u8 state)
2064 {
2065         struct mv88e6xxx_atu_entry entry = { 0 };
2066         struct mv88e6xxx_vtu_stu_entry vlan;
2067         int err;
2068
2069         /* Null VLAN ID corresponds to the port private database */
2070         if (vid == 0)
2071                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2072         else
2073                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2074         if (err)
2075                 return err;
2076
2077         entry.fid = vlan.fid;
2078         entry.state = state;
2079         ether_addr_copy(entry.mac, addr);
2080         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2081                 entry.trunk = false;
2082                 entry.portv_trunkid = BIT(port);
2083         }
2084
2085         return _mv88e6xxx_atu_load(chip, &entry);
2086 }
2087
2088 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2089                                       const struct switchdev_obj_port_fdb *fdb,
2090                                       struct switchdev_trans *trans)
2091 {
2092         /* We don't need any dynamic resource from the kernel (yet),
2093          * so skip the prepare phase.
2094          */
2095         return 0;
2096 }
2097
2098 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2099                                    const struct switchdev_obj_port_fdb *fdb,
2100                                    struct switchdev_trans *trans)
2101 {
2102         int state = is_multicast_ether_addr(fdb->addr) ?
2103                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2104                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2105         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2106
2107         mutex_lock(&chip->reg_lock);
2108         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2109                 netdev_err(ds->ports[port].netdev,
2110                            "failed to load MAC address\n");
2111         mutex_unlock(&chip->reg_lock);
2112 }
2113
2114 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2115                                   const struct switchdev_obj_port_fdb *fdb)
2116 {
2117         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2118         int ret;
2119
2120         mutex_lock(&chip->reg_lock);
2121         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2122                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2123         mutex_unlock(&chip->reg_lock);
2124
2125         return ret;
2126 }
2127
2128 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2129                                   struct mv88e6xxx_atu_entry *entry)
2130 {
2131         struct mv88e6xxx_atu_entry next = { 0 };
2132         int ret;
2133
2134         next.fid = fid;
2135
2136         ret = _mv88e6xxx_atu_wait(chip);
2137         if (ret < 0)
2138                 return ret;
2139
2140         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2141         if (ret < 0)
2142                 return ret;
2143
2144         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2145         if (ret < 0)
2146                 return ret;
2147
2148         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2149         if (ret < 0)
2150                 return ret;
2151
2152         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2153         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2154                 unsigned int mask, shift;
2155
2156                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2157                         next.trunk = true;
2158                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2159                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2160                 } else {
2161                         next.trunk = false;
2162                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2163                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2164                 }
2165
2166                 next.portv_trunkid = (ret & mask) >> shift;
2167         }
2168
2169         *entry = next;
2170         return 0;
2171 }
2172
2173 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2174                                         u16 fid, u16 vid, int port,
2175                                         struct switchdev_obj_port_fdb *fdb,
2176                                         int (*cb)(struct switchdev_obj *obj))
2177 {
2178         struct mv88e6xxx_atu_entry addr = {
2179                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2180         };
2181         int err;
2182
2183         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2184         if (err)
2185                 return err;
2186
2187         do {
2188                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2189                 if (err)
2190                         break;
2191
2192                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2193                         break;
2194
2195                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2196                         bool is_static = addr.state ==
2197                                 (is_multicast_ether_addr(addr.mac) ?
2198                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2199                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2200
2201                         fdb->vid = vid;
2202                         ether_addr_copy(fdb->addr, addr.mac);
2203                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2204
2205                         err = cb(&fdb->obj);
2206                         if (err)
2207                                 break;
2208                 }
2209         } while (!is_broadcast_ether_addr(addr.mac));
2210
2211         return err;
2212 }
2213
2214 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2215                                    struct switchdev_obj_port_fdb *fdb,
2216                                    int (*cb)(struct switchdev_obj *obj))
2217 {
2218         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2219         struct mv88e6xxx_vtu_stu_entry vlan = {
2220                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2221         };
2222         u16 fid;
2223         int err;
2224
2225         mutex_lock(&chip->reg_lock);
2226
2227         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2228         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2229         if (err)
2230                 goto unlock;
2231
2232         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2233         if (err)
2234                 goto unlock;
2235
2236         /* Dump VLANs' Filtering Information Databases */
2237         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2238         if (err)
2239                 goto unlock;
2240
2241         do {
2242                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2243                 if (err)
2244                         break;
2245
2246                 if (!vlan.valid)
2247                         break;
2248
2249                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2250                                                    port, fdb, cb);
2251                 if (err)
2252                         break;
2253         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2254
2255 unlock:
2256         mutex_unlock(&chip->reg_lock);
2257
2258         return err;
2259 }
2260
2261 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2262                                       struct net_device *bridge)
2263 {
2264         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2265         int i, err = 0;
2266
2267         mutex_lock(&chip->reg_lock);
2268
2269         /* Assign the bridge and remap each port's VLANTable */
2270         chip->ports[port].bridge_dev = bridge;
2271
2272         for (i = 0; i < chip->info->num_ports; ++i) {
2273                 if (chip->ports[i].bridge_dev == bridge) {
2274                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2275                         if (err)
2276                                 break;
2277                 }
2278         }
2279
2280         mutex_unlock(&chip->reg_lock);
2281
2282         return err;
2283 }
2284
2285 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2286 {
2287         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2288         struct net_device *bridge = chip->ports[port].bridge_dev;
2289         int i;
2290
2291         mutex_lock(&chip->reg_lock);
2292
2293         /* Unassign the bridge and remap each port's VLANTable */
2294         chip->ports[port].bridge_dev = NULL;
2295
2296         for (i = 0; i < chip->info->num_ports; ++i)
2297                 if (i == port || chip->ports[i].bridge_dev == bridge)
2298                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2299                                 netdev_warn(ds->ports[i].netdev,
2300                                             "failed to remap\n");
2301
2302         mutex_unlock(&chip->reg_lock);
2303 }
2304
2305 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2306                                       int port, int page, int reg, int val)
2307 {
2308         int ret;
2309
2310         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2311         if (ret < 0)
2312                 goto restore_page_0;
2313
2314         ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2315 restore_page_0:
2316         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2317
2318         return ret;
2319 }
2320
2321 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2322                                      int port, int page, int reg)
2323 {
2324         int ret;
2325
2326         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2327         if (ret < 0)
2328                 goto restore_page_0;
2329
2330         ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2331 restore_page_0:
2332         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2333
2334         return ret;
2335 }
2336
2337 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2338 {
2339         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2340         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2341         struct gpio_desc *gpiod = chip->reset;
2342         unsigned long timeout;
2343         int ret;
2344         int i;
2345
2346         /* Set all ports to the disabled state. */
2347         for (i = 0; i < chip->info->num_ports; i++) {
2348                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2349                 if (ret < 0)
2350                         return ret;
2351
2352                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2353                                            ret & 0xfffc);
2354                 if (ret)
2355                         return ret;
2356         }
2357
2358         /* Wait for transmit queues to drain. */
2359         usleep_range(2000, 4000);
2360
2361         /* If there is a gpio connected to the reset pin, toggle it */
2362         if (gpiod) {
2363                 gpiod_set_value_cansleep(gpiod, 1);
2364                 usleep_range(10000, 20000);
2365                 gpiod_set_value_cansleep(gpiod, 0);
2366                 usleep_range(10000, 20000);
2367         }
2368
2369         /* Reset the switch. Keep the PPU active if requested. The PPU
2370          * needs to be active to support indirect phy register access
2371          * through global registers 0x18 and 0x19.
2372          */
2373         if (ppu_active)
2374                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2375         else
2376                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2377         if (ret)
2378                 return ret;
2379
2380         /* Wait up to one second for reset to complete. */
2381         timeout = jiffies + 1 * HZ;
2382         while (time_before(jiffies, timeout)) {
2383                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2384                 if (ret < 0)
2385                         return ret;
2386
2387                 if ((ret & is_reset) == is_reset)
2388                         break;
2389                 usleep_range(1000, 2000);
2390         }
2391         if (time_after(jiffies, timeout))
2392                 ret = -ETIMEDOUT;
2393         else
2394                 ret = 0;
2395
2396         return ret;
2397 }
2398
2399 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2400 {
2401         int ret;
2402
2403         ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2404                                         PAGE_FIBER_SERDES, MII_BMCR);
2405         if (ret < 0)
2406                 return ret;
2407
2408         if (ret & BMCR_PDOWN) {
2409                 ret &= ~BMCR_PDOWN;
2410                 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2411                                                  PAGE_FIBER_SERDES, MII_BMCR,
2412                                                  ret);
2413         }
2414
2415         return ret;
2416 }
2417
2418 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2419                                int reg, u16 *val)
2420 {
2421         int addr = chip->info->port_base_addr + port;
2422
2423         if (port >= chip->info->num_ports)
2424                 return -EINVAL;
2425
2426         return mv88e6xxx_read(chip, addr, reg, val);
2427 }
2428
2429 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2430 {
2431         struct dsa_switch *ds = chip->ds;
2432         int ret;
2433         u16 reg;
2434
2435         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2436             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2437             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2438             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2439                 /* MAC Forcing register: don't force link, speed,
2440                  * duplex or flow control state to any particular
2441                  * values on physical ports, but force the CPU port
2442                  * and all DSA ports to their maximum bandwidth and
2443                  * full duplex.
2444                  */
2445                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2446                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2447                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2448                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2449                                 PORT_PCS_CTRL_LINK_UP |
2450                                 PORT_PCS_CTRL_DUPLEX_FULL |
2451                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2452                         if (mv88e6xxx_6065_family(chip))
2453                                 reg |= PORT_PCS_CTRL_100;
2454                         else
2455                                 reg |= PORT_PCS_CTRL_1000;
2456                 } else {
2457                         reg |= PORT_PCS_CTRL_UNFORCED;
2458                 }
2459
2460                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2461                                            PORT_PCS_CTRL, reg);
2462                 if (ret)
2463                         return ret;
2464         }
2465
2466         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2467          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2468          * tunneling, determine priority by looking at 802.1p and IP
2469          * priority fields (IP prio has precedence), and set STP state
2470          * to Forwarding.
2471          *
2472          * If this is the CPU link, use DSA or EDSA tagging depending
2473          * on which tagging mode was configured.
2474          *
2475          * If this is a link to another switch, use DSA tagging mode.
2476          *
2477          * If this is the upstream port for this switch, enable
2478          * forwarding of unknown unicasts and multicasts.
2479          */
2480         reg = 0;
2481         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2482             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2483             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2484             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2485                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2486                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2487                 PORT_CONTROL_STATE_FORWARDING;
2488         if (dsa_is_cpu_port(ds, port)) {
2489                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2490                         reg |= PORT_CONTROL_DSA_TAG;
2491                 if (mv88e6xxx_6352_family(chip) ||
2492                     mv88e6xxx_6351_family(chip) ||
2493                     mv88e6xxx_6165_family(chip) ||
2494                     mv88e6xxx_6097_family(chip) ||
2495                     mv88e6xxx_6320_family(chip)) {
2496                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2497                                 PORT_CONTROL_FORWARD_UNKNOWN |
2498                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2499                 }
2500
2501                 if (mv88e6xxx_6352_family(chip) ||
2502                     mv88e6xxx_6351_family(chip) ||
2503                     mv88e6xxx_6165_family(chip) ||
2504                     mv88e6xxx_6097_family(chip) ||
2505                     mv88e6xxx_6095_family(chip) ||
2506                     mv88e6xxx_6065_family(chip) ||
2507                     mv88e6xxx_6185_family(chip) ||
2508                     mv88e6xxx_6320_family(chip)) {
2509                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2510                 }
2511         }
2512         if (dsa_is_dsa_port(ds, port)) {
2513                 if (mv88e6xxx_6095_family(chip) ||
2514                     mv88e6xxx_6185_family(chip))
2515                         reg |= PORT_CONTROL_DSA_TAG;
2516                 if (mv88e6xxx_6352_family(chip) ||
2517                     mv88e6xxx_6351_family(chip) ||
2518                     mv88e6xxx_6165_family(chip) ||
2519                     mv88e6xxx_6097_family(chip) ||
2520                     mv88e6xxx_6320_family(chip)) {
2521                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2522                 }
2523
2524                 if (port == dsa_upstream_port(ds))
2525                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2526                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2527         }
2528         if (reg) {
2529                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2530                                            PORT_CONTROL, reg);
2531                 if (ret)
2532                         return ret;
2533         }
2534
2535         /* If this port is connected to a SerDes, make sure the SerDes is not
2536          * powered down.
2537          */
2538         if (mv88e6xxx_6352_family(chip)) {
2539                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2540                 if (ret < 0)
2541                         return ret;
2542                 ret &= PORT_STATUS_CMODE_MASK;
2543                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2544                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2545                     (ret == PORT_STATUS_CMODE_SGMII)) {
2546                         ret = mv88e6xxx_power_on_serdes(chip);
2547                         if (ret < 0)
2548                                 return ret;
2549                 }
2550         }
2551
2552         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2553          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2554          * untagged frames on this port, do a destination address lookup on all
2555          * received packets as usual, disable ARP mirroring and don't send a
2556          * copy of all transmitted/received frames on this port to the CPU.
2557          */
2558         reg = 0;
2559         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2560             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2561             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2562             mv88e6xxx_6185_family(chip))
2563                 reg = PORT_CONTROL_2_MAP_DA;
2564
2565         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2566             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2567                 reg |= PORT_CONTROL_2_JUMBO_10240;
2568
2569         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2570                 /* Set the upstream port this port should use */
2571                 reg |= dsa_upstream_port(ds);
2572                 /* enable forwarding of unknown multicast addresses to
2573                  * the upstream port
2574                  */
2575                 if (port == dsa_upstream_port(ds))
2576                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2577         }
2578
2579         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2580
2581         if (reg) {
2582                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2583                                            PORT_CONTROL_2, reg);
2584                 if (ret)
2585                         return ret;
2586         }
2587
2588         /* Port Association Vector: when learning source addresses
2589          * of packets, add the address to the address database using
2590          * a port bitmap that has only the bit for this port set and
2591          * the other bits clear.
2592          */
2593         reg = 1 << port;
2594         /* Disable learning for CPU port */
2595         if (dsa_is_cpu_port(ds, port))
2596                 reg = 0;
2597
2598         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2599                                    reg);
2600         if (ret)
2601                 return ret;
2602
2603         /* Egress rate control 2: disable egress rate control. */
2604         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2605                                    0x0000);
2606         if (ret)
2607                 return ret;
2608
2609         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2610             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2611             mv88e6xxx_6320_family(chip)) {
2612                 /* Do not limit the period of time that this port can
2613                  * be paused for by the remote end or the period of
2614                  * time that this port can pause the remote end.
2615                  */
2616                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2617                                            PORT_PAUSE_CTRL, 0x0000);
2618                 if (ret)
2619                         return ret;
2620
2621                 /* Port ATU control: disable limiting the number of
2622                  * address database entries that this port is allowed
2623                  * to use.
2624                  */
2625                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2626                                            PORT_ATU_CONTROL, 0x0000);
2627                 /* Priority Override: disable DA, SA and VTU priority
2628                  * override.
2629                  */
2630                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2631                                            PORT_PRI_OVERRIDE, 0x0000);
2632                 if (ret)
2633                         return ret;
2634
2635                 /* Port Ethertype: use the Ethertype DSA Ethertype
2636                  * value.
2637                  */
2638                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2639                                            PORT_ETH_TYPE, ETH_P_EDSA);
2640                 if (ret)
2641                         return ret;
2642                 /* Tag Remap: use an identity 802.1p prio -> switch
2643                  * prio mapping.
2644                  */
2645                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2646                                            PORT_TAG_REGMAP_0123, 0x3210);
2647                 if (ret)
2648                         return ret;
2649
2650                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2651                  * prio mapping.
2652                  */
2653                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2654                                            PORT_TAG_REGMAP_4567, 0x7654);
2655                 if (ret)
2656                         return ret;
2657         }
2658
2659         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2660             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2661             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2662             mv88e6xxx_6320_family(chip)) {
2663                 /* Rate Control: disable ingress rate limiting. */
2664                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2665                                            PORT_RATE_CONTROL, 0x0001);
2666                 if (ret)
2667                         return ret;
2668         }
2669
2670         /* Port Control 1: disable trunking, disable sending
2671          * learning messages to this port.
2672          */
2673         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2674                                    0x0000);
2675         if (ret)
2676                 return ret;
2677
2678         /* Port based VLAN map: give each port the same default address
2679          * database, and allow bidirectional communication between the
2680          * CPU and DSA port(s), and the other ports.
2681          */
2682         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2683         if (ret)
2684                 return ret;
2685
2686         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2687         if (ret)
2688                 return ret;
2689
2690         /* Default VLAN ID and priority: don't set a default VLAN
2691          * ID, and set the default packet priority to zero.
2692          */
2693         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2694                                    0x0000);
2695         if (ret)
2696                 return ret;
2697
2698         return 0;
2699 }
2700
2701 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2702 {
2703         int err;
2704
2705         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2706                               (addr[0] << 8) | addr[1]);
2707         if (err)
2708                 return err;
2709
2710         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2711                               (addr[2] << 8) | addr[3]);
2712         if (err)
2713                 return err;
2714
2715         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2716                                (addr[4] << 8) | addr[5]);
2717 }
2718
2719 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2720                                      unsigned int msecs)
2721 {
2722         const unsigned int coeff = chip->info->age_time_coeff;
2723         const unsigned int min = 0x01 * coeff;
2724         const unsigned int max = 0xff * coeff;
2725         u8 age_time;
2726         u16 val;
2727         int err;
2728
2729         if (msecs < min || msecs > max)
2730                 return -ERANGE;
2731
2732         /* Round to nearest multiple of coeff */
2733         age_time = (msecs + coeff / 2) / coeff;
2734
2735         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2736         if (err)
2737                 return err;
2738
2739         /* AgeTime is 11:4 bits */
2740         val &= ~0xff0;
2741         val |= age_time << 4;
2742
2743         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2744 }
2745
2746 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2747                                      unsigned int ageing_time)
2748 {
2749         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2750         int err;
2751
2752         mutex_lock(&chip->reg_lock);
2753         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2754         mutex_unlock(&chip->reg_lock);
2755
2756         return err;
2757 }
2758
2759 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2760 {
2761         struct dsa_switch *ds = chip->ds;
2762         u32 upstream_port = dsa_upstream_port(ds);
2763         u16 reg;
2764         int err;
2765
2766         /* Enable the PHY Polling Unit if present, don't discard any packets,
2767          * and mask all interrupt sources.
2768          */
2769         reg = 0;
2770         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2771             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2772                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2773
2774         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2775         if (err)
2776                 return err;
2777
2778         /* Configure the upstream port, and configure it as the port to which
2779          * ingress and egress and ARP monitor frames are to be sent.
2780          */
2781         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2782                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2783                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2784         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2785                                    reg);
2786         if (err)
2787                 return err;
2788
2789         /* Disable remote management, and set the switch's DSA device number. */
2790         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2791                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2792                                    (ds->index & 0x1f));
2793         if (err)
2794                 return err;
2795
2796         /* Clear all the VTU and STU entries */
2797         err = _mv88e6xxx_vtu_stu_flush(chip);
2798         if (err < 0)
2799                 return err;
2800
2801         /* Set the default address aging time to 5 minutes, and
2802          * enable address learn messages to be sent to all message
2803          * ports.
2804          */
2805         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2806                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2807         if (err)
2808                 return err;
2809
2810         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2811         if (err)
2812                 return err;
2813
2814         /* Clear all ATU entries */
2815         err = _mv88e6xxx_atu_flush(chip, 0, true);
2816         if (err)
2817                 return err;
2818
2819         /* Configure the IP ToS mapping registers. */
2820         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2821         if (err)
2822                 return err;
2823         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2824         if (err)
2825                 return err;
2826         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2827         if (err)
2828                 return err;
2829         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2830         if (err)
2831                 return err;
2832         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2833         if (err)
2834                 return err;
2835         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2836         if (err)
2837                 return err;
2838         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2839         if (err)
2840                 return err;
2841         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2842         if (err)
2843                 return err;
2844
2845         /* Configure the IEEE 802.1p priority mapping register. */
2846         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2847         if (err)
2848                 return err;
2849
2850         /* Clear the statistics counters for all ports */
2851         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2852                                    GLOBAL_STATS_OP_FLUSH_ALL);
2853         if (err)
2854                 return err;
2855
2856         /* Wait for the flush to complete. */
2857         err = _mv88e6xxx_stats_wait(chip);
2858         if (err)
2859                 return err;
2860
2861         return 0;
2862 }
2863
2864 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2865                                              int target, int port)
2866 {
2867         u16 val = (target << 8) | (port & 0xf);
2868
2869         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2870 }
2871
2872 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2873 {
2874         int target, port;
2875         int err;
2876
2877         /* Initialize the routing port to the 32 possible target devices */
2878         for (target = 0; target < 32; ++target) {
2879                 port = 0xf;
2880
2881                 if (target < DSA_MAX_SWITCHES) {
2882                         port = chip->ds->rtable[target];
2883                         if (port == DSA_RTABLE_NONE)
2884                                 port = 0xf;
2885                 }
2886
2887                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2888                 if (err)
2889                         break;
2890         }
2891
2892         return err;
2893 }
2894
2895 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2896                                          bool hask, u16 mask)
2897 {
2898         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2899         u16 val = (num << 12) | (mask & port_mask);
2900
2901         if (hask)
2902                 val |= GLOBAL2_TRUNK_MASK_HASK;
2903
2904         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2905 }
2906
2907 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2908                                             u16 map)
2909 {
2910         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2911         u16 val = (id << 11) | (map & port_mask);
2912
2913         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2914 }
2915
2916 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2917 {
2918         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2919         int i, err;
2920
2921         /* Clear all eight possible Trunk Mask vectors */
2922         for (i = 0; i < 8; ++i) {
2923                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2924                 if (err)
2925                         return err;
2926         }
2927
2928         /* Clear all sixteen possible Trunk ID routing vectors */
2929         for (i = 0; i < 16; ++i) {
2930                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2931                 if (err)
2932                         return err;
2933         }
2934
2935         return 0;
2936 }
2937
2938 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2939 {
2940         int port, err;
2941
2942         /* Init all Ingress Rate Limit resources of all ports */
2943         for (port = 0; port < chip->info->num_ports; ++port) {
2944                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2945                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2946                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2947                                       (port << 8));
2948                 if (err)
2949                         break;
2950
2951                 /* Wait for the operation to complete */
2952                 err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2953                                       GLOBAL2_IRL_CMD_BUSY);
2954                 if (err)
2955                         break;
2956         }
2957
2958         return err;
2959 }
2960
2961 /* Indirect write to the Switch MAC/WoL/WoF register */
2962 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2963                                          unsigned int pointer, u8 data)
2964 {
2965         u16 val = (pointer << 8) | data;
2966
2967         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2968 }
2969
2970 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2971 {
2972         int i, err;
2973
2974         for (i = 0; i < 6; i++) {
2975                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2976                 if (err)
2977                         break;
2978         }
2979
2980         return err;
2981 }
2982
2983 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2984                                   u8 data)
2985 {
2986         u16 val = (pointer << 8) | (data & 0x7);
2987
2988         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2989 }
2990
2991 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2992 {
2993         int i, err;
2994
2995         /* Clear all sixteen possible Priority Override entries */
2996         for (i = 0; i < 16; i++) {
2997                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2998                 if (err)
2999                         break;
3000         }
3001
3002         return err;
3003 }
3004
3005 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3006 {
3007         return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3008                                GLOBAL2_EEPROM_CMD_BUSY |
3009                                GLOBAL2_EEPROM_CMD_RUNNING);
3010 }
3011
3012 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3013 {
3014         int err;
3015
3016         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3017         if (err)
3018                 return err;
3019
3020         return mv88e6xxx_g2_eeprom_wait(chip);
3021 }
3022
3023 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3024                                       u8 addr, u16 *data)
3025 {
3026         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3027         int err;
3028
3029         err = mv88e6xxx_g2_eeprom_wait(chip);
3030         if (err)
3031                 return err;
3032
3033         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3034         if (err)
3035                 return err;
3036
3037         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3038 }
3039
3040 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3041                                        u8 addr, u16 data)
3042 {
3043         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3044         int err;
3045
3046         err = mv88e6xxx_g2_eeprom_wait(chip);
3047         if (err)
3048                 return err;
3049
3050         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3051         if (err)
3052                 return err;
3053
3054         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3055 }
3056
3057 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3058 {
3059         u16 reg;
3060         int err;
3061
3062         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3063                 /* Consider the frames with reserved multicast destination
3064                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3065                  */
3066                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3067                                       0xffff);
3068                 if (err)
3069                         return err;
3070         }
3071
3072         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3073                 /* Consider the frames with reserved multicast destination
3074                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3075                  */
3076                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3077                                       0xffff);
3078                 if (err)
3079                         return err;
3080         }
3081
3082         /* Ignore removed tag data on doubly tagged packets, disable
3083          * flow control messages, force flow control priority to the
3084          * highest, and send all special multicast frames to the CPU
3085          * port at the highest priority.
3086          */
3087         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3088         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3089             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3090                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3091         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3092         if (err)
3093                 return err;
3094
3095         /* Program the DSA routing table. */
3096         err = mv88e6xxx_g2_set_device_mapping(chip);
3097         if (err)
3098                 return err;
3099
3100         /* Clear all trunk masks and mapping. */
3101         err = mv88e6xxx_g2_clear_trunk(chip);
3102         if (err)
3103                 return err;
3104
3105         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3106                 /* Disable ingress rate limiting by resetting all per port
3107                  * ingress rate limit resources to their initial state.
3108                  */
3109                 err = mv88e6xxx_g2_clear_irl(chip);
3110                         if (err)
3111                                 return err;
3112         }
3113
3114         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3115                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3116                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3117                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3118                 if (err)
3119                         return err;
3120         }
3121
3122         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3123                 /* Clear the priority override table. */
3124                 err = mv88e6xxx_g2_clear_pot(chip);
3125                 if (err)
3126                         return err;
3127         }
3128
3129         return 0;
3130 }
3131
3132 static int mv88e6xxx_setup(struct dsa_switch *ds)
3133 {
3134         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3135         int err;
3136         int i;
3137
3138         chip->ds = ds;
3139         ds->slave_mii_bus = chip->mdio_bus;
3140
3141         mutex_lock(&chip->reg_lock);
3142
3143         err = mv88e6xxx_switch_reset(chip);
3144         if (err)
3145                 goto unlock;
3146
3147         /* Setup Switch Port Registers */
3148         for (i = 0; i < chip->info->num_ports; i++) {
3149                 err = mv88e6xxx_setup_port(chip, i);
3150                 if (err)
3151                         goto unlock;
3152         }
3153
3154         /* Setup Switch Global 1 Registers */
3155         err = mv88e6xxx_g1_setup(chip);
3156         if (err)
3157                 goto unlock;
3158
3159         /* Setup Switch Global 2 Registers */
3160         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3161                 err = mv88e6xxx_g2_setup(chip);
3162                 if (err)
3163                         goto unlock;
3164         }
3165
3166 unlock:
3167         mutex_unlock(&chip->reg_lock);
3168
3169         return err;
3170 }
3171
3172 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3173 {
3174         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3175         int err;
3176
3177         mutex_lock(&chip->reg_lock);
3178
3179         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3180         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3181                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3182         else
3183                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3184
3185         mutex_unlock(&chip->reg_lock);
3186
3187         return err;
3188 }
3189
3190 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3191                                     int reg)
3192 {
3193         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3194         int ret;
3195
3196         mutex_lock(&chip->reg_lock);
3197         ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3198         mutex_unlock(&chip->reg_lock);
3199
3200         return ret;
3201 }
3202
3203 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3204                                      int reg, int val)
3205 {
3206         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3207         int ret;
3208
3209         mutex_lock(&chip->reg_lock);
3210         ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3211         mutex_unlock(&chip->reg_lock);
3212
3213         return ret;
3214 }
3215
3216 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3217 {
3218         if (port >= 0 && port < chip->info->num_ports)
3219                 return port;
3220         return -EINVAL;
3221 }
3222
3223 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3224 {
3225         struct mv88e6xxx_chip *chip = bus->priv;
3226         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3227         int ret;
3228
3229         if (addr < 0)
3230                 return 0xffff;
3231
3232         mutex_lock(&chip->reg_lock);
3233
3234         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3235                 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3236         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3237                 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3238         else
3239                 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3240
3241         mutex_unlock(&chip->reg_lock);
3242         return ret;
3243 }
3244
3245 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3246                                 u16 val)
3247 {
3248         struct mv88e6xxx_chip *chip = bus->priv;
3249         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3250         int ret;
3251
3252         if (addr < 0)
3253                 return 0xffff;
3254
3255         mutex_lock(&chip->reg_lock);
3256
3257         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3258                 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3259         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3260                 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3261         else
3262                 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3263
3264         mutex_unlock(&chip->reg_lock);
3265         return ret;
3266 }
3267
3268 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3269                                    struct device_node *np)
3270 {
3271         static int index;
3272         struct mii_bus *bus;
3273         int err;
3274
3275         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3276                 mv88e6xxx_ppu_state_init(chip);
3277
3278         if (np)
3279                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3280
3281         bus = devm_mdiobus_alloc(chip->dev);
3282         if (!bus)
3283                 return -ENOMEM;
3284
3285         bus->priv = (void *)chip;
3286         if (np) {
3287                 bus->name = np->full_name;
3288                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3289         } else {
3290                 bus->name = "mv88e6xxx SMI";
3291                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3292         }
3293
3294         bus->read = mv88e6xxx_mdio_read;
3295         bus->write = mv88e6xxx_mdio_write;
3296         bus->parent = chip->dev;
3297
3298         if (chip->mdio_np)
3299                 err = of_mdiobus_register(bus, chip->mdio_np);
3300         else
3301                 err = mdiobus_register(bus);
3302         if (err) {
3303                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3304                 goto out;
3305         }
3306         chip->mdio_bus = bus;
3307
3308         return 0;
3309
3310 out:
3311         if (chip->mdio_np)
3312                 of_node_put(chip->mdio_np);
3313
3314         return err;
3315 }
3316
3317 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3318
3319 {
3320         struct mii_bus *bus = chip->mdio_bus;
3321
3322         mdiobus_unregister(bus);
3323
3324         if (chip->mdio_np)
3325                 of_node_put(chip->mdio_np);
3326 }
3327
3328 #ifdef CONFIG_NET_DSA_HWMON
3329
3330 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3331 {
3332         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3333         int ret;
3334         int val;
3335
3336         *temp = 0;
3337
3338         mutex_lock(&chip->reg_lock);
3339
3340         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3341         if (ret < 0)
3342                 goto error;
3343
3344         /* Enable temperature sensor */
3345         ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3346         if (ret < 0)
3347                 goto error;
3348
3349         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3350         if (ret < 0)
3351                 goto error;
3352
3353         /* Wait for temperature to stabilize */
3354         usleep_range(10000, 12000);
3355
3356         val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3357         if (val < 0) {
3358                 ret = val;
3359                 goto error;
3360         }
3361
3362         /* Disable temperature sensor */
3363         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3364         if (ret < 0)
3365                 goto error;
3366
3367         *temp = ((val & 0x1f) - 5) * 5;
3368
3369 error:
3370         mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3371         mutex_unlock(&chip->reg_lock);
3372         return ret;
3373 }
3374
3375 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3376 {
3377         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3378         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3379         int ret;
3380
3381         *temp = 0;
3382
3383         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3384         if (ret < 0)
3385                 return ret;
3386
3387         *temp = (ret & 0xff) - 25;
3388
3389         return 0;
3390 }
3391
3392 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3393 {
3394         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3395
3396         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3397                 return -EOPNOTSUPP;
3398
3399         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3400                 return mv88e63xx_get_temp(ds, temp);
3401
3402         return mv88e61xx_get_temp(ds, temp);
3403 }
3404
3405 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3406 {
3407         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3408         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3409         int ret;
3410
3411         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3412                 return -EOPNOTSUPP;
3413
3414         *temp = 0;
3415
3416         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3417         if (ret < 0)
3418                 return ret;
3419
3420         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3421
3422         return 0;
3423 }
3424
3425 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3426 {
3427         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3428         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3429         int ret;
3430
3431         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3432                 return -EOPNOTSUPP;
3433
3434         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3435         if (ret < 0)
3436                 return ret;
3437         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3438         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3439                                          (ret & 0xe0ff) | (temp << 8));
3440 }
3441
3442 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3443 {
3444         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3445         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3446         int ret;
3447
3448         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3449                 return -EOPNOTSUPP;
3450
3451         *alarm = false;
3452
3453         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3454         if (ret < 0)
3455                 return ret;
3456
3457         *alarm = !!(ret & 0x40);
3458
3459         return 0;
3460 }
3461 #endif /* CONFIG_NET_DSA_HWMON */
3462
3463 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3464 {
3465         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3466
3467         return chip->eeprom_len;
3468 }
3469
3470 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3471                                   struct ethtool_eeprom *eeprom, u8 *data)
3472 {
3473         unsigned int offset = eeprom->offset;
3474         unsigned int len = eeprom->len;
3475         u16 val;
3476         int err;
3477
3478         eeprom->len = 0;
3479
3480         if (offset & 1) {
3481                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3482                 if (err)
3483                         return err;
3484
3485                 *data++ = (val >> 8) & 0xff;
3486
3487                 offset++;
3488                 len--;
3489                 eeprom->len++;
3490         }
3491
3492         while (len >= 2) {
3493                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3494                 if (err)
3495                         return err;
3496
3497                 *data++ = val & 0xff;
3498                 *data++ = (val >> 8) & 0xff;
3499
3500                 offset += 2;
3501                 len -= 2;
3502                 eeprom->len += 2;
3503         }
3504
3505         if (len) {
3506                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3507                 if (err)
3508                         return err;
3509
3510                 *data++ = val & 0xff;
3511
3512                 offset++;
3513                 len--;
3514                 eeprom->len++;
3515         }
3516
3517         return 0;
3518 }
3519
3520 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3521                                 struct ethtool_eeprom *eeprom, u8 *data)
3522 {
3523         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3524         int err;
3525
3526         mutex_lock(&chip->reg_lock);
3527
3528         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3529                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3530         else
3531                 err = -EOPNOTSUPP;
3532
3533         mutex_unlock(&chip->reg_lock);
3534
3535         if (err)
3536                 return err;
3537
3538         eeprom->magic = 0xc3ec4951;
3539
3540         return 0;
3541 }
3542
3543 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3544                                   struct ethtool_eeprom *eeprom, u8 *data)
3545 {
3546         unsigned int offset = eeprom->offset;
3547         unsigned int len = eeprom->len;
3548         u16 val;
3549         int err;
3550
3551         /* Ensure the RO WriteEn bit is set */
3552         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3553         if (err)
3554                 return err;
3555
3556         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3557                 return -EROFS;
3558
3559         eeprom->len = 0;
3560
3561         if (offset & 1) {
3562                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3563                 if (err)
3564                         return err;
3565
3566                 val = (*data++ << 8) | (val & 0xff);
3567
3568                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3569                 if (err)
3570                         return err;
3571
3572                 offset++;
3573                 len--;
3574                 eeprom->len++;
3575         }
3576
3577         while (len >= 2) {
3578                 val = *data++;
3579                 val |= *data++ << 8;
3580
3581                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3582                 if (err)
3583                         return err;
3584
3585                 offset += 2;
3586                 len -= 2;
3587                 eeprom->len += 2;
3588         }
3589
3590         if (len) {
3591                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3592                 if (err)
3593                         return err;
3594
3595                 val = (val & 0xff00) | *data++;
3596
3597                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3598                 if (err)
3599                         return err;
3600
3601                 offset++;
3602                 len--;
3603                 eeprom->len++;
3604         }
3605
3606         return 0;
3607 }
3608
3609 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3610                                 struct ethtool_eeprom *eeprom, u8 *data)
3611 {
3612         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3613         int err;
3614
3615         if (eeprom->magic != 0xc3ec4951)
3616                 return -EINVAL;
3617
3618         mutex_lock(&chip->reg_lock);
3619
3620         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3621                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3622         else
3623                 err = -EOPNOTSUPP;
3624
3625         mutex_unlock(&chip->reg_lock);
3626
3627         return err;
3628 }
3629
3630 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3631         [MV88E6085] = {
3632                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3633                 .family = MV88E6XXX_FAMILY_6097,
3634                 .name = "Marvell 88E6085",
3635                 .num_databases = 4096,
3636                 .num_ports = 10,
3637                 .port_base_addr = 0x10,
3638                 .age_time_coeff = 15000,
3639                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3640         },
3641
3642         [MV88E6095] = {
3643                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3644                 .family = MV88E6XXX_FAMILY_6095,
3645                 .name = "Marvell 88E6095/88E6095F",
3646                 .num_databases = 256,
3647                 .num_ports = 11,
3648                 .port_base_addr = 0x10,
3649                 .age_time_coeff = 15000,
3650                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3651         },
3652
3653         [MV88E6123] = {
3654                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3655                 .family = MV88E6XXX_FAMILY_6165,
3656                 .name = "Marvell 88E6123",
3657                 .num_databases = 4096,
3658                 .num_ports = 3,
3659                 .port_base_addr = 0x10,
3660                 .age_time_coeff = 15000,
3661                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3662         },
3663
3664         [MV88E6131] = {
3665                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3666                 .family = MV88E6XXX_FAMILY_6185,
3667                 .name = "Marvell 88E6131",
3668                 .num_databases = 256,
3669                 .num_ports = 8,
3670                 .port_base_addr = 0x10,
3671                 .age_time_coeff = 15000,
3672                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3673         },
3674
3675         [MV88E6161] = {
3676                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3677                 .family = MV88E6XXX_FAMILY_6165,
3678                 .name = "Marvell 88E6161",
3679                 .num_databases = 4096,
3680                 .num_ports = 6,
3681                 .port_base_addr = 0x10,
3682                 .age_time_coeff = 15000,
3683                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3684         },
3685
3686         [MV88E6165] = {
3687                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3688                 .family = MV88E6XXX_FAMILY_6165,
3689                 .name = "Marvell 88E6165",
3690                 .num_databases = 4096,
3691                 .num_ports = 6,
3692                 .port_base_addr = 0x10,
3693                 .age_time_coeff = 15000,
3694                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3695         },
3696
3697         [MV88E6171] = {
3698                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3699                 .family = MV88E6XXX_FAMILY_6351,
3700                 .name = "Marvell 88E6171",
3701                 .num_databases = 4096,
3702                 .num_ports = 7,
3703                 .port_base_addr = 0x10,
3704                 .age_time_coeff = 15000,
3705                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3706         },
3707
3708         [MV88E6172] = {
3709                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3710                 .family = MV88E6XXX_FAMILY_6352,
3711                 .name = "Marvell 88E6172",
3712                 .num_databases = 4096,
3713                 .num_ports = 7,
3714                 .port_base_addr = 0x10,
3715                 .age_time_coeff = 15000,
3716                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3717         },
3718
3719         [MV88E6175] = {
3720                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3721                 .family = MV88E6XXX_FAMILY_6351,
3722                 .name = "Marvell 88E6175",
3723                 .num_databases = 4096,
3724                 .num_ports = 7,
3725                 .port_base_addr = 0x10,
3726                 .age_time_coeff = 15000,
3727                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3728         },
3729
3730         [MV88E6176] = {
3731                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3732                 .family = MV88E6XXX_FAMILY_6352,
3733                 .name = "Marvell 88E6176",
3734                 .num_databases = 4096,
3735                 .num_ports = 7,
3736                 .port_base_addr = 0x10,
3737                 .age_time_coeff = 15000,
3738                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3739         },
3740
3741         [MV88E6185] = {
3742                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3743                 .family = MV88E6XXX_FAMILY_6185,
3744                 .name = "Marvell 88E6185",
3745                 .num_databases = 256,
3746                 .num_ports = 10,
3747                 .port_base_addr = 0x10,
3748                 .age_time_coeff = 15000,
3749                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3750         },
3751
3752         [MV88E6240] = {
3753                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3754                 .family = MV88E6XXX_FAMILY_6352,
3755                 .name = "Marvell 88E6240",
3756                 .num_databases = 4096,
3757                 .num_ports = 7,
3758                 .port_base_addr = 0x10,
3759                 .age_time_coeff = 15000,
3760                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3761         },
3762
3763         [MV88E6320] = {
3764                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3765                 .family = MV88E6XXX_FAMILY_6320,
3766                 .name = "Marvell 88E6320",
3767                 .num_databases = 4096,
3768                 .num_ports = 7,
3769                 .port_base_addr = 0x10,
3770                 .age_time_coeff = 15000,
3771                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3772         },
3773
3774         [MV88E6321] = {
3775                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3776                 .family = MV88E6XXX_FAMILY_6320,
3777                 .name = "Marvell 88E6321",
3778                 .num_databases = 4096,
3779                 .num_ports = 7,
3780                 .port_base_addr = 0x10,
3781                 .age_time_coeff = 15000,
3782                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3783         },
3784
3785         [MV88E6350] = {
3786                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3787                 .family = MV88E6XXX_FAMILY_6351,
3788                 .name = "Marvell 88E6350",
3789                 .num_databases = 4096,
3790                 .num_ports = 7,
3791                 .port_base_addr = 0x10,
3792                 .age_time_coeff = 15000,
3793                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3794         },
3795
3796         [MV88E6351] = {
3797                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3798                 .family = MV88E6XXX_FAMILY_6351,
3799                 .name = "Marvell 88E6351",
3800                 .num_databases = 4096,
3801                 .num_ports = 7,
3802                 .port_base_addr = 0x10,
3803                 .age_time_coeff = 15000,
3804                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3805         },
3806
3807         [MV88E6352] = {
3808                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3809                 .family = MV88E6XXX_FAMILY_6352,
3810                 .name = "Marvell 88E6352",
3811                 .num_databases = 4096,
3812                 .num_ports = 7,
3813                 .port_base_addr = 0x10,
3814                 .age_time_coeff = 15000,
3815                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3816         },
3817 };
3818
3819 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3820 {
3821         int i;
3822
3823         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3824                 if (mv88e6xxx_table[i].prod_num == prod_num)
3825                         return &mv88e6xxx_table[i];
3826
3827         return NULL;
3828 }
3829
3830 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3831 {
3832         const struct mv88e6xxx_info *info;
3833         unsigned int prod_num, rev;
3834         u16 id;
3835         int err;
3836
3837         mutex_lock(&chip->reg_lock);
3838         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3839         mutex_unlock(&chip->reg_lock);
3840         if (err)
3841                 return err;
3842
3843         prod_num = (id & 0xfff0) >> 4;
3844         rev = id & 0x000f;
3845
3846         info = mv88e6xxx_lookup_info(prod_num);
3847         if (!info)
3848                 return -ENODEV;
3849
3850         /* Update the compatible info with the probed one */
3851         chip->info = info;
3852
3853         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3854                  chip->info->prod_num, chip->info->name, rev);
3855
3856         return 0;
3857 }
3858
3859 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3860 {
3861         struct mv88e6xxx_chip *chip;
3862
3863         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3864         if (!chip)
3865                 return NULL;
3866
3867         chip->dev = dev;
3868
3869         mutex_init(&chip->reg_lock);
3870
3871         return chip;
3872 }
3873
3874 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3875                               struct mii_bus *bus, int sw_addr)
3876 {
3877         /* ADDR[0] pin is unavailable externally and considered zero */
3878         if (sw_addr & 0x1)
3879                 return -EINVAL;
3880
3881         if (sw_addr == 0)
3882                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3883         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3884                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3885         else
3886                 return -EINVAL;
3887
3888         chip->bus = bus;
3889         chip->sw_addr = sw_addr;
3890
3891         return 0;
3892 }
3893
3894 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3895                                        struct device *host_dev, int sw_addr,
3896                                        void **priv)
3897 {
3898         struct mv88e6xxx_chip *chip;
3899         struct mii_bus *bus;
3900         int err;
3901
3902         bus = dsa_host_dev_to_mii_bus(host_dev);
3903         if (!bus)
3904                 return NULL;
3905
3906         chip = mv88e6xxx_alloc_chip(dsa_dev);
3907         if (!chip)
3908                 return NULL;
3909
3910         /* Legacy SMI probing will only support chips similar to 88E6085 */
3911         chip->info = &mv88e6xxx_table[MV88E6085];
3912
3913         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3914         if (err)
3915                 goto free;
3916
3917         err = mv88e6xxx_detect(chip);
3918         if (err)
3919                 goto free;
3920
3921         err = mv88e6xxx_mdio_register(chip, NULL);
3922         if (err)
3923                 goto free;
3924
3925         *priv = chip;
3926
3927         return chip->info->name;
3928 free:
3929         devm_kfree(dsa_dev, chip);
3930
3931         return NULL;
3932 }
3933
3934 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3935         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3936         .probe                  = mv88e6xxx_drv_probe,
3937         .setup                  = mv88e6xxx_setup,
3938         .set_addr               = mv88e6xxx_set_addr,
3939         .adjust_link            = mv88e6xxx_adjust_link,
3940         .get_strings            = mv88e6xxx_get_strings,
3941         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3942         .get_sset_count         = mv88e6xxx_get_sset_count,
3943         .set_eee                = mv88e6xxx_set_eee,
3944         .get_eee                = mv88e6xxx_get_eee,
3945 #ifdef CONFIG_NET_DSA_HWMON
3946         .get_temp               = mv88e6xxx_get_temp,
3947         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3948         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3949         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3950 #endif
3951         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3952         .get_eeprom             = mv88e6xxx_get_eeprom,
3953         .set_eeprom             = mv88e6xxx_set_eeprom,
3954         .get_regs_len           = mv88e6xxx_get_regs_len,
3955         .get_regs               = mv88e6xxx_get_regs,
3956         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3957         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3958         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3959         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3960         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3961         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3962         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3963         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3964         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3965         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3966         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3967         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3968         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3969 };
3970
3971 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3972                                      struct device_node *np)
3973 {
3974         struct device *dev = chip->dev;
3975         struct dsa_switch *ds;
3976
3977         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3978         if (!ds)
3979                 return -ENOMEM;
3980
3981         ds->dev = dev;
3982         ds->priv = chip;
3983         ds->drv = &mv88e6xxx_switch_driver;
3984
3985         dev_set_drvdata(dev, ds);
3986
3987         return dsa_register_switch(ds, np);
3988 }
3989
3990 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3991 {
3992         dsa_unregister_switch(chip->ds);
3993 }
3994
3995 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3996 {
3997         struct device *dev = &mdiodev->dev;
3998         struct device_node *np = dev->of_node;
3999         const struct mv88e6xxx_info *compat_info;
4000         struct mv88e6xxx_chip *chip;
4001         u32 eeprom_len;
4002         int err;
4003
4004         compat_info = of_device_get_match_data(dev);
4005         if (!compat_info)
4006                 return -EINVAL;
4007
4008         chip = mv88e6xxx_alloc_chip(dev);
4009         if (!chip)
4010                 return -ENOMEM;
4011
4012         chip->info = compat_info;
4013
4014         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4015         if (err)
4016                 return err;
4017
4018         err = mv88e6xxx_detect(chip);
4019         if (err)
4020                 return err;
4021
4022         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4023         if (IS_ERR(chip->reset))
4024                 return PTR_ERR(chip->reset);
4025
4026         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4027             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4028                 chip->eeprom_len = eeprom_len;
4029
4030         err = mv88e6xxx_mdio_register(chip, np);
4031         if (err)
4032                 return err;
4033
4034         err = mv88e6xxx_register_switch(chip, np);
4035         if (err) {
4036                 mv88e6xxx_mdio_unregister(chip);
4037                 return err;
4038         }
4039
4040         return 0;
4041 }
4042
4043 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4044 {
4045         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4046         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4047
4048         mv88e6xxx_unregister_switch(chip);
4049         mv88e6xxx_mdio_unregister(chip);
4050 }
4051
4052 static const struct of_device_id mv88e6xxx_of_match[] = {
4053         {
4054                 .compatible = "marvell,mv88e6085",
4055                 .data = &mv88e6xxx_table[MV88E6085],
4056         },
4057         { /* sentinel */ },
4058 };
4059
4060 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4061
4062 static struct mdio_driver mv88e6xxx_driver = {
4063         .probe  = mv88e6xxx_probe,
4064         .remove = mv88e6xxx_remove,
4065         .mdiodrv.driver = {
4066                 .name = "mv88e6085",
4067                 .of_match_table = mv88e6xxx_of_match,
4068         },
4069 };
4070
4071 static int __init mv88e6xxx_init(void)
4072 {
4073         register_switch_driver(&mv88e6xxx_switch_driver);
4074         return mdio_driver_register(&mv88e6xxx_driver);
4075 }
4076 module_init(mv88e6xxx_init);
4077
4078 static void __exit mv88e6xxx_cleanup(void)
4079 {
4080         mdio_driver_unregister(&mv88e6xxx_driver);
4081         unregister_switch_driver(&mv88e6xxx_switch_driver);
4082 }
4083 module_exit(mv88e6xxx_cleanup);
4084
4085 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4086 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4087 MODULE_LICENSE("GPL");