drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/dsa/mv88e6xxx.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/mdio.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/platform_data/mv88e6xxx.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/phylink.h>
  33 #include <net/dsa.h>
  34
  35 #include "chip.h"
  36 #include "devlink.h"
  37 #include "global1.h"
  38 #include "global2.h"
  39 #include "hwtstamp.h"
  40 #include "phy.h"
  41 #include "port.h"
  42 #include "ptp.h"
  43 #include "serdes.h"
  44 #include "smi.h"
  45
  46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  47 {
  48         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  49                 dev_err(chip->dev, "Switch registers lock not held!\n");
  50                 dump_stack();
  51         }
  52 }
  53
  54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  55 {
  56         int err;
  57
  58         assert_reg_lock(chip);
  59
  60         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  61         if (err)
  62                 return err;
  63
  64         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  65                 addr, reg, *val);
  66
  67         return 0;
  68 }
  69
  70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  71 {
  72         int err;
  73
  74         assert_reg_lock(chip);
  75
  76         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  77         if (err)
  78                 return err;
  79
  80         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  81                 addr, reg, val);
  82
  83         return 0;
  84 }
  85
  86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  87                         u16 mask, u16 val)
  88 {
  89         const unsigned long timeout = jiffies + msecs_to_jiffies(50);
  90         u16 data;
  91         int err;
  92         int i;
  93
  94         /* There's no bus specific operation to wait for a mask. Even
  95          * if the initial poll takes longer than 50ms, always do at
  96          * least one more attempt.
  97          */
  98         for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
  99                 err = mv88e6xxx_read(chip, addr, reg, &data);
 100                 if (err)
 101                         return err;
 102
 103                 if ((data & mask) == val)
 104                         return 0;
 105
 106                 if (i < 2)
 107                         cpu_relax();
 108                 else
 109                         usleep_range(1000, 2000);
 110         }
 111
 112         err = mv88e6xxx_read(chip, addr, reg, &data);
 113         if (err)
 114                 return err;
 115
 116         if ((data & mask) == val)
 117                 return 0;
 118
 119         dev_err(chip->dev, "Timeout while waiting for switch\n");
 120         return -ETIMEDOUT;
 121 }
 122
 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 124                        int bit, int val)
 125 {
 126         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 127                                    val ? BIT(bit) : 0x0000);
 128 }
 129
 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 131 {
 132         struct mv88e6xxx_mdio_bus *mdio_bus;
 133
 134         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 135                                     list);
 136         if (!mdio_bus)
 137                 return NULL;
 138
 139         return mdio_bus->bus;
 140 }
 141
 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 143 {
 144         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 145         unsigned int n = d->hwirq;
 146
 147         chip->g1_irq.masked |= (1 << n);
 148 }
 149
 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 151 {
 152         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 153         unsigned int n = d->hwirq;
 154
 155         chip->g1_irq.masked &= ~(1 << n);
 156 }
 157
 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 159 {
 160         unsigned int nhandled = 0;
 161         unsigned int sub_irq;
 162         unsigned int n;
 163         u16 reg;
 164         u16 ctl1;
 165         int err;
 166
 167         mv88e6xxx_reg_lock(chip);
 168         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 169         mv88e6xxx_reg_unlock(chip);
 170
 171         if (err)
 172                 goto out;
 173
 174         do {
 175                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 176                         if (reg & (1 << n)) {
 177                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 178                                                            n);
 179                                 handle_nested_irq(sub_irq);
 180                                 ++nhandled;
 181                         }
 182                 }
 183
 184                 mv88e6xxx_reg_lock(chip);
 185                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 186                 if (err)
 187                         goto unlock;
 188                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 189 unlock:
 190                 mv88e6xxx_reg_unlock(chip);
 191                 if (err)
 192                         goto out;
 193                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 194         } while (reg & ctl1);
 195
 196 out:
 197         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 198 }
 199
 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 201 {
 202         struct mv88e6xxx_chip *chip = dev_id;
 203
 204         return mv88e6xxx_g1_irq_thread_work(chip);
 205 }
 206
 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 208 {
 209         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 210
 211         mv88e6xxx_reg_lock(chip);
 212 }
 213
 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 215 {
 216         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 217         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 218         u16 reg;
 219         int err;
 220
 221         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 222         if (err)
 223                 goto out;
 224
 225         reg &= ~mask;
 226         reg |= (~chip->g1_irq.masked & mask);
 227
 228         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 229         if (err)
 230                 goto out;
 231
 232 out:
 233         mv88e6xxx_reg_unlock(chip);
 234 }
 235
 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 237         .name                   = "mv88e6xxx-g1",
 238         .irq_mask               = mv88e6xxx_g1_irq_mask,
 239         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 240         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 241         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 242 };
 243
 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 245                                        unsigned int irq,
 246                                        irq_hw_number_t hwirq)
 247 {
 248         struct mv88e6xxx_chip *chip = d->host_data;
 249
 250         irq_set_chip_data(irq, d->host_data);
 251         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 252         irq_set_noprobe(irq);
 253
 254         return 0;
 255 }
 256
 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 258         .map    = mv88e6xxx_g1_irq_domain_map,
 259         .xlate  = irq_domain_xlate_twocell,
 260 };
 261
 262 /* To be called with reg_lock held */
 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 264 {
 265         int irq, virq;
 266         u16 mask;
 267
 268         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 269         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 270         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 271
 272         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 273                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 274                 irq_dispose_mapping(virq);
 275         }
 276
 277         irq_domain_remove(chip->g1_irq.domain);
 278 }
 279
 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 281 {
 282         /*
 283          * free_irq must be called without reg_lock taken because the irq
 284          * handler takes this lock, too.
 285          */
 286         free_irq(chip->irq, chip);
 287
 288         mv88e6xxx_reg_lock(chip);
 289         mv88e6xxx_g1_irq_free_common(chip);
 290         mv88e6xxx_reg_unlock(chip);
 291 }
 292
 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 294 {
 295         int err, irq, virq;
 296         u16 reg, mask;
 297
 298         chip->g1_irq.nirqs = chip->info->g1_irqs;
 299         chip->g1_irq.domain = irq_domain_add_simple(
 300                 NULL, chip->g1_irq.nirqs, 0,
 301                 &mv88e6xxx_g1_irq_domain_ops, chip);
 302         if (!chip->g1_irq.domain)
 303                 return -ENOMEM;
 304
 305         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 306                 irq_create_mapping(chip->g1_irq.domain, irq);
 307
 308         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 309         chip->g1_irq.masked = ~0;
 310
 311         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 312         if (err)
 313                 goto out_mapping;
 314
 315         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 316
 317         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 318         if (err)
 319                 goto out_disable;
 320
 321         /* Reading the interrupt status clears (most of) them */
 322         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 323         if (err)
 324                 goto out_disable;
 325
 326         return 0;
 327
 328 out_disable:
 329         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 330         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 331
 332 out_mapping:
 333         for (irq = 0; irq < 16; irq++) {
 334                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 335                 irq_dispose_mapping(virq);
 336         }
 337
 338         irq_domain_remove(chip->g1_irq.domain);
 339
 340         return err;
 341 }
 342
 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 344 {
 345         static struct lock_class_key lock_key;
 346         static struct lock_class_key request_key;
 347         int err;
 348
 349         err = mv88e6xxx_g1_irq_setup_common(chip);
 350         if (err)
 351                 return err;
 352
 353         /* These lock classes tells lockdep that global 1 irqs are in
 354          * a different category than their parent GPIO, so it won't
 355          * report false recursion.
 356          */
 357         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 358
 359         snprintf(chip->irq_name, sizeof(chip->irq_name),
 360                  "mv88e6xxx-%s", dev_name(chip->dev));
 361
 362         mv88e6xxx_reg_unlock(chip);
 363         err = request_threaded_irq(chip->irq, NULL,
 364                                    mv88e6xxx_g1_irq_thread_fn,
 365                                    IRQF_ONESHOT | IRQF_SHARED,
 366                                    chip->irq_name, chip);
 367         mv88e6xxx_reg_lock(chip);
 368         if (err)
 369                 mv88e6xxx_g1_irq_free_common(chip);
 370
 371         return err;
 372 }
 373
 374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 375 {
 376         struct mv88e6xxx_chip *chip = container_of(work,
 377                                                    struct mv88e6xxx_chip,
 378                                                    irq_poll_work.work);
 379         mv88e6xxx_g1_irq_thread_work(chip);
 380
 381         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 382                                    msecs_to_jiffies(100));
 383 }
 384
 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 386 {
 387         int err;
 388
 389         err = mv88e6xxx_g1_irq_setup_common(chip);
 390         if (err)
 391                 return err;
 392
 393         kthread_init_delayed_work(&chip->irq_poll_work,
 394                                   mv88e6xxx_irq_poll);
 395
 396         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 397         if (IS_ERR(chip->kworker))
 398                 return PTR_ERR(chip->kworker);
 399
 400         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 401                                    msecs_to_jiffies(100));
 402
 403         return 0;
 404 }
 405
 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 407 {
 408         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 409         kthread_destroy_worker(chip->kworker);
 410
 411         mv88e6xxx_reg_lock(chip);
 412         mv88e6xxx_g1_irq_free_common(chip);
 413         mv88e6xxx_reg_unlock(chip);
 414 }
 415
 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 417                                            int port, phy_interface_t interface)
 418 {
 419         int err;
 420
 421         if (chip->info->ops->port_set_rgmii_delay) {
 422                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 423                                                             interface);
 424                 if (err && err != -EOPNOTSUPP)
 425                         return err;
 426         }
 427
 428         if (chip->info->ops->port_set_cmode) {
 429                 err = chip->info->ops->port_set_cmode(chip, port,
 430                                                       interface);
 431                 if (err && err != -EOPNOTSUPP)
 432                         return err;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 439                                     int link, int speed, int duplex, int pause,
 440                                     phy_interface_t mode)
 441 {
 442         int err;
 443
 444         if (!chip->info->ops->port_set_link)
 445                 return 0;
 446
 447         /* Port's MAC control must not be changed unless the link is down */
 448         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 449         if (err)
 450                 return err;
 451
 452         if (chip->info->ops->port_set_speed_duplex) {
 453                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 454                                                              speed, duplex);
 455                 if (err && err != -EOPNOTSUPP)
 456                         goto restore_link;
 457         }
 458
 459         if (chip->info->ops->port_set_pause) {
 460                 err = chip->info->ops->port_set_pause(chip, port, pause);
 461                 if (err)
 462                         goto restore_link;
 463         }
 464
 465         err = mv88e6xxx_port_config_interface(chip, port, mode);
 466 restore_link:
 467         if (chip->info->ops->port_set_link(chip, port, link))
 468                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 469
 470         return err;
 471 }
 472
 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
 474 {
 475         return port >= chip->info->internal_phys_offset &&
 476                 port < chip->info->num_internal_phys +
 477                         chip->info->internal_phys_offset;
 478 }
 479
 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 481 {
 482         u16 reg;
 483         int err;
 484
 485         /* The 88e6250 family does not have the PHY detect bit. Instead,
 486          * report whether the port is internal.
 487          */
 488         if (chip->info->family == MV88E6XXX_FAMILY_6250)
 489                 return mv88e6xxx_phy_is_internal(chip, port);
 490
 491         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 492         if (err) {
 493                 dev_err(chip->dev,
 494                         "p%d: %s: failed to read port status\n",
 495                         port, __func__);
 496                 return err;
 497         }
 498
 499         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 500 }
 501
 502 static const u8 mv88e6185_phy_interface_modes[] = {
 503         [MV88E6185_PORT_STS_CMODE_GMII_FD]       = PHY_INTERFACE_MODE_GMII,
 504         [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
 505         [MV88E6185_PORT_STS_CMODE_MII_100]       = PHY_INTERFACE_MODE_MII,
 506         [MV88E6185_PORT_STS_CMODE_MII_10]        = PHY_INTERFACE_MODE_MII,
 507         [MV88E6185_PORT_STS_CMODE_SERDES]        = PHY_INTERFACE_MODE_1000BASEX,
 508         [MV88E6185_PORT_STS_CMODE_1000BASE_X]    = PHY_INTERFACE_MODE_1000BASEX,
 509         [MV88E6185_PORT_STS_CMODE_PHY]           = PHY_INTERFACE_MODE_SGMII,
 510 };
 511
 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 513                                        struct phylink_config *config)
 514 {
 515         u8 cmode = chip->ports[port].cmode;
 516
 517         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 518
 519         if (mv88e6xxx_phy_is_internal(chip, port)) {
 520                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 521         } else {
 522                 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 523                     mv88e6185_phy_interface_modes[cmode])
 524                         __set_bit(mv88e6185_phy_interface_modes[cmode],
 525                                   config->supported_interfaces);
 526
 527                 config->mac_capabilities |= MAC_1000FD;
 528         }
 529 }
 530
 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 532                                        struct phylink_config *config)
 533 {
 534         u8 cmode = chip->ports[port].cmode;
 535
 536         if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 537             mv88e6185_phy_interface_modes[cmode])
 538                 __set_bit(mv88e6185_phy_interface_modes[cmode],
 539                           config->supported_interfaces);
 540
 541         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 542                                    MAC_1000FD;
 543 }
 544
 545 static const u8 mv88e6xxx_phy_interface_modes[] = {
 546         [MV88E6XXX_PORT_STS_CMODE_MII_PHY]      = PHY_INTERFACE_MODE_REVMII,
 547         [MV88E6XXX_PORT_STS_CMODE_MII]          = PHY_INTERFACE_MODE_MII,
 548         [MV88E6XXX_PORT_STS_CMODE_GMII]         = PHY_INTERFACE_MODE_GMII,
 549         [MV88E6XXX_PORT_STS_CMODE_RMII_PHY]     = PHY_INTERFACE_MODE_REVRMII,
 550         [MV88E6XXX_PORT_STS_CMODE_RMII]         = PHY_INTERFACE_MODE_RMII,
 551         [MV88E6XXX_PORT_STS_CMODE_100BASEX]     = PHY_INTERFACE_MODE_100BASEX,
 552         [MV88E6XXX_PORT_STS_CMODE_1000BASEX]    = PHY_INTERFACE_MODE_1000BASEX,
 553         [MV88E6XXX_PORT_STS_CMODE_SGMII]        = PHY_INTERFACE_MODE_SGMII,
 554         /* higher interface modes are not needed here, since ports supporting
 555          * them are writable, and so the supported interfaces are filled in the
 556          * corresponding .phylink_set_interfaces() implementation below
 557          */
 558 };
 559
 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
 561 {
 562         if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
 563             mv88e6xxx_phy_interface_modes[cmode])
 564                 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
 565         else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
 566                 phy_interface_set_rgmii(supported);
 567 }
 568
 569 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 570                                        struct phylink_config *config)
 571 {
 572         unsigned long *supported = config->supported_interfaces;
 573
 574         /* Translate the default cmode */
 575         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 576
 577         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 578 }
 579
 580 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
 581 {
 582         u16 reg, val;
 583         int err;
 584
 585         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &reg);
 586         if (err)
 587                 return err;
 588
 589         /* If PHY_DETECT is zero, then we are not in auto-media mode */
 590         if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
 591                 return 0xf;
 592
 593         val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
 594         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
 595         if (err)
 596                 return err;
 597
 598         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
 599         if (err)
 600                 return err;
 601
 602         /* Restore PHY_DETECT value */
 603         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
 604         if (err)
 605                 return err;
 606
 607         return val & MV88E6XXX_PORT_STS_CMODE_MASK;
 608 }
 609
 610 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 611                                        struct phylink_config *config)
 612 {
 613         unsigned long *supported = config->supported_interfaces;
 614         int err, cmode;
 615
 616         /* Translate the default cmode */
 617         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 618
 619         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 620                                    MAC_1000FD;
 621
 622         /* Port 4 supports automedia if the serdes is associated with it. */
 623         if (port == 4) {
 624                 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
 625                 if (err < 0)
 626                         dev_err(chip->dev, "p%d: failed to read scratch\n",
 627                                 port);
 628                 if (err <= 0)
 629                         return;
 630
 631                 cmode = mv88e6352_get_port4_serdes_cmode(chip);
 632                 if (cmode < 0)
 633                         dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
 634                                 port);
 635                 else
 636                         mv88e6xxx_translate_cmode(cmode, supported);
 637         }
 638 }
 639
 640 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 641                                        struct phylink_config *config)
 642 {
 643         unsigned long *supported = config->supported_interfaces;
 644
 645         /* Translate the default cmode */
 646         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 647
 648         /* No ethtool bits for 200Mbps */
 649         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 650                                    MAC_1000FD;
 651
 652         /* The C_Mode field is programmable on port 5 */
 653         if (port == 5) {
 654                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 655                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 656                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 657
 658                 config->mac_capabilities |= MAC_2500FD;
 659         }
 660 }
 661
 662 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 663                                        struct phylink_config *config)
 664 {
 665         unsigned long *supported = config->supported_interfaces;
 666
 667         /* Translate the default cmode */
 668         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 669
 670         /* No ethtool bits for 200Mbps */
 671         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 672                                    MAC_1000FD;
 673
 674         /* The C_Mode field is programmable on ports 9 and 10 */
 675         if (port == 9 || port == 10) {
 676                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 677                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 678                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 679
 680                 config->mac_capabilities |= MAC_2500FD;
 681         }
 682 }
 683
 684 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 685                                         struct phylink_config *config)
 686 {
 687         unsigned long *supported = config->supported_interfaces;
 688
 689         mv88e6390_phylink_get_caps(chip, port, config);
 690
 691         /* For the 6x90X, ports 2-7 can be in automedia mode.
 692          * (Note that 6x90 doesn't support RXAUI nor XAUI).
 693          *
 694          * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
 695          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 696          * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
 697          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 698          *
 699          * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
 700          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 701          * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
 702          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 703          *
 704          * For now, be permissive (as the old code was) and allow 1000BASE-X
 705          * on ports 2..7.
 706          */
 707         if (port >= 2 && port <= 7)
 708                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 709
 710         /* The C_Mode field can also be programmed for 10G speeds */
 711         if (port == 9 || port == 10) {
 712                 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
 713                 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
 714
 715                 config->mac_capabilities |= MAC_10000FD;
 716         }
 717 }
 718
 719 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 720                                         struct phylink_config *config)
 721 {
 722         unsigned long *supported = config->supported_interfaces;
 723         bool is_6191x =
 724                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
 725         bool is_6361 =
 726                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
 727
 728         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 729
 730         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 731                                    MAC_1000FD;
 732
 733         /* The C_Mode field can be programmed for ports 0, 9 and 10 */
 734         if (port == 0 || port == 9 || port == 10) {
 735                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 736                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 737
 738                 /* 6191X supports >1G modes only on port 10 */
 739                 if (!is_6191x || port == 10) {
 740                         __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 741                         config->mac_capabilities |= MAC_2500FD;
 742
 743                         /* 6361 only supports up to 2500BaseX */
 744                         if (!is_6361) {
 745                                 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
 746                                 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
 747                                 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
 748                                 config->mac_capabilities |= MAC_5000FD |
 749                                         MAC_10000FD;
 750                         }
 751                 }
 752         }
 753
 754         if (port == 0) {
 755                 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
 756                 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
 757                 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
 758                 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
 759                 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
 760         }
 761 }
 762
 763 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
 764                                struct phylink_config *config)
 765 {
 766         struct mv88e6xxx_chip *chip = ds->priv;
 767
 768         mv88e6xxx_reg_lock(chip);
 769         chip->info->ops->phylink_get_caps(chip, port, config);
 770         mv88e6xxx_reg_unlock(chip);
 771
 772         if (mv88e6xxx_phy_is_internal(chip, port)) {
 773                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 774                           config->supported_interfaces);
 775                 /* Internal ports with no phy-mode need GMII for PHYLIB */
 776                 __set_bit(PHY_INTERFACE_MODE_GMII,
 777                           config->supported_interfaces);
 778         }
 779 }
 780
 781 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
 782                                                     int port,
 783                                                     phy_interface_t interface)
 784 {
 785         struct mv88e6xxx_chip *chip = ds->priv;
 786         struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
 787
 788         if (chip->info->ops->pcs_ops)
 789                 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
 790                                                            interface);
 791
 792         return pcs;
 793 }
 794
 795 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
 796                                  unsigned int mode, phy_interface_t interface)
 797 {
 798         struct mv88e6xxx_chip *chip = ds->priv;
 799         int err = 0;
 800
 801         /* In inband mode, the link may come up at any time while the link
 802          * is not forced down. Force the link down while we reconfigure the
 803          * interface mode.
 804          */
 805         if (mode == MLO_AN_INBAND &&
 806             chip->ports[port].interface != interface &&
 807             chip->info->ops->port_set_link) {
 808                 mv88e6xxx_reg_lock(chip);
 809                 err = chip->info->ops->port_set_link(chip, port,
 810                                                      LINK_FORCED_DOWN);
 811                 mv88e6xxx_reg_unlock(chip);
 812         }
 813
 814         return err;
 815 }
 816
 817 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 818                                  unsigned int mode,
 819                                  const struct phylink_link_state *state)
 820 {
 821         struct mv88e6xxx_chip *chip = ds->priv;
 822         int err = 0;
 823
 824         mv88e6xxx_reg_lock(chip);
 825
 826         if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
 827                 err = mv88e6xxx_port_config_interface(chip, port,
 828                                                       state->interface);
 829                 if (err && err != -EOPNOTSUPP)
 830                         goto err_unlock;
 831         }
 832
 833 err_unlock:
 834         mv88e6xxx_reg_unlock(chip);
 835
 836         if (err && err != -EOPNOTSUPP)
 837                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 838 }
 839
 840 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
 841                                 unsigned int mode, phy_interface_t interface)
 842 {
 843         struct mv88e6xxx_chip *chip = ds->priv;
 844         int err = 0;
 845
 846         /* Undo the forced down state above after completing configuration
 847          * irrespective of its state on entry, which allows the link to come
 848          * up in the in-band case where there is no separate SERDES. Also
 849          * ensure that the link can come up if the PPU is in use and we are
 850          * in PHY mode (we treat the PPU as an effective in-band mechanism.)
 851          */
 852         mv88e6xxx_reg_lock(chip);
 853
 854         if (chip->info->ops->port_set_link &&
 855             ((mode == MLO_AN_INBAND &&
 856               chip->ports[port].interface != interface) ||
 857              (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
 858                 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 859
 860         mv88e6xxx_reg_unlock(chip);
 861
 862         chip->ports[port].interface = interface;
 863
 864         return err;
 865 }
 866
 867 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 868                                     unsigned int mode,
 869                                     phy_interface_t interface)
 870 {
 871         struct mv88e6xxx_chip *chip = ds->priv;
 872         const struct mv88e6xxx_ops *ops;
 873         int err = 0;
 874
 875         ops = chip->info->ops;
 876
 877         mv88e6xxx_reg_lock(chip);
 878         /* Force the link down if we know the port may not be automatically
 879          * updated by the switch or if we are using fixed-link mode.
 880          */
 881         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 882              mode == MLO_AN_FIXED) && ops->port_sync_link)
 883                 err = ops->port_sync_link(chip, port, mode, false);
 884
 885         if (!err && ops->port_set_speed_duplex)
 886                 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
 887                                                  DUPLEX_UNFORCED);
 888         mv88e6xxx_reg_unlock(chip);
 889
 890         if (err)
 891                 dev_err(chip->dev,
 892                         "p%d: failed to force MAC link down\n", port);
 893 }
 894
 895 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 896                                   unsigned int mode, phy_interface_t interface,
 897                                   struct phy_device *phydev,
 898                                   int speed, int duplex,
 899                                   bool tx_pause, bool rx_pause)
 900 {
 901         struct mv88e6xxx_chip *chip = ds->priv;
 902         const struct mv88e6xxx_ops *ops;
 903         int err = 0;
 904
 905         ops = chip->info->ops;
 906
 907         mv88e6xxx_reg_lock(chip);
 908         /* Configure and force the link up if we know that the port may not
 909          * automatically updated by the switch or if we are using fixed-link
 910          * mode.
 911          */
 912         if (!mv88e6xxx_port_ppu_updates(chip, port) ||
 913             mode == MLO_AN_FIXED) {
 914                 if (ops->port_set_speed_duplex) {
 915                         err = ops->port_set_speed_duplex(chip, port,
 916                                                          speed, duplex);
 917                         if (err && err != -EOPNOTSUPP)
 918                                 goto error;
 919                 }
 920
 921                 if (ops->port_sync_link)
 922                         err = ops->port_sync_link(chip, port, mode, true);
 923         }
 924 error:
 925         mv88e6xxx_reg_unlock(chip);
 926
 927         if (err && err != -EOPNOTSUPP)
 928                 dev_err(ds->dev,
 929                         "p%d: failed to configure MAC link up\n", port);
 930 }
 931
 932 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 933 {
 934         if (!chip->info->ops->stats_snapshot)
 935                 return -EOPNOTSUPP;
 936
 937         return chip->info->ops->stats_snapshot(chip, port);
 938 }
 939
 940 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 941         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 942         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 943         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 944         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 945         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 946         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 947         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 948         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 949         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 950         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 951         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 952         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 953         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 954         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 955         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 956         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 957         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 958         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 959         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 960         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 961         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 962         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 963         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 964         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 965         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 966         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 967         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 968         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 969         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 970         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 971         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 972         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 973         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 974         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 975         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 976         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 977         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 978         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 979         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 980         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 981         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 982         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 983         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 984         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 985         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 986         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 987         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 988         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 989         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 990         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 991         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 992         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 993         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 994         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 995         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 996         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 997         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 998         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 999         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
1000 };
1001
1002 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1003                                             struct mv88e6xxx_hw_stat *s,
1004                                             int port, u16 bank1_select,
1005                                             u16 histogram)
1006 {
1007         u32 low;
1008         u32 high = 0;
1009         u16 reg = 0;
1010         int err;
1011         u64 value;
1012
1013         switch (s->type) {
1014         case STATS_TYPE_PORT:
1015                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1016                 if (err)
1017                         return U64_MAX;
1018
1019                 low = reg;
1020                 if (s->size == 4) {
1021                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1022                         if (err)
1023                                 return U64_MAX;
1024                         low |= ((u32)reg) << 16;
1025                 }
1026                 break;
1027         case STATS_TYPE_BANK1:
1028                 reg = bank1_select;
1029                 fallthrough;
1030         case STATS_TYPE_BANK0:
1031                 reg |= s->reg | histogram;
1032                 mv88e6xxx_g1_stats_read(chip, reg, &low);
1033                 if (s->size == 8)
1034                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1035                 break;
1036         default:
1037                 return U64_MAX;
1038         }
1039         value = (((u64)high) << 32) | low;
1040         return value;
1041 }
1042
1043 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1044                                        uint8_t *data, int types)
1045 {
1046         struct mv88e6xxx_hw_stat *stat;
1047         int i, j;
1048
1049         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1050                 stat = &mv88e6xxx_hw_stats[i];
1051                 if (stat->type & types) {
1052                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1053                                ETH_GSTRING_LEN);
1054                         j++;
1055                 }
1056         }
1057
1058         return j;
1059 }
1060
1061 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1062                                        uint8_t *data)
1063 {
1064         return mv88e6xxx_stats_get_strings(chip, data,
1065                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1066 }
1067
1068 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1069                                        uint8_t *data)
1070 {
1071         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1072 }
1073
1074 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1075                                        uint8_t *data)
1076 {
1077         return mv88e6xxx_stats_get_strings(chip, data,
1078                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1079 }
1080
1081 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1082         "atu_member_violation",
1083         "atu_miss_violation",
1084         "atu_full_violation",
1085         "vtu_member_violation",
1086         "vtu_miss_violation",
1087 };
1088
1089 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1090 {
1091         unsigned int i;
1092
1093         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1094                 strscpy(data + i * ETH_GSTRING_LEN,
1095                         mv88e6xxx_atu_vtu_stats_strings[i],
1096                         ETH_GSTRING_LEN);
1097 }
1098
1099 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1100                                   u32 stringset, uint8_t *data)
1101 {
1102         struct mv88e6xxx_chip *chip = ds->priv;
1103         int count = 0;
1104
1105         if (stringset != ETH_SS_STATS)
1106                 return;
1107
1108         mv88e6xxx_reg_lock(chip);
1109
1110         if (chip->info->ops->stats_get_strings)
1111                 count = chip->info->ops->stats_get_strings(chip, data);
1112
1113         if (chip->info->ops->serdes_get_strings) {
1114                 data += count * ETH_GSTRING_LEN;
1115                 count = chip->info->ops->serdes_get_strings(chip, port, data);
1116         }
1117
1118         data += count * ETH_GSTRING_LEN;
1119         mv88e6xxx_atu_vtu_get_strings(data);
1120
1121         mv88e6xxx_reg_unlock(chip);
1122 }
1123
1124 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1125                                           int types)
1126 {
1127         struct mv88e6xxx_hw_stat *stat;
1128         int i, j;
1129
1130         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1131                 stat = &mv88e6xxx_hw_stats[i];
1132                 if (stat->type & types)
1133                         j++;
1134         }
1135         return j;
1136 }
1137
1138 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1139 {
1140         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1141                                               STATS_TYPE_PORT);
1142 }
1143
1144 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1145 {
1146         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1147 }
1148
1149 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1150 {
1151         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1152                                               STATS_TYPE_BANK1);
1153 }
1154
1155 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1156 {
1157         struct mv88e6xxx_chip *chip = ds->priv;
1158         int serdes_count = 0;
1159         int count = 0;
1160
1161         if (sset != ETH_SS_STATS)
1162                 return 0;
1163
1164         mv88e6xxx_reg_lock(chip);
1165         if (chip->info->ops->stats_get_sset_count)
1166                 count = chip->info->ops->stats_get_sset_count(chip);
1167         if (count < 0)
1168                 goto out;
1169
1170         if (chip->info->ops->serdes_get_sset_count)
1171                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1172                                                                       port);
1173         if (serdes_count < 0) {
1174                 count = serdes_count;
1175                 goto out;
1176         }
1177         count += serdes_count;
1178         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1179
1180 out:
1181         mv88e6xxx_reg_unlock(chip);
1182
1183         return count;
1184 }
1185
1186 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1187                                      uint64_t *data, int types,
1188                                      u16 bank1_select, u16 histogram)
1189 {
1190         struct mv88e6xxx_hw_stat *stat;
1191         int i, j;
1192
1193         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1194                 stat = &mv88e6xxx_hw_stats[i];
1195                 if (stat->type & types) {
1196                         mv88e6xxx_reg_lock(chip);
1197                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1198                                                               bank1_select,
1199                                                               histogram);
1200                         mv88e6xxx_reg_unlock(chip);
1201
1202                         j++;
1203                 }
1204         }
1205         return j;
1206 }
1207
1208 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1209                                      uint64_t *data)
1210 {
1211         return mv88e6xxx_stats_get_stats(chip, port, data,
1212                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1213                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1214 }
1215
1216 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1217                                      uint64_t *data)
1218 {
1219         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1220                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1221 }
1222
1223 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1224                                      uint64_t *data)
1225 {
1226         return mv88e6xxx_stats_get_stats(chip, port, data,
1227                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1228                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1229                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1230 }
1231
1232 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1233                                      uint64_t *data)
1234 {
1235         return mv88e6xxx_stats_get_stats(chip, port, data,
1236                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1237                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1238                                          0);
1239 }
1240
1241 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1242                                         uint64_t *data)
1243 {
1244         *data++ = chip->ports[port].atu_member_violation;
1245         *data++ = chip->ports[port].atu_miss_violation;
1246         *data++ = chip->ports[port].atu_full_violation;
1247         *data++ = chip->ports[port].vtu_member_violation;
1248         *data++ = chip->ports[port].vtu_miss_violation;
1249 }
1250
1251 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1252                                 uint64_t *data)
1253 {
1254         int count = 0;
1255
1256         if (chip->info->ops->stats_get_stats)
1257                 count = chip->info->ops->stats_get_stats(chip, port, data);
1258
1259         mv88e6xxx_reg_lock(chip);
1260         if (chip->info->ops->serdes_get_stats) {
1261                 data += count;
1262                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1263         }
1264         data += count;
1265         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1266         mv88e6xxx_reg_unlock(chip);
1267 }
1268
1269 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1270                                         uint64_t *data)
1271 {
1272         struct mv88e6xxx_chip *chip = ds->priv;
1273         int ret;
1274
1275         mv88e6xxx_reg_lock(chip);
1276
1277         ret = mv88e6xxx_stats_snapshot(chip, port);
1278         mv88e6xxx_reg_unlock(chip);
1279
1280         if (ret < 0)
1281                 return;
1282
1283         mv88e6xxx_get_stats(chip, port, data);
1284
1285 }
1286
1287 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1288 {
1289         struct mv88e6xxx_chip *chip = ds->priv;
1290         int len;
1291
1292         len = 32 * sizeof(u16);
1293         if (chip->info->ops->serdes_get_regs_len)
1294                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1295
1296         return len;
1297 }
1298
1299 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1300                                struct ethtool_regs *regs, void *_p)
1301 {
1302         struct mv88e6xxx_chip *chip = ds->priv;
1303         int err;
1304         u16 reg;
1305         u16 *p = _p;
1306         int i;
1307
1308         regs->version = chip->info->prod_num;
1309
1310         memset(p, 0xff, 32 * sizeof(u16));
1311
1312         mv88e6xxx_reg_lock(chip);
1313
1314         for (i = 0; i < 32; i++) {
1315
1316                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1317                 if (!err)
1318                         p[i] = reg;
1319         }
1320
1321         if (chip->info->ops->serdes_get_regs)
1322                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1323
1324         mv88e6xxx_reg_unlock(chip);
1325 }
1326
1327 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1328                                  struct ethtool_eee *e)
1329 {
1330         /* Nothing to do on the port's MAC */
1331         return 0;
1332 }
1333
1334 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1335                                  struct ethtool_eee *e)
1336 {
1337         /* Nothing to do on the port's MAC */
1338         return 0;
1339 }
1340
1341 /* Mask of the local ports allowed to receive frames from a given fabric port */
1342 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1343 {
1344         struct dsa_switch *ds = chip->ds;
1345         struct dsa_switch_tree *dst = ds->dst;
1346         struct dsa_port *dp, *other_dp;
1347         bool found = false;
1348         u16 pvlan;
1349
1350         /* dev is a physical switch */
1351         if (dev <= dst->last_switch) {
1352                 list_for_each_entry(dp, &dst->ports, list) {
1353                         if (dp->ds->index == dev && dp->index == port) {
1354                                 /* dp might be a DSA link or a user port, so it
1355                                  * might or might not have a bridge.
1356                                  * Use the "found" variable for both cases.
1357                                  */
1358                                 found = true;
1359                                 break;
1360                         }
1361                 }
1362         /* dev is a virtual bridge */
1363         } else {
1364                 list_for_each_entry(dp, &dst->ports, list) {
1365                         unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1366
1367                         if (!bridge_num)
1368                                 continue;
1369
1370                         if (bridge_num + dst->last_switch != dev)
1371                                 continue;
1372
1373                         found = true;
1374                         break;
1375                 }
1376         }
1377
1378         /* Prevent frames from unknown switch or virtual bridge */
1379         if (!found)
1380                 return 0;
1381
1382         /* Frames from DSA links and CPU ports can egress any local port */
1383         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1384                 return mv88e6xxx_port_mask(chip);
1385
1386         pvlan = 0;
1387
1388         /* Frames from standalone user ports can only egress on the
1389          * upstream port.
1390          */
1391         if (!dsa_port_bridge_dev_get(dp))
1392                 return BIT(dsa_switch_upstream_port(ds));
1393
1394         /* Frames from bridged user ports can egress any local DSA
1395          * links and CPU ports, as well as any local member of their
1396          * bridge group.
1397          */
1398         dsa_switch_for_each_port(other_dp, ds)
1399                 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1400                     other_dp->type == DSA_PORT_TYPE_DSA ||
1401                     dsa_port_bridge_same(dp, other_dp))
1402                         pvlan |= BIT(other_dp->index);
1403
1404         return pvlan;
1405 }
1406
1407 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1408 {
1409         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1410
1411         /* prevent frames from going back out of the port they came in on */
1412         output_ports &= ~BIT(port);
1413
1414         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1415 }
1416
1417 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1418                                          u8 state)
1419 {
1420         struct mv88e6xxx_chip *chip = ds->priv;
1421         int err;
1422
1423         mv88e6xxx_reg_lock(chip);
1424         err = mv88e6xxx_port_set_state(chip, port, state);
1425         mv88e6xxx_reg_unlock(chip);
1426
1427         if (err)
1428                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1429 }
1430
1431 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1432 {
1433         int err;
1434
1435         if (chip->info->ops->ieee_pri_map) {
1436                 err = chip->info->ops->ieee_pri_map(chip);
1437                 if (err)
1438                         return err;
1439         }
1440
1441         if (chip->info->ops->ip_pri_map) {
1442                 err = chip->info->ops->ip_pri_map(chip);
1443                 if (err)
1444                         return err;
1445         }
1446
1447         return 0;
1448 }
1449
1450 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1451 {
1452         struct dsa_switch *ds = chip->ds;
1453         int target, port;
1454         int err;
1455
1456         if (!chip->info->global2_addr)
1457                 return 0;
1458
1459         /* Initialize the routing port to the 32 possible target devices */
1460         for (target = 0; target < 32; target++) {
1461                 port = dsa_routing_port(ds, target);
1462                 if (port == ds->num_ports)
1463                         port = 0x1f;
1464
1465                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1466                 if (err)
1467                         return err;
1468         }
1469
1470         if (chip->info->ops->set_cascade_port) {
1471                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1472                 err = chip->info->ops->set_cascade_port(chip, port);
1473                 if (err)
1474                         return err;
1475         }
1476
1477         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1478         if (err)
1479                 return err;
1480
1481         return 0;
1482 }
1483
1484 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1485 {
1486         /* Clear all trunk masks and mapping */
1487         if (chip->info->global2_addr)
1488                 return mv88e6xxx_g2_trunk_clear(chip);
1489
1490         return 0;
1491 }
1492
1493 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1494 {
1495         if (chip->info->ops->rmu_disable)
1496                 return chip->info->ops->rmu_disable(chip);
1497
1498         return 0;
1499 }
1500
1501 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1502 {
1503         if (chip->info->ops->pot_clear)
1504                 return chip->info->ops->pot_clear(chip);
1505
1506         return 0;
1507 }
1508
1509 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1510 {
1511         if (chip->info->ops->mgmt_rsvd2cpu)
1512                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1513
1514         return 0;
1515 }
1516
1517 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1518 {
1519         int err;
1520
1521         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1522         if (err)
1523                 return err;
1524
1525         /* The chips that have a "learn2all" bit in Global1, ATU
1526          * Control are precisely those whose port registers have a
1527          * Message Port bit in Port Control 1 and hence implement
1528          * ->port_setup_message_port.
1529          */
1530         if (chip->info->ops->port_setup_message_port) {
1531                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1532                 if (err)
1533                         return err;
1534         }
1535
1536         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1537 }
1538
1539 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1540 {
1541         int port;
1542         int err;
1543
1544         if (!chip->info->ops->irl_init_all)
1545                 return 0;
1546
1547         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1548                 /* Disable ingress rate limiting by resetting all per port
1549                  * ingress rate limit resources to their initial state.
1550                  */
1551                 err = chip->info->ops->irl_init_all(chip, port);
1552                 if (err)
1553                         return err;
1554         }
1555
1556         return 0;
1557 }
1558
1559 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1560 {
1561         if (chip->info->ops->set_switch_mac) {
1562                 u8 addr[ETH_ALEN];
1563
1564                 eth_random_addr(addr);
1565
1566                 return chip->info->ops->set_switch_mac(chip, addr);
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1573 {
1574         struct dsa_switch_tree *dst = chip->ds->dst;
1575         struct dsa_switch *ds;
1576         struct dsa_port *dp;
1577         u16 pvlan = 0;
1578
1579         if (!mv88e6xxx_has_pvt(chip))
1580                 return 0;
1581
1582         /* Skip the local source device, which uses in-chip port VLAN */
1583         if (dev != chip->ds->index) {
1584                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1585
1586                 ds = dsa_switch_find(dst->index, dev);
1587                 dp = ds ? dsa_to_port(ds, port) : NULL;
1588                 if (dp && dp->lag) {
1589                         /* As the PVT is used to limit flooding of
1590                          * FORWARD frames, which use the LAG ID as the
1591                          * source port, we must translate dev/port to
1592                          * the special "LAG device" in the PVT, using
1593                          * the LAG ID (one-based) as the port number
1594                          * (zero-based).
1595                          */
1596                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1597                         port = dsa_port_lag_id_get(dp) - 1;
1598                 }
1599         }
1600
1601         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1602 }
1603
1604 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1605 {
1606         int dev, port;
1607         int err;
1608
1609         if (!mv88e6xxx_has_pvt(chip))
1610                 return 0;
1611
1612         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1613          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1614          */
1615         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1616         if (err)
1617                 return err;
1618
1619         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1620                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1621                         err = mv88e6xxx_pvt_map(chip, dev, port);
1622                         if (err)
1623                                 return err;
1624                 }
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1631                                        u16 fid)
1632 {
1633         if (dsa_to_port(chip->ds, port)->lag)
1634                 /* Hardware is incapable of fast-aging a LAG through a
1635                  * regular ATU move operation. Until we have something
1636                  * more fancy in place this is a no-op.
1637                  */
1638                 return -EOPNOTSUPP;
1639
1640         return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1641 }
1642
1643 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1644 {
1645         struct mv88e6xxx_chip *chip = ds->priv;
1646         int err;
1647
1648         mv88e6xxx_reg_lock(chip);
1649         err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1650         mv88e6xxx_reg_unlock(chip);
1651
1652         if (err)
1653                 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1654                         port, err);
1655 }
1656
1657 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1658 {
1659         if (!mv88e6xxx_max_vid(chip))
1660                 return 0;
1661
1662         return mv88e6xxx_g1_vtu_flush(chip);
1663 }
1664
1665 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1666                              struct mv88e6xxx_vtu_entry *entry)
1667 {
1668         int err;
1669
1670         if (!chip->info->ops->vtu_getnext)
1671                 return -EOPNOTSUPP;
1672
1673         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1674         entry->valid = false;
1675
1676         err = chip->info->ops->vtu_getnext(chip, entry);
1677
1678         if (entry->vid != vid)
1679                 entry->valid = false;
1680
1681         return err;
1682 }
1683
1684 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1685                        int (*cb)(struct mv88e6xxx_chip *chip,
1686                                  const struct mv88e6xxx_vtu_entry *entry,
1687                                  void *priv),
1688                        void *priv)
1689 {
1690         struct mv88e6xxx_vtu_entry entry = {
1691                 .vid = mv88e6xxx_max_vid(chip),
1692                 .valid = false,
1693         };
1694         int err;
1695
1696         if (!chip->info->ops->vtu_getnext)
1697                 return -EOPNOTSUPP;
1698
1699         do {
1700                 err = chip->info->ops->vtu_getnext(chip, &entry);
1701                 if (err)
1702                         return err;
1703
1704                 if (!entry.valid)
1705                         break;
1706
1707                 err = cb(chip, &entry, priv);
1708                 if (err)
1709                         return err;
1710         } while (entry.vid < mv88e6xxx_max_vid(chip));
1711
1712         return 0;
1713 }
1714
1715 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1716                                    struct mv88e6xxx_vtu_entry *entry)
1717 {
1718         if (!chip->info->ops->vtu_loadpurge)
1719                 return -EOPNOTSUPP;
1720
1721         return chip->info->ops->vtu_loadpurge(chip, entry);
1722 }
1723
1724 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1725                                   const struct mv88e6xxx_vtu_entry *entry,
1726                                   void *_fid_bitmap)
1727 {
1728         unsigned long *fid_bitmap = _fid_bitmap;
1729
1730         set_bit(entry->fid, fid_bitmap);
1731         return 0;
1732 }
1733
1734 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1735 {
1736         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1737
1738         /* Every FID has an associated VID, so walking the VTU
1739          * will discover the full set of FIDs in use.
1740          */
1741         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1742 }
1743
1744 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1745 {
1746         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1747         int err;
1748
1749         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1750         if (err)
1751                 return err;
1752
1753         *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1754         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1755                 return -ENOSPC;
1756
1757         /* Clear the database */
1758         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1759 }
1760
1761 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1762                                    struct mv88e6xxx_stu_entry *entry)
1763 {
1764         if (!chip->info->ops->stu_loadpurge)
1765                 return -EOPNOTSUPP;
1766
1767         return chip->info->ops->stu_loadpurge(chip, entry);
1768 }
1769
1770 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1771 {
1772         struct mv88e6xxx_stu_entry stu = {
1773                 .valid = true,
1774                 .sid = 0
1775         };
1776
1777         if (!mv88e6xxx_has_stu(chip))
1778                 return 0;
1779
1780         /* Make sure that SID 0 is always valid. This is used by VTU
1781          * entries that do not make use of the STU, e.g. when creating
1782          * a VLAN upper on a port that is also part of a VLAN
1783          * filtering bridge.
1784          */
1785         return mv88e6xxx_stu_loadpurge(chip, &stu);
1786 }
1787
1788 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1789 {
1790         DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1791         struct mv88e6xxx_mst *mst;
1792
1793         __set_bit(0, busy);
1794
1795         list_for_each_entry(mst, &chip->msts, node)
1796                 __set_bit(mst->stu.sid, busy);
1797
1798         *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1799
1800         return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1801 }
1802
1803 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1804 {
1805         struct mv88e6xxx_mst *mst, *tmp;
1806         int err;
1807
1808         if (!sid)
1809                 return 0;
1810
1811         list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1812                 if (mst->stu.sid != sid)
1813                         continue;
1814
1815                 if (!refcount_dec_and_test(&mst->refcnt))
1816                         return 0;
1817
1818                 mst->stu.valid = false;
1819                 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1820                 if (err) {
1821                         refcount_set(&mst->refcnt, 1);
1822                         return err;
1823                 }
1824
1825                 list_del(&mst->node);
1826                 kfree(mst);
1827                 return 0;
1828         }
1829
1830         return -ENOENT;
1831 }
1832
1833 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1834                              u16 msti, u8 *sid)
1835 {
1836         struct mv88e6xxx_mst *mst;
1837         int err, i;
1838
1839         if (!mv88e6xxx_has_stu(chip)) {
1840                 err = -EOPNOTSUPP;
1841                 goto err;
1842         }
1843
1844         if (!msti) {
1845                 *sid = 0;
1846                 return 0;
1847         }
1848
1849         list_for_each_entry(mst, &chip->msts, node) {
1850                 if (mst->br == br && mst->msti == msti) {
1851                         refcount_inc(&mst->refcnt);
1852                         *sid = mst->stu.sid;
1853                         return 0;
1854                 }
1855         }
1856
1857         err = mv88e6xxx_sid_get(chip, sid);
1858         if (err)
1859                 goto err;
1860
1861         mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1862         if (!mst) {
1863                 err = -ENOMEM;
1864                 goto err;
1865         }
1866
1867         INIT_LIST_HEAD(&mst->node);
1868         refcount_set(&mst->refcnt, 1);
1869         mst->br = br;
1870         mst->msti = msti;
1871         mst->stu.valid = true;
1872         mst->stu.sid = *sid;
1873
1874         /* The bridge starts out all ports in the disabled state. But
1875          * a STU state of disabled means to go by the port-global
1876          * state. So we set all user port's initial state to blocking,
1877          * to match the bridge's behavior.
1878          */
1879         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1880                 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1881                         MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1882                         MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1883
1884         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1885         if (err)
1886                 goto err_free;
1887
1888         list_add_tail(&mst->node, &chip->msts);
1889         return 0;
1890
1891 err_free:
1892         kfree(mst);
1893 err:
1894         return err;
1895 }
1896
1897 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1898                                         const struct switchdev_mst_state *st)
1899 {
1900         struct dsa_port *dp = dsa_to_port(ds, port);
1901         struct mv88e6xxx_chip *chip = ds->priv;
1902         struct mv88e6xxx_mst *mst;
1903         u8 state;
1904         int err;
1905
1906         if (!mv88e6xxx_has_stu(chip))
1907                 return -EOPNOTSUPP;
1908
1909         switch (st->state) {
1910         case BR_STATE_DISABLED:
1911         case BR_STATE_BLOCKING:
1912         case BR_STATE_LISTENING:
1913                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1914                 break;
1915         case BR_STATE_LEARNING:
1916                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1917                 break;
1918         case BR_STATE_FORWARDING:
1919                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1920                 break;
1921         default:
1922                 return -EINVAL;
1923         }
1924
1925         list_for_each_entry(mst, &chip->msts, node) {
1926                 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1927                     mst->msti == st->msti) {
1928                         if (mst->stu.state[port] == state)
1929                                 return 0;
1930
1931                         mst->stu.state[port] = state;
1932                         mv88e6xxx_reg_lock(chip);
1933                         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1934                         mv88e6xxx_reg_unlock(chip);
1935                         return err;
1936                 }
1937         }
1938
1939         return -ENOENT;
1940 }
1941
1942 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1943                                         u16 vid)
1944 {
1945         struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1946         struct mv88e6xxx_chip *chip = ds->priv;
1947         struct mv88e6xxx_vtu_entry vlan;
1948         int err;
1949
1950         /* DSA and CPU ports have to be members of multiple vlans */
1951         if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
1952                 return 0;
1953
1954         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1955         if (err)
1956                 return err;
1957
1958         if (!vlan.valid)
1959                 return 0;
1960
1961         dsa_switch_for_each_user_port(other_dp, ds) {
1962                 struct net_device *other_br;
1963
1964                 if (vlan.member[other_dp->index] ==
1965                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1966                         continue;
1967
1968                 if (dsa_port_bridge_same(dp, other_dp))
1969                         break; /* same bridge, check next VLAN */
1970
1971                 other_br = dsa_port_bridge_dev_get(other_dp);
1972                 if (!other_br)
1973                         continue;
1974
1975                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1976                         port, vlan.vid, other_dp->index, netdev_name(other_br));
1977                 return -EOPNOTSUPP;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
1984 {
1985         struct dsa_port *dp = dsa_to_port(chip->ds, port);
1986         struct net_device *br = dsa_port_bridge_dev_get(dp);
1987         struct mv88e6xxx_port *p = &chip->ports[port];
1988         u16 pvid = MV88E6XXX_VID_STANDALONE;
1989         bool drop_untagged = false;
1990         int err;
1991
1992         if (br) {
1993                 if (br_vlan_enabled(br)) {
1994                         pvid = p->bridge_pvid.vid;
1995                         drop_untagged = !p->bridge_pvid.valid;
1996                 } else {
1997                         pvid = MV88E6XXX_VID_BRIDGED;
1998                 }
1999         }
2000
2001         err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2002         if (err)
2003                 return err;
2004
2005         return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2006 }
2007
2008 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2009                                          bool vlan_filtering,
2010                                          struct netlink_ext_ack *extack)
2011 {
2012         struct mv88e6xxx_chip *chip = ds->priv;
2013         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2014                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2015         int err;
2016
2017         if (!mv88e6xxx_max_vid(chip))
2018                 return -EOPNOTSUPP;
2019
2020         mv88e6xxx_reg_lock(chip);
2021
2022         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2023         if (err)
2024                 goto unlock;
2025
2026         err = mv88e6xxx_port_commit_pvid(chip, port);
2027         if (err)
2028                 goto unlock;
2029
2030 unlock:
2031         mv88e6xxx_reg_unlock(chip);
2032
2033         return err;
2034 }
2035
2036 static int
2037 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2038                             const struct switchdev_obj_port_vlan *vlan)
2039 {
2040         struct mv88e6xxx_chip *chip = ds->priv;
2041         int err;
2042
2043         if (!mv88e6xxx_max_vid(chip))
2044                 return -EOPNOTSUPP;
2045
2046         /* If the requested port doesn't belong to the same bridge as the VLAN
2047          * members, do not support it (yet) and fallback to software VLAN.
2048          */
2049         mv88e6xxx_reg_lock(chip);
2050         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2051         mv88e6xxx_reg_unlock(chip);
2052
2053         return err;
2054 }
2055
2056 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2057                                         const unsigned char *addr, u16 vid,
2058                                         u8 state)
2059 {
2060         struct mv88e6xxx_atu_entry entry;
2061         struct mv88e6xxx_vtu_entry vlan;
2062         u16 fid;
2063         int err;
2064
2065         /* Ports have two private address databases: one for when the port is
2066          * standalone and one for when the port is under a bridge and the
2067          * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2068          * address database to remain 100% empty, so we never load an ATU entry
2069          * into a standalone port's database. Therefore, translate the null
2070          * VLAN ID into the port's database used for VLAN-unaware bridging.
2071          */
2072         if (vid == 0) {
2073                 fid = MV88E6XXX_FID_BRIDGED;
2074         } else {
2075                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2076                 if (err)
2077                         return err;
2078
2079                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2080                 if (!vlan.valid)
2081                         return -EOPNOTSUPP;
2082
2083                 fid = vlan.fid;
2084         }
2085
2086         entry.state = 0;
2087         ether_addr_copy(entry.mac, addr);
2088         eth_addr_dec(entry.mac);
2089
2090         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2091         if (err)
2092                 return err;
2093
2094         /* Initialize a fresh ATU entry if it isn't found */
2095         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2096                 memset(&entry, 0, sizeof(entry));
2097                 ether_addr_copy(entry.mac, addr);
2098         }
2099
2100         /* Purge the ATU entry only if no port is using it anymore */
2101         if (!state) {
2102                 entry.portvec &= ~BIT(port);
2103                 if (!entry.portvec)
2104                         entry.state = 0;
2105         } else {
2106                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2107                         entry.portvec = BIT(port);
2108                 else
2109                         entry.portvec |= BIT(port);
2110
2111                 entry.state = state;
2112         }
2113
2114         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2115 }
2116
2117 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2118                                   const struct mv88e6xxx_policy *policy)
2119 {
2120         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2121         enum mv88e6xxx_policy_action action = policy->action;
2122         const u8 *addr = policy->addr;
2123         u16 vid = policy->vid;
2124         u8 state;
2125         int err;
2126         int id;
2127
2128         if (!chip->info->ops->port_set_policy)
2129                 return -EOPNOTSUPP;
2130
2131         switch (mapping) {
2132         case MV88E6XXX_POLICY_MAPPING_DA:
2133         case MV88E6XXX_POLICY_MAPPING_SA:
2134                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2135                         state = 0; /* Dissociate the port and address */
2136                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2137                          is_multicast_ether_addr(addr))
2138                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2139                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2140                          is_unicast_ether_addr(addr))
2141                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2142                 else
2143                         return -EOPNOTSUPP;
2144
2145                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2146                                                    state);
2147                 if (err)
2148                         return err;
2149                 break;
2150         default:
2151                 return -EOPNOTSUPP;
2152         }
2153
2154         /* Skip the port's policy clearing if the mapping is still in use */
2155         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2156                 idr_for_each_entry(&chip->policies, policy, id)
2157                         if (policy->port == port &&
2158                             policy->mapping == mapping &&
2159                             policy->action != action)
2160                                 return 0;
2161
2162         return chip->info->ops->port_set_policy(chip, port, mapping, action);
2163 }
2164
2165 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2166                                    struct ethtool_rx_flow_spec *fs)
2167 {
2168         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2169         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2170         enum mv88e6xxx_policy_mapping mapping;
2171         enum mv88e6xxx_policy_action action;
2172         struct mv88e6xxx_policy *policy;
2173         u16 vid = 0;
2174         u8 *addr;
2175         int err;
2176         int id;
2177
2178         if (fs->location != RX_CLS_LOC_ANY)
2179                 return -EINVAL;
2180
2181         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2182                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2183         else
2184                 return -EOPNOTSUPP;
2185
2186         switch (fs->flow_type & ~FLOW_EXT) {
2187         case ETHER_FLOW:
2188                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2189                     is_zero_ether_addr(mac_mask->h_source)) {
2190                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
2191                         addr = mac_entry->h_dest;
2192                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2193                     !is_zero_ether_addr(mac_mask->h_source)) {
2194                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
2195                         addr = mac_entry->h_source;
2196                 } else {
2197                         /* Cannot support DA and SA mapping in the same rule */
2198                         return -EOPNOTSUPP;
2199                 }
2200                 break;
2201         default:
2202                 return -EOPNOTSUPP;
2203         }
2204
2205         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2206                 if (fs->m_ext.vlan_tci != htons(0xffff))
2207                         return -EOPNOTSUPP;
2208                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2209         }
2210
2211         idr_for_each_entry(&chip->policies, policy, id) {
2212                 if (policy->port == port && policy->mapping == mapping &&
2213                     policy->action == action && policy->vid == vid &&
2214                     ether_addr_equal(policy->addr, addr))
2215                         return -EEXIST;
2216         }
2217
2218         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2219         if (!policy)
2220                 return -ENOMEM;
2221
2222         fs->location = 0;
2223         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2224                             GFP_KERNEL);
2225         if (err) {
2226                 devm_kfree(chip->dev, policy);
2227                 return err;
2228         }
2229
2230         memcpy(&policy->fs, fs, sizeof(*fs));
2231         ether_addr_copy(policy->addr, addr);
2232         policy->mapping = mapping;
2233         policy->action = action;
2234         policy->port = port;
2235         policy->vid = vid;
2236
2237         err = mv88e6xxx_policy_apply(chip, port, policy);
2238         if (err) {
2239                 idr_remove(&chip->policies, fs->location);
2240                 devm_kfree(chip->dev, policy);
2241                 return err;
2242         }
2243
2244         return 0;
2245 }
2246
2247 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2248                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2249 {
2250         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2251         struct mv88e6xxx_chip *chip = ds->priv;
2252         struct mv88e6xxx_policy *policy;
2253         int err;
2254         int id;
2255
2256         mv88e6xxx_reg_lock(chip);
2257
2258         switch (rxnfc->cmd) {
2259         case ETHTOOL_GRXCLSRLCNT:
2260                 rxnfc->data = 0;
2261                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2262                 rxnfc->rule_cnt = 0;
2263                 idr_for_each_entry(&chip->policies, policy, id)
2264                         if (policy->port == port)
2265                                 rxnfc->rule_cnt++;
2266                 err = 0;
2267                 break;
2268         case ETHTOOL_GRXCLSRULE:
2269                 err = -ENOENT;
2270                 policy = idr_find(&chip->policies, fs->location);
2271                 if (policy) {
2272                         memcpy(fs, &policy->fs, sizeof(*fs));
2273                         err = 0;
2274                 }
2275                 break;
2276         case ETHTOOL_GRXCLSRLALL:
2277                 rxnfc->data = 0;
2278                 rxnfc->rule_cnt = 0;
2279                 idr_for_each_entry(&chip->policies, policy, id)
2280                         if (policy->port == port)
2281                                 rule_locs[rxnfc->rule_cnt++] = id;
2282                 err = 0;
2283                 break;
2284         default:
2285                 err = -EOPNOTSUPP;
2286                 break;
2287         }
2288
2289         mv88e6xxx_reg_unlock(chip);
2290
2291         return err;
2292 }
2293
2294 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2295                                struct ethtool_rxnfc *rxnfc)
2296 {
2297         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2298         struct mv88e6xxx_chip *chip = ds->priv;
2299         struct mv88e6xxx_policy *policy;
2300         int err;
2301
2302         mv88e6xxx_reg_lock(chip);
2303
2304         switch (rxnfc->cmd) {
2305         case ETHTOOL_SRXCLSRLINS:
2306                 err = mv88e6xxx_policy_insert(chip, port, fs);
2307                 break;
2308         case ETHTOOL_SRXCLSRLDEL:
2309                 err = -ENOENT;
2310                 policy = idr_remove(&chip->policies, fs->location);
2311                 if (policy) {
2312                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2313                         err = mv88e6xxx_policy_apply(chip, port, policy);
2314                         devm_kfree(chip->dev, policy);
2315                 }
2316                 break;
2317         default:
2318                 err = -EOPNOTSUPP;
2319                 break;
2320         }
2321
2322         mv88e6xxx_reg_unlock(chip);
2323
2324         return err;
2325 }
2326
2327 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2328                                         u16 vid)
2329 {
2330         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2331         u8 broadcast[ETH_ALEN];
2332
2333         eth_broadcast_addr(broadcast);
2334
2335         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2336 }
2337
2338 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2339 {
2340         int port;
2341         int err;
2342
2343         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2344                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2345                 struct net_device *brport;
2346
2347                 if (dsa_is_unused_port(chip->ds, port))
2348                         continue;
2349
2350                 brport = dsa_port_to_bridge_port(dp);
2351                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2352                         /* Skip bridged user ports where broadcast
2353                          * flooding is disabled.
2354                          */
2355                         continue;
2356
2357                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2358                 if (err)
2359                         return err;
2360         }
2361
2362         return 0;
2363 }
2364
2365 struct mv88e6xxx_port_broadcast_sync_ctx {
2366         int port;
2367         bool flood;
2368 };
2369
2370 static int
2371 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2372                                    const struct mv88e6xxx_vtu_entry *vlan,
2373                                    void *_ctx)
2374 {
2375         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2376         u8 broadcast[ETH_ALEN];
2377         u8 state;
2378
2379         if (ctx->flood)
2380                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2381         else
2382                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2383
2384         eth_broadcast_addr(broadcast);
2385
2386         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2387                                             vlan->vid, state);
2388 }
2389
2390 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2391                                          bool flood)
2392 {
2393         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2394                 .port = port,
2395                 .flood = flood,
2396         };
2397         struct mv88e6xxx_vtu_entry vid0 = {
2398                 .vid = 0,
2399         };
2400         int err;
2401
2402         /* Update the port's private database... */
2403         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2404         if (err)
2405                 return err;
2406
2407         /* ...and the database for all VLANs. */
2408         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2409                                   &ctx);
2410 }
2411
2412 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2413                                     u16 vid, u8 member, bool warn)
2414 {
2415         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2416         struct mv88e6xxx_vtu_entry vlan;
2417         int i, err;
2418
2419         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2420         if (err)
2421                 return err;
2422
2423         if (!vlan.valid) {
2424                 memset(&vlan, 0, sizeof(vlan));
2425
2426                 if (vid == MV88E6XXX_VID_STANDALONE)
2427                         vlan.policy = true;
2428
2429                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2430                 if (err)
2431                         return err;
2432
2433                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2434                         if (i == port)
2435                                 vlan.member[i] = member;
2436                         else
2437                                 vlan.member[i] = non_member;
2438
2439                 vlan.vid = vid;
2440                 vlan.valid = true;
2441
2442                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2443                 if (err)
2444                         return err;
2445
2446                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2447                 if (err)
2448                         return err;
2449         } else if (vlan.member[port] != member) {
2450                 vlan.member[port] = member;
2451
2452                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2453                 if (err)
2454                         return err;
2455         } else if (warn) {
2456                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2457                          port, vid);
2458         }
2459
2460         return 0;
2461 }
2462
2463 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2464                                    const struct switchdev_obj_port_vlan *vlan,
2465                                    struct netlink_ext_ack *extack)
2466 {
2467         struct mv88e6xxx_chip *chip = ds->priv;
2468         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2469         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2470         struct mv88e6xxx_port *p = &chip->ports[port];
2471         bool warn;
2472         u8 member;
2473         int err;
2474
2475         if (!vlan->vid)
2476                 return 0;
2477
2478         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2479         if (err)
2480                 return err;
2481
2482         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2483                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2484         else if (untagged)
2485                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2486         else
2487                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2488
2489         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2490          * and then the CPU port. Do not warn for duplicates for the CPU port.
2491          */
2492         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2493
2494         mv88e6xxx_reg_lock(chip);
2495
2496         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2497         if (err) {
2498                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2499                         vlan->vid, untagged ? 'u' : 't');
2500                 goto out;
2501         }
2502
2503         if (pvid) {
2504                 p->bridge_pvid.vid = vlan->vid;
2505                 p->bridge_pvid.valid = true;
2506
2507                 err = mv88e6xxx_port_commit_pvid(chip, port);
2508                 if (err)
2509                         goto out;
2510         } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2511                 /* The old pvid was reinstalled as a non-pvid VLAN */
2512                 p->bridge_pvid.valid = false;
2513
2514                 err = mv88e6xxx_port_commit_pvid(chip, port);
2515                 if (err)
2516                         goto out;
2517         }
2518
2519 out:
2520         mv88e6xxx_reg_unlock(chip);
2521
2522         return err;
2523 }
2524
2525 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2526                                      int port, u16 vid)
2527 {
2528         struct mv88e6xxx_vtu_entry vlan;
2529         int i, err;
2530
2531         if (!vid)
2532                 return 0;
2533
2534         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2535         if (err)
2536                 return err;
2537
2538         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2539          * tell switchdev that this VLAN is likely handled in software.
2540          */
2541         if (!vlan.valid ||
2542             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2543                 return -EOPNOTSUPP;
2544
2545         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2546
2547         /* keep the VLAN unless all ports are excluded */
2548         vlan.valid = false;
2549         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2550                 if (vlan.member[i] !=
2551                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2552                         vlan.valid = true;
2553                         break;
2554                 }
2555         }
2556
2557         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2558         if (err)
2559                 return err;
2560
2561         if (!vlan.valid) {
2562                 err = mv88e6xxx_mst_put(chip, vlan.sid);
2563                 if (err)
2564                         return err;
2565         }
2566
2567         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2568 }
2569
2570 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2571                                    const struct switchdev_obj_port_vlan *vlan)
2572 {
2573         struct mv88e6xxx_chip *chip = ds->priv;
2574         struct mv88e6xxx_port *p = &chip->ports[port];
2575         int err = 0;
2576         u16 pvid;
2577
2578         if (!mv88e6xxx_max_vid(chip))
2579                 return -EOPNOTSUPP;
2580
2581         /* The ATU removal procedure needs the FID to be mapped in the VTU,
2582          * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2583          * switchdev workqueue to ensure that all FDB entries are deleted
2584          * before we remove the VLAN.
2585          */
2586         dsa_flush_workqueue();
2587
2588         mv88e6xxx_reg_lock(chip);
2589
2590         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2591         if (err)
2592                 goto unlock;
2593
2594         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2595         if (err)
2596                 goto unlock;
2597
2598         if (vlan->vid == pvid) {
2599                 p->bridge_pvid.valid = false;
2600
2601                 err = mv88e6xxx_port_commit_pvid(chip, port);
2602                 if (err)
2603                         goto unlock;
2604         }
2605
2606 unlock:
2607         mv88e6xxx_reg_unlock(chip);
2608
2609         return err;
2610 }
2611
2612 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2613 {
2614         struct mv88e6xxx_chip *chip = ds->priv;
2615         struct mv88e6xxx_vtu_entry vlan;
2616         int err;
2617
2618         mv88e6xxx_reg_lock(chip);
2619
2620         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2621         if (err)
2622                 goto unlock;
2623
2624         err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2625
2626 unlock:
2627         mv88e6xxx_reg_unlock(chip);
2628
2629         return err;
2630 }
2631
2632 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2633                                    struct dsa_bridge bridge,
2634                                    const struct switchdev_vlan_msti *msti)
2635 {
2636         struct mv88e6xxx_chip *chip = ds->priv;
2637         struct mv88e6xxx_vtu_entry vlan;
2638         u8 old_sid, new_sid;
2639         int err;
2640
2641         if (!mv88e6xxx_has_stu(chip))
2642                 return -EOPNOTSUPP;
2643
2644         mv88e6xxx_reg_lock(chip);
2645
2646         err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2647         if (err)
2648                 goto unlock;
2649
2650         if (!vlan.valid) {
2651                 err = -EINVAL;
2652                 goto unlock;
2653         }
2654
2655         old_sid = vlan.sid;
2656
2657         err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2658         if (err)
2659                 goto unlock;
2660
2661         if (new_sid != old_sid) {
2662                 vlan.sid = new_sid;
2663
2664                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2665                 if (err) {
2666                         mv88e6xxx_mst_put(chip, new_sid);
2667                         goto unlock;
2668                 }
2669         }
2670
2671         err = mv88e6xxx_mst_put(chip, old_sid);
2672
2673 unlock:
2674         mv88e6xxx_reg_unlock(chip);
2675         return err;
2676 }
2677
2678 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2679                                   const unsigned char *addr, u16 vid,
2680                                   struct dsa_db db)
2681 {
2682         struct mv88e6xxx_chip *chip = ds->priv;
2683         int err;
2684
2685         mv88e6xxx_reg_lock(chip);
2686         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2687                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2688         mv88e6xxx_reg_unlock(chip);
2689
2690         return err;
2691 }
2692
2693 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2694                                   const unsigned char *addr, u16 vid,
2695                                   struct dsa_db db)
2696 {
2697         struct mv88e6xxx_chip *chip = ds->priv;
2698         int err;
2699
2700         mv88e6xxx_reg_lock(chip);
2701         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2702         mv88e6xxx_reg_unlock(chip);
2703
2704         return err;
2705 }
2706
2707 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2708                                       u16 fid, u16 vid, int port,
2709                                       dsa_fdb_dump_cb_t *cb, void *data)
2710 {
2711         struct mv88e6xxx_atu_entry addr;
2712         bool is_static;
2713         int err;
2714
2715         addr.state = 0;
2716         eth_broadcast_addr(addr.mac);
2717
2718         do {
2719                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2720                 if (err)
2721                         return err;
2722
2723                 if (!addr.state)
2724                         break;
2725
2726                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2727                         continue;
2728
2729                 if (!is_unicast_ether_addr(addr.mac))
2730                         continue;
2731
2732                 is_static = (addr.state ==
2733                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2734                 err = cb(addr.mac, vid, is_static, data);
2735                 if (err)
2736                         return err;
2737         } while (!is_broadcast_ether_addr(addr.mac));
2738
2739         return err;
2740 }
2741
2742 struct mv88e6xxx_port_db_dump_vlan_ctx {
2743         int port;
2744         dsa_fdb_dump_cb_t *cb;
2745         void *data;
2746 };
2747
2748 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2749                                        const struct mv88e6xxx_vtu_entry *entry,
2750                                        void *_data)
2751 {
2752         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2753
2754         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2755                                           ctx->port, ctx->cb, ctx->data);
2756 }
2757
2758 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2759                                   dsa_fdb_dump_cb_t *cb, void *data)
2760 {
2761         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2762                 .port = port,
2763                 .cb = cb,
2764                 .data = data,
2765         };
2766         u16 fid;
2767         int err;
2768
2769         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2770         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2771         if (err)
2772                 return err;
2773
2774         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2775         if (err)
2776                 return err;
2777
2778         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2779 }
2780
2781 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2782                                    dsa_fdb_dump_cb_t *cb, void *data)
2783 {
2784         struct mv88e6xxx_chip *chip = ds->priv;
2785         int err;
2786
2787         mv88e6xxx_reg_lock(chip);
2788         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2789         mv88e6xxx_reg_unlock(chip);
2790
2791         return err;
2792 }
2793
2794 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2795                                 struct dsa_bridge bridge)
2796 {
2797         struct dsa_switch *ds = chip->ds;
2798         struct dsa_switch_tree *dst = ds->dst;
2799         struct dsa_port *dp;
2800         int err;
2801
2802         list_for_each_entry(dp, &dst->ports, list) {
2803                 if (dsa_port_offloads_bridge(dp, &bridge)) {
2804                         if (dp->ds == ds) {
2805                                 /* This is a local bridge group member,
2806                                  * remap its Port VLAN Map.
2807                                  */
2808                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2809                                 if (err)
2810                                         return err;
2811                         } else {
2812                                 /* This is an external bridge group member,
2813                                  * remap its cross-chip Port VLAN Table entry.
2814                                  */
2815                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2816                                                         dp->index);
2817                                 if (err)
2818                                         return err;
2819                         }
2820                 }
2821         }
2822
2823         return 0;
2824 }
2825
2826 /* Treat the software bridge as a virtual single-port switch behind the
2827  * CPU and map in the PVT. First dst->last_switch elements are taken by
2828  * physical switches, so start from beyond that range.
2829  */
2830 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2831                                                unsigned int bridge_num)
2832 {
2833         u8 dev = bridge_num + ds->dst->last_switch;
2834         struct mv88e6xxx_chip *chip = ds->priv;
2835
2836         return mv88e6xxx_pvt_map(chip, dev, 0);
2837 }
2838
2839 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2840                                       struct dsa_bridge bridge,
2841                                       bool *tx_fwd_offload,
2842                                       struct netlink_ext_ack *extack)
2843 {
2844         struct mv88e6xxx_chip *chip = ds->priv;
2845         int err;
2846
2847         mv88e6xxx_reg_lock(chip);
2848
2849         err = mv88e6xxx_bridge_map(chip, bridge);
2850         if (err)
2851                 goto unlock;
2852
2853         err = mv88e6xxx_port_set_map_da(chip, port, true);
2854         if (err)
2855                 goto unlock;
2856
2857         err = mv88e6xxx_port_commit_pvid(chip, port);
2858         if (err)
2859                 goto unlock;
2860
2861         if (mv88e6xxx_has_pvt(chip)) {
2862                 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2863                 if (err)
2864                         goto unlock;
2865
2866                 *tx_fwd_offload = true;
2867         }
2868
2869 unlock:
2870         mv88e6xxx_reg_unlock(chip);
2871
2872         return err;
2873 }
2874
2875 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2876                                         struct dsa_bridge bridge)
2877 {
2878         struct mv88e6xxx_chip *chip = ds->priv;
2879         int err;
2880
2881         mv88e6xxx_reg_lock(chip);
2882
2883         if (bridge.tx_fwd_offload &&
2884             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2885                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2886
2887         if (mv88e6xxx_bridge_map(chip, bridge) ||
2888             mv88e6xxx_port_vlan_map(chip, port))
2889                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2890
2891         err = mv88e6xxx_port_set_map_da(chip, port, false);
2892         if (err)
2893                 dev_err(ds->dev,
2894                         "port %d failed to restore map-DA: %pe\n",
2895                         port, ERR_PTR(err));
2896
2897         err = mv88e6xxx_port_commit_pvid(chip, port);
2898         if (err)
2899                 dev_err(ds->dev,
2900                         "port %d failed to restore standalone pvid: %pe\n",
2901                         port, ERR_PTR(err));
2902
2903         mv88e6xxx_reg_unlock(chip);
2904 }
2905
2906 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2907                                            int tree_index, int sw_index,
2908                                            int port, struct dsa_bridge bridge,
2909                                            struct netlink_ext_ack *extack)
2910 {
2911         struct mv88e6xxx_chip *chip = ds->priv;
2912         int err;
2913
2914         if (tree_index != ds->dst->index)
2915                 return 0;
2916
2917         mv88e6xxx_reg_lock(chip);
2918         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2919         err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2920         mv88e6xxx_reg_unlock(chip);
2921
2922         return err;
2923 }
2924
2925 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2926                                              int tree_index, int sw_index,
2927                                              int port, struct dsa_bridge bridge)
2928 {
2929         struct mv88e6xxx_chip *chip = ds->priv;
2930
2931         if (tree_index != ds->dst->index)
2932                 return;
2933
2934         mv88e6xxx_reg_lock(chip);
2935         if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2936             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2937                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2938         mv88e6xxx_reg_unlock(chip);
2939 }
2940
2941 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2942 {
2943         if (chip->info->ops->reset)
2944                 return chip->info->ops->reset(chip);
2945
2946         return 0;
2947 }
2948
2949 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2950 {
2951         struct gpio_desc *gpiod = chip->reset;
2952
2953         /* If there is a GPIO connected to the reset pin, toggle it */
2954         if (gpiod) {
2955                 /* If the switch has just been reset and not yet completed
2956                  * loading EEPROM, the reset may interrupt the I2C transaction
2957                  * mid-byte, causing the first EEPROM read after the reset
2958                  * from the wrong location resulting in the switch booting
2959                  * to wrong mode and inoperable.
2960                  */
2961                 if (chip->info->ops->get_eeprom)
2962                         mv88e6xxx_g2_eeprom_wait(chip);
2963
2964                 gpiod_set_value_cansleep(gpiod, 1);
2965                 usleep_range(10000, 20000);
2966                 gpiod_set_value_cansleep(gpiod, 0);
2967                 usleep_range(10000, 20000);
2968
2969                 if (chip->info->ops->get_eeprom)
2970                         mv88e6xxx_g2_eeprom_wait(chip);
2971         }
2972 }
2973
2974 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2975 {
2976         int i, err;
2977
2978         /* Set all ports to the Disabled state */
2979         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2980                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2981                 if (err)
2982                         return err;
2983         }
2984
2985         /* Wait for transmit queues to drain,
2986          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2987          */
2988         usleep_range(2000, 4000);
2989
2990         return 0;
2991 }
2992
2993 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2994 {
2995         int err;
2996
2997         err = mv88e6xxx_disable_ports(chip);
2998         if (err)
2999                 return err;
3000
3001         mv88e6xxx_hardware_reset(chip);
3002
3003         return mv88e6xxx_software_reset(chip);
3004 }
3005
3006 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3007                                    enum mv88e6xxx_frame_mode frame,
3008                                    enum mv88e6xxx_egress_mode egress, u16 etype)
3009 {
3010         int err;
3011
3012         if (!chip->info->ops->port_set_frame_mode)
3013                 return -EOPNOTSUPP;
3014
3015         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3016         if (err)
3017                 return err;
3018
3019         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3020         if (err)
3021                 return err;
3022
3023         if (chip->info->ops->port_set_ether_type)
3024                 return chip->info->ops->port_set_ether_type(chip, port, etype);
3025
3026         return 0;
3027 }
3028
3029 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3030 {
3031         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3032                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3033                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3034 }
3035
3036 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3037 {
3038         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3039                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3040                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3041 }
3042
3043 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3044 {
3045         return mv88e6xxx_set_port_mode(chip, port,
3046                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
3047                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3048                                        ETH_P_EDSA);
3049 }
3050
3051 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3052 {
3053         if (dsa_is_dsa_port(chip->ds, port))
3054                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3055
3056         if (dsa_is_user_port(chip->ds, port))
3057                 return mv88e6xxx_set_port_mode_normal(chip, port);
3058
3059         /* Setup CPU port mode depending on its supported tag format */
3060         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3061                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3062
3063         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3064                 return mv88e6xxx_set_port_mode_edsa(chip, port);
3065
3066         return -EINVAL;
3067 }
3068
3069 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3070 {
3071         bool message = dsa_is_dsa_port(chip->ds, port);
3072
3073         return mv88e6xxx_port_set_message_port(chip, port, message);
3074 }
3075
3076 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3077 {
3078         int err;
3079
3080         if (chip->info->ops->port_set_ucast_flood) {
3081                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3082                 if (err)
3083                         return err;
3084         }
3085         if (chip->info->ops->port_set_mcast_flood) {
3086                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3087                 if (err)
3088                         return err;
3089         }
3090
3091         return 0;
3092 }
3093
3094 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3095                                      enum mv88e6xxx_egress_direction direction,
3096                                      int port)
3097 {
3098         int err;
3099
3100         if (!chip->info->ops->set_egress_port)
3101                 return -EOPNOTSUPP;
3102
3103         err = chip->info->ops->set_egress_port(chip, direction, port);
3104         if (err)
3105                 return err;
3106
3107         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3108                 chip->ingress_dest_port = port;
3109         else
3110                 chip->egress_dest_port = port;
3111
3112         return 0;
3113 }
3114
3115 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3116 {
3117         struct dsa_switch *ds = chip->ds;
3118         int upstream_port;
3119         int err;
3120
3121         upstream_port = dsa_upstream_port(ds, port);
3122         if (chip->info->ops->port_set_upstream_port) {
3123                 err = chip->info->ops->port_set_upstream_port(chip, port,
3124                                                               upstream_port);
3125                 if (err)
3126                         return err;
3127         }
3128
3129         if (port == upstream_port) {
3130                 if (chip->info->ops->set_cpu_port) {
3131                         err = chip->info->ops->set_cpu_port(chip,
3132                                                             upstream_port);
3133                         if (err)
3134                                 return err;
3135                 }
3136
3137                 err = mv88e6xxx_set_egress_port(chip,
3138                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
3139                                                 upstream_port);
3140                 if (err && err != -EOPNOTSUPP)
3141                         return err;
3142
3143                 err = mv88e6xxx_set_egress_port(chip,
3144                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
3145                                                 upstream_port);
3146                 if (err && err != -EOPNOTSUPP)
3147                         return err;
3148         }
3149
3150         return 0;
3151 }
3152
3153 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3154 {
3155         struct device_node *phy_handle = NULL;
3156         struct dsa_switch *ds = chip->ds;
3157         struct dsa_port *dp;
3158         int tx_amp;
3159         int err;
3160         u16 reg;
3161
3162         chip->ports[port].chip = chip;
3163         chip->ports[port].port = port;
3164
3165         err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3166                                        SPEED_UNFORCED, DUPLEX_UNFORCED,
3167                                        PAUSE_ON, PHY_INTERFACE_MODE_NA);
3168         if (err)
3169                 return err;
3170
3171         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3172          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3173          * tunneling, determine priority by looking at 802.1p and IP
3174          * priority fields (IP prio has precedence), and set STP state
3175          * to Forwarding.
3176          *
3177          * If this is the CPU link, use DSA or EDSA tagging depending
3178          * on which tagging mode was configured.
3179          *
3180          * If this is a link to another switch, use DSA tagging mode.
3181          *
3182          * If this is the upstream port for this switch, enable
3183          * forwarding of unknown unicasts and multicasts.
3184          */
3185         reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3186                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3187         /* Forward any IPv4 IGMP or IPv6 MLD frames received
3188          * by a USER port to the CPU port to allow snooping.
3189          */
3190         if (dsa_is_user_port(ds, port))
3191                 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3192
3193         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3194         if (err)
3195                 return err;
3196
3197         err = mv88e6xxx_setup_port_mode(chip, port);
3198         if (err)
3199                 return err;
3200
3201         err = mv88e6xxx_setup_egress_floods(chip, port);
3202         if (err)
3203                 return err;
3204
3205         /* Port Control 2: don't force a good FCS, set the MTU size to
3206          * 10222 bytes, disable 802.1q tags checking, don't discard
3207          * tagged or untagged frames on this port, skip destination
3208          * address lookup on user ports, disable ARP mirroring and don't
3209          * send a copy of all transmitted/received frames on this port
3210          * to the CPU.
3211          */
3212         err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3213         if (err)
3214                 return err;
3215
3216         err = mv88e6xxx_setup_upstream_port(chip, port);
3217         if (err)
3218                 return err;
3219
3220         /* On chips that support it, set all downstream DSA ports'
3221          * VLAN policy to TRAP. In combination with loading
3222          * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3223          * provides a better isolation barrier between standalone
3224          * ports, as the ATU is bypassed on any intermediate switches
3225          * between the incoming port and the CPU.
3226          */
3227         if (dsa_is_downstream_port(ds, port) &&
3228             chip->info->ops->port_set_policy) {
3229                 err = chip->info->ops->port_set_policy(chip, port,
3230                                                 MV88E6XXX_POLICY_MAPPING_VTU,
3231                                                 MV88E6XXX_POLICY_ACTION_TRAP);
3232                 if (err)
3233                         return err;
3234         }
3235
3236         /* User ports start out in standalone mode and 802.1Q is
3237          * therefore disabled. On DSA ports, all valid VIDs are always
3238          * loaded in the VTU - therefore, enable 802.1Q in order to take
3239          * advantage of VLAN policy on chips that supports it.
3240          */
3241         err = mv88e6xxx_port_set_8021q_mode(chip, port,
3242                                 dsa_is_user_port(ds, port) ?
3243                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3244                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3245         if (err)
3246                 return err;
3247
3248         /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3249          * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3250          * the first free FID. This will be used as the private PVID for
3251          * unbridged ports. Shared (DSA and CPU) ports must also be
3252          * members of this VID, in order to trap all frames assigned to
3253          * it to the CPU.
3254          */
3255         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3256                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3257                                        false);
3258         if (err)
3259                 return err;
3260
3261         /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3262          * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3263          * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3264          * as the private PVID on ports under a VLAN-unaware bridge.
3265          * Shared (DSA and CPU) ports must also be members of it, to translate
3266          * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3267          * relying on their port default FID.
3268          */
3269         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3270                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3271                                        false);
3272         if (err)
3273                 return err;
3274
3275         if (chip->info->ops->port_set_jumbo_size) {
3276                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3277                 if (err)
3278                         return err;
3279         }
3280
3281         /* Port Association Vector: disable automatic address learning
3282          * on all user ports since they start out in standalone
3283          * mode. When joining a bridge, learning will be configured to
3284          * match the bridge port settings. Enable learning on all
3285          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3286          * learning process.
3287          *
3288          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3289          * and RefreshLocked. I.e. setup standard automatic learning.
3290          */
3291         if (dsa_is_user_port(ds, port))
3292                 reg = 0;
3293         else
3294                 reg = 1 << port;
3295
3296         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3297                                    reg);
3298         if (err)
3299                 return err;
3300
3301         /* Egress rate control 2: disable egress rate control. */
3302         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3303                                    0x0000);
3304         if (err)
3305                 return err;
3306
3307         if (chip->info->ops->port_pause_limit) {
3308                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3309                 if (err)
3310                         return err;
3311         }
3312
3313         if (chip->info->ops->port_disable_learn_limit) {
3314                 err = chip->info->ops->port_disable_learn_limit(chip, port);
3315                 if (err)
3316                         return err;
3317         }
3318
3319         if (chip->info->ops->port_disable_pri_override) {
3320                 err = chip->info->ops->port_disable_pri_override(chip, port);
3321                 if (err)
3322                         return err;
3323         }
3324
3325         if (chip->info->ops->port_tag_remap) {
3326                 err = chip->info->ops->port_tag_remap(chip, port);
3327                 if (err)
3328                         return err;
3329         }
3330
3331         if (chip->info->ops->port_egress_rate_limiting) {
3332                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3333                 if (err)
3334                         return err;
3335         }
3336
3337         if (chip->info->ops->port_setup_message_port) {
3338                 err = chip->info->ops->port_setup_message_port(chip, port);
3339                 if (err)
3340                         return err;
3341         }
3342
3343         if (chip->info->ops->serdes_set_tx_amplitude) {
3344                 dp = dsa_to_port(ds, port);
3345                 if (dp)
3346                         phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3347
3348                 if (phy_handle && !of_property_read_u32(phy_handle,
3349                                                         "tx-p2p-microvolt",
3350                                                         &tx_amp))
3351                         err = chip->info->ops->serdes_set_tx_amplitude(chip,
3352                                                                 port, tx_amp);
3353                 if (phy_handle) {
3354                         of_node_put(phy_handle);
3355                         if (err)
3356                                 return err;
3357                 }
3358         }
3359
3360         /* Port based VLAN map: give each port the same default address
3361          * database, and allow bidirectional communication between the
3362          * CPU and DSA port(s), and the other ports.
3363          */
3364         err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3365         if (err)
3366                 return err;
3367
3368         err = mv88e6xxx_port_vlan_map(chip, port);
3369         if (err)
3370                 return err;
3371
3372         /* Default VLAN ID and priority: don't set a default VLAN
3373          * ID, and set the default packet priority to zero.
3374          */
3375         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3376 }
3377
3378 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3379 {
3380         struct mv88e6xxx_chip *chip = ds->priv;
3381
3382         if (chip->info->ops->port_set_jumbo_size)
3383                 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3384         else if (chip->info->ops->set_max_frame_size)
3385                 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3386         return ETH_DATA_LEN;
3387 }
3388
3389 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3390 {
3391         struct mv88e6xxx_chip *chip = ds->priv;
3392         int ret = 0;
3393
3394         /* For families where we don't know how to alter the MTU,
3395          * just accept any value up to ETH_DATA_LEN
3396          */
3397         if (!chip->info->ops->port_set_jumbo_size &&
3398             !chip->info->ops->set_max_frame_size) {
3399                 if (new_mtu > ETH_DATA_LEN)
3400                         return -EINVAL;
3401
3402                 return 0;
3403         }
3404
3405         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3406                 new_mtu += EDSA_HLEN;
3407
3408         mv88e6xxx_reg_lock(chip);
3409         if (chip->info->ops->port_set_jumbo_size)
3410                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3411         else if (chip->info->ops->set_max_frame_size)
3412                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3413         mv88e6xxx_reg_unlock(chip);
3414
3415         return ret;
3416 }
3417
3418 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3419                                      unsigned int ageing_time)
3420 {
3421         struct mv88e6xxx_chip *chip = ds->priv;
3422         int err;
3423
3424         mv88e6xxx_reg_lock(chip);
3425         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3426         mv88e6xxx_reg_unlock(chip);
3427
3428         return err;
3429 }
3430
3431 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3432 {
3433         int err;
3434
3435         /* Initialize the statistics unit */
3436         if (chip->info->ops->stats_set_histogram) {
3437                 err = chip->info->ops->stats_set_histogram(chip);
3438                 if (err)
3439                         return err;
3440         }
3441
3442         return mv88e6xxx_g1_stats_clear(chip);
3443 }
3444
3445 /* Check if the errata has already been applied. */
3446 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3447 {
3448         int port;
3449         int err;
3450         u16 val;
3451
3452         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3453                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3454                 if (err) {
3455                         dev_err(chip->dev,
3456                                 "Error reading hidden register: %d\n", err);
3457                         return false;
3458                 }
3459                 if (val != 0x01c0)
3460                         return false;
3461         }
3462
3463         return true;
3464 }
3465
3466 /* The 6390 copper ports have an errata which require poking magic
3467  * values into undocumented hidden registers and then performing a
3468  * software reset.
3469  */
3470 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3471 {
3472         int port;
3473         int err;
3474
3475         if (mv88e6390_setup_errata_applied(chip))
3476                 return 0;
3477
3478         /* Set the ports into blocking mode */
3479         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3480                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3481                 if (err)
3482                         return err;
3483         }
3484
3485         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3486                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3487                 if (err)
3488                         return err;
3489         }
3490
3491         return mv88e6xxx_software_reset(chip);
3492 }
3493
3494 /* prod_id for switch families which do not have a PHY model number */
3495 static const u16 family_prod_id_table[] = {
3496         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3497         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3498         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3499 };
3500
3501 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3502 {
3503         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3504         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3505         u16 prod_id;
3506         u16 val;
3507         int err;
3508
3509         if (!chip->info->ops->phy_read)
3510                 return -EOPNOTSUPP;
3511
3512         mv88e6xxx_reg_lock(chip);
3513         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3514         mv88e6xxx_reg_unlock(chip);
3515
3516         /* Some internal PHYs don't have a model number. */
3517         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3518             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3519                 prod_id = family_prod_id_table[chip->info->family];
3520                 if (prod_id)
3521                         val |= prod_id >> 4;
3522         }
3523
3524         return err ? err : val;
3525 }
3526
3527 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3528                                    int reg)
3529 {
3530         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3531         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3532         u16 val;
3533         int err;
3534
3535         if (!chip->info->ops->phy_read_c45)
3536                 return -EOPNOTSUPP;
3537
3538         mv88e6xxx_reg_lock(chip);
3539         err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3540         mv88e6xxx_reg_unlock(chip);
3541
3542         return err ? err : val;
3543 }
3544
3545 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3546 {
3547         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3548         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3549         int err;
3550
3551         if (!chip->info->ops->phy_write)
3552                 return -EOPNOTSUPP;
3553
3554         mv88e6xxx_reg_lock(chip);
3555         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3556         mv88e6xxx_reg_unlock(chip);
3557
3558         return err;
3559 }
3560
3561 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3562                                     int reg, u16 val)
3563 {
3564         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3565         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3566         int err;
3567
3568         if (!chip->info->ops->phy_write_c45)
3569                 return -EOPNOTSUPP;
3570
3571         mv88e6xxx_reg_lock(chip);
3572         err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3573         mv88e6xxx_reg_unlock(chip);
3574
3575         return err;
3576 }
3577
3578 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3579                                    struct device_node *np,
3580                                    bool external)
3581 {
3582         static int index;
3583         struct mv88e6xxx_mdio_bus *mdio_bus;
3584         struct mii_bus *bus;
3585         int err;
3586
3587         if (external) {
3588                 mv88e6xxx_reg_lock(chip);
3589                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3590                 mv88e6xxx_reg_unlock(chip);
3591
3592                 if (err)
3593                         return err;
3594         }
3595
3596         bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3597         if (!bus)
3598                 return -ENOMEM;
3599
3600         mdio_bus = bus->priv;
3601         mdio_bus->bus = bus;
3602         mdio_bus->chip = chip;
3603         INIT_LIST_HEAD(&mdio_bus->list);
3604         mdio_bus->external = external;
3605
3606         if (np) {
3607                 bus->name = np->full_name;
3608                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3609         } else {
3610                 bus->name = "mv88e6xxx SMI";
3611                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3612         }
3613
3614         bus->read = mv88e6xxx_mdio_read;
3615         bus->write = mv88e6xxx_mdio_write;
3616         bus->read_c45 = mv88e6xxx_mdio_read_c45;
3617         bus->write_c45 = mv88e6xxx_mdio_write_c45;
3618         bus->parent = chip->dev;
3619         bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3620                                  mv88e6xxx_num_ports(chip) - 1,
3621                                  chip->info->phy_base_addr);
3622
3623         if (!external) {
3624                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3625                 if (err)
3626                         goto out;
3627         }
3628
3629         err = of_mdiobus_register(bus, np);
3630         if (err) {
3631                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3632                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3633                 goto out;
3634         }
3635
3636         if (external)
3637                 list_add_tail(&mdio_bus->list, &chip->mdios);
3638         else
3639                 list_add(&mdio_bus->list, &chip->mdios);
3640
3641         return 0;
3642
3643 out:
3644         mdiobus_free(bus);
3645         return err;
3646 }
3647
3648 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3649
3650 {
3651         struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3652         struct mii_bus *bus;
3653
3654         list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3655                 bus = mdio_bus->bus;
3656
3657                 if (!mdio_bus->external)
3658                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3659
3660                 mdiobus_unregister(bus);
3661                 mdiobus_free(bus);
3662         }
3663 }
3664
3665 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3666 {
3667         struct device_node *np = chip->dev->of_node;
3668         struct device_node *child;
3669         int err;
3670
3671         /* Always register one mdio bus for the internal/default mdio
3672          * bus. This maybe represented in the device tree, but is
3673          * optional.
3674          */
3675         child = of_get_child_by_name(np, "mdio");
3676         err = mv88e6xxx_mdio_register(chip, child, false);
3677         of_node_put(child);
3678         if (err)
3679                 return err;
3680
3681         /* Walk the device tree, and see if there are any other nodes
3682          * which say they are compatible with the external mdio
3683          * bus.
3684          */
3685         for_each_available_child_of_node(np, child) {
3686                 if (of_device_is_compatible(
3687                             child, "marvell,mv88e6xxx-mdio-external")) {
3688                         err = mv88e6xxx_mdio_register(chip, child, true);
3689                         if (err) {
3690                                 mv88e6xxx_mdios_unregister(chip);
3691                                 of_node_put(child);
3692                                 return err;
3693                         }
3694                 }
3695         }
3696
3697         return 0;
3698 }
3699
3700 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3701 {
3702         struct mv88e6xxx_chip *chip = ds->priv;
3703
3704         mv88e6xxx_teardown_devlink_params(ds);
3705         dsa_devlink_resources_unregister(ds);
3706         mv88e6xxx_teardown_devlink_regions_global(ds);
3707         mv88e6xxx_mdios_unregister(chip);
3708 }
3709
3710 static int mv88e6xxx_setup(struct dsa_switch *ds)
3711 {
3712         struct mv88e6xxx_chip *chip = ds->priv;
3713         u8 cmode;
3714         int err;
3715         int i;
3716
3717         err = mv88e6xxx_mdios_register(chip);
3718         if (err)
3719                 return err;
3720
3721         chip->ds = ds;
3722         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3723
3724         /* Since virtual bridges are mapped in the PVT, the number we support
3725          * depends on the physical switch topology. We need to let DSA figure
3726          * that out and therefore we cannot set this at dsa_register_switch()
3727          * time.
3728          */
3729         if (mv88e6xxx_has_pvt(chip))
3730                 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3731                                       ds->dst->last_switch - 1;
3732
3733         mv88e6xxx_reg_lock(chip);
3734
3735         if (chip->info->ops->setup_errata) {
3736                 err = chip->info->ops->setup_errata(chip);
3737                 if (err)
3738                         goto unlock;
3739         }
3740
3741         /* Cache the cmode of each port. */
3742         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3743                 if (chip->info->ops->port_get_cmode) {
3744                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3745                         if (err)
3746                                 goto unlock;
3747
3748                         chip->ports[i].cmode = cmode;
3749                 }
3750         }
3751
3752         err = mv88e6xxx_vtu_setup(chip);
3753         if (err)
3754                 goto unlock;
3755
3756         /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3757          * VTU, thereby also flushing the STU).
3758          */
3759         err = mv88e6xxx_stu_setup(chip);
3760         if (err)
3761                 goto unlock;
3762
3763         /* Setup Switch Port Registers */
3764         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3765                 if (dsa_is_unused_port(ds, i))
3766                         continue;
3767
3768                 /* Prevent the use of an invalid port. */
3769                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3770                         dev_err(chip->dev, "port %d is invalid\n", i);
3771                         err = -EINVAL;
3772                         goto unlock;
3773                 }
3774
3775                 err = mv88e6xxx_setup_port(chip, i);
3776                 if (err)
3777                         goto unlock;
3778         }
3779
3780         err = mv88e6xxx_irl_setup(chip);
3781         if (err)
3782                 goto unlock;
3783
3784         err = mv88e6xxx_mac_setup(chip);
3785         if (err)
3786                 goto unlock;
3787
3788         err = mv88e6xxx_phy_setup(chip);
3789         if (err)
3790                 goto unlock;
3791
3792         err = mv88e6xxx_pvt_setup(chip);
3793         if (err)
3794                 goto unlock;
3795
3796         err = mv88e6xxx_atu_setup(chip);
3797         if (err)
3798                 goto unlock;
3799
3800         err = mv88e6xxx_broadcast_setup(chip, 0);
3801         if (err)
3802                 goto unlock;
3803
3804         err = mv88e6xxx_pot_setup(chip);
3805         if (err)
3806                 goto unlock;
3807
3808         err = mv88e6xxx_rmu_setup(chip);
3809         if (err)
3810                 goto unlock;
3811
3812         err = mv88e6xxx_rsvd2cpu_setup(chip);
3813         if (err)
3814                 goto unlock;
3815
3816         err = mv88e6xxx_trunk_setup(chip);
3817         if (err)
3818                 goto unlock;
3819
3820         err = mv88e6xxx_devmap_setup(chip);
3821         if (err)
3822                 goto unlock;
3823
3824         err = mv88e6xxx_pri_setup(chip);
3825         if (err)
3826                 goto unlock;
3827
3828         /* Setup PTP Hardware Clock and timestamping */
3829         if (chip->info->ptp_support) {
3830                 err = mv88e6xxx_ptp_setup(chip);
3831                 if (err)
3832                         goto unlock;
3833
3834                 err = mv88e6xxx_hwtstamp_setup(chip);
3835                 if (err)
3836                         goto unlock;
3837         }
3838
3839         err = mv88e6xxx_stats_setup(chip);
3840         if (err)
3841                 goto unlock;
3842
3843 unlock:
3844         mv88e6xxx_reg_unlock(chip);
3845
3846         if (err)
3847                 goto out_mdios;
3848
3849         /* Have to be called without holding the register lock, since
3850          * they take the devlink lock, and we later take the locks in
3851          * the reverse order when getting/setting parameters or
3852          * resource occupancy.
3853          */
3854         err = mv88e6xxx_setup_devlink_resources(ds);
3855         if (err)
3856                 goto out_mdios;
3857
3858         err = mv88e6xxx_setup_devlink_params(ds);
3859         if (err)
3860                 goto out_resources;
3861
3862         err = mv88e6xxx_setup_devlink_regions_global(ds);
3863         if (err)
3864                 goto out_params;
3865
3866         return 0;
3867
3868 out_params:
3869         mv88e6xxx_teardown_devlink_params(ds);
3870 out_resources:
3871         dsa_devlink_resources_unregister(ds);
3872 out_mdios:
3873         mv88e6xxx_mdios_unregister(chip);
3874
3875         return err;
3876 }
3877
3878 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3879 {
3880         struct mv88e6xxx_chip *chip = ds->priv;
3881         int err;
3882
3883         if (chip->info->ops->pcs_ops->pcs_init) {
3884                 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
3885                 if (err)
3886                         return err;
3887         }
3888
3889         return mv88e6xxx_setup_devlink_regions_port(ds, port);
3890 }
3891
3892 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3893 {
3894         struct mv88e6xxx_chip *chip = ds->priv;
3895
3896         mv88e6xxx_teardown_devlink_regions_port(ds, port);
3897
3898         if (chip->info->ops->pcs_ops->pcs_teardown)
3899                 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
3900 }
3901
3902 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3903 {
3904         struct mv88e6xxx_chip *chip = ds->priv;
3905
3906         return chip->eeprom_len;
3907 }
3908
3909 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3910                                 struct ethtool_eeprom *eeprom, u8 *data)
3911 {
3912         struct mv88e6xxx_chip *chip = ds->priv;
3913         int err;
3914
3915         if (!chip->info->ops->get_eeprom)
3916                 return -EOPNOTSUPP;
3917
3918         mv88e6xxx_reg_lock(chip);
3919         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3920         mv88e6xxx_reg_unlock(chip);
3921
3922         if (err)
3923                 return err;
3924
3925         eeprom->magic = 0xc3ec4951;
3926
3927         return 0;
3928 }
3929
3930 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3931                                 struct ethtool_eeprom *eeprom, u8 *data)
3932 {
3933         struct mv88e6xxx_chip *chip = ds->priv;
3934         int err;
3935
3936         if (!chip->info->ops->set_eeprom)
3937                 return -EOPNOTSUPP;
3938
3939         if (eeprom->magic != 0xc3ec4951)
3940                 return -EINVAL;
3941
3942         mv88e6xxx_reg_lock(chip);
3943         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3944         mv88e6xxx_reg_unlock(chip);
3945
3946         return err;
3947 }
3948
3949 static const struct mv88e6xxx_ops mv88e6085_ops = {
3950         /* MV88E6XXX_FAMILY_6097 */
3951         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3952         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3953         .irl_init_all = mv88e6352_g2_irl_init_all,
3954         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3955         .phy_read = mv88e6185_phy_ppu_read,
3956         .phy_write = mv88e6185_phy_ppu_write,
3957         .port_set_link = mv88e6xxx_port_set_link,
3958         .port_sync_link = mv88e6xxx_port_sync_link,
3959         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3960         .port_tag_remap = mv88e6095_port_tag_remap,
3961         .port_set_policy = mv88e6352_port_set_policy,
3962         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3963         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3964         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3965         .port_set_ether_type = mv88e6351_port_set_ether_type,
3966         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3967         .port_pause_limit = mv88e6097_port_pause_limit,
3968         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3969         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3970         .port_get_cmode = mv88e6185_port_get_cmode,
3971         .port_setup_message_port = mv88e6xxx_setup_message_port,
3972         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3973         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3974         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3975         .stats_get_strings = mv88e6095_stats_get_strings,
3976         .stats_get_stats = mv88e6095_stats_get_stats,
3977         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3978         .set_egress_port = mv88e6095_g1_set_egress_port,
3979         .watchdog_ops = &mv88e6097_watchdog_ops,
3980         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3981         .pot_clear = mv88e6xxx_g2_pot_clear,
3982         .ppu_enable = mv88e6185_g1_ppu_enable,
3983         .ppu_disable = mv88e6185_g1_ppu_disable,
3984         .reset = mv88e6185_g1_reset,
3985         .rmu_disable = mv88e6085_g1_rmu_disable,
3986         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3987         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3988         .stu_getnext = mv88e6352_g1_stu_getnext,
3989         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
3990         .phylink_get_caps = mv88e6185_phylink_get_caps,
3991         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3992 };
3993
3994 static const struct mv88e6xxx_ops mv88e6095_ops = {
3995         /* MV88E6XXX_FAMILY_6095 */
3996         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3997         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3998         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3999         .phy_read = mv88e6185_phy_ppu_read,
4000         .phy_write = mv88e6185_phy_ppu_write,
4001         .port_set_link = mv88e6xxx_port_set_link,
4002         .port_sync_link = mv88e6185_port_sync_link,
4003         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4004         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4005         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4006         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4007         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4008         .port_get_cmode = mv88e6185_port_get_cmode,
4009         .port_setup_message_port = mv88e6xxx_setup_message_port,
4010         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4011         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4012         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4013         .stats_get_strings = mv88e6095_stats_get_strings,
4014         .stats_get_stats = mv88e6095_stats_get_stats,
4015         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4016         .ppu_enable = mv88e6185_g1_ppu_enable,
4017         .ppu_disable = mv88e6185_g1_ppu_disable,
4018         .reset = mv88e6185_g1_reset,
4019         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4020         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4021         .phylink_get_caps = mv88e6095_phylink_get_caps,
4022         .pcs_ops = &mv88e6185_pcs_ops,
4023         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4024 };
4025
4026 static const struct mv88e6xxx_ops mv88e6097_ops = {
4027         /* MV88E6XXX_FAMILY_6097 */
4028         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4029         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4030         .irl_init_all = mv88e6352_g2_irl_init_all,
4031         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4032         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4033         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4034         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4035         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4036         .port_set_link = mv88e6xxx_port_set_link,
4037         .port_sync_link = mv88e6185_port_sync_link,
4038         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4039         .port_tag_remap = mv88e6095_port_tag_remap,
4040         .port_set_policy = mv88e6352_port_set_policy,
4041         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4042         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4043         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4044         .port_set_ether_type = mv88e6351_port_set_ether_type,
4045         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4046         .port_pause_limit = mv88e6097_port_pause_limit,
4047         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4048         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4049         .port_get_cmode = mv88e6185_port_get_cmode,
4050         .port_setup_message_port = mv88e6xxx_setup_message_port,
4051         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4052         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4053         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4054         .stats_get_strings = mv88e6095_stats_get_strings,
4055         .stats_get_stats = mv88e6095_stats_get_stats,
4056         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4057         .set_egress_port = mv88e6095_g1_set_egress_port,
4058         .watchdog_ops = &mv88e6097_watchdog_ops,
4059         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4060         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4061         .pot_clear = mv88e6xxx_g2_pot_clear,
4062         .reset = mv88e6352_g1_reset,
4063         .rmu_disable = mv88e6085_g1_rmu_disable,
4064         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4065         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4066         .phylink_get_caps = mv88e6095_phylink_get_caps,
4067         .pcs_ops = &mv88e6185_pcs_ops,
4068         .stu_getnext = mv88e6352_g1_stu_getnext,
4069         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4070         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4071 };
4072
4073 static const struct mv88e6xxx_ops mv88e6123_ops = {
4074         /* MV88E6XXX_FAMILY_6165 */
4075         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4076         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4077         .irl_init_all = mv88e6352_g2_irl_init_all,
4078         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4079         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4080         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4081         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4082         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4083         .port_set_link = mv88e6xxx_port_set_link,
4084         .port_sync_link = mv88e6xxx_port_sync_link,
4085         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4086         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4087         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4088         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4089         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4090         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4091         .port_get_cmode = mv88e6185_port_get_cmode,
4092         .port_setup_message_port = mv88e6xxx_setup_message_port,
4093         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4094         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4095         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4096         .stats_get_strings = mv88e6095_stats_get_strings,
4097         .stats_get_stats = mv88e6095_stats_get_stats,
4098         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4099         .set_egress_port = mv88e6095_g1_set_egress_port,
4100         .watchdog_ops = &mv88e6097_watchdog_ops,
4101         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4102         .pot_clear = mv88e6xxx_g2_pot_clear,
4103         .reset = mv88e6352_g1_reset,
4104         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4105         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4106         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4107         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4108         .stu_getnext = mv88e6352_g1_stu_getnext,
4109         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4110         .phylink_get_caps = mv88e6185_phylink_get_caps,
4111         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4112 };
4113
4114 static const struct mv88e6xxx_ops mv88e6131_ops = {
4115         /* MV88E6XXX_FAMILY_6185 */
4116         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4117         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4118         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4119         .phy_read = mv88e6185_phy_ppu_read,
4120         .phy_write = mv88e6185_phy_ppu_write,
4121         .port_set_link = mv88e6xxx_port_set_link,
4122         .port_sync_link = mv88e6xxx_port_sync_link,
4123         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4124         .port_tag_remap = mv88e6095_port_tag_remap,
4125         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4126         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4127         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4128         .port_set_ether_type = mv88e6351_port_set_ether_type,
4129         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4130         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4131         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4132         .port_pause_limit = mv88e6097_port_pause_limit,
4133         .port_set_pause = mv88e6185_port_set_pause,
4134         .port_get_cmode = mv88e6185_port_get_cmode,
4135         .port_setup_message_port = mv88e6xxx_setup_message_port,
4136         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4137         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4138         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4139         .stats_get_strings = mv88e6095_stats_get_strings,
4140         .stats_get_stats = mv88e6095_stats_get_stats,
4141         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4142         .set_egress_port = mv88e6095_g1_set_egress_port,
4143         .watchdog_ops = &mv88e6097_watchdog_ops,
4144         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4145         .ppu_enable = mv88e6185_g1_ppu_enable,
4146         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4147         .ppu_disable = mv88e6185_g1_ppu_disable,
4148         .reset = mv88e6185_g1_reset,
4149         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4150         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4151         .phylink_get_caps = mv88e6185_phylink_get_caps,
4152 };
4153
4154 static const struct mv88e6xxx_ops mv88e6141_ops = {
4155         /* MV88E6XXX_FAMILY_6341 */
4156         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4157         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4158         .irl_init_all = mv88e6352_g2_irl_init_all,
4159         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4160         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4161         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4162         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4163         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4164         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4165         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4166         .port_set_link = mv88e6xxx_port_set_link,
4167         .port_sync_link = mv88e6xxx_port_sync_link,
4168         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4169         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4170         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4171         .port_tag_remap = mv88e6095_port_tag_remap,
4172         .port_set_policy = mv88e6352_port_set_policy,
4173         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4174         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4175         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4176         .port_set_ether_type = mv88e6351_port_set_ether_type,
4177         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4178         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4179         .port_pause_limit = mv88e6097_port_pause_limit,
4180         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4181         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4182         .port_get_cmode = mv88e6352_port_get_cmode,
4183         .port_set_cmode = mv88e6341_port_set_cmode,
4184         .port_setup_message_port = mv88e6xxx_setup_message_port,
4185         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4186         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4187         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4188         .stats_get_strings = mv88e6320_stats_get_strings,
4189         .stats_get_stats = mv88e6390_stats_get_stats,
4190         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4191         .set_egress_port = mv88e6390_g1_set_egress_port,
4192         .watchdog_ops = &mv88e6390_watchdog_ops,
4193         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4194         .pot_clear = mv88e6xxx_g2_pot_clear,
4195         .reset = mv88e6352_g1_reset,
4196         .rmu_disable = mv88e6390_g1_rmu_disable,
4197         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4198         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4199         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4200         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4201         .stu_getnext = mv88e6352_g1_stu_getnext,
4202         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4203         .serdes_get_lane = mv88e6341_serdes_get_lane,
4204         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4205         .gpio_ops = &mv88e6352_gpio_ops,
4206         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4207         .serdes_get_strings = mv88e6390_serdes_get_strings,
4208         .serdes_get_stats = mv88e6390_serdes_get_stats,
4209         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4210         .serdes_get_regs = mv88e6390_serdes_get_regs,
4211         .phylink_get_caps = mv88e6341_phylink_get_caps,
4212         .pcs_ops = &mv88e6390_pcs_ops,
4213 };
4214
4215 static const struct mv88e6xxx_ops mv88e6161_ops = {
4216         /* MV88E6XXX_FAMILY_6165 */
4217         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4218         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4219         .irl_init_all = mv88e6352_g2_irl_init_all,
4220         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4221         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4222         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4223         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4224         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4225         .port_set_link = mv88e6xxx_port_set_link,
4226         .port_sync_link = mv88e6xxx_port_sync_link,
4227         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4228         .port_tag_remap = mv88e6095_port_tag_remap,
4229         .port_set_policy = mv88e6352_port_set_policy,
4230         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4231         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4232         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4233         .port_set_ether_type = mv88e6351_port_set_ether_type,
4234         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4235         .port_pause_limit = mv88e6097_port_pause_limit,
4236         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4237         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4238         .port_get_cmode = mv88e6185_port_get_cmode,
4239         .port_setup_message_port = mv88e6xxx_setup_message_port,
4240         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4241         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4242         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4243         .stats_get_strings = mv88e6095_stats_get_strings,
4244         .stats_get_stats = mv88e6095_stats_get_stats,
4245         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4246         .set_egress_port = mv88e6095_g1_set_egress_port,
4247         .watchdog_ops = &mv88e6097_watchdog_ops,
4248         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4249         .pot_clear = mv88e6xxx_g2_pot_clear,
4250         .reset = mv88e6352_g1_reset,
4251         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4252         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4253         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4254         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4255         .stu_getnext = mv88e6352_g1_stu_getnext,
4256         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4257         .avb_ops = &mv88e6165_avb_ops,
4258         .ptp_ops = &mv88e6165_ptp_ops,
4259         .phylink_get_caps = mv88e6185_phylink_get_caps,
4260         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4261 };
4262
4263 static const struct mv88e6xxx_ops mv88e6165_ops = {
4264         /* MV88E6XXX_FAMILY_6165 */
4265         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4266         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4267         .irl_init_all = mv88e6352_g2_irl_init_all,
4268         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4269         .phy_read = mv88e6165_phy_read,
4270         .phy_write = mv88e6165_phy_write,
4271         .port_set_link = mv88e6xxx_port_set_link,
4272         .port_sync_link = mv88e6xxx_port_sync_link,
4273         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4274         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4275         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4276         .port_get_cmode = mv88e6185_port_get_cmode,
4277         .port_setup_message_port = mv88e6xxx_setup_message_port,
4278         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4279         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4280         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4281         .stats_get_strings = mv88e6095_stats_get_strings,
4282         .stats_get_stats = mv88e6095_stats_get_stats,
4283         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4284         .set_egress_port = mv88e6095_g1_set_egress_port,
4285         .watchdog_ops = &mv88e6097_watchdog_ops,
4286         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4287         .pot_clear = mv88e6xxx_g2_pot_clear,
4288         .reset = mv88e6352_g1_reset,
4289         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4290         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4291         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4292         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4293         .stu_getnext = mv88e6352_g1_stu_getnext,
4294         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4295         .avb_ops = &mv88e6165_avb_ops,
4296         .ptp_ops = &mv88e6165_ptp_ops,
4297         .phylink_get_caps = mv88e6185_phylink_get_caps,
4298 };
4299
4300 static const struct mv88e6xxx_ops mv88e6171_ops = {
4301         /* MV88E6XXX_FAMILY_6351 */
4302         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4303         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4304         .irl_init_all = mv88e6352_g2_irl_init_all,
4305         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4306         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4307         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4308         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4309         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4310         .port_set_link = mv88e6xxx_port_set_link,
4311         .port_sync_link = mv88e6xxx_port_sync_link,
4312         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4313         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4314         .port_tag_remap = mv88e6095_port_tag_remap,
4315         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4316         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4317         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4318         .port_set_ether_type = mv88e6351_port_set_ether_type,
4319         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4320         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4321         .port_pause_limit = mv88e6097_port_pause_limit,
4322         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4323         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4324         .port_get_cmode = mv88e6352_port_get_cmode,
4325         .port_setup_message_port = mv88e6xxx_setup_message_port,
4326         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4327         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4328         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4329         .stats_get_strings = mv88e6095_stats_get_strings,
4330         .stats_get_stats = mv88e6095_stats_get_stats,
4331         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4332         .set_egress_port = mv88e6095_g1_set_egress_port,
4333         .watchdog_ops = &mv88e6097_watchdog_ops,
4334         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4335         .pot_clear = mv88e6xxx_g2_pot_clear,
4336         .reset = mv88e6352_g1_reset,
4337         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4338         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4339         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4340         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4341         .stu_getnext = mv88e6352_g1_stu_getnext,
4342         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4343         .phylink_get_caps = mv88e6185_phylink_get_caps,
4344 };
4345
4346 static const struct mv88e6xxx_ops mv88e6172_ops = {
4347         /* MV88E6XXX_FAMILY_6352 */
4348         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4349         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4350         .irl_init_all = mv88e6352_g2_irl_init_all,
4351         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4352         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4353         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4354         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4355         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4356         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4357         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4358         .port_set_link = mv88e6xxx_port_set_link,
4359         .port_sync_link = mv88e6xxx_port_sync_link,
4360         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4361         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4362         .port_tag_remap = mv88e6095_port_tag_remap,
4363         .port_set_policy = mv88e6352_port_set_policy,
4364         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4365         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4366         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4367         .port_set_ether_type = mv88e6351_port_set_ether_type,
4368         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4369         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4370         .port_pause_limit = mv88e6097_port_pause_limit,
4371         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4372         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4373         .port_get_cmode = mv88e6352_port_get_cmode,
4374         .port_setup_message_port = mv88e6xxx_setup_message_port,
4375         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4376         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4377         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4378         .stats_get_strings = mv88e6095_stats_get_strings,
4379         .stats_get_stats = mv88e6095_stats_get_stats,
4380         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4381         .set_egress_port = mv88e6095_g1_set_egress_port,
4382         .watchdog_ops = &mv88e6097_watchdog_ops,
4383         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4384         .pot_clear = mv88e6xxx_g2_pot_clear,
4385         .reset = mv88e6352_g1_reset,
4386         .rmu_disable = mv88e6352_g1_rmu_disable,
4387         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4388         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4389         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4390         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4391         .stu_getnext = mv88e6352_g1_stu_getnext,
4392         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4393         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4394         .serdes_get_regs = mv88e6352_serdes_get_regs,
4395         .gpio_ops = &mv88e6352_gpio_ops,
4396         .phylink_get_caps = mv88e6352_phylink_get_caps,
4397         .pcs_ops = &mv88e6352_pcs_ops,
4398 };
4399
4400 static const struct mv88e6xxx_ops mv88e6175_ops = {
4401         /* MV88E6XXX_FAMILY_6351 */
4402         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4403         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4404         .irl_init_all = mv88e6352_g2_irl_init_all,
4405         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4406         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4407         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4408         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4409         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4410         .port_set_link = mv88e6xxx_port_set_link,
4411         .port_sync_link = mv88e6xxx_port_sync_link,
4412         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4413         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4414         .port_tag_remap = mv88e6095_port_tag_remap,
4415         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4416         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4417         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4418         .port_set_ether_type = mv88e6351_port_set_ether_type,
4419         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4420         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4421         .port_pause_limit = mv88e6097_port_pause_limit,
4422         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4423         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4424         .port_get_cmode = mv88e6352_port_get_cmode,
4425         .port_setup_message_port = mv88e6xxx_setup_message_port,
4426         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4427         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4428         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4429         .stats_get_strings = mv88e6095_stats_get_strings,
4430         .stats_get_stats = mv88e6095_stats_get_stats,
4431         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4432         .set_egress_port = mv88e6095_g1_set_egress_port,
4433         .watchdog_ops = &mv88e6097_watchdog_ops,
4434         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4435         .pot_clear = mv88e6xxx_g2_pot_clear,
4436         .reset = mv88e6352_g1_reset,
4437         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4438         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4439         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4440         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4441         .stu_getnext = mv88e6352_g1_stu_getnext,
4442         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4443         .phylink_get_caps = mv88e6185_phylink_get_caps,
4444 };
4445
4446 static const struct mv88e6xxx_ops mv88e6176_ops = {
4447         /* MV88E6XXX_FAMILY_6352 */
4448         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4449         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4450         .irl_init_all = mv88e6352_g2_irl_init_all,
4451         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4452         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4453         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4454         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4455         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4456         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4457         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4458         .port_set_link = mv88e6xxx_port_set_link,
4459         .port_sync_link = mv88e6xxx_port_sync_link,
4460         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4461         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4462         .port_tag_remap = mv88e6095_port_tag_remap,
4463         .port_set_policy = mv88e6352_port_set_policy,
4464         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4465         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4466         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4467         .port_set_ether_type = mv88e6351_port_set_ether_type,
4468         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4469         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4470         .port_pause_limit = mv88e6097_port_pause_limit,
4471         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4472         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4473         .port_get_cmode = mv88e6352_port_get_cmode,
4474         .port_setup_message_port = mv88e6xxx_setup_message_port,
4475         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4476         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4477         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4478         .stats_get_strings = mv88e6095_stats_get_strings,
4479         .stats_get_stats = mv88e6095_stats_get_stats,
4480         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4481         .set_egress_port = mv88e6095_g1_set_egress_port,
4482         .watchdog_ops = &mv88e6097_watchdog_ops,
4483         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4484         .pot_clear = mv88e6xxx_g2_pot_clear,
4485         .reset = mv88e6352_g1_reset,
4486         .rmu_disable = mv88e6352_g1_rmu_disable,
4487         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4488         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4489         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4490         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4491         .stu_getnext = mv88e6352_g1_stu_getnext,
4492         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4493         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4494         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4495         .serdes_get_regs = mv88e6352_serdes_get_regs,
4496         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4497         .gpio_ops = &mv88e6352_gpio_ops,
4498         .phylink_get_caps = mv88e6352_phylink_get_caps,
4499         .pcs_ops = &mv88e6352_pcs_ops,
4500 };
4501
4502 static const struct mv88e6xxx_ops mv88e6185_ops = {
4503         /* MV88E6XXX_FAMILY_6185 */
4504         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4505         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4506         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4507         .phy_read = mv88e6185_phy_ppu_read,
4508         .phy_write = mv88e6185_phy_ppu_write,
4509         .port_set_link = mv88e6xxx_port_set_link,
4510         .port_sync_link = mv88e6185_port_sync_link,
4511         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4512         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4513         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4514         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4515         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4516         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4517         .port_set_pause = mv88e6185_port_set_pause,
4518         .port_get_cmode = mv88e6185_port_get_cmode,
4519         .port_setup_message_port = mv88e6xxx_setup_message_port,
4520         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4521         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4522         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4523         .stats_get_strings = mv88e6095_stats_get_strings,
4524         .stats_get_stats = mv88e6095_stats_get_stats,
4525         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4526         .set_egress_port = mv88e6095_g1_set_egress_port,
4527         .watchdog_ops = &mv88e6097_watchdog_ops,
4528         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4529         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4530         .ppu_enable = mv88e6185_g1_ppu_enable,
4531         .ppu_disable = mv88e6185_g1_ppu_disable,
4532         .reset = mv88e6185_g1_reset,
4533         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4534         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4535         .phylink_get_caps = mv88e6185_phylink_get_caps,
4536         .pcs_ops = &mv88e6185_pcs_ops,
4537         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4538 };
4539
4540 static const struct mv88e6xxx_ops mv88e6190_ops = {
4541         /* MV88E6XXX_FAMILY_6390 */
4542         .setup_errata = mv88e6390_setup_errata,
4543         .irl_init_all = mv88e6390_g2_irl_init_all,
4544         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4545         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4546         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4547         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4548         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4549         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4550         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4551         .port_set_link = mv88e6xxx_port_set_link,
4552         .port_sync_link = mv88e6xxx_port_sync_link,
4553         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4554         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4555         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4556         .port_tag_remap = mv88e6390_port_tag_remap,
4557         .port_set_policy = mv88e6352_port_set_policy,
4558         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4559         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4560         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4561         .port_set_ether_type = mv88e6351_port_set_ether_type,
4562         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4563         .port_pause_limit = mv88e6390_port_pause_limit,
4564         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4565         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4566         .port_get_cmode = mv88e6352_port_get_cmode,
4567         .port_set_cmode = mv88e6390_port_set_cmode,
4568         .port_setup_message_port = mv88e6xxx_setup_message_port,
4569         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4570         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4571         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4572         .stats_get_strings = mv88e6320_stats_get_strings,
4573         .stats_get_stats = mv88e6390_stats_get_stats,
4574         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4575         .set_egress_port = mv88e6390_g1_set_egress_port,
4576         .watchdog_ops = &mv88e6390_watchdog_ops,
4577         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4578         .pot_clear = mv88e6xxx_g2_pot_clear,
4579         .reset = mv88e6352_g1_reset,
4580         .rmu_disable = mv88e6390_g1_rmu_disable,
4581         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4582         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4583         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4584         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4585         .stu_getnext = mv88e6390_g1_stu_getnext,
4586         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4587         .serdes_get_lane = mv88e6390_serdes_get_lane,
4588         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4589         .serdes_get_strings = mv88e6390_serdes_get_strings,
4590         .serdes_get_stats = mv88e6390_serdes_get_stats,
4591         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4592         .serdes_get_regs = mv88e6390_serdes_get_regs,
4593         .gpio_ops = &mv88e6352_gpio_ops,
4594         .phylink_get_caps = mv88e6390_phylink_get_caps,
4595         .pcs_ops = &mv88e6390_pcs_ops,
4596 };
4597
4598 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4599         /* MV88E6XXX_FAMILY_6390 */
4600         .setup_errata = mv88e6390_setup_errata,
4601         .irl_init_all = mv88e6390_g2_irl_init_all,
4602         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4603         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4604         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4605         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4606         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4607         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4608         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4609         .port_set_link = mv88e6xxx_port_set_link,
4610         .port_sync_link = mv88e6xxx_port_sync_link,
4611         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4612         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4613         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4614         .port_tag_remap = mv88e6390_port_tag_remap,
4615         .port_set_policy = mv88e6352_port_set_policy,
4616         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4617         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4618         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4619         .port_set_ether_type = mv88e6351_port_set_ether_type,
4620         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4621         .port_pause_limit = mv88e6390_port_pause_limit,
4622         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4623         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4624         .port_get_cmode = mv88e6352_port_get_cmode,
4625         .port_set_cmode = mv88e6390x_port_set_cmode,
4626         .port_setup_message_port = mv88e6xxx_setup_message_port,
4627         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4628         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4629         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4630         .stats_get_strings = mv88e6320_stats_get_strings,
4631         .stats_get_stats = mv88e6390_stats_get_stats,
4632         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4633         .set_egress_port = mv88e6390_g1_set_egress_port,
4634         .watchdog_ops = &mv88e6390_watchdog_ops,
4635         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4636         .pot_clear = mv88e6xxx_g2_pot_clear,
4637         .reset = mv88e6352_g1_reset,
4638         .rmu_disable = mv88e6390_g1_rmu_disable,
4639         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4640         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4641         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4642         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4643         .stu_getnext = mv88e6390_g1_stu_getnext,
4644         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4645         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4646         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4647         .serdes_get_strings = mv88e6390_serdes_get_strings,
4648         .serdes_get_stats = mv88e6390_serdes_get_stats,
4649         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4650         .serdes_get_regs = mv88e6390_serdes_get_regs,
4651         .gpio_ops = &mv88e6352_gpio_ops,
4652         .phylink_get_caps = mv88e6390x_phylink_get_caps,
4653         .pcs_ops = &mv88e6390_pcs_ops,
4654 };
4655
4656 static const struct mv88e6xxx_ops mv88e6191_ops = {
4657         /* MV88E6XXX_FAMILY_6390 */
4658         .setup_errata = mv88e6390_setup_errata,
4659         .irl_init_all = mv88e6390_g2_irl_init_all,
4660         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4661         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4662         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4663         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4664         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4665         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4666         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4667         .port_set_link = mv88e6xxx_port_set_link,
4668         .port_sync_link = mv88e6xxx_port_sync_link,
4669         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4670         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4671         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4672         .port_tag_remap = mv88e6390_port_tag_remap,
4673         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4674         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4675         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4676         .port_set_ether_type = mv88e6351_port_set_ether_type,
4677         .port_pause_limit = mv88e6390_port_pause_limit,
4678         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4679         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4680         .port_get_cmode = mv88e6352_port_get_cmode,
4681         .port_set_cmode = mv88e6390_port_set_cmode,
4682         .port_setup_message_port = mv88e6xxx_setup_message_port,
4683         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4684         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4685         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4686         .stats_get_strings = mv88e6320_stats_get_strings,
4687         .stats_get_stats = mv88e6390_stats_get_stats,
4688         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4689         .set_egress_port = mv88e6390_g1_set_egress_port,
4690         .watchdog_ops = &mv88e6390_watchdog_ops,
4691         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4692         .pot_clear = mv88e6xxx_g2_pot_clear,
4693         .reset = mv88e6352_g1_reset,
4694         .rmu_disable = mv88e6390_g1_rmu_disable,
4695         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4696         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4697         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4698         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4699         .stu_getnext = mv88e6390_g1_stu_getnext,
4700         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4701         .serdes_get_lane = mv88e6390_serdes_get_lane,
4702         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4703         .serdes_get_strings = mv88e6390_serdes_get_strings,
4704         .serdes_get_stats = mv88e6390_serdes_get_stats,
4705         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4706         .serdes_get_regs = mv88e6390_serdes_get_regs,
4707         .avb_ops = &mv88e6390_avb_ops,
4708         .ptp_ops = &mv88e6352_ptp_ops,
4709         .phylink_get_caps = mv88e6390_phylink_get_caps,
4710         .pcs_ops = &mv88e6390_pcs_ops,
4711 };
4712
4713 static const struct mv88e6xxx_ops mv88e6240_ops = {
4714         /* MV88E6XXX_FAMILY_6352 */
4715         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4716         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4717         .irl_init_all = mv88e6352_g2_irl_init_all,
4718         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4719         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4720         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4721         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4722         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4723         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4724         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4725         .port_set_link = mv88e6xxx_port_set_link,
4726         .port_sync_link = mv88e6xxx_port_sync_link,
4727         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4728         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4729         .port_tag_remap = mv88e6095_port_tag_remap,
4730         .port_set_policy = mv88e6352_port_set_policy,
4731         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4732         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4733         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4734         .port_set_ether_type = mv88e6351_port_set_ether_type,
4735         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4736         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4737         .port_pause_limit = mv88e6097_port_pause_limit,
4738         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4739         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4740         .port_get_cmode = mv88e6352_port_get_cmode,
4741         .port_setup_message_port = mv88e6xxx_setup_message_port,
4742         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4743         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4744         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4745         .stats_get_strings = mv88e6095_stats_get_strings,
4746         .stats_get_stats = mv88e6095_stats_get_stats,
4747         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4748         .set_egress_port = mv88e6095_g1_set_egress_port,
4749         .watchdog_ops = &mv88e6097_watchdog_ops,
4750         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4751         .pot_clear = mv88e6xxx_g2_pot_clear,
4752         .reset = mv88e6352_g1_reset,
4753         .rmu_disable = mv88e6352_g1_rmu_disable,
4754         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4755         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4756         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4757         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4758         .stu_getnext = mv88e6352_g1_stu_getnext,
4759         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4760         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4761         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4762         .serdes_get_regs = mv88e6352_serdes_get_regs,
4763         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4764         .gpio_ops = &mv88e6352_gpio_ops,
4765         .avb_ops = &mv88e6352_avb_ops,
4766         .ptp_ops = &mv88e6352_ptp_ops,
4767         .phylink_get_caps = mv88e6352_phylink_get_caps,
4768         .pcs_ops = &mv88e6352_pcs_ops,
4769 };
4770
4771 static const struct mv88e6xxx_ops mv88e6250_ops = {
4772         /* MV88E6XXX_FAMILY_6250 */
4773         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4774         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4775         .irl_init_all = mv88e6352_g2_irl_init_all,
4776         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4777         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4778         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4779         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4780         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4781         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4782         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4783         .port_set_link = mv88e6xxx_port_set_link,
4784         .port_sync_link = mv88e6xxx_port_sync_link,
4785         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4786         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4787         .port_tag_remap = mv88e6095_port_tag_remap,
4788         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4789         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4790         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4791         .port_set_ether_type = mv88e6351_port_set_ether_type,
4792         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4793         .port_pause_limit = mv88e6097_port_pause_limit,
4794         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4795         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4796         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4797         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4798         .stats_get_strings = mv88e6250_stats_get_strings,
4799         .stats_get_stats = mv88e6250_stats_get_stats,
4800         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4801         .set_egress_port = mv88e6095_g1_set_egress_port,
4802         .watchdog_ops = &mv88e6250_watchdog_ops,
4803         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4804         .pot_clear = mv88e6xxx_g2_pot_clear,
4805         .reset = mv88e6250_g1_reset,
4806         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4807         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4808         .avb_ops = &mv88e6352_avb_ops,
4809         .ptp_ops = &mv88e6250_ptp_ops,
4810         .phylink_get_caps = mv88e6250_phylink_get_caps,
4811         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4812 };
4813
4814 static const struct mv88e6xxx_ops mv88e6290_ops = {
4815         /* MV88E6XXX_FAMILY_6390 */
4816         .setup_errata = mv88e6390_setup_errata,
4817         .irl_init_all = mv88e6390_g2_irl_init_all,
4818         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4819         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4820         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4821         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4822         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4823         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4824         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4825         .port_set_link = mv88e6xxx_port_set_link,
4826         .port_sync_link = mv88e6xxx_port_sync_link,
4827         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4828         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4829         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4830         .port_tag_remap = mv88e6390_port_tag_remap,
4831         .port_set_policy = mv88e6352_port_set_policy,
4832         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4833         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4834         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4835         .port_set_ether_type = mv88e6351_port_set_ether_type,
4836         .port_pause_limit = mv88e6390_port_pause_limit,
4837         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4838         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4839         .port_get_cmode = mv88e6352_port_get_cmode,
4840         .port_set_cmode = mv88e6390_port_set_cmode,
4841         .port_setup_message_port = mv88e6xxx_setup_message_port,
4842         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4843         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4844         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4845         .stats_get_strings = mv88e6320_stats_get_strings,
4846         .stats_get_stats = mv88e6390_stats_get_stats,
4847         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4848         .set_egress_port = mv88e6390_g1_set_egress_port,
4849         .watchdog_ops = &mv88e6390_watchdog_ops,
4850         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4851         .pot_clear = mv88e6xxx_g2_pot_clear,
4852         .reset = mv88e6352_g1_reset,
4853         .rmu_disable = mv88e6390_g1_rmu_disable,
4854         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4855         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4856         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4857         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4858         .stu_getnext = mv88e6390_g1_stu_getnext,
4859         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4860         .serdes_get_lane = mv88e6390_serdes_get_lane,
4861         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4862         .serdes_get_strings = mv88e6390_serdes_get_strings,
4863         .serdes_get_stats = mv88e6390_serdes_get_stats,
4864         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4865         .serdes_get_regs = mv88e6390_serdes_get_regs,
4866         .gpio_ops = &mv88e6352_gpio_ops,
4867         .avb_ops = &mv88e6390_avb_ops,
4868         .ptp_ops = &mv88e6390_ptp_ops,
4869         .phylink_get_caps = mv88e6390_phylink_get_caps,
4870         .pcs_ops = &mv88e6390_pcs_ops,
4871 };
4872
4873 static const struct mv88e6xxx_ops mv88e6320_ops = {
4874         /* MV88E6XXX_FAMILY_6320 */
4875         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4876         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4877         .irl_init_all = mv88e6352_g2_irl_init_all,
4878         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4879         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4880         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4881         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4882         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4883         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4884         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4885         .port_set_link = mv88e6xxx_port_set_link,
4886         .port_sync_link = mv88e6xxx_port_sync_link,
4887         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
4888         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4889         .port_tag_remap = mv88e6095_port_tag_remap,
4890         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4891         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4892         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4893         .port_set_ether_type = mv88e6351_port_set_ether_type,
4894         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4895         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4896         .port_pause_limit = mv88e6097_port_pause_limit,
4897         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4898         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4899         .port_get_cmode = mv88e6352_port_get_cmode,
4900         .port_setup_message_port = mv88e6xxx_setup_message_port,
4901         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4902         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4903         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4904         .stats_get_strings = mv88e6320_stats_get_strings,
4905         .stats_get_stats = mv88e6320_stats_get_stats,
4906         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4907         .set_egress_port = mv88e6095_g1_set_egress_port,
4908         .watchdog_ops = &mv88e6390_watchdog_ops,
4909         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4910         .pot_clear = mv88e6xxx_g2_pot_clear,
4911         .reset = mv88e6352_g1_reset,
4912         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4913         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4914         .gpio_ops = &mv88e6352_gpio_ops,
4915         .avb_ops = &mv88e6352_avb_ops,
4916         .ptp_ops = &mv88e6352_ptp_ops,
4917         .phylink_get_caps = mv88e6185_phylink_get_caps,
4918 };
4919
4920 static const struct mv88e6xxx_ops mv88e6321_ops = {
4921         /* MV88E6XXX_FAMILY_6320 */
4922         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4923         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4924         .irl_init_all = mv88e6352_g2_irl_init_all,
4925         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4926         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4927         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4928         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4929         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4930         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4931         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4932         .port_set_link = mv88e6xxx_port_set_link,
4933         .port_sync_link = mv88e6xxx_port_sync_link,
4934         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
4935         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4936         .port_tag_remap = mv88e6095_port_tag_remap,
4937         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4938         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4939         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4940         .port_set_ether_type = mv88e6351_port_set_ether_type,
4941         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4942         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4943         .port_pause_limit = mv88e6097_port_pause_limit,
4944         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4945         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4946         .port_get_cmode = mv88e6352_port_get_cmode,
4947         .port_setup_message_port = mv88e6xxx_setup_message_port,
4948         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4949         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4950         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4951         .stats_get_strings = mv88e6320_stats_get_strings,
4952         .stats_get_stats = mv88e6320_stats_get_stats,
4953         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4954         .set_egress_port = mv88e6095_g1_set_egress_port,
4955         .watchdog_ops = &mv88e6390_watchdog_ops,
4956         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4957         .reset = mv88e6352_g1_reset,
4958         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4959         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4960         .gpio_ops = &mv88e6352_gpio_ops,
4961         .avb_ops = &mv88e6352_avb_ops,
4962         .ptp_ops = &mv88e6352_ptp_ops,
4963         .phylink_get_caps = mv88e6185_phylink_get_caps,
4964 };
4965
4966 static const struct mv88e6xxx_ops mv88e6341_ops = {
4967         /* MV88E6XXX_FAMILY_6341 */
4968         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4969         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4970         .irl_init_all = mv88e6352_g2_irl_init_all,
4971         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4972         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4973         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4974         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4975         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4976         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4977         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4978         .port_set_link = mv88e6xxx_port_set_link,
4979         .port_sync_link = mv88e6xxx_port_sync_link,
4980         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4981         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4982         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4983         .port_tag_remap = mv88e6095_port_tag_remap,
4984         .port_set_policy = mv88e6352_port_set_policy,
4985         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4986         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4987         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4988         .port_set_ether_type = mv88e6351_port_set_ether_type,
4989         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4990         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4991         .port_pause_limit = mv88e6097_port_pause_limit,
4992         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4993         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4994         .port_get_cmode = mv88e6352_port_get_cmode,
4995         .port_set_cmode = mv88e6341_port_set_cmode,
4996         .port_setup_message_port = mv88e6xxx_setup_message_port,
4997         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4998         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4999         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5000         .stats_get_strings = mv88e6320_stats_get_strings,
5001         .stats_get_stats = mv88e6390_stats_get_stats,
5002         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5003         .set_egress_port = mv88e6390_g1_set_egress_port,
5004         .watchdog_ops = &mv88e6390_watchdog_ops,
5005         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5006         .pot_clear = mv88e6xxx_g2_pot_clear,
5007         .reset = mv88e6352_g1_reset,
5008         .rmu_disable = mv88e6390_g1_rmu_disable,
5009         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5010         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5011         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5012         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5013         .stu_getnext = mv88e6352_g1_stu_getnext,
5014         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5015         .serdes_get_lane = mv88e6341_serdes_get_lane,
5016         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5017         .gpio_ops = &mv88e6352_gpio_ops,
5018         .avb_ops = &mv88e6390_avb_ops,
5019         .ptp_ops = &mv88e6352_ptp_ops,
5020         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5021         .serdes_get_strings = mv88e6390_serdes_get_strings,
5022         .serdes_get_stats = mv88e6390_serdes_get_stats,
5023         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5024         .serdes_get_regs = mv88e6390_serdes_get_regs,
5025         .phylink_get_caps = mv88e6341_phylink_get_caps,
5026         .pcs_ops = &mv88e6390_pcs_ops,
5027 };
5028
5029 static const struct mv88e6xxx_ops mv88e6350_ops = {
5030         /* MV88E6XXX_FAMILY_6351 */
5031         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5032         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5033         .irl_init_all = mv88e6352_g2_irl_init_all,
5034         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5035         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5036         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5037         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5038         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5039         .port_set_link = mv88e6xxx_port_set_link,
5040         .port_sync_link = mv88e6xxx_port_sync_link,
5041         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5042         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5043         .port_tag_remap = mv88e6095_port_tag_remap,
5044         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5045         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5046         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5047         .port_set_ether_type = mv88e6351_port_set_ether_type,
5048         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5049         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5050         .port_pause_limit = mv88e6097_port_pause_limit,
5051         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5052         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5053         .port_get_cmode = mv88e6352_port_get_cmode,
5054         .port_setup_message_port = mv88e6xxx_setup_message_port,
5055         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5056         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5057         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5058         .stats_get_strings = mv88e6095_stats_get_strings,
5059         .stats_get_stats = mv88e6095_stats_get_stats,
5060         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5061         .set_egress_port = mv88e6095_g1_set_egress_port,
5062         .watchdog_ops = &mv88e6097_watchdog_ops,
5063         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5064         .pot_clear = mv88e6xxx_g2_pot_clear,
5065         .reset = mv88e6352_g1_reset,
5066         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5067         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5068         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5069         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5070         .stu_getnext = mv88e6352_g1_stu_getnext,
5071         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5072         .phylink_get_caps = mv88e6185_phylink_get_caps,
5073 };
5074
5075 static const struct mv88e6xxx_ops mv88e6351_ops = {
5076         /* MV88E6XXX_FAMILY_6351 */
5077         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5078         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5079         .irl_init_all = mv88e6352_g2_irl_init_all,
5080         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5081         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5082         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5083         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5084         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5085         .port_set_link = mv88e6xxx_port_set_link,
5086         .port_sync_link = mv88e6xxx_port_sync_link,
5087         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5088         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5089         .port_tag_remap = mv88e6095_port_tag_remap,
5090         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5091         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5092         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5093         .port_set_ether_type = mv88e6351_port_set_ether_type,
5094         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5095         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5096         .port_pause_limit = mv88e6097_port_pause_limit,
5097         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5098         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5099         .port_get_cmode = mv88e6352_port_get_cmode,
5100         .port_setup_message_port = mv88e6xxx_setup_message_port,
5101         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5102         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5103         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5104         .stats_get_strings = mv88e6095_stats_get_strings,
5105         .stats_get_stats = mv88e6095_stats_get_stats,
5106         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5107         .set_egress_port = mv88e6095_g1_set_egress_port,
5108         .watchdog_ops = &mv88e6097_watchdog_ops,
5109         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5110         .pot_clear = mv88e6xxx_g2_pot_clear,
5111         .reset = mv88e6352_g1_reset,
5112         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5113         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5114         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5115         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5116         .stu_getnext = mv88e6352_g1_stu_getnext,
5117         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5118         .avb_ops = &mv88e6352_avb_ops,
5119         .ptp_ops = &mv88e6352_ptp_ops,
5120         .phylink_get_caps = mv88e6185_phylink_get_caps,
5121 };
5122
5123 static const struct mv88e6xxx_ops mv88e6352_ops = {
5124         /* MV88E6XXX_FAMILY_6352 */
5125         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5126         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5127         .irl_init_all = mv88e6352_g2_irl_init_all,
5128         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5129         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5130         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5131         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5132         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5133         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5134         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5135         .port_set_link = mv88e6xxx_port_set_link,
5136         .port_sync_link = mv88e6xxx_port_sync_link,
5137         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5138         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5139         .port_tag_remap = mv88e6095_port_tag_remap,
5140         .port_set_policy = mv88e6352_port_set_policy,
5141         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5142         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5143         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5144         .port_set_ether_type = mv88e6351_port_set_ether_type,
5145         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5146         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5147         .port_pause_limit = mv88e6097_port_pause_limit,
5148         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5149         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5150         .port_get_cmode = mv88e6352_port_get_cmode,
5151         .port_setup_message_port = mv88e6xxx_setup_message_port,
5152         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5153         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5154         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5155         .stats_get_strings = mv88e6095_stats_get_strings,
5156         .stats_get_stats = mv88e6095_stats_get_stats,
5157         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5158         .set_egress_port = mv88e6095_g1_set_egress_port,
5159         .watchdog_ops = &mv88e6097_watchdog_ops,
5160         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5161         .pot_clear = mv88e6xxx_g2_pot_clear,
5162         .reset = mv88e6352_g1_reset,
5163         .rmu_disable = mv88e6352_g1_rmu_disable,
5164         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5165         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5166         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5167         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5168         .stu_getnext = mv88e6352_g1_stu_getnext,
5169         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5170         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5171         .gpio_ops = &mv88e6352_gpio_ops,
5172         .avb_ops = &mv88e6352_avb_ops,
5173         .ptp_ops = &mv88e6352_ptp_ops,
5174         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5175         .serdes_get_strings = mv88e6352_serdes_get_strings,
5176         .serdes_get_stats = mv88e6352_serdes_get_stats,
5177         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5178         .serdes_get_regs = mv88e6352_serdes_get_regs,
5179         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5180         .phylink_get_caps = mv88e6352_phylink_get_caps,
5181         .pcs_ops = &mv88e6352_pcs_ops,
5182 };
5183
5184 static const struct mv88e6xxx_ops mv88e6390_ops = {
5185         /* MV88E6XXX_FAMILY_6390 */
5186         .setup_errata = mv88e6390_setup_errata,
5187         .irl_init_all = mv88e6390_g2_irl_init_all,
5188         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5189         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5190         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5191         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5192         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5193         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5194         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5195         .port_set_link = mv88e6xxx_port_set_link,
5196         .port_sync_link = mv88e6xxx_port_sync_link,
5197         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5198         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5199         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5200         .port_tag_remap = mv88e6390_port_tag_remap,
5201         .port_set_policy = mv88e6352_port_set_policy,
5202         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5203         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5204         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5205         .port_set_ether_type = mv88e6351_port_set_ether_type,
5206         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5207         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5208         .port_pause_limit = mv88e6390_port_pause_limit,
5209         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5210         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5211         .port_get_cmode = mv88e6352_port_get_cmode,
5212         .port_set_cmode = mv88e6390_port_set_cmode,
5213         .port_setup_message_port = mv88e6xxx_setup_message_port,
5214         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5215         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5216         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5217         .stats_get_strings = mv88e6320_stats_get_strings,
5218         .stats_get_stats = mv88e6390_stats_get_stats,
5219         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5220         .set_egress_port = mv88e6390_g1_set_egress_port,
5221         .watchdog_ops = &mv88e6390_watchdog_ops,
5222         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5223         .pot_clear = mv88e6xxx_g2_pot_clear,
5224         .reset = mv88e6352_g1_reset,
5225         .rmu_disable = mv88e6390_g1_rmu_disable,
5226         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5227         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5228         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5229         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5230         .stu_getnext = mv88e6390_g1_stu_getnext,
5231         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5232         .serdes_get_lane = mv88e6390_serdes_get_lane,
5233         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5234         .gpio_ops = &mv88e6352_gpio_ops,
5235         .avb_ops = &mv88e6390_avb_ops,
5236         .ptp_ops = &mv88e6390_ptp_ops,
5237         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5238         .serdes_get_strings = mv88e6390_serdes_get_strings,
5239         .serdes_get_stats = mv88e6390_serdes_get_stats,
5240         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5241         .serdes_get_regs = mv88e6390_serdes_get_regs,
5242         .phylink_get_caps = mv88e6390_phylink_get_caps,
5243         .pcs_ops = &mv88e6390_pcs_ops,
5244 };
5245
5246 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5247         /* MV88E6XXX_FAMILY_6390 */
5248         .setup_errata = mv88e6390_setup_errata,
5249         .irl_init_all = mv88e6390_g2_irl_init_all,
5250         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5251         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5252         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5253         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5254         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5255         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5256         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5257         .port_set_link = mv88e6xxx_port_set_link,
5258         .port_sync_link = mv88e6xxx_port_sync_link,
5259         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5260         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5261         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5262         .port_tag_remap = mv88e6390_port_tag_remap,
5263         .port_set_policy = mv88e6352_port_set_policy,
5264         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5265         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5266         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5267         .port_set_ether_type = mv88e6351_port_set_ether_type,
5268         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5269         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5270         .port_pause_limit = mv88e6390_port_pause_limit,
5271         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5272         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5273         .port_get_cmode = mv88e6352_port_get_cmode,
5274         .port_set_cmode = mv88e6390x_port_set_cmode,
5275         .port_setup_message_port = mv88e6xxx_setup_message_port,
5276         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5277         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5278         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5279         .stats_get_strings = mv88e6320_stats_get_strings,
5280         .stats_get_stats = mv88e6390_stats_get_stats,
5281         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5282         .set_egress_port = mv88e6390_g1_set_egress_port,
5283         .watchdog_ops = &mv88e6390_watchdog_ops,
5284         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5285         .pot_clear = mv88e6xxx_g2_pot_clear,
5286         .reset = mv88e6352_g1_reset,
5287         .rmu_disable = mv88e6390_g1_rmu_disable,
5288         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5289         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5290         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5291         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5292         .stu_getnext = mv88e6390_g1_stu_getnext,
5293         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5294         .serdes_get_lane = mv88e6390x_serdes_get_lane,
5295         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5296         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5297         .serdes_get_strings = mv88e6390_serdes_get_strings,
5298         .serdes_get_stats = mv88e6390_serdes_get_stats,
5299         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5300         .serdes_get_regs = mv88e6390_serdes_get_regs,
5301         .gpio_ops = &mv88e6352_gpio_ops,
5302         .avb_ops = &mv88e6390_avb_ops,
5303         .ptp_ops = &mv88e6390_ptp_ops,
5304         .phylink_get_caps = mv88e6390x_phylink_get_caps,
5305         .pcs_ops = &mv88e6390_pcs_ops,
5306 };
5307
5308 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5309         /* MV88E6XXX_FAMILY_6393 */
5310         .irl_init_all = mv88e6390_g2_irl_init_all,
5311         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5312         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5313         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5314         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5315         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5316         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5317         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5318         .port_set_link = mv88e6xxx_port_set_link,
5319         .port_sync_link = mv88e6xxx_port_sync_link,
5320         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5321         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5322         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5323         .port_tag_remap = mv88e6390_port_tag_remap,
5324         .port_set_policy = mv88e6393x_port_set_policy,
5325         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5326         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5327         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5328         .port_set_ether_type = mv88e6393x_port_set_ether_type,
5329         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5330         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5331         .port_pause_limit = mv88e6390_port_pause_limit,
5332         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5333         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5334         .port_get_cmode = mv88e6352_port_get_cmode,
5335         .port_set_cmode = mv88e6393x_port_set_cmode,
5336         .port_setup_message_port = mv88e6xxx_setup_message_port,
5337         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5338         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5339         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5340         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5341         .stats_get_strings = mv88e6320_stats_get_strings,
5342         .stats_get_stats = mv88e6390_stats_get_stats,
5343         /* .set_cpu_port is missing because this family does not support a global
5344          * CPU port, only per port CPU port which is set via
5345          * .port_set_upstream_port method.
5346          */
5347         .set_egress_port = mv88e6393x_set_egress_port,
5348         .watchdog_ops = &mv88e6393x_watchdog_ops,
5349         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5350         .pot_clear = mv88e6xxx_g2_pot_clear,
5351         .reset = mv88e6352_g1_reset,
5352         .rmu_disable = mv88e6390_g1_rmu_disable,
5353         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5354         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5355         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5356         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5357         .stu_getnext = mv88e6390_g1_stu_getnext,
5358         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5359         .serdes_get_lane = mv88e6393x_serdes_get_lane,
5360         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5361         /* TODO: serdes stats */
5362         .gpio_ops = &mv88e6352_gpio_ops,
5363         .avb_ops = &mv88e6390_avb_ops,
5364         .ptp_ops = &mv88e6352_ptp_ops,
5365         .phylink_get_caps = mv88e6393x_phylink_get_caps,
5366         .pcs_ops = &mv88e6393x_pcs_ops,
5367 };
5368
5369 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5370         [MV88E6020] = {
5371                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5372                 .family = MV88E6XXX_FAMILY_6250,
5373                 .name = "Marvell 88E6020",
5374                 .num_databases = 64,
5375                 .num_ports = 4,
5376                 .num_internal_phys = 2,
5377                 .max_vid = 4095,
5378                 .port_base_addr = 0x8,
5379                 .phy_base_addr = 0x0,
5380                 .global1_addr = 0xf,
5381                 .global2_addr = 0x7,
5382                 .age_time_coeff = 15000,
5383                 .g1_irqs = 9,
5384                 .g2_irqs = 5,
5385                 .atu_move_port_mask = 0xf,
5386                 .dual_chip = true,
5387                 .ops = &mv88e6250_ops,
5388         },
5389
5390         [MV88E6071] = {
5391                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5392                 .family = MV88E6XXX_FAMILY_6250,
5393                 .name = "Marvell 88E6071",
5394                 .num_databases = 64,
5395                 .num_ports = 7,
5396                 .num_internal_phys = 5,
5397                 .max_vid = 4095,
5398                 .port_base_addr = 0x08,
5399                 .phy_base_addr = 0x00,
5400                 .global1_addr = 0x0f,
5401                 .global2_addr = 0x07,
5402                 .age_time_coeff = 15000,
5403                 .g1_irqs = 9,
5404                 .g2_irqs = 5,
5405                 .atu_move_port_mask = 0xf,
5406                 .dual_chip = true,
5407                 .ops = &mv88e6250_ops,
5408         },
5409
5410         [MV88E6085] = {
5411                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5412                 .family = MV88E6XXX_FAMILY_6097,
5413                 .name = "Marvell 88E6085",
5414                 .num_databases = 4096,
5415                 .num_macs = 8192,
5416                 .num_ports = 10,
5417                 .num_internal_phys = 5,
5418                 .max_vid = 4095,
5419                 .max_sid = 63,
5420                 .port_base_addr = 0x10,
5421                 .phy_base_addr = 0x0,
5422                 .global1_addr = 0x1b,
5423                 .global2_addr = 0x1c,
5424                 .age_time_coeff = 15000,
5425                 .g1_irqs = 8,
5426                 .g2_irqs = 10,
5427                 .atu_move_port_mask = 0xf,
5428                 .pvt = true,
5429                 .multi_chip = true,
5430                 .ops = &mv88e6085_ops,
5431         },
5432
5433         [MV88E6095] = {
5434                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5435                 .family = MV88E6XXX_FAMILY_6095,
5436                 .name = "Marvell 88E6095/88E6095F",
5437                 .num_databases = 256,
5438                 .num_macs = 8192,
5439                 .num_ports = 11,
5440                 .num_internal_phys = 0,
5441                 .max_vid = 4095,
5442                 .port_base_addr = 0x10,
5443                 .phy_base_addr = 0x0,
5444                 .global1_addr = 0x1b,
5445                 .global2_addr = 0x1c,
5446                 .age_time_coeff = 15000,
5447                 .g1_irqs = 8,
5448                 .atu_move_port_mask = 0xf,
5449                 .multi_chip = true,
5450                 .ops = &mv88e6095_ops,
5451         },
5452
5453         [MV88E6097] = {
5454                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5455                 .family = MV88E6XXX_FAMILY_6097,
5456                 .name = "Marvell 88E6097/88E6097F",
5457                 .num_databases = 4096,
5458                 .num_macs = 8192,
5459                 .num_ports = 11,
5460                 .num_internal_phys = 8,
5461                 .max_vid = 4095,
5462                 .max_sid = 63,
5463                 .port_base_addr = 0x10,
5464                 .phy_base_addr = 0x0,
5465                 .global1_addr = 0x1b,
5466                 .global2_addr = 0x1c,
5467                 .age_time_coeff = 15000,
5468                 .g1_irqs = 8,
5469                 .g2_irqs = 10,
5470                 .atu_move_port_mask = 0xf,
5471                 .pvt = true,
5472                 .multi_chip = true,
5473                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5474                 .ops = &mv88e6097_ops,
5475         },
5476
5477         [MV88E6123] = {
5478                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5479                 .family = MV88E6XXX_FAMILY_6165,
5480                 .name = "Marvell 88E6123",
5481                 .num_databases = 4096,
5482                 .num_macs = 1024,
5483                 .num_ports = 3,
5484                 .num_internal_phys = 5,
5485                 .max_vid = 4095,
5486                 .max_sid = 63,
5487                 .port_base_addr = 0x10,
5488                 .phy_base_addr = 0x0,
5489                 .global1_addr = 0x1b,
5490                 .global2_addr = 0x1c,
5491                 .age_time_coeff = 15000,
5492                 .g1_irqs = 9,
5493                 .g2_irqs = 10,
5494                 .atu_move_port_mask = 0xf,
5495                 .pvt = true,
5496                 .multi_chip = true,
5497                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5498                 .ops = &mv88e6123_ops,
5499         },
5500
5501         [MV88E6131] = {
5502                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5503                 .family = MV88E6XXX_FAMILY_6185,
5504                 .name = "Marvell 88E6131",
5505                 .num_databases = 256,
5506                 .num_macs = 8192,
5507                 .num_ports = 8,
5508                 .num_internal_phys = 0,
5509                 .max_vid = 4095,
5510                 .port_base_addr = 0x10,
5511                 .phy_base_addr = 0x0,
5512                 .global1_addr = 0x1b,
5513                 .global2_addr = 0x1c,
5514                 .age_time_coeff = 15000,
5515                 .g1_irqs = 9,
5516                 .atu_move_port_mask = 0xf,
5517                 .multi_chip = true,
5518                 .ops = &mv88e6131_ops,
5519         },
5520
5521         [MV88E6141] = {
5522                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5523                 .family = MV88E6XXX_FAMILY_6341,
5524                 .name = "Marvell 88E6141",
5525                 .num_databases = 4096,
5526                 .num_macs = 2048,
5527                 .num_ports = 6,
5528                 .num_internal_phys = 5,
5529                 .num_gpio = 11,
5530                 .max_vid = 4095,
5531                 .max_sid = 63,
5532                 .port_base_addr = 0x10,
5533                 .phy_base_addr = 0x10,
5534                 .global1_addr = 0x1b,
5535                 .global2_addr = 0x1c,
5536                 .age_time_coeff = 3750,
5537                 .atu_move_port_mask = 0x1f,
5538                 .g1_irqs = 9,
5539                 .g2_irqs = 10,
5540                 .pvt = true,
5541                 .multi_chip = true,
5542                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5543                 .ops = &mv88e6141_ops,
5544         },
5545
5546         [MV88E6161] = {
5547                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5548                 .family = MV88E6XXX_FAMILY_6165,
5549                 .name = "Marvell 88E6161",
5550                 .num_databases = 4096,
5551                 .num_macs = 1024,
5552                 .num_ports = 6,
5553                 .num_internal_phys = 5,
5554                 .max_vid = 4095,
5555                 .max_sid = 63,
5556                 .port_base_addr = 0x10,
5557                 .phy_base_addr = 0x0,
5558                 .global1_addr = 0x1b,
5559                 .global2_addr = 0x1c,
5560                 .age_time_coeff = 15000,
5561                 .g1_irqs = 9,
5562                 .g2_irqs = 10,
5563                 .atu_move_port_mask = 0xf,
5564                 .pvt = true,
5565                 .multi_chip = true,
5566                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5567                 .ptp_support = true,
5568                 .ops = &mv88e6161_ops,
5569         },
5570
5571         [MV88E6165] = {
5572                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5573                 .family = MV88E6XXX_FAMILY_6165,
5574                 .name = "Marvell 88E6165",
5575                 .num_databases = 4096,
5576                 .num_macs = 8192,
5577                 .num_ports = 6,
5578                 .num_internal_phys = 0,
5579                 .max_vid = 4095,
5580                 .max_sid = 63,
5581                 .port_base_addr = 0x10,
5582                 .phy_base_addr = 0x0,
5583                 .global1_addr = 0x1b,
5584                 .global2_addr = 0x1c,
5585                 .age_time_coeff = 15000,
5586                 .g1_irqs = 9,
5587                 .g2_irqs = 10,
5588                 .atu_move_port_mask = 0xf,
5589                 .pvt = true,
5590                 .multi_chip = true,
5591                 .ptp_support = true,
5592                 .ops = &mv88e6165_ops,
5593         },
5594
5595         [MV88E6171] = {
5596                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5597                 .family = MV88E6XXX_FAMILY_6351,
5598                 .name = "Marvell 88E6171",
5599                 .num_databases = 4096,
5600                 .num_macs = 8192,
5601                 .num_ports = 7,
5602                 .num_internal_phys = 5,
5603                 .max_vid = 4095,
5604                 .max_sid = 63,
5605                 .port_base_addr = 0x10,
5606                 .phy_base_addr = 0x0,
5607                 .global1_addr = 0x1b,
5608                 .global2_addr = 0x1c,
5609                 .age_time_coeff = 15000,
5610                 .g1_irqs = 9,
5611                 .g2_irqs = 10,
5612                 .atu_move_port_mask = 0xf,
5613                 .pvt = true,
5614                 .multi_chip = true,
5615                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5616                 .ops = &mv88e6171_ops,
5617         },
5618
5619         [MV88E6172] = {
5620                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5621                 .family = MV88E6XXX_FAMILY_6352,
5622                 .name = "Marvell 88E6172",
5623                 .num_databases = 4096,
5624                 .num_macs = 8192,
5625                 .num_ports = 7,
5626                 .num_internal_phys = 5,
5627                 .num_gpio = 15,
5628                 .max_vid = 4095,
5629                 .max_sid = 63,
5630                 .port_base_addr = 0x10,
5631                 .phy_base_addr = 0x0,
5632                 .global1_addr = 0x1b,
5633                 .global2_addr = 0x1c,
5634                 .age_time_coeff = 15000,
5635                 .g1_irqs = 9,
5636                 .g2_irqs = 10,
5637                 .atu_move_port_mask = 0xf,
5638                 .pvt = true,
5639                 .multi_chip = true,
5640                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5641                 .ops = &mv88e6172_ops,
5642         },
5643
5644         [MV88E6175] = {
5645                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5646                 .family = MV88E6XXX_FAMILY_6351,
5647                 .name = "Marvell 88E6175",
5648                 .num_databases = 4096,
5649                 .num_macs = 8192,
5650                 .num_ports = 7,
5651                 .num_internal_phys = 5,
5652                 .max_vid = 4095,
5653                 .max_sid = 63,
5654                 .port_base_addr = 0x10,
5655                 .phy_base_addr = 0x0,
5656                 .global1_addr = 0x1b,
5657                 .global2_addr = 0x1c,
5658                 .age_time_coeff = 15000,
5659                 .g1_irqs = 9,
5660                 .g2_irqs = 10,
5661                 .atu_move_port_mask = 0xf,
5662                 .pvt = true,
5663                 .multi_chip = true,
5664                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5665                 .ops = &mv88e6175_ops,
5666         },
5667
5668         [MV88E6176] = {
5669                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5670                 .family = MV88E6XXX_FAMILY_6352,
5671                 .name = "Marvell 88E6176",
5672                 .num_databases = 4096,
5673                 .num_macs = 8192,
5674                 .num_ports = 7,
5675                 .num_internal_phys = 5,
5676                 .num_gpio = 15,
5677                 .max_vid = 4095,
5678                 .max_sid = 63,
5679                 .port_base_addr = 0x10,
5680                 .phy_base_addr = 0x0,
5681                 .global1_addr = 0x1b,
5682                 .global2_addr = 0x1c,
5683                 .age_time_coeff = 15000,
5684                 .g1_irqs = 9,
5685                 .g2_irqs = 10,
5686                 .atu_move_port_mask = 0xf,
5687                 .pvt = true,
5688                 .multi_chip = true,
5689                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5690                 .ops = &mv88e6176_ops,
5691         },
5692
5693         [MV88E6185] = {
5694                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5695                 .family = MV88E6XXX_FAMILY_6185,
5696                 .name = "Marvell 88E6185",
5697                 .num_databases = 256,
5698                 .num_macs = 8192,
5699                 .num_ports = 10,
5700                 .num_internal_phys = 0,
5701                 .max_vid = 4095,
5702                 .port_base_addr = 0x10,
5703                 .phy_base_addr = 0x0,
5704                 .global1_addr = 0x1b,
5705                 .global2_addr = 0x1c,
5706                 .age_time_coeff = 15000,
5707                 .g1_irqs = 8,
5708                 .atu_move_port_mask = 0xf,
5709                 .multi_chip = true,
5710                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5711                 .ops = &mv88e6185_ops,
5712         },
5713
5714         [MV88E6190] = {
5715                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5716                 .family = MV88E6XXX_FAMILY_6390,
5717                 .name = "Marvell 88E6190",
5718                 .num_databases = 4096,
5719                 .num_macs = 16384,
5720                 .num_ports = 11,        /* 10 + Z80 */
5721                 .num_internal_phys = 9,
5722                 .num_gpio = 16,
5723                 .max_vid = 8191,
5724                 .max_sid = 63,
5725                 .port_base_addr = 0x0,
5726                 .phy_base_addr = 0x0,
5727                 .global1_addr = 0x1b,
5728                 .global2_addr = 0x1c,
5729                 .age_time_coeff = 3750,
5730                 .g1_irqs = 9,
5731                 .g2_irqs = 14,
5732                 .pvt = true,
5733                 .multi_chip = true,
5734                 .atu_move_port_mask = 0x1f,
5735                 .ops = &mv88e6190_ops,
5736         },
5737
5738         [MV88E6190X] = {
5739                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5740                 .family = MV88E6XXX_FAMILY_6390,
5741                 .name = "Marvell 88E6190X",
5742                 .num_databases = 4096,
5743                 .num_macs = 16384,
5744                 .num_ports = 11,        /* 10 + Z80 */
5745                 .num_internal_phys = 9,
5746                 .num_gpio = 16,
5747                 .max_vid = 8191,
5748                 .max_sid = 63,
5749                 .port_base_addr = 0x0,
5750                 .phy_base_addr = 0x0,
5751                 .global1_addr = 0x1b,
5752                 .global2_addr = 0x1c,
5753                 .age_time_coeff = 3750,
5754                 .g1_irqs = 9,
5755                 .g2_irqs = 14,
5756                 .atu_move_port_mask = 0x1f,
5757                 .pvt = true,
5758                 .multi_chip = true,
5759                 .ops = &mv88e6190x_ops,
5760         },
5761
5762         [MV88E6191] = {
5763                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5764                 .family = MV88E6XXX_FAMILY_6390,
5765                 .name = "Marvell 88E6191",
5766                 .num_databases = 4096,
5767                 .num_macs = 16384,
5768                 .num_ports = 11,        /* 10 + Z80 */
5769                 .num_internal_phys = 9,
5770                 .max_vid = 8191,
5771                 .max_sid = 63,
5772                 .port_base_addr = 0x0,
5773                 .phy_base_addr = 0x0,
5774                 .global1_addr = 0x1b,
5775                 .global2_addr = 0x1c,
5776                 .age_time_coeff = 3750,
5777                 .g1_irqs = 9,
5778                 .g2_irqs = 14,
5779                 .atu_move_port_mask = 0x1f,
5780                 .pvt = true,
5781                 .multi_chip = true,
5782                 .ptp_support = true,
5783                 .ops = &mv88e6191_ops,
5784         },
5785
5786         [MV88E6191X] = {
5787                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5788                 .family = MV88E6XXX_FAMILY_6393,
5789                 .name = "Marvell 88E6191X",
5790                 .num_databases = 4096,
5791                 .num_ports = 11,        /* 10 + Z80 */
5792                 .num_internal_phys = 8,
5793                 .internal_phys_offset = 1,
5794                 .max_vid = 8191,
5795                 .max_sid = 63,
5796                 .port_base_addr = 0x0,
5797                 .phy_base_addr = 0x0,
5798                 .global1_addr = 0x1b,
5799                 .global2_addr = 0x1c,
5800                 .age_time_coeff = 3750,
5801                 .g1_irqs = 10,
5802                 .g2_irqs = 14,
5803                 .atu_move_port_mask = 0x1f,
5804                 .pvt = true,
5805                 .multi_chip = true,
5806                 .ptp_support = true,
5807                 .ops = &mv88e6393x_ops,
5808         },
5809
5810         [MV88E6193X] = {
5811                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5812                 .family = MV88E6XXX_FAMILY_6393,
5813                 .name = "Marvell 88E6193X",
5814                 .num_databases = 4096,
5815                 .num_ports = 11,        /* 10 + Z80 */
5816                 .num_internal_phys = 8,
5817                 .internal_phys_offset = 1,
5818                 .max_vid = 8191,
5819                 .max_sid = 63,
5820                 .port_base_addr = 0x0,
5821                 .phy_base_addr = 0x0,
5822                 .global1_addr = 0x1b,
5823                 .global2_addr = 0x1c,
5824                 .age_time_coeff = 3750,
5825                 .g1_irqs = 10,
5826                 .g2_irqs = 14,
5827                 .atu_move_port_mask = 0x1f,
5828                 .pvt = true,
5829                 .multi_chip = true,
5830                 .ptp_support = true,
5831                 .ops = &mv88e6393x_ops,
5832         },
5833
5834         [MV88E6220] = {
5835                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5836                 .family = MV88E6XXX_FAMILY_6250,
5837                 .name = "Marvell 88E6220",
5838                 .num_databases = 64,
5839
5840                 /* Ports 2-4 are not routed to pins
5841                  * => usable ports 0, 1, 5, 6
5842                  */
5843                 .num_ports = 7,
5844                 .num_internal_phys = 2,
5845                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5846                 .max_vid = 4095,
5847                 .port_base_addr = 0x08,
5848                 .phy_base_addr = 0x00,
5849                 .global1_addr = 0x0f,
5850                 .global2_addr = 0x07,
5851                 .age_time_coeff = 15000,
5852                 .g1_irqs = 9,
5853                 .g2_irqs = 10,
5854                 .atu_move_port_mask = 0xf,
5855                 .dual_chip = true,
5856                 .ptp_support = true,
5857                 .ops = &mv88e6250_ops,
5858         },
5859
5860         [MV88E6240] = {
5861                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5862                 .family = MV88E6XXX_FAMILY_6352,
5863                 .name = "Marvell 88E6240",
5864                 .num_databases = 4096,
5865                 .num_macs = 8192,
5866                 .num_ports = 7,
5867                 .num_internal_phys = 5,
5868                 .num_gpio = 15,
5869                 .max_vid = 4095,
5870                 .max_sid = 63,
5871                 .port_base_addr = 0x10,
5872                 .phy_base_addr = 0x0,
5873                 .global1_addr = 0x1b,
5874                 .global2_addr = 0x1c,
5875                 .age_time_coeff = 15000,
5876                 .g1_irqs = 9,
5877                 .g2_irqs = 10,
5878                 .atu_move_port_mask = 0xf,
5879                 .pvt = true,
5880                 .multi_chip = true,
5881                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5882                 .ptp_support = true,
5883                 .ops = &mv88e6240_ops,
5884         },
5885
5886         [MV88E6250] = {
5887                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5888                 .family = MV88E6XXX_FAMILY_6250,
5889                 .name = "Marvell 88E6250",
5890                 .num_databases = 64,
5891                 .num_ports = 7,
5892                 .num_internal_phys = 5,
5893                 .max_vid = 4095,
5894                 .port_base_addr = 0x08,
5895                 .phy_base_addr = 0x00,
5896                 .global1_addr = 0x0f,
5897                 .global2_addr = 0x07,
5898                 .age_time_coeff = 15000,
5899                 .g1_irqs = 9,
5900                 .g2_irqs = 10,
5901                 .atu_move_port_mask = 0xf,
5902                 .dual_chip = true,
5903                 .ptp_support = true,
5904                 .ops = &mv88e6250_ops,
5905         },
5906
5907         [MV88E6290] = {
5908                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5909                 .family = MV88E6XXX_FAMILY_6390,
5910                 .name = "Marvell 88E6290",
5911                 .num_databases = 4096,
5912                 .num_ports = 11,        /* 10 + Z80 */
5913                 .num_internal_phys = 9,
5914                 .num_gpio = 16,
5915                 .max_vid = 8191,
5916                 .max_sid = 63,
5917                 .port_base_addr = 0x0,
5918                 .phy_base_addr = 0x0,
5919                 .global1_addr = 0x1b,
5920                 .global2_addr = 0x1c,
5921                 .age_time_coeff = 3750,
5922                 .g1_irqs = 9,
5923                 .g2_irqs = 14,
5924                 .atu_move_port_mask = 0x1f,
5925                 .pvt = true,
5926                 .multi_chip = true,
5927                 .ptp_support = true,
5928                 .ops = &mv88e6290_ops,
5929         },
5930
5931         [MV88E6320] = {
5932                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5933                 .family = MV88E6XXX_FAMILY_6320,
5934                 .name = "Marvell 88E6320",
5935                 .num_databases = 4096,
5936                 .num_macs = 8192,
5937                 .num_ports = 7,
5938                 .num_internal_phys = 5,
5939                 .num_gpio = 15,
5940                 .max_vid = 4095,
5941                 .port_base_addr = 0x10,
5942                 .phy_base_addr = 0x0,
5943                 .global1_addr = 0x1b,
5944                 .global2_addr = 0x1c,
5945                 .age_time_coeff = 15000,
5946                 .g1_irqs = 8,
5947                 .g2_irqs = 10,
5948                 .atu_move_port_mask = 0xf,
5949                 .pvt = true,
5950                 .multi_chip = true,
5951                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5952                 .ptp_support = true,
5953                 .ops = &mv88e6320_ops,
5954         },
5955
5956         [MV88E6321] = {
5957                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5958                 .family = MV88E6XXX_FAMILY_6320,
5959                 .name = "Marvell 88E6321",
5960                 .num_databases = 4096,
5961                 .num_macs = 8192,
5962                 .num_ports = 7,
5963                 .num_internal_phys = 5,
5964                 .num_gpio = 15,
5965                 .max_vid = 4095,
5966                 .port_base_addr = 0x10,
5967                 .phy_base_addr = 0x0,
5968                 .global1_addr = 0x1b,
5969                 .global2_addr = 0x1c,
5970                 .age_time_coeff = 15000,
5971                 .g1_irqs = 8,
5972                 .g2_irqs = 10,
5973                 .atu_move_port_mask = 0xf,
5974                 .multi_chip = true,
5975                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5976                 .ptp_support = true,
5977                 .ops = &mv88e6321_ops,
5978         },
5979
5980         [MV88E6341] = {
5981                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5982                 .family = MV88E6XXX_FAMILY_6341,
5983                 .name = "Marvell 88E6341",
5984                 .num_databases = 4096,
5985                 .num_macs = 2048,
5986                 .num_internal_phys = 5,
5987                 .num_ports = 6,
5988                 .num_gpio = 11,
5989                 .max_vid = 4095,
5990                 .max_sid = 63,
5991                 .port_base_addr = 0x10,
5992                 .phy_base_addr = 0x10,
5993                 .global1_addr = 0x1b,
5994                 .global2_addr = 0x1c,
5995                 .age_time_coeff = 3750,
5996                 .atu_move_port_mask = 0x1f,
5997                 .g1_irqs = 9,
5998                 .g2_irqs = 10,
5999                 .pvt = true,
6000                 .multi_chip = true,
6001                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6002                 .ptp_support = true,
6003                 .ops = &mv88e6341_ops,
6004         },
6005
6006         [MV88E6350] = {
6007                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6008                 .family = MV88E6XXX_FAMILY_6351,
6009                 .name = "Marvell 88E6350",
6010                 .num_databases = 4096,
6011                 .num_macs = 8192,
6012                 .num_ports = 7,
6013                 .num_internal_phys = 5,
6014                 .max_vid = 4095,
6015                 .max_sid = 63,
6016                 .port_base_addr = 0x10,
6017                 .phy_base_addr = 0x0,
6018                 .global1_addr = 0x1b,
6019                 .global2_addr = 0x1c,
6020                 .age_time_coeff = 15000,
6021                 .g1_irqs = 9,
6022                 .g2_irqs = 10,
6023                 .atu_move_port_mask = 0xf,
6024                 .pvt = true,
6025                 .multi_chip = true,
6026                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6027                 .ops = &mv88e6350_ops,
6028         },
6029
6030         [MV88E6351] = {
6031                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6032                 .family = MV88E6XXX_FAMILY_6351,
6033                 .name = "Marvell 88E6351",
6034                 .num_databases = 4096,
6035                 .num_macs = 8192,
6036                 .num_ports = 7,
6037                 .num_internal_phys = 5,
6038                 .max_vid = 4095,
6039                 .max_sid = 63,
6040                 .port_base_addr = 0x10,
6041                 .phy_base_addr = 0x0,
6042                 .global1_addr = 0x1b,
6043                 .global2_addr = 0x1c,
6044                 .age_time_coeff = 15000,
6045                 .g1_irqs = 9,
6046                 .g2_irqs = 10,
6047                 .atu_move_port_mask = 0xf,
6048                 .pvt = true,
6049                 .multi_chip = true,
6050                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6051                 .ops = &mv88e6351_ops,
6052         },
6053
6054         [MV88E6352] = {
6055                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6056                 .family = MV88E6XXX_FAMILY_6352,
6057                 .name = "Marvell 88E6352",
6058                 .num_databases = 4096,
6059                 .num_macs = 8192,
6060                 .num_ports = 7,
6061                 .num_internal_phys = 5,
6062                 .num_gpio = 15,
6063                 .max_vid = 4095,
6064                 .max_sid = 63,
6065                 .port_base_addr = 0x10,
6066                 .phy_base_addr = 0x0,
6067                 .global1_addr = 0x1b,
6068                 .global2_addr = 0x1c,
6069                 .age_time_coeff = 15000,
6070                 .g1_irqs = 9,
6071                 .g2_irqs = 10,
6072                 .atu_move_port_mask = 0xf,
6073                 .pvt = true,
6074                 .multi_chip = true,
6075                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6076                 .ptp_support = true,
6077                 .ops = &mv88e6352_ops,
6078         },
6079         [MV88E6361] = {
6080                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6081                 .family = MV88E6XXX_FAMILY_6393,
6082                 .name = "Marvell 88E6361",
6083                 .num_databases = 4096,
6084                 .num_macs = 16384,
6085                 .num_ports = 11,
6086                 /* Ports 1, 2 and 8 are not routed */
6087                 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6088                 .num_internal_phys = 5,
6089                 .internal_phys_offset = 3,
6090                 .max_vid = 4095,
6091                 .max_sid = 63,
6092                 .port_base_addr = 0x0,
6093                 .phy_base_addr = 0x0,
6094                 .global1_addr = 0x1b,
6095                 .global2_addr = 0x1c,
6096                 .age_time_coeff = 3750,
6097                 .g1_irqs = 10,
6098                 .g2_irqs = 14,
6099                 .atu_move_port_mask = 0x1f,
6100                 .pvt = true,
6101                 .multi_chip = true,
6102                 .ptp_support = true,
6103                 .ops = &mv88e6393x_ops,
6104         },
6105         [MV88E6390] = {
6106                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6107                 .family = MV88E6XXX_FAMILY_6390,
6108                 .name = "Marvell 88E6390",
6109                 .num_databases = 4096,
6110                 .num_macs = 16384,
6111                 .num_ports = 11,        /* 10 + Z80 */
6112                 .num_internal_phys = 9,
6113                 .num_gpio = 16,
6114                 .max_vid = 8191,
6115                 .max_sid = 63,
6116                 .port_base_addr = 0x0,
6117                 .phy_base_addr = 0x0,
6118                 .global1_addr = 0x1b,
6119                 .global2_addr = 0x1c,
6120                 .age_time_coeff = 3750,
6121                 .g1_irqs = 9,
6122                 .g2_irqs = 14,
6123                 .atu_move_port_mask = 0x1f,
6124                 .pvt = true,
6125                 .multi_chip = true,
6126                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6127                 .ptp_support = true,
6128                 .ops = &mv88e6390_ops,
6129         },
6130         [MV88E6390X] = {
6131                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6132                 .family = MV88E6XXX_FAMILY_6390,
6133                 .name = "Marvell 88E6390X",
6134                 .num_databases = 4096,
6135                 .num_macs = 16384,
6136                 .num_ports = 11,        /* 10 + Z80 */
6137                 .num_internal_phys = 9,
6138                 .num_gpio = 16,
6139                 .max_vid = 8191,
6140                 .max_sid = 63,
6141                 .port_base_addr = 0x0,
6142                 .phy_base_addr = 0x0,
6143                 .global1_addr = 0x1b,
6144                 .global2_addr = 0x1c,
6145                 .age_time_coeff = 3750,
6146                 .g1_irqs = 9,
6147                 .g2_irqs = 14,
6148                 .atu_move_port_mask = 0x1f,
6149                 .pvt = true,
6150                 .multi_chip = true,
6151                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6152                 .ptp_support = true,
6153                 .ops = &mv88e6390x_ops,
6154         },
6155
6156         [MV88E6393X] = {
6157                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6158                 .family = MV88E6XXX_FAMILY_6393,
6159                 .name = "Marvell 88E6393X",
6160                 .num_databases = 4096,
6161                 .num_ports = 11,        /* 10 + Z80 */
6162                 .num_internal_phys = 8,
6163                 .internal_phys_offset = 1,
6164                 .max_vid = 8191,
6165                 .max_sid = 63,
6166                 .port_base_addr = 0x0,
6167                 .phy_base_addr = 0x0,
6168                 .global1_addr = 0x1b,
6169                 .global2_addr = 0x1c,
6170                 .age_time_coeff = 3750,
6171                 .g1_irqs = 10,
6172                 .g2_irqs = 14,
6173                 .atu_move_port_mask = 0x1f,
6174                 .pvt = true,
6175                 .multi_chip = true,
6176                 .ptp_support = true,
6177                 .ops = &mv88e6393x_ops,
6178         },
6179 };
6180
6181 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6182 {
6183         int i;
6184
6185         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6186                 if (mv88e6xxx_table[i].prod_num == prod_num)
6187                         return &mv88e6xxx_table[i];
6188
6189         return NULL;
6190 }
6191
6192 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6193 {
6194         const struct mv88e6xxx_info *info;
6195         unsigned int prod_num, rev;
6196         u16 id;
6197         int err;
6198
6199         mv88e6xxx_reg_lock(chip);
6200         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6201         mv88e6xxx_reg_unlock(chip);
6202         if (err)
6203                 return err;
6204
6205         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6206         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6207
6208         info = mv88e6xxx_lookup_info(prod_num);
6209         if (!info)
6210                 return -ENODEV;
6211
6212         /* Update the compatible info with the probed one */
6213         chip->info = info;
6214
6215         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6216                  chip->info->prod_num, chip->info->name, rev);
6217
6218         return 0;
6219 }
6220
6221 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6222                                         struct mdio_device *mdiodev)
6223 {
6224         int err;
6225
6226         /* dual_chip takes precedence over single/multi-chip modes */
6227         if (chip->info->dual_chip)
6228                 return -EINVAL;
6229
6230         /* If the mdio addr is 16 indicating the first port address of a switch
6231          * (e.g. mv88e6*41) in single chip addressing mode the device may be
6232          * configured in single chip addressing mode. Setup the smi access as
6233          * single chip addressing mode and attempt to detect the model of the
6234          * switch, if this fails the device is not configured in single chip
6235          * addressing mode.
6236          */
6237         if (mdiodev->addr != 16)
6238                 return -EINVAL;
6239
6240         err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6241         if (err)
6242                 return err;
6243
6244         return mv88e6xxx_detect(chip);
6245 }
6246
6247 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6248 {
6249         struct mv88e6xxx_chip *chip;
6250
6251         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6252         if (!chip)
6253                 return NULL;
6254
6255         chip->dev = dev;
6256
6257         mutex_init(&chip->reg_lock);
6258         INIT_LIST_HEAD(&chip->mdios);
6259         idr_init(&chip->policies);
6260         INIT_LIST_HEAD(&chip->msts);
6261
6262         return chip;
6263 }
6264
6265 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6266                                                         int port,
6267                                                         enum dsa_tag_protocol m)
6268 {
6269         struct mv88e6xxx_chip *chip = ds->priv;
6270
6271         return chip->tag_protocol;
6272 }
6273
6274 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6275                                          enum dsa_tag_protocol proto)
6276 {
6277         struct mv88e6xxx_chip *chip = ds->priv;
6278         enum dsa_tag_protocol old_protocol;
6279         struct dsa_port *cpu_dp;
6280         int err;
6281
6282         switch (proto) {
6283         case DSA_TAG_PROTO_EDSA:
6284                 switch (chip->info->edsa_support) {
6285                 case MV88E6XXX_EDSA_UNSUPPORTED:
6286                         return -EPROTONOSUPPORT;
6287                 case MV88E6XXX_EDSA_UNDOCUMENTED:
6288                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6289                         fallthrough;
6290                 case MV88E6XXX_EDSA_SUPPORTED:
6291                         break;
6292                 }
6293                 break;
6294         case DSA_TAG_PROTO_DSA:
6295                 break;
6296         default:
6297                 return -EPROTONOSUPPORT;
6298         }
6299
6300         old_protocol = chip->tag_protocol;
6301         chip->tag_protocol = proto;
6302
6303         mv88e6xxx_reg_lock(chip);
6304         dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6305                 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6306                 if (err) {
6307                         mv88e6xxx_reg_unlock(chip);
6308                         goto unwind;
6309                 }
6310         }
6311         mv88e6xxx_reg_unlock(chip);
6312
6313         return 0;
6314
6315 unwind:
6316         chip->tag_protocol = old_protocol;
6317
6318         mv88e6xxx_reg_lock(chip);
6319         dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6320                 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6321         mv88e6xxx_reg_unlock(chip);
6322
6323         return err;
6324 }
6325
6326 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6327                                   const struct switchdev_obj_port_mdb *mdb,
6328                                   struct dsa_db db)
6329 {
6330         struct mv88e6xxx_chip *chip = ds->priv;
6331         int err;
6332
6333         mv88e6xxx_reg_lock(chip);
6334         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6335                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6336         mv88e6xxx_reg_unlock(chip);
6337
6338         return err;
6339 }
6340
6341 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6342                                   const struct switchdev_obj_port_mdb *mdb,
6343                                   struct dsa_db db)
6344 {
6345         struct mv88e6xxx_chip *chip = ds->priv;
6346         int err;
6347
6348         mv88e6xxx_reg_lock(chip);
6349         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6350         mv88e6xxx_reg_unlock(chip);
6351
6352         return err;
6353 }
6354
6355 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6356                                      struct dsa_mall_mirror_tc_entry *mirror,
6357                                      bool ingress,
6358                                      struct netlink_ext_ack *extack)
6359 {
6360         enum mv88e6xxx_egress_direction direction = ingress ?
6361                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6362                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6363         struct mv88e6xxx_chip *chip = ds->priv;
6364         bool other_mirrors = false;
6365         int i;
6366         int err;
6367
6368         mutex_lock(&chip->reg_lock);
6369         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6370             mirror->to_local_port) {
6371                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6372                         other_mirrors |= ingress ?
6373                                          chip->ports[i].mirror_ingress :
6374                                          chip->ports[i].mirror_egress;
6375
6376                 /* Can't change egress port when other mirror is active */
6377                 if (other_mirrors) {
6378                         err = -EBUSY;
6379                         goto out;
6380                 }
6381
6382                 err = mv88e6xxx_set_egress_port(chip, direction,
6383                                                 mirror->to_local_port);
6384                 if (err)
6385                         goto out;
6386         }
6387
6388         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6389 out:
6390         mutex_unlock(&chip->reg_lock);
6391
6392         return err;
6393 }
6394
6395 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6396                                       struct dsa_mall_mirror_tc_entry *mirror)
6397 {
6398         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6399                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6400                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6401         struct mv88e6xxx_chip *chip = ds->priv;
6402         bool other_mirrors = false;
6403         int i;
6404
6405         mutex_lock(&chip->reg_lock);
6406         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6407                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6408
6409         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6410                 other_mirrors |= mirror->ingress ?
6411                                  chip->ports[i].mirror_ingress :
6412                                  chip->ports[i].mirror_egress;
6413
6414         /* Reset egress port when no other mirror is active */
6415         if (!other_mirrors) {
6416                 if (mv88e6xxx_set_egress_port(chip, direction,
6417                                               dsa_upstream_port(ds, port)))
6418                         dev_err(ds->dev, "failed to set egress port\n");
6419         }
6420
6421         mutex_unlock(&chip->reg_lock);
6422 }
6423
6424 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6425                                            struct switchdev_brport_flags flags,
6426                                            struct netlink_ext_ack *extack)
6427 {
6428         struct mv88e6xxx_chip *chip = ds->priv;
6429         const struct mv88e6xxx_ops *ops;
6430
6431         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6432                            BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6433                 return -EINVAL;
6434
6435         ops = chip->info->ops;
6436
6437         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6438                 return -EINVAL;
6439
6440         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6441                 return -EINVAL;
6442
6443         return 0;
6444 }
6445
6446 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6447                                        struct switchdev_brport_flags flags,
6448                                        struct netlink_ext_ack *extack)
6449 {
6450         struct mv88e6xxx_chip *chip = ds->priv;
6451         int err = 0;
6452
6453         mv88e6xxx_reg_lock(chip);
6454
6455         if (flags.mask & BR_LEARNING) {
6456                 bool learning = !!(flags.val & BR_LEARNING);
6457                 u16 pav = learning ? (1 << port) : 0;
6458
6459                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6460                 if (err)
6461                         goto out;
6462         }
6463
6464         if (flags.mask & BR_FLOOD) {
6465                 bool unicast = !!(flags.val & BR_FLOOD);
6466
6467                 err = chip->info->ops->port_set_ucast_flood(chip, port,
6468                                                             unicast);
6469                 if (err)
6470                         goto out;
6471         }
6472
6473         if (flags.mask & BR_MCAST_FLOOD) {
6474                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6475
6476                 err = chip->info->ops->port_set_mcast_flood(chip, port,
6477                                                             multicast);
6478                 if (err)
6479                         goto out;
6480         }
6481
6482         if (flags.mask & BR_BCAST_FLOOD) {
6483                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6484
6485                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6486                 if (err)
6487                         goto out;
6488         }
6489
6490         if (flags.mask & BR_PORT_MAB) {
6491                 bool mab = !!(flags.val & BR_PORT_MAB);
6492
6493                 mv88e6xxx_port_set_mab(chip, port, mab);
6494         }
6495
6496         if (flags.mask & BR_PORT_LOCKED) {
6497                 bool locked = !!(flags.val & BR_PORT_LOCKED);
6498
6499                 err = mv88e6xxx_port_set_lock(chip, port, locked);
6500                 if (err)
6501                         goto out;
6502         }
6503 out:
6504         mv88e6xxx_reg_unlock(chip);
6505
6506         return err;
6507 }
6508
6509 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6510                                       struct dsa_lag lag,
6511                                       struct netdev_lag_upper_info *info,
6512                                       struct netlink_ext_ack *extack)
6513 {
6514         struct mv88e6xxx_chip *chip = ds->priv;
6515         struct dsa_port *dp;
6516         int members = 0;
6517
6518         if (!mv88e6xxx_has_lag(chip)) {
6519                 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6520                 return false;
6521         }
6522
6523         if (!lag.id)
6524                 return false;
6525
6526         dsa_lag_foreach_port(dp, ds->dst, &lag)
6527                 /* Includes the port joining the LAG */
6528                 members++;
6529
6530         if (members > 8) {
6531                 NL_SET_ERR_MSG_MOD(extack,
6532                                    "Cannot offload more than 8 LAG ports");
6533                 return false;
6534         }
6535
6536         /* We could potentially relax this to include active
6537          * backup in the future.
6538          */
6539         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6540                 NL_SET_ERR_MSG_MOD(extack,
6541                                    "Can only offload LAG using hash TX type");
6542                 return false;
6543         }
6544
6545         /* Ideally we would also validate that the hash type matches
6546          * the hardware. Alas, this is always set to unknown on team
6547          * interfaces.
6548          */
6549         return true;
6550 }
6551
6552 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6553 {
6554         struct mv88e6xxx_chip *chip = ds->priv;
6555         struct dsa_port *dp;
6556         u16 map = 0;
6557         int id;
6558
6559         /* DSA LAG IDs are one-based, hardware is zero-based */
6560         id = lag.id - 1;
6561
6562         /* Build the map of all ports to distribute flows destined for
6563          * this LAG. This can be either a local user port, or a DSA
6564          * port if the LAG port is on a remote chip.
6565          */
6566         dsa_lag_foreach_port(dp, ds->dst, &lag)
6567                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6568
6569         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6570 }
6571
6572 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6573         /* Row number corresponds to the number of active members in a
6574          * LAG. Each column states which of the eight hash buckets are
6575          * mapped to the column:th port in the LAG.
6576          *
6577          * Example: In a LAG with three active ports, the second port
6578          * ([2][1]) would be selected for traffic mapped to buckets
6579          * 3,4,5 (0x38).
6580          */
6581         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
6582         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6583         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6584         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6585         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6586         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6587         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6588         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6589 };
6590
6591 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6592                                         int num_tx, int nth)
6593 {
6594         u8 active = 0;
6595         int i;
6596
6597         num_tx = num_tx <= 8 ? num_tx : 8;
6598         if (nth < num_tx)
6599                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6600
6601         for (i = 0; i < 8; i++) {
6602                 if (BIT(i) & active)
6603                         mask[i] |= BIT(port);
6604         }
6605 }
6606
6607 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6608 {
6609         struct mv88e6xxx_chip *chip = ds->priv;
6610         unsigned int id, num_tx;
6611         struct dsa_port *dp;
6612         struct dsa_lag *lag;
6613         int i, err, nth;
6614         u16 mask[8];
6615         u16 ivec;
6616
6617         /* Assume no port is a member of any LAG. */
6618         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6619
6620         /* Disable all masks for ports that _are_ members of a LAG. */
6621         dsa_switch_for_each_port(dp, ds) {
6622                 if (!dp->lag)
6623                         continue;
6624
6625                 ivec &= ~BIT(dp->index);
6626         }
6627
6628         for (i = 0; i < 8; i++)
6629                 mask[i] = ivec;
6630
6631         /* Enable the correct subset of masks for all LAG ports that
6632          * are in the Tx set.
6633          */
6634         dsa_lags_foreach_id(id, ds->dst) {
6635                 lag = dsa_lag_by_id(ds->dst, id);
6636                 if (!lag)
6637                         continue;
6638
6639                 num_tx = 0;
6640                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6641                         if (dp->lag_tx_enabled)
6642                                 num_tx++;
6643                 }
6644
6645                 if (!num_tx)
6646                         continue;
6647
6648                 nth = 0;
6649                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6650                         if (!dp->lag_tx_enabled)
6651                                 continue;
6652
6653                         if (dp->ds == ds)
6654                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6655                                                             num_tx, nth);
6656
6657                         nth++;
6658                 }
6659         }
6660
6661         for (i = 0; i < 8; i++) {
6662                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6663                 if (err)
6664                         return err;
6665         }
6666
6667         return 0;
6668 }
6669
6670 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6671                                         struct dsa_lag lag)
6672 {
6673         int err;
6674
6675         err = mv88e6xxx_lag_sync_masks(ds);
6676
6677         if (!err)
6678                 err = mv88e6xxx_lag_sync_map(ds, lag);
6679
6680         return err;
6681 }
6682
6683 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6684 {
6685         struct mv88e6xxx_chip *chip = ds->priv;
6686         int err;
6687
6688         mv88e6xxx_reg_lock(chip);
6689         err = mv88e6xxx_lag_sync_masks(ds);
6690         mv88e6xxx_reg_unlock(chip);
6691         return err;
6692 }
6693
6694 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6695                                    struct dsa_lag lag,
6696                                    struct netdev_lag_upper_info *info,
6697                                    struct netlink_ext_ack *extack)
6698 {
6699         struct mv88e6xxx_chip *chip = ds->priv;
6700         int err, id;
6701
6702         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6703                 return -EOPNOTSUPP;
6704
6705         /* DSA LAG IDs are one-based */
6706         id = lag.id - 1;
6707
6708         mv88e6xxx_reg_lock(chip);
6709
6710         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6711         if (err)
6712                 goto err_unlock;
6713
6714         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6715         if (err)
6716                 goto err_clear_trunk;
6717
6718         mv88e6xxx_reg_unlock(chip);
6719         return 0;
6720
6721 err_clear_trunk:
6722         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6723 err_unlock:
6724         mv88e6xxx_reg_unlock(chip);
6725         return err;
6726 }
6727
6728 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6729                                     struct dsa_lag lag)
6730 {
6731         struct mv88e6xxx_chip *chip = ds->priv;
6732         int err_sync, err_trunk;
6733
6734         mv88e6xxx_reg_lock(chip);
6735         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6736         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6737         mv88e6xxx_reg_unlock(chip);
6738         return err_sync ? : err_trunk;
6739 }
6740
6741 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6742                                           int port)
6743 {
6744         struct mv88e6xxx_chip *chip = ds->priv;
6745         int err;
6746
6747         mv88e6xxx_reg_lock(chip);
6748         err = mv88e6xxx_lag_sync_masks(ds);
6749         mv88e6xxx_reg_unlock(chip);
6750         return err;
6751 }
6752
6753 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6754                                         int port, struct dsa_lag lag,
6755                                         struct netdev_lag_upper_info *info,
6756                                         struct netlink_ext_ack *extack)
6757 {
6758         struct mv88e6xxx_chip *chip = ds->priv;
6759         int err;
6760
6761         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6762                 return -EOPNOTSUPP;
6763
6764         mv88e6xxx_reg_lock(chip);
6765
6766         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6767         if (err)
6768                 goto unlock;
6769
6770         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6771
6772 unlock:
6773         mv88e6xxx_reg_unlock(chip);
6774         return err;
6775 }
6776
6777 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6778                                          int port, struct dsa_lag lag)
6779 {
6780         struct mv88e6xxx_chip *chip = ds->priv;
6781         int err_sync, err_pvt;
6782
6783         mv88e6xxx_reg_lock(chip);
6784         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6785         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6786         mv88e6xxx_reg_unlock(chip);
6787         return err_sync ? : err_pvt;
6788 }
6789
6790 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6791         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6792         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6793         .setup                  = mv88e6xxx_setup,
6794         .teardown               = mv88e6xxx_teardown,
6795         .port_setup             = mv88e6xxx_port_setup,
6796         .port_teardown          = mv88e6xxx_port_teardown,
6797         .phylink_get_caps       = mv88e6xxx_get_caps,
6798         .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6799         .phylink_mac_prepare    = mv88e6xxx_mac_prepare,
6800         .phylink_mac_config     = mv88e6xxx_mac_config,
6801         .phylink_mac_finish     = mv88e6xxx_mac_finish,
6802         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6803         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6804         .get_strings            = mv88e6xxx_get_strings,
6805         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6806         .get_sset_count         = mv88e6xxx_get_sset_count,
6807         .port_max_mtu           = mv88e6xxx_get_max_mtu,
6808         .port_change_mtu        = mv88e6xxx_change_mtu,
6809         .get_mac_eee            = mv88e6xxx_get_mac_eee,
6810         .set_mac_eee            = mv88e6xxx_set_mac_eee,
6811         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
6812         .get_eeprom             = mv88e6xxx_get_eeprom,
6813         .set_eeprom             = mv88e6xxx_set_eeprom,
6814         .get_regs_len           = mv88e6xxx_get_regs_len,
6815         .get_regs               = mv88e6xxx_get_regs,
6816         .get_rxnfc              = mv88e6xxx_get_rxnfc,
6817         .set_rxnfc              = mv88e6xxx_set_rxnfc,
6818         .set_ageing_time        = mv88e6xxx_set_ageing_time,
6819         .port_bridge_join       = mv88e6xxx_port_bridge_join,
6820         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
6821         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
6822         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
6823         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
6824         .port_mst_state_set     = mv88e6xxx_port_mst_state_set,
6825         .port_fast_age          = mv88e6xxx_port_fast_age,
6826         .port_vlan_fast_age     = mv88e6xxx_port_vlan_fast_age,
6827         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
6828         .port_vlan_add          = mv88e6xxx_port_vlan_add,
6829         .port_vlan_del          = mv88e6xxx_port_vlan_del,
6830         .vlan_msti_set          = mv88e6xxx_vlan_msti_set,
6831         .port_fdb_add           = mv88e6xxx_port_fdb_add,
6832         .port_fdb_del           = mv88e6xxx_port_fdb_del,
6833         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
6834         .port_mdb_add           = mv88e6xxx_port_mdb_add,
6835         .port_mdb_del           = mv88e6xxx_port_mdb_del,
6836         .port_mirror_add        = mv88e6xxx_port_mirror_add,
6837         .port_mirror_del        = mv88e6xxx_port_mirror_del,
6838         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
6839         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6840         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
6841         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
6842         .port_txtstamp          = mv88e6xxx_port_txtstamp,
6843         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
6844         .get_ts_info            = mv88e6xxx_get_ts_info,
6845         .devlink_param_get      = mv88e6xxx_devlink_param_get,
6846         .devlink_param_set      = mv88e6xxx_devlink_param_set,
6847         .devlink_info_get       = mv88e6xxx_devlink_info_get,
6848         .port_lag_change        = mv88e6xxx_port_lag_change,
6849         .port_lag_join          = mv88e6xxx_port_lag_join,
6850         .port_lag_leave         = mv88e6xxx_port_lag_leave,
6851         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
6852         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
6853         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
6854 };
6855
6856 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6857 {
6858         struct device *dev = chip->dev;
6859         struct dsa_switch *ds;
6860
6861         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6862         if (!ds)
6863                 return -ENOMEM;
6864
6865         ds->dev = dev;
6866         ds->num_ports = mv88e6xxx_num_ports(chip);
6867         ds->priv = chip;
6868         ds->dev = dev;
6869         ds->ops = &mv88e6xxx_switch_ops;
6870         ds->ageing_time_min = chip->info->age_time_coeff;
6871         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6872
6873         /* Some chips support up to 32, but that requires enabling the
6874          * 5-bit port mode, which we do not support. 640k^W16 ought to
6875          * be enough for anyone.
6876          */
6877         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6878
6879         dev_set_drvdata(dev, ds);
6880
6881         return dsa_register_switch(ds);
6882 }
6883
6884 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6885 {
6886         dsa_unregister_switch(chip->ds);
6887 }
6888
6889 static const void *pdata_device_get_match_data(struct device *dev)
6890 {
6891         const struct of_device_id *matches = dev->driver->of_match_table;
6892         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6893
6894         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6895              matches++) {
6896                 if (!strcmp(pdata->compatible, matches->compatible))
6897                         return matches->data;
6898         }
6899         return NULL;
6900 }
6901
6902 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6903  * would be lost after a power cycle so prevent it to be suspended.
6904  */
6905 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6906 {
6907         return -EOPNOTSUPP;
6908 }
6909
6910 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6911 {
6912         return 0;
6913 }
6914
6915 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6916
6917 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6918 {
6919         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6920         const struct mv88e6xxx_info *compat_info = NULL;
6921         struct device *dev = &mdiodev->dev;
6922         struct device_node *np = dev->of_node;
6923         struct mv88e6xxx_chip *chip;
6924         int port;
6925         int err;
6926
6927         if (!np && !pdata)
6928                 return -EINVAL;
6929
6930         if (np)
6931                 compat_info = of_device_get_match_data(dev);
6932
6933         if (pdata) {
6934                 compat_info = pdata_device_get_match_data(dev);
6935
6936                 if (!pdata->netdev)
6937                         return -EINVAL;
6938
6939                 for (port = 0; port < DSA_MAX_PORTS; port++) {
6940                         if (!(pdata->enabled_ports & (1 << port)))
6941                                 continue;
6942                         if (strcmp(pdata->cd.port_names[port], "cpu"))
6943                                 continue;
6944                         pdata->cd.netdev[port] = &pdata->netdev->dev;
6945                         break;
6946                 }
6947         }
6948
6949         if (!compat_info)
6950                 return -EINVAL;
6951
6952         chip = mv88e6xxx_alloc_chip(dev);
6953         if (!chip) {
6954                 err = -ENOMEM;
6955                 goto out;
6956         }
6957
6958         chip->info = compat_info;
6959
6960         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6961         if (IS_ERR(chip->reset)) {
6962                 err = PTR_ERR(chip->reset);
6963                 goto out;
6964         }
6965         if (chip->reset)
6966                 usleep_range(10000, 20000);
6967
6968         /* Detect if the device is configured in single chip addressing mode,
6969          * otherwise continue with address specific smi init/detection.
6970          */
6971         err = mv88e6xxx_single_chip_detect(chip, mdiodev);
6972         if (err) {
6973                 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6974                 if (err)
6975                         goto out;
6976
6977                 err = mv88e6xxx_detect(chip);
6978                 if (err)
6979                         goto out;
6980         }
6981
6982         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6983                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6984         else
6985                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6986
6987         mv88e6xxx_phy_init(chip);
6988
6989         if (chip->info->ops->get_eeprom) {
6990                 if (np)
6991                         of_property_read_u32(np, "eeprom-length",
6992                                              &chip->eeprom_len);
6993                 else
6994                         chip->eeprom_len = pdata->eeprom_len;
6995         }
6996
6997         mv88e6xxx_reg_lock(chip);
6998         err = mv88e6xxx_switch_reset(chip);
6999         mv88e6xxx_reg_unlock(chip);
7000         if (err)
7001                 goto out;
7002
7003         if (np) {
7004                 chip->irq = of_irq_get(np, 0);
7005                 if (chip->irq == -EPROBE_DEFER) {
7006                         err = chip->irq;
7007                         goto out;
7008                 }
7009         }
7010
7011         if (pdata)
7012                 chip->irq = pdata->irq;
7013
7014         /* Has to be performed before the MDIO bus is created, because
7015          * the PHYs will link their interrupts to these interrupt
7016          * controllers
7017          */
7018         mv88e6xxx_reg_lock(chip);
7019         if (chip->irq > 0)
7020                 err = mv88e6xxx_g1_irq_setup(chip);
7021         else
7022                 err = mv88e6xxx_irq_poll_setup(chip);
7023         mv88e6xxx_reg_unlock(chip);
7024
7025         if (err)
7026                 goto out;
7027
7028         if (chip->info->g2_irqs > 0) {
7029                 err = mv88e6xxx_g2_irq_setup(chip);
7030                 if (err)
7031                         goto out_g1_irq;
7032         }
7033
7034         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7035         if (err)
7036                 goto out_g2_irq;
7037
7038         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7039         if (err)
7040                 goto out_g1_atu_prob_irq;
7041
7042         err = mv88e6xxx_register_switch(chip);
7043         if (err)
7044                 goto out_g1_vtu_prob_irq;
7045
7046         return 0;
7047
7048 out_g1_vtu_prob_irq:
7049         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7050 out_g1_atu_prob_irq:
7051         mv88e6xxx_g1_atu_prob_irq_free(chip);
7052 out_g2_irq:
7053         if (chip->info->g2_irqs > 0)
7054                 mv88e6xxx_g2_irq_free(chip);
7055 out_g1_irq:
7056         if (chip->irq > 0)
7057                 mv88e6xxx_g1_irq_free(chip);
7058         else
7059                 mv88e6xxx_irq_poll_free(chip);
7060 out:
7061         if (pdata)
7062                 dev_put(pdata->netdev);
7063
7064         return err;
7065 }
7066
7067 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7068 {
7069         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7070         struct mv88e6xxx_chip *chip;
7071
7072         if (!ds)
7073                 return;
7074
7075         chip = ds->priv;
7076
7077         if (chip->info->ptp_support) {
7078                 mv88e6xxx_hwtstamp_free(chip);
7079                 mv88e6xxx_ptp_free(chip);
7080         }
7081
7082         mv88e6xxx_phy_destroy(chip);
7083         mv88e6xxx_unregister_switch(chip);
7084
7085         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7086         mv88e6xxx_g1_atu_prob_irq_free(chip);
7087
7088         if (chip->info->g2_irqs > 0)
7089                 mv88e6xxx_g2_irq_free(chip);
7090
7091         if (chip->irq > 0)
7092                 mv88e6xxx_g1_irq_free(chip);
7093         else
7094                 mv88e6xxx_irq_poll_free(chip);
7095 }
7096
7097 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7098 {
7099         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7100
7101         if (!ds)
7102                 return;
7103
7104         dsa_switch_shutdown(ds);
7105
7106         dev_set_drvdata(&mdiodev->dev, NULL);
7107 }
7108
7109 static const struct of_device_id mv88e6xxx_of_match[] = {
7110         {
7111                 .compatible = "marvell,mv88e6085",
7112                 .data = &mv88e6xxx_table[MV88E6085],
7113         },
7114         {
7115                 .compatible = "marvell,mv88e6190",
7116                 .data = &mv88e6xxx_table[MV88E6190],
7117         },
7118         {
7119                 .compatible = "marvell,mv88e6250",
7120                 .data = &mv88e6xxx_table[MV88E6250],
7121         },
7122         { /* sentinel */ },
7123 };
7124
7125 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7126
7127 static struct mdio_driver mv88e6xxx_driver = {
7128         .probe  = mv88e6xxx_probe,
7129         .remove = mv88e6xxx_remove,
7130         .shutdown = mv88e6xxx_shutdown,
7131         .mdiodrv.driver = {
7132                 .name = "mv88e6085",
7133                 .of_match_table = mv88e6xxx_of_match,
7134                 .pm = &mv88e6xxx_pm_ops,
7135         },
7136 };
7137
7138 mdio_module_driver(mv88e6xxx_driver);
7139
7140 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7141 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7142 MODULE_LICENSE("GPL");