2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
43 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 *val)
69 return chip->smi_ops->read(chip, addr, reg, val);
72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 val)
78 return chip->smi_ops->write(chip, addr, reg, val);
81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
82 int addr, int reg, u16 *val)
86 ret = mdiobus_read_nested(chip->bus, addr, reg);
95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
96 int addr, int reg, u16 val)
100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 for (i = 0; i < 16; i++) {
118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
122 if ((ret & SMI_CMD_BUSY) == 0)
129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
130 int addr, int reg, u16 *val)
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
139 /* Transmit the read command. */
140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
145 /* Wait for the read command to complete. */
146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161 int addr, int reg, u16 val)
165 /* Wait for the bus to become free. */
166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
170 /* Transmit the data to write. */
171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
175 /* Transmit the write command. */
176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
181 /* Wait for the write command to complete. */
182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
198 assert_reg_lock(chip);
200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
214 assert_reg_lock(chip);
216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
228 struct mv88e6xxx_mdio_bus *mdio_bus;
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 return mdio_bus->bus;
238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
243 chip->g1_irq.masked |= (1 << n);
246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
251 chip->g1_irq.masked &= ~(1 << n);
254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
263 mutex_lock(&chip->reg_lock);
264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
265 mutex_unlock(&chip->reg_lock);
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
285 mutex_lock(&chip->reg_lock);
288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
300 reg |= (~chip->g1_irq.masked & mask);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
307 mutex_unlock(&chip->reg_lock);
310 static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
320 irq_hw_number_t hwirq)
322 struct mv88e6xxx_chip *chip = d->host_data;
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
345 free_irq(chip->irq, chip);
347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 irq_dispose_mapping(virq);
352 irq_domain_remove(chip->g1_irq.domain);
355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
383 /* Reading the interrupt status clears (most of) them */
384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
407 irq_domain_remove(chip->g1_irq.domain);
412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
416 for (i = 0; i < 16; i++) {
420 err = mv88e6xxx_read(chip, addr, reg, &val);
427 usleep_range(1000, 2000);
430 dev_err(chip->dev, "Timeout while waiting for switch\n");
434 /* Indirect write to single pointer-data register with an Update bit */
435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
440 /* Wait until the previous operation is completed */
441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
448 return mv88e6xxx_write(chip, addr, reg, val);
451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
457 if (!chip->info->ops->port_set_link)
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
491 if (chip->info->ops->port_set_link(chip, port, link))
492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
497 /* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
504 struct mv88e6xxx_chip *chip = ds->priv;
507 if (!phy_is_pseudo_fixed_link(phydev))
510 mutex_lock(&chip->reg_lock);
511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
513 mutex_unlock(&chip->reg_lock);
515 if (err && err != -EOPNOTSUPP)
516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
521 if (!chip->info->ops->stats_snapshot)
524 return chip->info->ops->stats_snapshot(chip, port);
527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590 struct mv88e6xxx_hw_stat *s,
591 int port, u16 bank1_select,
601 case STATS_TYPE_PORT:
602 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
607 if (s->sizeof_stat == 4) {
608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
614 case STATS_TYPE_BANK1:
617 case STATS_TYPE_BANK0:
618 reg |= s->reg | histogram;
619 mv88e6xxx_g1_stats_read(chip, reg, &low);
620 if (s->sizeof_stat == 8)
621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
626 value = (((u64)high) << 16) | low;
630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
633 struct mv88e6xxx_hw_stat *stat;
636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
638 if (stat->type & types) {
639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
663 struct mv88e6xxx_chip *chip = ds->priv;
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
672 struct mv88e6xxx_hw_stat *stat;
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
677 if (stat->type & types)
683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
697 struct mv88e6xxx_chip *chip = ds->priv;
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
709 struct mv88e6xxx_hw_stat *stat;
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
726 return mv88e6xxx_stats_get_stats(chip, port, data,
727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
734 return mv88e6xxx_stats_get_stats(chip, port, data,
735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
759 struct mv88e6xxx_chip *chip = ds->priv;
762 mutex_lock(&chip->reg_lock);
764 ret = mv88e6xxx_stats_snapshot(chip, port);
766 mutex_unlock(&chip->reg_lock);
770 mv88e6xxx_get_stats(chip, port, data);
772 mutex_unlock(&chip->reg_lock);
775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
785 return 32 * sizeof(u16);
788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
791 struct mv88e6xxx_chip *chip = ds->priv;
799 memset(p, 0xff, 32 * sizeof(u16));
801 mutex_lock(&chip->reg_lock);
803 for (i = 0; i < 32; i++) {
805 err = mv88e6xxx_port_read(chip, port, i, ®);
810 mutex_unlock(&chip->reg_lock);
813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
814 struct ethtool_eee *e)
816 /* Nothing to do on the port's MAC */
820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
821 struct ethtool_eee *e)
823 /* Nothing to do on the port's MAC */
827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
829 struct dsa_switch *ds = NULL;
830 struct net_device *br;
834 if (dev < DSA_MAX_SWITCHES)
835 ds = chip->ds->dst->ds[dev];
837 /* Prevent frames from unknown switch or port */
838 if (!ds || port >= ds->num_ports)
841 /* Frames from DSA links and CPU ports can egress any local port */
842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
843 return mv88e6xxx_port_mask(chip);
845 br = ds->ports[port].bridge_dev;
848 /* Frames from user ports can egress any local DSA links and CPU ports,
849 * as well as any local member of their bridge group.
851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
852 if (dsa_is_cpu_port(chip->ds, i) ||
853 dsa_is_dsa_port(chip->ds, i) ||
854 (br && chip->ds->ports[i].bridge_dev == br))
860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
864 /* prevent frames from going back out of the port they came in on */
865 output_ports &= ~BIT(port);
867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
873 struct mv88e6xxx_chip *chip = ds->priv;
876 mutex_lock(&chip->reg_lock);
877 err = mv88e6xxx_port_set_state(chip, port, state);
878 mutex_unlock(&chip->reg_lock);
881 dev_err(ds->dev, "p%d: failed to update state\n", port);
884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
886 if (chip->info->ops->pot_clear)
887 return chip->info->ops->pot_clear(chip);
892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
894 if (chip->info->ops->mgmt_rsvd2cpu)
895 return chip->info->ops->mgmt_rsvd2cpu(chip);
900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
904 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
920 if (!chip->info->ops->irl_init_all)
923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
924 /* Disable ingress rate limiting by resetting all per port
925 * ingress rate limit resources to their initial state.
927 err = chip->info->ops->irl_init_all(chip, port);
935 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
939 if (!mv88e6xxx_has_pvt(chip))
942 /* Skip the local source device, which uses in-chip port VLAN */
943 if (dev != chip->ds->index)
944 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
946 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
949 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
954 if (!mv88e6xxx_has_pvt(chip))
957 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
958 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
960 err = mv88e6xxx_g2_misc_4_bit_port(chip);
964 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
965 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
966 err = mv88e6xxx_pvt_map(chip, dev, port);
975 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
977 struct mv88e6xxx_chip *chip = ds->priv;
980 mutex_lock(&chip->reg_lock);
981 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
982 mutex_unlock(&chip->reg_lock);
985 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
988 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
990 if (!chip->info->max_vid)
993 return mv88e6xxx_g1_vtu_flush(chip);
996 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
997 struct mv88e6xxx_vtu_entry *entry)
999 if (!chip->info->ops->vtu_getnext)
1002 return chip->info->ops->vtu_getnext(chip, entry);
1005 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1006 struct mv88e6xxx_vtu_entry *entry)
1008 if (!chip->info->ops->vtu_loadpurge)
1011 return chip->info->ops->vtu_loadpurge(chip, entry);
1014 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1015 struct switchdev_obj_port_vlan *vlan,
1016 switchdev_obj_dump_cb_t *cb)
1018 struct mv88e6xxx_chip *chip = ds->priv;
1019 struct mv88e6xxx_vtu_entry next = {
1020 .vid = chip->info->max_vid,
1025 if (!chip->info->max_vid)
1028 mutex_lock(&chip->reg_lock);
1030 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1035 err = mv88e6xxx_vtu_getnext(chip, &next);
1042 if (next.member[port] ==
1043 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1046 /* reinit and dump this VLAN obj */
1047 vlan->vid_begin = next.vid;
1048 vlan->vid_end = next.vid;
1051 if (next.member[port] ==
1052 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
1053 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1055 if (next.vid == pvid)
1056 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1058 err = cb(&vlan->obj);
1061 } while (next.vid < chip->info->max_vid);
1064 mutex_unlock(&chip->reg_lock);
1069 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1071 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1072 struct mv88e6xxx_vtu_entry vlan = {
1073 .vid = chip->info->max_vid,
1077 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1079 /* Set every FID bit used by the (un)bridged ports */
1080 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1081 err = mv88e6xxx_port_get_fid(chip, i, fid);
1085 set_bit(*fid, fid_bitmap);
1088 /* Set every FID bit used by the VLAN entries */
1090 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1097 set_bit(vlan.fid, fid_bitmap);
1098 } while (vlan.vid < chip->info->max_vid);
1100 /* The reset value 0x000 is used to indicate that multiple address
1101 * databases are not needed. Return the next positive available.
1103 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1104 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1107 /* Clear the database */
1108 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1111 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1112 struct mv88e6xxx_vtu_entry *entry, bool new)
1119 entry->vid = vid - 1;
1120 entry->valid = false;
1122 err = mv88e6xxx_vtu_getnext(chip, entry);
1126 if (entry->vid == vid && entry->valid)
1132 /* Initialize a fresh VLAN entry */
1133 memset(entry, 0, sizeof(*entry));
1134 entry->valid = true;
1137 /* Exclude all ports */
1138 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1140 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1142 return mv88e6xxx_atu_new(chip, &entry->fid);
1145 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1149 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1150 u16 vid_begin, u16 vid_end)
1152 struct mv88e6xxx_chip *chip = ds->priv;
1153 struct mv88e6xxx_vtu_entry vlan = {
1154 .vid = vid_begin - 1,
1161 mutex_lock(&chip->reg_lock);
1164 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1171 if (vlan.vid > vid_end)
1174 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1175 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1178 if (!ds->ports[port].netdev)
1181 if (vlan.member[i] ==
1182 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1185 if (ds->ports[i].bridge_dev ==
1186 ds->ports[port].bridge_dev)
1187 break; /* same bridge, check next VLAN */
1189 if (!ds->ports[i].bridge_dev)
1192 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1194 netdev_name(ds->ports[i].bridge_dev));
1198 } while (vlan.vid < vid_end);
1201 mutex_unlock(&chip->reg_lock);
1206 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1207 bool vlan_filtering)
1209 struct mv88e6xxx_chip *chip = ds->priv;
1210 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1211 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1214 if (!chip->info->max_vid)
1217 mutex_lock(&chip->reg_lock);
1218 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1219 mutex_unlock(&chip->reg_lock);
1225 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1226 const struct switchdev_obj_port_vlan *vlan,
1227 struct switchdev_trans *trans)
1229 struct mv88e6xxx_chip *chip = ds->priv;
1232 if (!chip->info->max_vid)
1235 /* If the requested port doesn't belong to the same bridge as the VLAN
1236 * members, do not support it (yet) and fallback to software VLAN.
1238 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1243 /* We don't need any dynamic resource from the kernel (yet),
1244 * so skip the prepare phase.
1249 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1252 struct mv88e6xxx_vtu_entry vlan;
1255 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1259 vlan.member[port] = member;
1261 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1264 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1265 const struct switchdev_obj_port_vlan *vlan,
1266 struct switchdev_trans *trans)
1268 struct mv88e6xxx_chip *chip = ds->priv;
1269 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1270 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1274 if (!chip->info->max_vid)
1277 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1278 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1280 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1282 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1284 mutex_lock(&chip->reg_lock);
1286 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1287 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1288 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1289 vid, untagged ? 'u' : 't');
1291 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1292 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1295 mutex_unlock(&chip->reg_lock);
1298 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1301 struct mv88e6xxx_vtu_entry vlan;
1304 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1308 /* Tell switchdev if this VLAN is handled in software */
1309 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1312 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1314 /* keep the VLAN unless all ports are excluded */
1316 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1317 if (vlan.member[i] !=
1318 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1324 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1328 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1331 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1332 const struct switchdev_obj_port_vlan *vlan)
1334 struct mv88e6xxx_chip *chip = ds->priv;
1338 if (!chip->info->max_vid)
1341 mutex_lock(&chip->reg_lock);
1343 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1347 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1348 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1353 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1360 mutex_unlock(&chip->reg_lock);
1365 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1366 const unsigned char *addr, u16 vid,
1369 struct mv88e6xxx_vtu_entry vlan;
1370 struct mv88e6xxx_atu_entry entry;
1373 /* Null VLAN ID corresponds to the port private database */
1375 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1377 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1381 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1382 ether_addr_copy(entry.mac, addr);
1383 eth_addr_dec(entry.mac);
1385 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1389 /* Initialize a fresh ATU entry if it isn't found */
1390 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1391 !ether_addr_equal(entry.mac, addr)) {
1392 memset(&entry, 0, sizeof(entry));
1393 ether_addr_copy(entry.mac, addr);
1396 /* Purge the ATU entry only if no port is using it anymore */
1397 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1398 entry.portvec &= ~BIT(port);
1400 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1402 entry.portvec |= BIT(port);
1403 entry.state = state;
1406 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1409 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1410 const unsigned char *addr, u16 vid)
1412 struct mv88e6xxx_chip *chip = ds->priv;
1415 mutex_lock(&chip->reg_lock);
1416 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1417 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1418 mutex_unlock(&chip->reg_lock);
1423 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1424 const unsigned char *addr, u16 vid)
1426 struct mv88e6xxx_chip *chip = ds->priv;
1429 mutex_lock(&chip->reg_lock);
1430 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1431 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1432 mutex_unlock(&chip->reg_lock);
1437 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1438 u16 fid, u16 vid, int port,
1439 struct switchdev_obj *obj,
1440 switchdev_obj_dump_cb_t *cb)
1442 struct mv88e6xxx_atu_entry addr;
1445 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1446 eth_broadcast_addr(addr.mac);
1449 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1453 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1456 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1459 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1460 struct switchdev_obj_port_fdb *fdb;
1462 if (!is_unicast_ether_addr(addr.mac))
1465 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
1467 ether_addr_copy(fdb->addr, addr.mac);
1468 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1469 fdb->ndm_state = NUD_NOARP;
1471 fdb->ndm_state = NUD_REACHABLE;
1472 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1473 struct switchdev_obj_port_mdb *mdb;
1475 if (!is_multicast_ether_addr(addr.mac))
1478 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1480 ether_addr_copy(mdb->addr, addr.mac);
1488 } while (!is_broadcast_ether_addr(addr.mac));
1493 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1494 struct switchdev_obj *obj,
1495 switchdev_obj_dump_cb_t *cb)
1497 struct mv88e6xxx_vtu_entry vlan = {
1498 .vid = chip->info->max_vid,
1503 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1504 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1508 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1512 /* Dump VLANs' Filtering Information Databases */
1514 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1521 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1525 } while (vlan.vid < chip->info->max_vid);
1530 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1531 struct switchdev_obj_port_fdb *fdb,
1532 switchdev_obj_dump_cb_t *cb)
1534 struct mv88e6xxx_chip *chip = ds->priv;
1537 mutex_lock(&chip->reg_lock);
1538 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
1539 mutex_unlock(&chip->reg_lock);
1544 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1545 struct net_device *br)
1547 struct dsa_switch *ds;
1552 /* Remap the Port VLAN of each local bridge group member */
1553 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1554 if (chip->ds->ports[port].bridge_dev == br) {
1555 err = mv88e6xxx_port_vlan_map(chip, port);
1561 if (!mv88e6xxx_has_pvt(chip))
1564 /* Remap the Port VLAN of each cross-chip bridge group member */
1565 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1566 ds = chip->ds->dst->ds[dev];
1570 for (port = 0; port < ds->num_ports; ++port) {
1571 if (ds->ports[port].bridge_dev == br) {
1572 err = mv88e6xxx_pvt_map(chip, dev, port);
1582 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1583 struct net_device *br)
1585 struct mv88e6xxx_chip *chip = ds->priv;
1588 mutex_lock(&chip->reg_lock);
1589 err = mv88e6xxx_bridge_map(chip, br);
1590 mutex_unlock(&chip->reg_lock);
1595 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1596 struct net_device *br)
1598 struct mv88e6xxx_chip *chip = ds->priv;
1600 mutex_lock(&chip->reg_lock);
1601 if (mv88e6xxx_bridge_map(chip, br) ||
1602 mv88e6xxx_port_vlan_map(chip, port))
1603 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1604 mutex_unlock(&chip->reg_lock);
1607 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1608 int port, struct net_device *br)
1610 struct mv88e6xxx_chip *chip = ds->priv;
1613 if (!mv88e6xxx_has_pvt(chip))
1616 mutex_lock(&chip->reg_lock);
1617 err = mv88e6xxx_pvt_map(chip, dev, port);
1618 mutex_unlock(&chip->reg_lock);
1623 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1624 int port, struct net_device *br)
1626 struct mv88e6xxx_chip *chip = ds->priv;
1628 if (!mv88e6xxx_has_pvt(chip))
1631 mutex_lock(&chip->reg_lock);
1632 if (mv88e6xxx_pvt_map(chip, dev, port))
1633 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1634 mutex_unlock(&chip->reg_lock);
1637 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1639 if (chip->info->ops->reset)
1640 return chip->info->ops->reset(chip);
1645 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1647 struct gpio_desc *gpiod = chip->reset;
1649 /* If there is a GPIO connected to the reset pin, toggle it */
1651 gpiod_set_value_cansleep(gpiod, 1);
1652 usleep_range(10000, 20000);
1653 gpiod_set_value_cansleep(gpiod, 0);
1654 usleep_range(10000, 20000);
1658 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1662 /* Set all ports to the Disabled state */
1663 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1664 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1669 /* Wait for transmit queues to drain,
1670 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1672 usleep_range(2000, 4000);
1677 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1681 err = mv88e6xxx_disable_ports(chip);
1685 mv88e6xxx_hardware_reset(chip);
1687 return mv88e6xxx_software_reset(chip);
1690 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1691 enum mv88e6xxx_frame_mode frame,
1692 enum mv88e6xxx_egress_mode egress, u16 etype)
1696 if (!chip->info->ops->port_set_frame_mode)
1699 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1703 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1707 if (chip->info->ops->port_set_ether_type)
1708 return chip->info->ops->port_set_ether_type(chip, port, etype);
1713 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1715 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1716 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1717 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1720 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1722 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1723 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1724 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1727 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1729 return mv88e6xxx_set_port_mode(chip, port,
1730 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1731 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1735 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1737 if (dsa_is_dsa_port(chip->ds, port))
1738 return mv88e6xxx_set_port_mode_dsa(chip, port);
1740 if (dsa_is_normal_port(chip->ds, port))
1741 return mv88e6xxx_set_port_mode_normal(chip, port);
1743 /* Setup CPU port mode depending on its supported tag format */
1744 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1745 return mv88e6xxx_set_port_mode_dsa(chip, port);
1747 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1748 return mv88e6xxx_set_port_mode_edsa(chip, port);
1753 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1755 bool message = dsa_is_dsa_port(chip->ds, port);
1757 return mv88e6xxx_port_set_message_port(chip, port, message);
1760 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1762 bool flood = port == dsa_upstream_port(chip->ds);
1764 /* Upstream ports flood frames with unknown unicast or multicast DA */
1765 if (chip->info->ops->port_set_egress_floods)
1766 return chip->info->ops->port_set_egress_floods(chip, port,
1772 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1775 if (chip->info->ops->serdes_power)
1776 return chip->info->ops->serdes_power(chip, port, on);
1781 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1783 struct dsa_switch *ds = chip->ds;
1787 /* MAC Forcing register: don't force link, speed, duplex or flow control
1788 * state to any particular values on physical ports, but force the CPU
1789 * port and all DSA ports to their maximum bandwidth and full duplex.
1791 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1792 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1793 SPEED_MAX, DUPLEX_FULL,
1794 PHY_INTERFACE_MODE_NA);
1796 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1797 SPEED_UNFORCED, DUPLEX_UNFORCED,
1798 PHY_INTERFACE_MODE_NA);
1802 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1803 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1804 * tunneling, determine priority by looking at 802.1p and IP
1805 * priority fields (IP prio has precedence), and set STP state
1808 * If this is the CPU link, use DSA or EDSA tagging depending
1809 * on which tagging mode was configured.
1811 * If this is a link to another switch, use DSA tagging mode.
1813 * If this is the upstream port for this switch, enable
1814 * forwarding of unknown unicasts and multicasts.
1816 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1817 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1818 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1819 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1823 err = mv88e6xxx_setup_port_mode(chip, port);
1827 err = mv88e6xxx_setup_egress_floods(chip, port);
1831 /* Enable the SERDES interface for DSA and CPU ports. Normal
1832 * ports SERDES are enabled when the port is enabled, thus
1833 * saving a bit of power.
1835 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1836 err = mv88e6xxx_serdes_power(chip, port, true);
1841 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1842 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1843 * untagged frames on this port, do a destination address lookup on all
1844 * received packets as usual, disable ARP mirroring and don't send a
1845 * copy of all transmitted/received frames on this port to the CPU.
1847 err = mv88e6xxx_port_set_map_da(chip, port);
1852 if (chip->info->ops->port_set_upstream_port) {
1853 err = chip->info->ops->port_set_upstream_port(
1854 chip, port, dsa_upstream_port(ds));
1859 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1860 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1864 if (chip->info->ops->port_set_jumbo_size) {
1865 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1870 /* Port Association Vector: when learning source addresses
1871 * of packets, add the address to the address database using
1872 * a port bitmap that has only the bit for this port set and
1873 * the other bits clear.
1876 /* Disable learning for CPU port */
1877 if (dsa_is_cpu_port(ds, port))
1880 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1885 /* Egress rate control 2: disable egress rate control. */
1886 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1891 if (chip->info->ops->port_pause_limit) {
1892 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1897 if (chip->info->ops->port_disable_learn_limit) {
1898 err = chip->info->ops->port_disable_learn_limit(chip, port);
1903 if (chip->info->ops->port_disable_pri_override) {
1904 err = chip->info->ops->port_disable_pri_override(chip, port);
1909 if (chip->info->ops->port_tag_remap) {
1910 err = chip->info->ops->port_tag_remap(chip, port);
1915 if (chip->info->ops->port_egress_rate_limiting) {
1916 err = chip->info->ops->port_egress_rate_limiting(chip, port);
1921 err = mv88e6xxx_setup_message_port(chip, port);
1925 /* Port based VLAN map: give each port the same default address
1926 * database, and allow bidirectional communication between the
1927 * CPU and DSA port(s), and the other ports.
1929 err = mv88e6xxx_port_set_fid(chip, port, 0);
1933 err = mv88e6xxx_port_vlan_map(chip, port);
1937 /* Default VLAN ID and priority: don't set a default VLAN
1938 * ID, and set the default packet priority to zero.
1940 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1943 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1944 struct phy_device *phydev)
1946 struct mv88e6xxx_chip *chip = ds->priv;
1949 mutex_lock(&chip->reg_lock);
1950 err = mv88e6xxx_serdes_power(chip, port, true);
1951 mutex_unlock(&chip->reg_lock);
1956 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1957 struct phy_device *phydev)
1959 struct mv88e6xxx_chip *chip = ds->priv;
1961 mutex_lock(&chip->reg_lock);
1962 if (mv88e6xxx_serdes_power(chip, port, false))
1963 dev_err(chip->dev, "failed to power off SERDES\n");
1964 mutex_unlock(&chip->reg_lock);
1967 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1968 unsigned int ageing_time)
1970 struct mv88e6xxx_chip *chip = ds->priv;
1973 mutex_lock(&chip->reg_lock);
1974 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1975 mutex_unlock(&chip->reg_lock);
1980 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1982 struct dsa_switch *ds = chip->ds;
1983 u32 upstream_port = dsa_upstream_port(ds);
1986 if (chip->info->ops->set_cpu_port) {
1987 err = chip->info->ops->set_cpu_port(chip, upstream_port);
1992 if (chip->info->ops->set_egress_port) {
1993 err = chip->info->ops->set_egress_port(chip, upstream_port);
1998 /* Disable remote management, and set the switch's DSA device number. */
1999 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2000 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2001 (ds->index & 0x1f));
2005 /* Configure the IP ToS mapping registers. */
2006 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2009 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2012 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2015 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2018 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2021 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2024 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2027 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2031 /* Configure the IEEE 802.1p priority mapping register. */
2032 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2036 /* Initialize the statistics unit */
2037 err = mv88e6xxx_stats_set_histogram(chip);
2041 /* Clear the statistics counters for all ports */
2042 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2043 MV88E6XXX_G1_STATS_OP_BUSY |
2044 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
2048 /* Wait for the flush to complete. */
2049 err = mv88e6xxx_g1_stats_wait(chip);
2056 static int mv88e6xxx_setup(struct dsa_switch *ds)
2058 struct mv88e6xxx_chip *chip = ds->priv;
2063 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2065 mutex_lock(&chip->reg_lock);
2067 /* Setup Switch Port Registers */
2068 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2069 err = mv88e6xxx_setup_port(chip, i);
2074 /* Setup Switch Global 1 Registers */
2075 err = mv88e6xxx_g1_setup(chip);
2079 /* Setup Switch Global 2 Registers */
2080 if (chip->info->global2_addr) {
2081 err = mv88e6xxx_g2_setup(chip);
2086 err = mv88e6xxx_irl_setup(chip);
2090 err = mv88e6xxx_phy_setup(chip);
2094 err = mv88e6xxx_vtu_setup(chip);
2098 err = mv88e6xxx_pvt_setup(chip);
2102 err = mv88e6xxx_atu_setup(chip);
2106 err = mv88e6xxx_pot_setup(chip);
2110 err = mv88e6xxx_rsvd2cpu_setup(chip);
2115 mutex_unlock(&chip->reg_lock);
2120 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2122 struct mv88e6xxx_chip *chip = ds->priv;
2125 if (!chip->info->ops->set_switch_mac)
2128 mutex_lock(&chip->reg_lock);
2129 err = chip->info->ops->set_switch_mac(chip, addr);
2130 mutex_unlock(&chip->reg_lock);
2135 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2137 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2138 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2142 if (!chip->info->ops->phy_read)
2145 mutex_lock(&chip->reg_lock);
2146 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2147 mutex_unlock(&chip->reg_lock);
2149 if (reg == MII_PHYSID2) {
2150 /* Some internal PHYS don't have a model number. Use
2151 * the mv88e6390 family model number instead.
2154 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2157 return err ? err : val;
2160 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2162 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2163 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2166 if (!chip->info->ops->phy_write)
2169 mutex_lock(&chip->reg_lock);
2170 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2171 mutex_unlock(&chip->reg_lock);
2176 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2177 struct device_node *np,
2181 struct mv88e6xxx_mdio_bus *mdio_bus;
2182 struct mii_bus *bus;
2185 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2189 mdio_bus = bus->priv;
2190 mdio_bus->bus = bus;
2191 mdio_bus->chip = chip;
2192 INIT_LIST_HEAD(&mdio_bus->list);
2193 mdio_bus->external = external;
2196 bus->name = np->full_name;
2197 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2199 bus->name = "mv88e6xxx SMI";
2200 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2203 bus->read = mv88e6xxx_mdio_read;
2204 bus->write = mv88e6xxx_mdio_write;
2205 bus->parent = chip->dev;
2208 err = of_mdiobus_register(bus, np);
2210 err = mdiobus_register(bus);
2212 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2217 list_add_tail(&mdio_bus->list, &chip->mdios);
2219 list_add(&mdio_bus->list, &chip->mdios);
2224 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2225 { .compatible = "marvell,mv88e6xxx-mdio-external",
2226 .data = (void *)true },
2230 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2231 struct device_node *np)
2233 const struct of_device_id *match;
2234 struct device_node *child;
2237 /* Always register one mdio bus for the internal/default mdio
2238 * bus. This maybe represented in the device tree, but is
2241 child = of_get_child_by_name(np, "mdio");
2242 err = mv88e6xxx_mdio_register(chip, child, false);
2246 /* Walk the device tree, and see if there are any other nodes
2247 * which say they are compatible with the external mdio
2250 for_each_available_child_of_node(np, child) {
2251 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2253 err = mv88e6xxx_mdio_register(chip, child, true);
2262 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2265 struct mv88e6xxx_mdio_bus *mdio_bus;
2266 struct mii_bus *bus;
2268 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2269 bus = mdio_bus->bus;
2271 mdiobus_unregister(bus);
2275 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2277 struct mv88e6xxx_chip *chip = ds->priv;
2279 return chip->eeprom_len;
2282 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2283 struct ethtool_eeprom *eeprom, u8 *data)
2285 struct mv88e6xxx_chip *chip = ds->priv;
2288 if (!chip->info->ops->get_eeprom)
2291 mutex_lock(&chip->reg_lock);
2292 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2293 mutex_unlock(&chip->reg_lock);
2298 eeprom->magic = 0xc3ec4951;
2303 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2304 struct ethtool_eeprom *eeprom, u8 *data)
2306 struct mv88e6xxx_chip *chip = ds->priv;
2309 if (!chip->info->ops->set_eeprom)
2312 if (eeprom->magic != 0xc3ec4951)
2315 mutex_lock(&chip->reg_lock);
2316 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2317 mutex_unlock(&chip->reg_lock);
2322 static const struct mv88e6xxx_ops mv88e6085_ops = {
2323 /* MV88E6XXX_FAMILY_6097 */
2324 .irl_init_all = mv88e6352_g2_irl_init_all,
2325 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2326 .phy_read = mv88e6185_phy_ppu_read,
2327 .phy_write = mv88e6185_phy_ppu_write,
2328 .port_set_link = mv88e6xxx_port_set_link,
2329 .port_set_duplex = mv88e6xxx_port_set_duplex,
2330 .port_set_speed = mv88e6185_port_set_speed,
2331 .port_tag_remap = mv88e6095_port_tag_remap,
2332 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2333 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2334 .port_set_ether_type = mv88e6351_port_set_ether_type,
2335 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2336 .port_pause_limit = mv88e6097_port_pause_limit,
2337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2339 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2340 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2341 .stats_get_strings = mv88e6095_stats_get_strings,
2342 .stats_get_stats = mv88e6095_stats_get_stats,
2343 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2344 .set_egress_port = mv88e6095_g1_set_egress_port,
2345 .watchdog_ops = &mv88e6097_watchdog_ops,
2346 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2347 .pot_clear = mv88e6xxx_g2_pot_clear,
2348 .ppu_enable = mv88e6185_g1_ppu_enable,
2349 .ppu_disable = mv88e6185_g1_ppu_disable,
2350 .reset = mv88e6185_g1_reset,
2351 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2352 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2355 static const struct mv88e6xxx_ops mv88e6095_ops = {
2356 /* MV88E6XXX_FAMILY_6095 */
2357 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2358 .phy_read = mv88e6185_phy_ppu_read,
2359 .phy_write = mv88e6185_phy_ppu_write,
2360 .port_set_link = mv88e6xxx_port_set_link,
2361 .port_set_duplex = mv88e6xxx_port_set_duplex,
2362 .port_set_speed = mv88e6185_port_set_speed,
2363 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2364 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2365 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2366 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2367 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2368 .stats_get_strings = mv88e6095_stats_get_strings,
2369 .stats_get_stats = mv88e6095_stats_get_stats,
2370 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2371 .ppu_enable = mv88e6185_g1_ppu_enable,
2372 .ppu_disable = mv88e6185_g1_ppu_disable,
2373 .reset = mv88e6185_g1_reset,
2374 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2375 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2378 static const struct mv88e6xxx_ops mv88e6097_ops = {
2379 /* MV88E6XXX_FAMILY_6097 */
2380 .irl_init_all = mv88e6352_g2_irl_init_all,
2381 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2382 .phy_read = mv88e6xxx_g2_smi_phy_read,
2383 .phy_write = mv88e6xxx_g2_smi_phy_write,
2384 .port_set_link = mv88e6xxx_port_set_link,
2385 .port_set_duplex = mv88e6xxx_port_set_duplex,
2386 .port_set_speed = mv88e6185_port_set_speed,
2387 .port_tag_remap = mv88e6095_port_tag_remap,
2388 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2389 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2390 .port_set_ether_type = mv88e6351_port_set_ether_type,
2391 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2392 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2393 .port_pause_limit = mv88e6097_port_pause_limit,
2394 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2395 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2396 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2397 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2398 .stats_get_strings = mv88e6095_stats_get_strings,
2399 .stats_get_stats = mv88e6095_stats_get_stats,
2400 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2401 .set_egress_port = mv88e6095_g1_set_egress_port,
2402 .watchdog_ops = &mv88e6097_watchdog_ops,
2403 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2404 .pot_clear = mv88e6xxx_g2_pot_clear,
2405 .reset = mv88e6352_g1_reset,
2406 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2407 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2410 static const struct mv88e6xxx_ops mv88e6123_ops = {
2411 /* MV88E6XXX_FAMILY_6165 */
2412 .irl_init_all = mv88e6352_g2_irl_init_all,
2413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2414 .phy_read = mv88e6xxx_g2_smi_phy_read,
2415 .phy_write = mv88e6xxx_g2_smi_phy_write,
2416 .port_set_link = mv88e6xxx_port_set_link,
2417 .port_set_duplex = mv88e6xxx_port_set_duplex,
2418 .port_set_speed = mv88e6185_port_set_speed,
2419 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2420 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2421 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2422 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2423 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2424 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2425 .stats_get_strings = mv88e6095_stats_get_strings,
2426 .stats_get_stats = mv88e6095_stats_get_stats,
2427 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2428 .set_egress_port = mv88e6095_g1_set_egress_port,
2429 .watchdog_ops = &mv88e6097_watchdog_ops,
2430 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2431 .pot_clear = mv88e6xxx_g2_pot_clear,
2432 .reset = mv88e6352_g1_reset,
2433 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2434 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2437 static const struct mv88e6xxx_ops mv88e6131_ops = {
2438 /* MV88E6XXX_FAMILY_6185 */
2439 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2440 .phy_read = mv88e6185_phy_ppu_read,
2441 .phy_write = mv88e6185_phy_ppu_write,
2442 .port_set_link = mv88e6xxx_port_set_link,
2443 .port_set_duplex = mv88e6xxx_port_set_duplex,
2444 .port_set_speed = mv88e6185_port_set_speed,
2445 .port_tag_remap = mv88e6095_port_tag_remap,
2446 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2447 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2448 .port_set_ether_type = mv88e6351_port_set_ether_type,
2449 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2450 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2451 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2452 .port_pause_limit = mv88e6097_port_pause_limit,
2453 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2454 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2455 .stats_get_strings = mv88e6095_stats_get_strings,
2456 .stats_get_stats = mv88e6095_stats_get_stats,
2457 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2458 .set_egress_port = mv88e6095_g1_set_egress_port,
2459 .watchdog_ops = &mv88e6097_watchdog_ops,
2460 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2461 .ppu_enable = mv88e6185_g1_ppu_enable,
2462 .ppu_disable = mv88e6185_g1_ppu_disable,
2463 .reset = mv88e6185_g1_reset,
2464 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2465 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2468 static const struct mv88e6xxx_ops mv88e6141_ops = {
2469 /* MV88E6XXX_FAMILY_6341 */
2470 .irl_init_all = mv88e6352_g2_irl_init_all,
2471 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2472 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2473 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2474 .phy_read = mv88e6xxx_g2_smi_phy_read,
2475 .phy_write = mv88e6xxx_g2_smi_phy_write,
2476 .port_set_link = mv88e6xxx_port_set_link,
2477 .port_set_duplex = mv88e6xxx_port_set_duplex,
2478 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2479 .port_set_speed = mv88e6390_port_set_speed,
2480 .port_tag_remap = mv88e6095_port_tag_remap,
2481 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2482 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2483 .port_set_ether_type = mv88e6351_port_set_ether_type,
2484 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2485 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2486 .port_pause_limit = mv88e6097_port_pause_limit,
2487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2489 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2490 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2491 .stats_get_strings = mv88e6320_stats_get_strings,
2492 .stats_get_stats = mv88e6390_stats_get_stats,
2493 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2494 .set_egress_port = mv88e6390_g1_set_egress_port,
2495 .watchdog_ops = &mv88e6390_watchdog_ops,
2496 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2497 .pot_clear = mv88e6xxx_g2_pot_clear,
2498 .reset = mv88e6352_g1_reset,
2499 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2500 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2503 static const struct mv88e6xxx_ops mv88e6161_ops = {
2504 /* MV88E6XXX_FAMILY_6165 */
2505 .irl_init_all = mv88e6352_g2_irl_init_all,
2506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2507 .phy_read = mv88e6xxx_g2_smi_phy_read,
2508 .phy_write = mv88e6xxx_g2_smi_phy_write,
2509 .port_set_link = mv88e6xxx_port_set_link,
2510 .port_set_duplex = mv88e6xxx_port_set_duplex,
2511 .port_set_speed = mv88e6185_port_set_speed,
2512 .port_tag_remap = mv88e6095_port_tag_remap,
2513 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2514 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2515 .port_set_ether_type = mv88e6351_port_set_ether_type,
2516 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2517 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2518 .port_pause_limit = mv88e6097_port_pause_limit,
2519 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2520 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2521 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2522 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2523 .stats_get_strings = mv88e6095_stats_get_strings,
2524 .stats_get_stats = mv88e6095_stats_get_stats,
2525 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2526 .set_egress_port = mv88e6095_g1_set_egress_port,
2527 .watchdog_ops = &mv88e6097_watchdog_ops,
2528 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2529 .pot_clear = mv88e6xxx_g2_pot_clear,
2530 .reset = mv88e6352_g1_reset,
2531 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2532 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2535 static const struct mv88e6xxx_ops mv88e6165_ops = {
2536 /* MV88E6XXX_FAMILY_6165 */
2537 .irl_init_all = mv88e6352_g2_irl_init_all,
2538 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2539 .phy_read = mv88e6165_phy_read,
2540 .phy_write = mv88e6165_phy_write,
2541 .port_set_link = mv88e6xxx_port_set_link,
2542 .port_set_duplex = mv88e6xxx_port_set_duplex,
2543 .port_set_speed = mv88e6185_port_set_speed,
2544 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2545 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2546 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2547 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2548 .stats_get_strings = mv88e6095_stats_get_strings,
2549 .stats_get_stats = mv88e6095_stats_get_stats,
2550 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2551 .set_egress_port = mv88e6095_g1_set_egress_port,
2552 .watchdog_ops = &mv88e6097_watchdog_ops,
2553 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2554 .pot_clear = mv88e6xxx_g2_pot_clear,
2555 .reset = mv88e6352_g1_reset,
2556 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2557 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2560 static const struct mv88e6xxx_ops mv88e6171_ops = {
2561 /* MV88E6XXX_FAMILY_6351 */
2562 .irl_init_all = mv88e6352_g2_irl_init_all,
2563 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2564 .phy_read = mv88e6xxx_g2_smi_phy_read,
2565 .phy_write = mv88e6xxx_g2_smi_phy_write,
2566 .port_set_link = mv88e6xxx_port_set_link,
2567 .port_set_duplex = mv88e6xxx_port_set_duplex,
2568 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2569 .port_set_speed = mv88e6185_port_set_speed,
2570 .port_tag_remap = mv88e6095_port_tag_remap,
2571 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2572 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2573 .port_set_ether_type = mv88e6351_port_set_ether_type,
2574 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2575 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2576 .port_pause_limit = mv88e6097_port_pause_limit,
2577 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2578 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2579 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2580 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2581 .stats_get_strings = mv88e6095_stats_get_strings,
2582 .stats_get_stats = mv88e6095_stats_get_stats,
2583 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2584 .set_egress_port = mv88e6095_g1_set_egress_port,
2585 .watchdog_ops = &mv88e6097_watchdog_ops,
2586 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2587 .pot_clear = mv88e6xxx_g2_pot_clear,
2588 .reset = mv88e6352_g1_reset,
2589 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2593 static const struct mv88e6xxx_ops mv88e6172_ops = {
2594 /* MV88E6XXX_FAMILY_6352 */
2595 .irl_init_all = mv88e6352_g2_irl_init_all,
2596 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2597 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2599 .phy_read = mv88e6xxx_g2_smi_phy_read,
2600 .phy_write = mv88e6xxx_g2_smi_phy_write,
2601 .port_set_link = mv88e6xxx_port_set_link,
2602 .port_set_duplex = mv88e6xxx_port_set_duplex,
2603 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2604 .port_set_speed = mv88e6352_port_set_speed,
2605 .port_tag_remap = mv88e6095_port_tag_remap,
2606 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2607 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2608 .port_set_ether_type = mv88e6351_port_set_ether_type,
2609 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2610 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2611 .port_pause_limit = mv88e6097_port_pause_limit,
2612 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2613 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2614 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2615 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2616 .stats_get_strings = mv88e6095_stats_get_strings,
2617 .stats_get_stats = mv88e6095_stats_get_stats,
2618 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2619 .set_egress_port = mv88e6095_g1_set_egress_port,
2620 .watchdog_ops = &mv88e6097_watchdog_ops,
2621 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2622 .pot_clear = mv88e6xxx_g2_pot_clear,
2623 .reset = mv88e6352_g1_reset,
2624 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2626 .serdes_power = mv88e6352_serdes_power,
2629 static const struct mv88e6xxx_ops mv88e6175_ops = {
2630 /* MV88E6XXX_FAMILY_6351 */
2631 .irl_init_all = mv88e6352_g2_irl_init_all,
2632 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2633 .phy_read = mv88e6xxx_g2_smi_phy_read,
2634 .phy_write = mv88e6xxx_g2_smi_phy_write,
2635 .port_set_link = mv88e6xxx_port_set_link,
2636 .port_set_duplex = mv88e6xxx_port_set_duplex,
2637 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2638 .port_set_speed = mv88e6185_port_set_speed,
2639 .port_tag_remap = mv88e6095_port_tag_remap,
2640 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2641 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2642 .port_set_ether_type = mv88e6351_port_set_ether_type,
2643 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2644 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2645 .port_pause_limit = mv88e6097_port_pause_limit,
2646 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2647 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2648 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2649 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2650 .stats_get_strings = mv88e6095_stats_get_strings,
2651 .stats_get_stats = mv88e6095_stats_get_stats,
2652 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2653 .set_egress_port = mv88e6095_g1_set_egress_port,
2654 .watchdog_ops = &mv88e6097_watchdog_ops,
2655 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2656 .pot_clear = mv88e6xxx_g2_pot_clear,
2657 .reset = mv88e6352_g1_reset,
2658 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2662 static const struct mv88e6xxx_ops mv88e6176_ops = {
2663 /* MV88E6XXX_FAMILY_6352 */
2664 .irl_init_all = mv88e6352_g2_irl_init_all,
2665 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2666 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2667 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2668 .phy_read = mv88e6xxx_g2_smi_phy_read,
2669 .phy_write = mv88e6xxx_g2_smi_phy_write,
2670 .port_set_link = mv88e6xxx_port_set_link,
2671 .port_set_duplex = mv88e6xxx_port_set_duplex,
2672 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2673 .port_set_speed = mv88e6352_port_set_speed,
2674 .port_tag_remap = mv88e6095_port_tag_remap,
2675 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2676 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2677 .port_set_ether_type = mv88e6351_port_set_ether_type,
2678 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2679 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2680 .port_pause_limit = mv88e6097_port_pause_limit,
2681 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2682 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2683 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2684 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2685 .stats_get_strings = mv88e6095_stats_get_strings,
2686 .stats_get_stats = mv88e6095_stats_get_stats,
2687 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2688 .set_egress_port = mv88e6095_g1_set_egress_port,
2689 .watchdog_ops = &mv88e6097_watchdog_ops,
2690 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2691 .pot_clear = mv88e6xxx_g2_pot_clear,
2692 .reset = mv88e6352_g1_reset,
2693 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2694 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2695 .serdes_power = mv88e6352_serdes_power,
2698 static const struct mv88e6xxx_ops mv88e6185_ops = {
2699 /* MV88E6XXX_FAMILY_6185 */
2700 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2701 .phy_read = mv88e6185_phy_ppu_read,
2702 .phy_write = mv88e6185_phy_ppu_write,
2703 .port_set_link = mv88e6xxx_port_set_link,
2704 .port_set_duplex = mv88e6xxx_port_set_duplex,
2705 .port_set_speed = mv88e6185_port_set_speed,
2706 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2707 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2708 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2709 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2710 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2711 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2712 .stats_get_strings = mv88e6095_stats_get_strings,
2713 .stats_get_stats = mv88e6095_stats_get_stats,
2714 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2715 .set_egress_port = mv88e6095_g1_set_egress_port,
2716 .watchdog_ops = &mv88e6097_watchdog_ops,
2717 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2718 .ppu_enable = mv88e6185_g1_ppu_enable,
2719 .ppu_disable = mv88e6185_g1_ppu_disable,
2720 .reset = mv88e6185_g1_reset,
2721 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2722 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2725 static const struct mv88e6xxx_ops mv88e6190_ops = {
2726 /* MV88E6XXX_FAMILY_6390 */
2727 .irl_init_all = mv88e6390_g2_irl_init_all,
2728 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2729 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2730 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2731 .phy_read = mv88e6xxx_g2_smi_phy_read,
2732 .phy_write = mv88e6xxx_g2_smi_phy_write,
2733 .port_set_link = mv88e6xxx_port_set_link,
2734 .port_set_duplex = mv88e6xxx_port_set_duplex,
2735 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2736 .port_set_speed = mv88e6390_port_set_speed,
2737 .port_tag_remap = mv88e6390_port_tag_remap,
2738 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2739 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2740 .port_set_ether_type = mv88e6351_port_set_ether_type,
2741 .port_pause_limit = mv88e6390_port_pause_limit,
2742 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2743 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2744 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2745 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2746 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2747 .stats_get_strings = mv88e6320_stats_get_strings,
2748 .stats_get_stats = mv88e6390_stats_get_stats,
2749 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2750 .set_egress_port = mv88e6390_g1_set_egress_port,
2751 .watchdog_ops = &mv88e6390_watchdog_ops,
2752 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2753 .pot_clear = mv88e6xxx_g2_pot_clear,
2754 .reset = mv88e6352_g1_reset,
2755 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2756 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2757 .serdes_power = mv88e6390_serdes_power,
2760 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2761 /* MV88E6XXX_FAMILY_6390 */
2762 .irl_init_all = mv88e6390_g2_irl_init_all,
2763 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2764 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2765 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2766 .phy_read = mv88e6xxx_g2_smi_phy_read,
2767 .phy_write = mv88e6xxx_g2_smi_phy_write,
2768 .port_set_link = mv88e6xxx_port_set_link,
2769 .port_set_duplex = mv88e6xxx_port_set_duplex,
2770 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2771 .port_set_speed = mv88e6390x_port_set_speed,
2772 .port_tag_remap = mv88e6390_port_tag_remap,
2773 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2774 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2775 .port_set_ether_type = mv88e6351_port_set_ether_type,
2776 .port_pause_limit = mv88e6390_port_pause_limit,
2777 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2778 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2779 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2780 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2781 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2782 .stats_get_strings = mv88e6320_stats_get_strings,
2783 .stats_get_stats = mv88e6390_stats_get_stats,
2784 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2785 .set_egress_port = mv88e6390_g1_set_egress_port,
2786 .watchdog_ops = &mv88e6390_watchdog_ops,
2787 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2788 .pot_clear = mv88e6xxx_g2_pot_clear,
2789 .reset = mv88e6352_g1_reset,
2790 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2791 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2792 .serdes_power = mv88e6390_serdes_power,
2795 static const struct mv88e6xxx_ops mv88e6191_ops = {
2796 /* MV88E6XXX_FAMILY_6390 */
2797 .irl_init_all = mv88e6390_g2_irl_init_all,
2798 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2799 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2800 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2801 .phy_read = mv88e6xxx_g2_smi_phy_read,
2802 .phy_write = mv88e6xxx_g2_smi_phy_write,
2803 .port_set_link = mv88e6xxx_port_set_link,
2804 .port_set_duplex = mv88e6xxx_port_set_duplex,
2805 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2806 .port_set_speed = mv88e6390_port_set_speed,
2807 .port_tag_remap = mv88e6390_port_tag_remap,
2808 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2809 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2810 .port_set_ether_type = mv88e6351_port_set_ether_type,
2811 .port_pause_limit = mv88e6390_port_pause_limit,
2812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2814 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2815 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2816 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2817 .stats_get_strings = mv88e6320_stats_get_strings,
2818 .stats_get_stats = mv88e6390_stats_get_stats,
2819 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2820 .set_egress_port = mv88e6390_g1_set_egress_port,
2821 .watchdog_ops = &mv88e6390_watchdog_ops,
2822 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2823 .pot_clear = mv88e6xxx_g2_pot_clear,
2824 .reset = mv88e6352_g1_reset,
2825 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2827 .serdes_power = mv88e6390_serdes_power,
2830 static const struct mv88e6xxx_ops mv88e6240_ops = {
2831 /* MV88E6XXX_FAMILY_6352 */
2832 .irl_init_all = mv88e6352_g2_irl_init_all,
2833 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2834 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2835 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2836 .phy_read = mv88e6xxx_g2_smi_phy_read,
2837 .phy_write = mv88e6xxx_g2_smi_phy_write,
2838 .port_set_link = mv88e6xxx_port_set_link,
2839 .port_set_duplex = mv88e6xxx_port_set_duplex,
2840 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2841 .port_set_speed = mv88e6352_port_set_speed,
2842 .port_tag_remap = mv88e6095_port_tag_remap,
2843 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2844 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2845 .port_set_ether_type = mv88e6351_port_set_ether_type,
2846 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2847 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2848 .port_pause_limit = mv88e6097_port_pause_limit,
2849 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2850 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2851 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2852 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2853 .stats_get_strings = mv88e6095_stats_get_strings,
2854 .stats_get_stats = mv88e6095_stats_get_stats,
2855 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2856 .set_egress_port = mv88e6095_g1_set_egress_port,
2857 .watchdog_ops = &mv88e6097_watchdog_ops,
2858 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2859 .pot_clear = mv88e6xxx_g2_pot_clear,
2860 .reset = mv88e6352_g1_reset,
2861 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2862 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2863 .serdes_power = mv88e6352_serdes_power,
2866 static const struct mv88e6xxx_ops mv88e6290_ops = {
2867 /* MV88E6XXX_FAMILY_6390 */
2868 .irl_init_all = mv88e6390_g2_irl_init_all,
2869 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2870 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2871 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2872 .phy_read = mv88e6xxx_g2_smi_phy_read,
2873 .phy_write = mv88e6xxx_g2_smi_phy_write,
2874 .port_set_link = mv88e6xxx_port_set_link,
2875 .port_set_duplex = mv88e6xxx_port_set_duplex,
2876 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2877 .port_set_speed = mv88e6390_port_set_speed,
2878 .port_tag_remap = mv88e6390_port_tag_remap,
2879 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2880 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2881 .port_set_ether_type = mv88e6351_port_set_ether_type,
2882 .port_pause_limit = mv88e6390_port_pause_limit,
2883 .port_set_cmode = mv88e6390x_port_set_cmode,
2884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2886 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2887 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2888 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2889 .stats_get_strings = mv88e6320_stats_get_strings,
2890 .stats_get_stats = mv88e6390_stats_get_stats,
2891 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2892 .set_egress_port = mv88e6390_g1_set_egress_port,
2893 .watchdog_ops = &mv88e6390_watchdog_ops,
2894 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2895 .pot_clear = mv88e6xxx_g2_pot_clear,
2896 .reset = mv88e6352_g1_reset,
2897 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2898 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2899 .serdes_power = mv88e6390_serdes_power,
2902 static const struct mv88e6xxx_ops mv88e6320_ops = {
2903 /* MV88E6XXX_FAMILY_6320 */
2904 .irl_init_all = mv88e6352_g2_irl_init_all,
2905 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2906 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2907 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2908 .phy_read = mv88e6xxx_g2_smi_phy_read,
2909 .phy_write = mv88e6xxx_g2_smi_phy_write,
2910 .port_set_link = mv88e6xxx_port_set_link,
2911 .port_set_duplex = mv88e6xxx_port_set_duplex,
2912 .port_set_speed = mv88e6185_port_set_speed,
2913 .port_tag_remap = mv88e6095_port_tag_remap,
2914 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2915 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2916 .port_set_ether_type = mv88e6351_port_set_ether_type,
2917 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2918 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2919 .port_pause_limit = mv88e6097_port_pause_limit,
2920 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2921 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2922 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2923 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2924 .stats_get_strings = mv88e6320_stats_get_strings,
2925 .stats_get_stats = mv88e6320_stats_get_stats,
2926 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2927 .set_egress_port = mv88e6095_g1_set_egress_port,
2928 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2929 .pot_clear = mv88e6xxx_g2_pot_clear,
2930 .reset = mv88e6352_g1_reset,
2931 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2932 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2935 static const struct mv88e6xxx_ops mv88e6321_ops = {
2936 /* MV88E6XXX_FAMILY_6320 */
2937 .irl_init_all = mv88e6352_g2_irl_init_all,
2938 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2939 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2940 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2941 .phy_read = mv88e6xxx_g2_smi_phy_read,
2942 .phy_write = mv88e6xxx_g2_smi_phy_write,
2943 .port_set_link = mv88e6xxx_port_set_link,
2944 .port_set_duplex = mv88e6xxx_port_set_duplex,
2945 .port_set_speed = mv88e6185_port_set_speed,
2946 .port_tag_remap = mv88e6095_port_tag_remap,
2947 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2948 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2949 .port_set_ether_type = mv88e6351_port_set_ether_type,
2950 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2951 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2952 .port_pause_limit = mv88e6097_port_pause_limit,
2953 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2954 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2955 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2956 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2957 .stats_get_strings = mv88e6320_stats_get_strings,
2958 .stats_get_stats = mv88e6320_stats_get_stats,
2959 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2960 .set_egress_port = mv88e6095_g1_set_egress_port,
2961 .reset = mv88e6352_g1_reset,
2962 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2963 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2966 static const struct mv88e6xxx_ops mv88e6341_ops = {
2967 /* MV88E6XXX_FAMILY_6341 */
2968 .irl_init_all = mv88e6352_g2_irl_init_all,
2969 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2970 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2972 .phy_read = mv88e6xxx_g2_smi_phy_read,
2973 .phy_write = mv88e6xxx_g2_smi_phy_write,
2974 .port_set_link = mv88e6xxx_port_set_link,
2975 .port_set_duplex = mv88e6xxx_port_set_duplex,
2976 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2977 .port_set_speed = mv88e6390_port_set_speed,
2978 .port_tag_remap = mv88e6095_port_tag_remap,
2979 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2980 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2981 .port_set_ether_type = mv88e6351_port_set_ether_type,
2982 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2983 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2984 .port_pause_limit = mv88e6097_port_pause_limit,
2985 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2986 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2987 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2988 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2989 .stats_get_strings = mv88e6320_stats_get_strings,
2990 .stats_get_stats = mv88e6390_stats_get_stats,
2991 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2992 .set_egress_port = mv88e6390_g1_set_egress_port,
2993 .watchdog_ops = &mv88e6390_watchdog_ops,
2994 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2995 .pot_clear = mv88e6xxx_g2_pot_clear,
2996 .reset = mv88e6352_g1_reset,
2997 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2998 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3001 static const struct mv88e6xxx_ops mv88e6350_ops = {
3002 /* MV88E6XXX_FAMILY_6351 */
3003 .irl_init_all = mv88e6352_g2_irl_init_all,
3004 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3005 .phy_read = mv88e6xxx_g2_smi_phy_read,
3006 .phy_write = mv88e6xxx_g2_smi_phy_write,
3007 .port_set_link = mv88e6xxx_port_set_link,
3008 .port_set_duplex = mv88e6xxx_port_set_duplex,
3009 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3010 .port_set_speed = mv88e6185_port_set_speed,
3011 .port_tag_remap = mv88e6095_port_tag_remap,
3012 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3013 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3014 .port_set_ether_type = mv88e6351_port_set_ether_type,
3015 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3016 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3017 .port_pause_limit = mv88e6097_port_pause_limit,
3018 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3019 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3020 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3021 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3022 .stats_get_strings = mv88e6095_stats_get_strings,
3023 .stats_get_stats = mv88e6095_stats_get_stats,
3024 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3025 .set_egress_port = mv88e6095_g1_set_egress_port,
3026 .watchdog_ops = &mv88e6097_watchdog_ops,
3027 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3028 .pot_clear = mv88e6xxx_g2_pot_clear,
3029 .reset = mv88e6352_g1_reset,
3030 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3031 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3034 static const struct mv88e6xxx_ops mv88e6351_ops = {
3035 /* MV88E6XXX_FAMILY_6351 */
3036 .irl_init_all = mv88e6352_g2_irl_init_all,
3037 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3038 .phy_read = mv88e6xxx_g2_smi_phy_read,
3039 .phy_write = mv88e6xxx_g2_smi_phy_write,
3040 .port_set_link = mv88e6xxx_port_set_link,
3041 .port_set_duplex = mv88e6xxx_port_set_duplex,
3042 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3043 .port_set_speed = mv88e6185_port_set_speed,
3044 .port_tag_remap = mv88e6095_port_tag_remap,
3045 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3046 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3047 .port_set_ether_type = mv88e6351_port_set_ether_type,
3048 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3049 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3050 .port_pause_limit = mv88e6097_port_pause_limit,
3051 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3052 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3053 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3054 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3055 .stats_get_strings = mv88e6095_stats_get_strings,
3056 .stats_get_stats = mv88e6095_stats_get_stats,
3057 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3058 .set_egress_port = mv88e6095_g1_set_egress_port,
3059 .watchdog_ops = &mv88e6097_watchdog_ops,
3060 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3061 .pot_clear = mv88e6xxx_g2_pot_clear,
3062 .reset = mv88e6352_g1_reset,
3063 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3064 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3067 static const struct mv88e6xxx_ops mv88e6352_ops = {
3068 /* MV88E6XXX_FAMILY_6352 */
3069 .irl_init_all = mv88e6352_g2_irl_init_all,
3070 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3071 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3072 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3073 .phy_read = mv88e6xxx_g2_smi_phy_read,
3074 .phy_write = mv88e6xxx_g2_smi_phy_write,
3075 .port_set_link = mv88e6xxx_port_set_link,
3076 .port_set_duplex = mv88e6xxx_port_set_duplex,
3077 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3078 .port_set_speed = mv88e6352_port_set_speed,
3079 .port_tag_remap = mv88e6095_port_tag_remap,
3080 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3081 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3082 .port_set_ether_type = mv88e6351_port_set_ether_type,
3083 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3084 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3085 .port_pause_limit = mv88e6097_port_pause_limit,
3086 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3087 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3088 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3089 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3090 .stats_get_strings = mv88e6095_stats_get_strings,
3091 .stats_get_stats = mv88e6095_stats_get_stats,
3092 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3093 .set_egress_port = mv88e6095_g1_set_egress_port,
3094 .watchdog_ops = &mv88e6097_watchdog_ops,
3095 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3096 .pot_clear = mv88e6xxx_g2_pot_clear,
3097 .reset = mv88e6352_g1_reset,
3098 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3099 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3100 .serdes_power = mv88e6352_serdes_power,
3103 static const struct mv88e6xxx_ops mv88e6390_ops = {
3104 /* MV88E6XXX_FAMILY_6390 */
3105 .irl_init_all = mv88e6390_g2_irl_init_all,
3106 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3107 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3108 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3109 .phy_read = mv88e6xxx_g2_smi_phy_read,
3110 .phy_write = mv88e6xxx_g2_smi_phy_write,
3111 .port_set_link = mv88e6xxx_port_set_link,
3112 .port_set_duplex = mv88e6xxx_port_set_duplex,
3113 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3114 .port_set_speed = mv88e6390_port_set_speed,
3115 .port_tag_remap = mv88e6390_port_tag_remap,
3116 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3117 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3118 .port_set_ether_type = mv88e6351_port_set_ether_type,
3119 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3120 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3121 .port_pause_limit = mv88e6390_port_pause_limit,
3122 .port_set_cmode = mv88e6390x_port_set_cmode,
3123 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3124 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3125 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3126 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3127 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3128 .stats_get_strings = mv88e6320_stats_get_strings,
3129 .stats_get_stats = mv88e6390_stats_get_stats,
3130 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3131 .set_egress_port = mv88e6390_g1_set_egress_port,
3132 .watchdog_ops = &mv88e6390_watchdog_ops,
3133 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3134 .pot_clear = mv88e6xxx_g2_pot_clear,
3135 .reset = mv88e6352_g1_reset,
3136 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3137 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3138 .serdes_power = mv88e6390_serdes_power,
3141 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3142 /* MV88E6XXX_FAMILY_6390 */
3143 .irl_init_all = mv88e6390_g2_irl_init_all,
3144 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3145 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3146 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3147 .phy_read = mv88e6xxx_g2_smi_phy_read,
3148 .phy_write = mv88e6xxx_g2_smi_phy_write,
3149 .port_set_link = mv88e6xxx_port_set_link,
3150 .port_set_duplex = mv88e6xxx_port_set_duplex,
3151 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3152 .port_set_speed = mv88e6390x_port_set_speed,
3153 .port_tag_remap = mv88e6390_port_tag_remap,
3154 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3155 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3156 .port_set_ether_type = mv88e6351_port_set_ether_type,
3157 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3158 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3159 .port_pause_limit = mv88e6390_port_pause_limit,
3160 .port_set_cmode = mv88e6390x_port_set_cmode,
3161 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3162 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3163 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3164 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3165 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3166 .stats_get_strings = mv88e6320_stats_get_strings,
3167 .stats_get_stats = mv88e6390_stats_get_stats,
3168 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3169 .set_egress_port = mv88e6390_g1_set_egress_port,
3170 .watchdog_ops = &mv88e6390_watchdog_ops,
3171 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3172 .pot_clear = mv88e6xxx_g2_pot_clear,
3173 .reset = mv88e6352_g1_reset,
3174 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3175 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3176 .serdes_power = mv88e6390_serdes_power,
3179 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3181 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3182 .family = MV88E6XXX_FAMILY_6097,
3183 .name = "Marvell 88E6085",
3184 .num_databases = 4096,
3187 .port_base_addr = 0x10,
3188 .global1_addr = 0x1b,
3189 .global2_addr = 0x1c,
3190 .age_time_coeff = 15000,
3193 .atu_move_port_mask = 0xf,
3196 .tag_protocol = DSA_TAG_PROTO_DSA,
3197 .ops = &mv88e6085_ops,
3201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3202 .family = MV88E6XXX_FAMILY_6095,
3203 .name = "Marvell 88E6095/88E6095F",
3204 .num_databases = 256,
3207 .port_base_addr = 0x10,
3208 .global1_addr = 0x1b,
3209 .global2_addr = 0x1c,
3210 .age_time_coeff = 15000,
3212 .atu_move_port_mask = 0xf,
3214 .tag_protocol = DSA_TAG_PROTO_DSA,
3215 .ops = &mv88e6095_ops,
3219 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3220 .family = MV88E6XXX_FAMILY_6097,
3221 .name = "Marvell 88E6097/88E6097F",
3222 .num_databases = 4096,
3225 .port_base_addr = 0x10,
3226 .global1_addr = 0x1b,
3227 .global2_addr = 0x1c,
3228 .age_time_coeff = 15000,
3231 .atu_move_port_mask = 0xf,
3234 .tag_protocol = DSA_TAG_PROTO_EDSA,
3235 .ops = &mv88e6097_ops,
3239 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3240 .family = MV88E6XXX_FAMILY_6165,
3241 .name = "Marvell 88E6123",
3242 .num_databases = 4096,
3245 .port_base_addr = 0x10,
3246 .global1_addr = 0x1b,
3247 .global2_addr = 0x1c,
3248 .age_time_coeff = 15000,
3251 .atu_move_port_mask = 0xf,
3254 .tag_protocol = DSA_TAG_PROTO_EDSA,
3255 .ops = &mv88e6123_ops,
3259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3260 .family = MV88E6XXX_FAMILY_6185,
3261 .name = "Marvell 88E6131",
3262 .num_databases = 256,
3265 .port_base_addr = 0x10,
3266 .global1_addr = 0x1b,
3267 .global2_addr = 0x1c,
3268 .age_time_coeff = 15000,
3270 .atu_move_port_mask = 0xf,
3272 .tag_protocol = DSA_TAG_PROTO_DSA,
3273 .ops = &mv88e6131_ops,
3277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3278 .family = MV88E6XXX_FAMILY_6341,
3279 .name = "Marvell 88E6341",
3280 .num_databases = 4096,
3283 .port_base_addr = 0x10,
3284 .global1_addr = 0x1b,
3285 .global2_addr = 0x1c,
3286 .age_time_coeff = 3750,
3287 .atu_move_port_mask = 0x1f,
3291 .tag_protocol = DSA_TAG_PROTO_EDSA,
3292 .ops = &mv88e6141_ops,
3296 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3297 .family = MV88E6XXX_FAMILY_6165,
3298 .name = "Marvell 88E6161",
3299 .num_databases = 4096,
3302 .port_base_addr = 0x10,
3303 .global1_addr = 0x1b,
3304 .global2_addr = 0x1c,
3305 .age_time_coeff = 15000,
3308 .atu_move_port_mask = 0xf,
3311 .tag_protocol = DSA_TAG_PROTO_EDSA,
3312 .ops = &mv88e6161_ops,
3316 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3317 .family = MV88E6XXX_FAMILY_6165,
3318 .name = "Marvell 88E6165",
3319 .num_databases = 4096,
3322 .port_base_addr = 0x10,
3323 .global1_addr = 0x1b,
3324 .global2_addr = 0x1c,
3325 .age_time_coeff = 15000,
3328 .atu_move_port_mask = 0xf,
3331 .tag_protocol = DSA_TAG_PROTO_DSA,
3332 .ops = &mv88e6165_ops,
3336 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3337 .family = MV88E6XXX_FAMILY_6351,
3338 .name = "Marvell 88E6171",
3339 .num_databases = 4096,
3342 .port_base_addr = 0x10,
3343 .global1_addr = 0x1b,
3344 .global2_addr = 0x1c,
3345 .age_time_coeff = 15000,
3348 .atu_move_port_mask = 0xf,
3351 .tag_protocol = DSA_TAG_PROTO_EDSA,
3352 .ops = &mv88e6171_ops,
3356 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3357 .family = MV88E6XXX_FAMILY_6352,
3358 .name = "Marvell 88E6172",
3359 .num_databases = 4096,
3362 .port_base_addr = 0x10,
3363 .global1_addr = 0x1b,
3364 .global2_addr = 0x1c,
3365 .age_time_coeff = 15000,
3368 .atu_move_port_mask = 0xf,
3371 .tag_protocol = DSA_TAG_PROTO_EDSA,
3372 .ops = &mv88e6172_ops,
3376 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3377 .family = MV88E6XXX_FAMILY_6351,
3378 .name = "Marvell 88E6175",
3379 .num_databases = 4096,
3382 .port_base_addr = 0x10,
3383 .global1_addr = 0x1b,
3384 .global2_addr = 0x1c,
3385 .age_time_coeff = 15000,
3388 .atu_move_port_mask = 0xf,
3391 .tag_protocol = DSA_TAG_PROTO_EDSA,
3392 .ops = &mv88e6175_ops,
3396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3397 .family = MV88E6XXX_FAMILY_6352,
3398 .name = "Marvell 88E6176",
3399 .num_databases = 4096,
3402 .port_base_addr = 0x10,
3403 .global1_addr = 0x1b,
3404 .global2_addr = 0x1c,
3405 .age_time_coeff = 15000,
3408 .atu_move_port_mask = 0xf,
3411 .tag_protocol = DSA_TAG_PROTO_EDSA,
3412 .ops = &mv88e6176_ops,
3416 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3417 .family = MV88E6XXX_FAMILY_6185,
3418 .name = "Marvell 88E6185",
3419 .num_databases = 256,
3422 .port_base_addr = 0x10,
3423 .global1_addr = 0x1b,
3424 .global2_addr = 0x1c,
3425 .age_time_coeff = 15000,
3427 .atu_move_port_mask = 0xf,
3429 .tag_protocol = DSA_TAG_PROTO_EDSA,
3430 .ops = &mv88e6185_ops,
3434 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3435 .family = MV88E6XXX_FAMILY_6390,
3436 .name = "Marvell 88E6190",
3437 .num_databases = 4096,
3438 .num_ports = 11, /* 10 + Z80 */
3440 .port_base_addr = 0x0,
3441 .global1_addr = 0x1b,
3442 .global2_addr = 0x1c,
3443 .tag_protocol = DSA_TAG_PROTO_DSA,
3444 .age_time_coeff = 3750,
3449 .atu_move_port_mask = 0x1f,
3450 .ops = &mv88e6190_ops,
3454 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3455 .family = MV88E6XXX_FAMILY_6390,
3456 .name = "Marvell 88E6190X",
3457 .num_databases = 4096,
3458 .num_ports = 11, /* 10 + Z80 */
3460 .port_base_addr = 0x0,
3461 .global1_addr = 0x1b,
3462 .global2_addr = 0x1c,
3463 .age_time_coeff = 3750,
3466 .atu_move_port_mask = 0x1f,
3469 .tag_protocol = DSA_TAG_PROTO_DSA,
3470 .ops = &mv88e6190x_ops,
3474 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3475 .family = MV88E6XXX_FAMILY_6390,
3476 .name = "Marvell 88E6191",
3477 .num_databases = 4096,
3478 .num_ports = 11, /* 10 + Z80 */
3480 .port_base_addr = 0x0,
3481 .global1_addr = 0x1b,
3482 .global2_addr = 0x1c,
3483 .age_time_coeff = 3750,
3486 .atu_move_port_mask = 0x1f,
3489 .tag_protocol = DSA_TAG_PROTO_DSA,
3490 .ops = &mv88e6191_ops,
3494 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3495 .family = MV88E6XXX_FAMILY_6352,
3496 .name = "Marvell 88E6240",
3497 .num_databases = 4096,
3500 .port_base_addr = 0x10,
3501 .global1_addr = 0x1b,
3502 .global2_addr = 0x1c,
3503 .age_time_coeff = 15000,
3506 .atu_move_port_mask = 0xf,
3509 .tag_protocol = DSA_TAG_PROTO_EDSA,
3510 .ops = &mv88e6240_ops,
3514 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3515 .family = MV88E6XXX_FAMILY_6390,
3516 .name = "Marvell 88E6290",
3517 .num_databases = 4096,
3518 .num_ports = 11, /* 10 + Z80 */
3520 .port_base_addr = 0x0,
3521 .global1_addr = 0x1b,
3522 .global2_addr = 0x1c,
3523 .age_time_coeff = 3750,
3526 .atu_move_port_mask = 0x1f,
3529 .tag_protocol = DSA_TAG_PROTO_DSA,
3530 .ops = &mv88e6290_ops,
3534 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3535 .family = MV88E6XXX_FAMILY_6320,
3536 .name = "Marvell 88E6320",
3537 .num_databases = 4096,
3540 .port_base_addr = 0x10,
3541 .global1_addr = 0x1b,
3542 .global2_addr = 0x1c,
3543 .age_time_coeff = 15000,
3545 .atu_move_port_mask = 0xf,
3548 .tag_protocol = DSA_TAG_PROTO_EDSA,
3549 .ops = &mv88e6320_ops,
3553 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3554 .family = MV88E6XXX_FAMILY_6320,
3555 .name = "Marvell 88E6321",
3556 .num_databases = 4096,
3559 .port_base_addr = 0x10,
3560 .global1_addr = 0x1b,
3561 .global2_addr = 0x1c,
3562 .age_time_coeff = 15000,
3564 .atu_move_port_mask = 0xf,
3566 .tag_protocol = DSA_TAG_PROTO_EDSA,
3567 .ops = &mv88e6321_ops,
3571 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3572 .family = MV88E6XXX_FAMILY_6341,
3573 .name = "Marvell 88E6341",
3574 .num_databases = 4096,
3577 .port_base_addr = 0x10,
3578 .global1_addr = 0x1b,
3579 .global2_addr = 0x1c,
3580 .age_time_coeff = 3750,
3581 .atu_move_port_mask = 0x1f,
3585 .tag_protocol = DSA_TAG_PROTO_EDSA,
3586 .ops = &mv88e6341_ops,
3590 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3591 .family = MV88E6XXX_FAMILY_6351,
3592 .name = "Marvell 88E6350",
3593 .num_databases = 4096,
3596 .port_base_addr = 0x10,
3597 .global1_addr = 0x1b,
3598 .global2_addr = 0x1c,
3599 .age_time_coeff = 15000,
3602 .atu_move_port_mask = 0xf,
3605 .tag_protocol = DSA_TAG_PROTO_EDSA,
3606 .ops = &mv88e6350_ops,
3610 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3611 .family = MV88E6XXX_FAMILY_6351,
3612 .name = "Marvell 88E6351",
3613 .num_databases = 4096,
3616 .port_base_addr = 0x10,
3617 .global1_addr = 0x1b,
3618 .global2_addr = 0x1c,
3619 .age_time_coeff = 15000,
3622 .atu_move_port_mask = 0xf,
3625 .tag_protocol = DSA_TAG_PROTO_EDSA,
3626 .ops = &mv88e6351_ops,
3630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3631 .family = MV88E6XXX_FAMILY_6352,
3632 .name = "Marvell 88E6352",
3633 .num_databases = 4096,
3636 .port_base_addr = 0x10,
3637 .global1_addr = 0x1b,
3638 .global2_addr = 0x1c,
3639 .age_time_coeff = 15000,
3642 .atu_move_port_mask = 0xf,
3645 .tag_protocol = DSA_TAG_PROTO_EDSA,
3646 .ops = &mv88e6352_ops,
3649 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3650 .family = MV88E6XXX_FAMILY_6390,
3651 .name = "Marvell 88E6390",
3652 .num_databases = 4096,
3653 .num_ports = 11, /* 10 + Z80 */
3655 .port_base_addr = 0x0,
3656 .global1_addr = 0x1b,
3657 .global2_addr = 0x1c,
3658 .age_time_coeff = 3750,
3661 .atu_move_port_mask = 0x1f,
3664 .tag_protocol = DSA_TAG_PROTO_DSA,
3665 .ops = &mv88e6390_ops,
3668 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3669 .family = MV88E6XXX_FAMILY_6390,
3670 .name = "Marvell 88E6390X",
3671 .num_databases = 4096,
3672 .num_ports = 11, /* 10 + Z80 */
3674 .port_base_addr = 0x0,
3675 .global1_addr = 0x1b,
3676 .global2_addr = 0x1c,
3677 .age_time_coeff = 3750,
3680 .atu_move_port_mask = 0x1f,
3683 .tag_protocol = DSA_TAG_PROTO_DSA,
3684 .ops = &mv88e6390x_ops,
3688 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3692 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3693 if (mv88e6xxx_table[i].prod_num == prod_num)
3694 return &mv88e6xxx_table[i];
3699 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3701 const struct mv88e6xxx_info *info;
3702 unsigned int prod_num, rev;
3706 mutex_lock(&chip->reg_lock);
3707 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3708 mutex_unlock(&chip->reg_lock);
3712 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3713 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3715 info = mv88e6xxx_lookup_info(prod_num);
3719 /* Update the compatible info with the probed one */
3722 err = mv88e6xxx_g2_require(chip);
3726 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3727 chip->info->prod_num, chip->info->name, rev);
3732 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3734 struct mv88e6xxx_chip *chip;
3736 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3742 mutex_init(&chip->reg_lock);
3743 INIT_LIST_HEAD(&chip->mdios);
3748 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3749 struct mii_bus *bus, int sw_addr)
3752 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3753 else if (chip->info->multi_chip)
3754 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3759 chip->sw_addr = sw_addr;
3764 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3766 struct mv88e6xxx_chip *chip = ds->priv;
3768 return chip->info->tag_protocol;
3771 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3772 struct device *host_dev, int sw_addr,
3775 struct mv88e6xxx_chip *chip;
3776 struct mii_bus *bus;
3779 bus = dsa_host_dev_to_mii_bus(host_dev);
3783 chip = mv88e6xxx_alloc_chip(dsa_dev);
3787 /* Legacy SMI probing will only support chips similar to 88E6085 */
3788 chip->info = &mv88e6xxx_table[MV88E6085];
3790 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3794 err = mv88e6xxx_detect(chip);
3798 mutex_lock(&chip->reg_lock);
3799 err = mv88e6xxx_switch_reset(chip);
3800 mutex_unlock(&chip->reg_lock);
3804 mv88e6xxx_phy_init(chip);
3806 err = mv88e6xxx_mdios_register(chip, NULL);
3812 return chip->info->name;
3814 devm_kfree(dsa_dev, chip);
3819 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3820 const struct switchdev_obj_port_mdb *mdb,
3821 struct switchdev_trans *trans)
3823 /* We don't need any dynamic resource from the kernel (yet),
3824 * so skip the prepare phase.
3830 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3831 const struct switchdev_obj_port_mdb *mdb,
3832 struct switchdev_trans *trans)
3834 struct mv88e6xxx_chip *chip = ds->priv;
3836 mutex_lock(&chip->reg_lock);
3837 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3838 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3839 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3841 mutex_unlock(&chip->reg_lock);
3844 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3845 const struct switchdev_obj_port_mdb *mdb)
3847 struct mv88e6xxx_chip *chip = ds->priv;
3850 mutex_lock(&chip->reg_lock);
3851 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3852 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3853 mutex_unlock(&chip->reg_lock);
3858 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3859 struct switchdev_obj_port_mdb *mdb,
3860 switchdev_obj_dump_cb_t *cb)
3862 struct mv88e6xxx_chip *chip = ds->priv;
3865 mutex_lock(&chip->reg_lock);
3866 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3867 mutex_unlock(&chip->reg_lock);
3872 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3873 .probe = mv88e6xxx_drv_probe,
3874 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3875 .setup = mv88e6xxx_setup,
3876 .set_addr = mv88e6xxx_set_addr,
3877 .adjust_link = mv88e6xxx_adjust_link,
3878 .get_strings = mv88e6xxx_get_strings,
3879 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3880 .get_sset_count = mv88e6xxx_get_sset_count,
3881 .port_enable = mv88e6xxx_port_enable,
3882 .port_disable = mv88e6xxx_port_disable,
3883 .get_mac_eee = mv88e6xxx_get_mac_eee,
3884 .set_mac_eee = mv88e6xxx_set_mac_eee,
3885 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3886 .get_eeprom = mv88e6xxx_get_eeprom,
3887 .set_eeprom = mv88e6xxx_set_eeprom,
3888 .get_regs_len = mv88e6xxx_get_regs_len,
3889 .get_regs = mv88e6xxx_get_regs,
3890 .set_ageing_time = mv88e6xxx_set_ageing_time,
3891 .port_bridge_join = mv88e6xxx_port_bridge_join,
3892 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3893 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3894 .port_fast_age = mv88e6xxx_port_fast_age,
3895 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3896 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3897 .port_vlan_add = mv88e6xxx_port_vlan_add,
3898 .port_vlan_del = mv88e6xxx_port_vlan_del,
3899 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3900 .port_fdb_add = mv88e6xxx_port_fdb_add,
3901 .port_fdb_del = mv88e6xxx_port_fdb_del,
3902 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3903 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3904 .port_mdb_add = mv88e6xxx_port_mdb_add,
3905 .port_mdb_del = mv88e6xxx_port_mdb_del,
3906 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3907 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3908 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
3911 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3912 .ops = &mv88e6xxx_switch_ops,
3915 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3917 struct device *dev = chip->dev;
3918 struct dsa_switch *ds;
3920 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3925 ds->ops = &mv88e6xxx_switch_ops;
3926 ds->ageing_time_min = chip->info->age_time_coeff;
3927 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3929 dev_set_drvdata(dev, ds);
3931 return dsa_register_switch(ds);
3934 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3936 dsa_unregister_switch(chip->ds);
3939 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3941 struct device *dev = &mdiodev->dev;
3942 struct device_node *np = dev->of_node;
3943 const struct mv88e6xxx_info *compat_info;
3944 struct mv88e6xxx_chip *chip;
3948 compat_info = of_device_get_match_data(dev);
3952 chip = mv88e6xxx_alloc_chip(dev);
3956 chip->info = compat_info;
3958 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3962 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3963 if (IS_ERR(chip->reset))
3964 return PTR_ERR(chip->reset);
3966 err = mv88e6xxx_detect(chip);
3970 mv88e6xxx_phy_init(chip);
3972 if (chip->info->ops->get_eeprom &&
3973 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3974 chip->eeprom_len = eeprom_len;
3976 mutex_lock(&chip->reg_lock);
3977 err = mv88e6xxx_switch_reset(chip);
3978 mutex_unlock(&chip->reg_lock);
3982 chip->irq = of_irq_get(np, 0);
3983 if (chip->irq == -EPROBE_DEFER) {
3988 if (chip->irq > 0) {
3989 /* Has to be performed before the MDIO bus is created,
3990 * because the PHYs will link there interrupts to these
3991 * interrupt controllers
3993 mutex_lock(&chip->reg_lock);
3994 err = mv88e6xxx_g1_irq_setup(chip);
3995 mutex_unlock(&chip->reg_lock);
4000 if (chip->info->g2_irqs > 0) {
4001 err = mv88e6xxx_g2_irq_setup(chip);
4007 err = mv88e6xxx_mdios_register(chip, np);
4011 err = mv88e6xxx_register_switch(chip);
4018 mv88e6xxx_mdios_unregister(chip);
4020 if (chip->info->g2_irqs > 0 && chip->irq > 0)
4021 mv88e6xxx_g2_irq_free(chip);
4023 if (chip->irq > 0) {
4024 mutex_lock(&chip->reg_lock);
4025 mv88e6xxx_g1_irq_free(chip);
4026 mutex_unlock(&chip->reg_lock);
4032 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4034 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4035 struct mv88e6xxx_chip *chip = ds->priv;
4037 mv88e6xxx_phy_destroy(chip);
4038 mv88e6xxx_unregister_switch(chip);
4039 mv88e6xxx_mdios_unregister(chip);
4041 if (chip->irq > 0) {
4042 if (chip->info->g2_irqs > 0)
4043 mv88e6xxx_g2_irq_free(chip);
4044 mv88e6xxx_g1_irq_free(chip);
4048 static const struct of_device_id mv88e6xxx_of_match[] = {
4050 .compatible = "marvell,mv88e6085",
4051 .data = &mv88e6xxx_table[MV88E6085],
4054 .compatible = "marvell,mv88e6190",
4055 .data = &mv88e6xxx_table[MV88E6190],
4060 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4062 static struct mdio_driver mv88e6xxx_driver = {
4063 .probe = mv88e6xxx_probe,
4064 .remove = mv88e6xxx_remove,
4066 .name = "mv88e6085",
4067 .of_match_table = mv88e6xxx_of_match,
4071 static int __init mv88e6xxx_init(void)
4073 register_switch_driver(&mv88e6xxx_switch_drv);
4074 return mdio_driver_register(&mv88e6xxx_driver);
4076 module_init(mv88e6xxx_init);
4078 static void __exit mv88e6xxx_cleanup(void)
4080 mdio_driver_unregister(&mv88e6xxx_driver);
4081 unregister_switch_driver(&mv88e6xxx_switch_drv);
4083 module_exit(mv88e6xxx_cleanup);
4085 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4086 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4087 MODULE_LICENSE("GPL");