drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/dsa/mv88e6xxx.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/mdio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/platform_data/mv88e6xxx.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/phylink.h>
  33 #include <net/dsa.h>
  34
  35 #include "chip.h"
  36 #include "devlink.h"
  37 #include "global1.h"
  38 #include "global2.h"
  39 #include "hwtstamp.h"
  40 #include "phy.h"
  41 #include "port.h"
  42 #include "ptp.h"
  43 #include "serdes.h"
  44 #include "smi.h"
  45
  46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  47 {
  48         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  49                 dev_err(chip->dev, "Switch registers lock not held!\n");
  50                 dump_stack();
  51         }
  52 }
  53
  54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  55 {
  56         int err;
  57
  58         assert_reg_lock(chip);
  59
  60         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  61         if (err)
  62                 return err;
  63
  64         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  65                 addr, reg, *val);
  66
  67         return 0;
  68 }
  69
  70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  71 {
  72         int err;
  73
  74         assert_reg_lock(chip);
  75
  76         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  77         if (err)
  78                 return err;
  79
  80         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  81                 addr, reg, val);
  82
  83         return 0;
  84 }
  85
  86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  87                         u16 mask, u16 val)
  88 {
  89         const unsigned long timeout = jiffies + msecs_to_jiffies(50);
  90         u16 data;
  91         int err;
  92         int i;
  93
  94         /* There's no bus specific operation to wait for a mask. Even
  95          * if the initial poll takes longer than 50ms, always do at
  96          * least one more attempt.
  97          */
  98         for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
  99                 err = mv88e6xxx_read(chip, addr, reg, &data);
 100                 if (err)
 101                         return err;
 102
 103                 if ((data & mask) == val)
 104                         return 0;
 105
 106                 if (i < 2)
 107                         cpu_relax();
 108                 else
 109                         usleep_range(1000, 2000);
 110         }
 111
 112         dev_err(chip->dev, "Timeout while waiting for switch\n");
 113         return -ETIMEDOUT;
 114 }
 115
 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 117                        int bit, int val)
 118 {
 119         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 120                                    val ? BIT(bit) : 0x0000);
 121 }
 122
 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 124 {
 125         struct mv88e6xxx_mdio_bus *mdio_bus;
 126
 127         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 128                                     list);
 129         if (!mdio_bus)
 130                 return NULL;
 131
 132         return mdio_bus->bus;
 133 }
 134
 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 136 {
 137         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 138         unsigned int n = d->hwirq;
 139
 140         chip->g1_irq.masked |= (1 << n);
 141 }
 142
 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 144 {
 145         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 146         unsigned int n = d->hwirq;
 147
 148         chip->g1_irq.masked &= ~(1 << n);
 149 }
 150
 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 152 {
 153         unsigned int nhandled = 0;
 154         unsigned int sub_irq;
 155         unsigned int n;
 156         u16 reg;
 157         u16 ctl1;
 158         int err;
 159
 160         mv88e6xxx_reg_lock(chip);
 161         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 162         mv88e6xxx_reg_unlock(chip);
 163
 164         if (err)
 165                 goto out;
 166
 167         do {
 168                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 169                         if (reg & (1 << n)) {
 170                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 171                                                            n);
 172                                 handle_nested_irq(sub_irq);
 173                                 ++nhandled;
 174                         }
 175                 }
 176
 177                 mv88e6xxx_reg_lock(chip);
 178                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 179                 if (err)
 180                         goto unlock;
 181                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 182 unlock:
 183                 mv88e6xxx_reg_unlock(chip);
 184                 if (err)
 185                         goto out;
 186                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 187         } while (reg & ctl1);
 188
 189 out:
 190         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 191 }
 192
 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 194 {
 195         struct mv88e6xxx_chip *chip = dev_id;
 196
 197         return mv88e6xxx_g1_irq_thread_work(chip);
 198 }
 199
 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 201 {
 202         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 203
 204         mv88e6xxx_reg_lock(chip);
 205 }
 206
 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 208 {
 209         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 210         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 211         u16 reg;
 212         int err;
 213
 214         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 215         if (err)
 216                 goto out;
 217
 218         reg &= ~mask;
 219         reg |= (~chip->g1_irq.masked & mask);
 220
 221         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 222         if (err)
 223                 goto out;
 224
 225 out:
 226         mv88e6xxx_reg_unlock(chip);
 227 }
 228
 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 230         .name                   = "mv88e6xxx-g1",
 231         .irq_mask               = mv88e6xxx_g1_irq_mask,
 232         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 233         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 234         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 235 };
 236
 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 238                                        unsigned int irq,
 239                                        irq_hw_number_t hwirq)
 240 {
 241         struct mv88e6xxx_chip *chip = d->host_data;
 242
 243         irq_set_chip_data(irq, d->host_data);
 244         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 245         irq_set_noprobe(irq);
 246
 247         return 0;
 248 }
 249
 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 251         .map    = mv88e6xxx_g1_irq_domain_map,
 252         .xlate  = irq_domain_xlate_twocell,
 253 };
 254
 255 /* To be called with reg_lock held */
 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 257 {
 258         int irq, virq;
 259         u16 mask;
 260
 261         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 262         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 263         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 264
 265         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 266                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 267                 irq_dispose_mapping(virq);
 268         }
 269
 270         irq_domain_remove(chip->g1_irq.domain);
 271 }
 272
 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 274 {
 275         /*
 276          * free_irq must be called without reg_lock taken because the irq
 277          * handler takes this lock, too.
 278          */
 279         free_irq(chip->irq, chip);
 280
 281         mv88e6xxx_reg_lock(chip);
 282         mv88e6xxx_g1_irq_free_common(chip);
 283         mv88e6xxx_reg_unlock(chip);
 284 }
 285
 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 287 {
 288         int err, irq, virq;
 289         u16 reg, mask;
 290
 291         chip->g1_irq.nirqs = chip->info->g1_irqs;
 292         chip->g1_irq.domain = irq_domain_add_simple(
 293                 NULL, chip->g1_irq.nirqs, 0,
 294                 &mv88e6xxx_g1_irq_domain_ops, chip);
 295         if (!chip->g1_irq.domain)
 296                 return -ENOMEM;
 297
 298         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 299                 irq_create_mapping(chip->g1_irq.domain, irq);
 300
 301         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 302         chip->g1_irq.masked = ~0;
 303
 304         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 305         if (err)
 306                 goto out_mapping;
 307
 308         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 309
 310         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 311         if (err)
 312                 goto out_disable;
 313
 314         /* Reading the interrupt status clears (most of) them */
 315         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 316         if (err)
 317                 goto out_disable;
 318
 319         return 0;
 320
 321 out_disable:
 322         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 323         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 324
 325 out_mapping:
 326         for (irq = 0; irq < 16; irq++) {
 327                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 328                 irq_dispose_mapping(virq);
 329         }
 330
 331         irq_domain_remove(chip->g1_irq.domain);
 332
 333         return err;
 334 }
 335
 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 337 {
 338         static struct lock_class_key lock_key;
 339         static struct lock_class_key request_key;
 340         int err;
 341
 342         err = mv88e6xxx_g1_irq_setup_common(chip);
 343         if (err)
 344                 return err;
 345
 346         /* These lock classes tells lockdep that global 1 irqs are in
 347          * a different category than their parent GPIO, so it won't
 348          * report false recursion.
 349          */
 350         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 351
 352         snprintf(chip->irq_name, sizeof(chip->irq_name),
 353                  "mv88e6xxx-%s", dev_name(chip->dev));
 354
 355         mv88e6xxx_reg_unlock(chip);
 356         err = request_threaded_irq(chip->irq, NULL,
 357                                    mv88e6xxx_g1_irq_thread_fn,
 358                                    IRQF_ONESHOT | IRQF_SHARED,
 359                                    chip->irq_name, chip);
 360         mv88e6xxx_reg_lock(chip);
 361         if (err)
 362                 mv88e6xxx_g1_irq_free_common(chip);
 363
 364         return err;
 365 }
 366
 367 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 368 {
 369         struct mv88e6xxx_chip *chip = container_of(work,
 370                                                    struct mv88e6xxx_chip,
 371                                                    irq_poll_work.work);
 372         mv88e6xxx_g1_irq_thread_work(chip);
 373
 374         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 375                                    msecs_to_jiffies(100));
 376 }
 377
 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 379 {
 380         int err;
 381
 382         err = mv88e6xxx_g1_irq_setup_common(chip);
 383         if (err)
 384                 return err;
 385
 386         kthread_init_delayed_work(&chip->irq_poll_work,
 387                                   mv88e6xxx_irq_poll);
 388
 389         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 390         if (IS_ERR(chip->kworker))
 391                 return PTR_ERR(chip->kworker);
 392
 393         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 394                                    msecs_to_jiffies(100));
 395
 396         return 0;
 397 }
 398
 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 400 {
 401         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 402         kthread_destroy_worker(chip->kworker);
 403
 404         mv88e6xxx_reg_lock(chip);
 405         mv88e6xxx_g1_irq_free_common(chip);
 406         mv88e6xxx_reg_unlock(chip);
 407 }
 408
 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 410                                            int port, phy_interface_t interface)
 411 {
 412         int err;
 413
 414         if (chip->info->ops->port_set_rgmii_delay) {
 415                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 416                                                             interface);
 417                 if (err && err != -EOPNOTSUPP)
 418                         return err;
 419         }
 420
 421         if (chip->info->ops->port_set_cmode) {
 422                 err = chip->info->ops->port_set_cmode(chip, port,
 423                                                       interface);
 424                 if (err && err != -EOPNOTSUPP)
 425                         return err;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 432                                     int link, int speed, int duplex, int pause,
 433                                     phy_interface_t mode)
 434 {
 435         int err;
 436
 437         if (!chip->info->ops->port_set_link)
 438                 return 0;
 439
 440         /* Port's MAC control must not be changed unless the link is down */
 441         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 442         if (err)
 443                 return err;
 444
 445         if (chip->info->ops->port_set_speed_duplex) {
 446                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 447                                                              speed, duplex);
 448                 if (err && err != -EOPNOTSUPP)
 449                         goto restore_link;
 450         }
 451
 452         if (chip->info->ops->port_set_pause) {
 453                 err = chip->info->ops->port_set_pause(chip, port, pause);
 454                 if (err)
 455                         goto restore_link;
 456         }
 457
 458         err = mv88e6xxx_port_config_interface(chip, port, mode);
 459 restore_link:
 460         if (chip->info->ops->port_set_link(chip, port, link))
 461                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 462
 463         return err;
 464 }
 465
 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 467 {
 468         struct mv88e6xxx_chip *chip = ds->priv;
 469
 470         return port < chip->info->num_internal_phys;
 471 }
 472
 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 474 {
 475         u16 reg;
 476         int err;
 477
 478         /* The 88e6250 family does not have the PHY detect bit. Instead,
 479          * report whether the port is internal.
 480          */
 481         if (chip->info->family == MV88E6XXX_FAMILY_6250)
 482                 return port < chip->info->num_internal_phys;
 483
 484         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 485         if (err) {
 486                 dev_err(chip->dev,
 487                         "p%d: %s: failed to read port status\n",
 488                         port, __func__);
 489                 return err;
 490         }
 491
 492         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 493 }
 494
 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 496                                           struct phylink_link_state *state)
 497 {
 498         struct mv88e6xxx_chip *chip = ds->priv;
 499         int lane;
 500         int err;
 501
 502         mv88e6xxx_reg_lock(chip);
 503         lane = mv88e6xxx_serdes_get_lane(chip, port);
 504         if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
 505                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 506                                                             state);
 507         else
 508                 err = -EOPNOTSUPP;
 509         mv88e6xxx_reg_unlock(chip);
 510
 511         return err;
 512 }
 513
 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 515                                        unsigned int mode,
 516                                        phy_interface_t interface,
 517                                        const unsigned long *advertise)
 518 {
 519         const struct mv88e6xxx_ops *ops = chip->info->ops;
 520         int lane;
 521
 522         if (ops->serdes_pcs_config) {
 523                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 524                 if (lane >= 0)
 525                         return ops->serdes_pcs_config(chip, port, lane, mode,
 526                                                       interface, advertise);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 533 {
 534         struct mv88e6xxx_chip *chip = ds->priv;
 535         const struct mv88e6xxx_ops *ops;
 536         int err = 0;
 537         int lane;
 538
 539         ops = chip->info->ops;
 540
 541         if (ops->serdes_pcs_an_restart) {
 542                 mv88e6xxx_reg_lock(chip);
 543                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 544                 if (lane >= 0)
 545                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 546                 mv88e6xxx_reg_unlock(chip);
 547
 548                 if (err)
 549                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 550         }
 551 }
 552
 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 554                                         unsigned int mode,
 555                                         int speed, int duplex)
 556 {
 557         const struct mv88e6xxx_ops *ops = chip->info->ops;
 558         int lane;
 559
 560         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 561                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 562                 if (lane >= 0)
 563                         return ops->serdes_pcs_link_up(chip, port, lane,
 564                                                        speed, duplex);
 565         }
 566
 567         return 0;
 568 }
 569
 570 static const u8 mv88e6185_phy_interface_modes[] = {
 571         [MV88E6185_PORT_STS_CMODE_GMII_FD]       = PHY_INTERFACE_MODE_GMII,
 572         [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
 573         [MV88E6185_PORT_STS_CMODE_MII_100]       = PHY_INTERFACE_MODE_MII,
 574         [MV88E6185_PORT_STS_CMODE_MII_10]        = PHY_INTERFACE_MODE_MII,
 575         [MV88E6185_PORT_STS_CMODE_SERDES]        = PHY_INTERFACE_MODE_1000BASEX,
 576         [MV88E6185_PORT_STS_CMODE_1000BASE_X]    = PHY_INTERFACE_MODE_1000BASEX,
 577         [MV88E6185_PORT_STS_CMODE_PHY]           = PHY_INTERFACE_MODE_SGMII,
 578 };
 579
 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 581                                        struct phylink_config *config)
 582 {
 583         u8 cmode = chip->ports[port].cmode;
 584
 585         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 586
 587         if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
 588                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 589         } else {
 590                 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 591                     mv88e6185_phy_interface_modes[cmode])
 592                         __set_bit(mv88e6185_phy_interface_modes[cmode],
 593                                   config->supported_interfaces);
 594
 595                 config->mac_capabilities |= MAC_1000FD;
 596         }
 597 }
 598
 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 600                                        struct phylink_config *config)
 601 {
 602         u8 cmode = chip->ports[port].cmode;
 603
 604         if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 605             mv88e6185_phy_interface_modes[cmode])
 606                 __set_bit(mv88e6185_phy_interface_modes[cmode],
 607                           config->supported_interfaces);
 608
 609         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 610                                    MAC_1000FD;
 611 }
 612
 613 static const u8 mv88e6xxx_phy_interface_modes[] = {
 614         [MV88E6XXX_PORT_STS_CMODE_MII_PHY]      = PHY_INTERFACE_MODE_MII,
 615         [MV88E6XXX_PORT_STS_CMODE_MII]          = PHY_INTERFACE_MODE_MII,
 616         [MV88E6XXX_PORT_STS_CMODE_GMII]         = PHY_INTERFACE_MODE_GMII,
 617         [MV88E6XXX_PORT_STS_CMODE_RMII_PHY]     = PHY_INTERFACE_MODE_RMII,
 618         [MV88E6XXX_PORT_STS_CMODE_RMII]         = PHY_INTERFACE_MODE_RMII,
 619         [MV88E6XXX_PORT_STS_CMODE_100BASEX]     = PHY_INTERFACE_MODE_100BASEX,
 620         [MV88E6XXX_PORT_STS_CMODE_1000BASEX]    = PHY_INTERFACE_MODE_1000BASEX,
 621         [MV88E6XXX_PORT_STS_CMODE_SGMII]        = PHY_INTERFACE_MODE_SGMII,
 622         /* higher interface modes are not needed here, since ports supporting
 623          * them are writable, and so the supported interfaces are filled in the
 624          * corresponding .phylink_set_interfaces() implementation below
 625          */
 626 };
 627
 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
 629 {
 630         if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
 631             mv88e6xxx_phy_interface_modes[cmode])
 632                 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
 633         else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
 634                 phy_interface_set_rgmii(supported);
 635 }
 636
 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 638                                        struct phylink_config *config)
 639 {
 640         unsigned long *supported = config->supported_interfaces;
 641
 642         /* Translate the default cmode */
 643         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 644
 645         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 646 }
 647
 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
 649 {
 650         u16 reg, val;
 651         int err;
 652
 653         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &reg);
 654         if (err)
 655                 return err;
 656
 657         /* If PHY_DETECT is zero, then we are not in auto-media mode */
 658         if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
 659                 return 0xf;
 660
 661         val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
 662         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
 663         if (err)
 664                 return err;
 665
 666         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
 667         if (err)
 668                 return err;
 669
 670         /* Restore PHY_DETECT value */
 671         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
 672         if (err)
 673                 return err;
 674
 675         return val & MV88E6XXX_PORT_STS_CMODE_MASK;
 676 }
 677
 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 679                                        struct phylink_config *config)
 680 {
 681         unsigned long *supported = config->supported_interfaces;
 682         int err, cmode;
 683
 684         /* Translate the default cmode */
 685         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 686
 687         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 688                                    MAC_1000FD;
 689
 690         /* Port 4 supports automedia if the serdes is associated with it. */
 691         if (port == 4) {
 692                 mv88e6xxx_reg_lock(chip);
 693                 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
 694                 if (err < 0)
 695                         dev_err(chip->dev, "p%d: failed to read scratch\n",
 696                                 port);
 697                 if (err <= 0)
 698                         goto unlock;
 699
 700                 cmode = mv88e6352_get_port4_serdes_cmode(chip);
 701                 if (cmode < 0)
 702                         dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
 703                                 port);
 704                 else
 705                         mv88e6xxx_translate_cmode(cmode, supported);
 706 unlock:
 707                 mv88e6xxx_reg_unlock(chip);
 708         }
 709 }
 710
 711 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 712                                        struct phylink_config *config)
 713 {
 714         unsigned long *supported = config->supported_interfaces;
 715
 716         /* Translate the default cmode */
 717         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 718
 719         /* No ethtool bits for 200Mbps */
 720         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 721                                    MAC_1000FD;
 722
 723         /* The C_Mode field is programmable on port 5 */
 724         if (port == 5) {
 725                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 726                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 727                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 728
 729                 config->mac_capabilities |= MAC_2500FD;
 730         }
 731 }
 732
 733 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 734                                        struct phylink_config *config)
 735 {
 736         unsigned long *supported = config->supported_interfaces;
 737
 738         /* Translate the default cmode */
 739         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 740
 741         /* No ethtool bits for 200Mbps */
 742         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 743                                    MAC_1000FD;
 744
 745         /* The C_Mode field is programmable on ports 9 and 10 */
 746         if (port == 9 || port == 10) {
 747                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 748                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 749                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 750
 751                 config->mac_capabilities |= MAC_2500FD;
 752         }
 753 }
 754
 755 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 756                                         struct phylink_config *config)
 757 {
 758         unsigned long *supported = config->supported_interfaces;
 759
 760         mv88e6390_phylink_get_caps(chip, port, config);
 761
 762         /* For the 6x90X, ports 2-7 can be in automedia mode.
 763          * (Note that 6x90 doesn't support RXAUI nor XAUI).
 764          *
 765          * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
 766          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 767          * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
 768          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 769          *
 770          * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
 771          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 772          * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
 773          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 774          *
 775          * For now, be permissive (as the old code was) and allow 1000BASE-X
 776          * on ports 2..7.
 777          */
 778         if (port >= 2 && port <= 7)
 779                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 780
 781         /* The C_Mode field can also be programmed for 10G speeds */
 782         if (port == 9 || port == 10) {
 783                 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
 784                 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
 785
 786                 config->mac_capabilities |= MAC_10000FD;
 787         }
 788 }
 789
 790 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 791                                         struct phylink_config *config)
 792 {
 793         unsigned long *supported = config->supported_interfaces;
 794         bool is_6191x =
 795                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
 796
 797         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 798
 799         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 800                                    MAC_1000FD;
 801
 802         /* The C_Mode field can be programmed for ports 0, 9 and 10 */
 803         if (port == 0 || port == 9 || port == 10) {
 804                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 805                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 806
 807                 /* 6191X supports >1G modes only on port 10 */
 808                 if (!is_6191x || port == 10) {
 809                         __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 810                         __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
 811                         __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
 812                         /* FIXME: USXGMII is not supported yet */
 813                         /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
 814
 815                         config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
 816                                 MAC_10000FD;
 817                 }
 818         }
 819 }
 820
 821 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
 822                                struct phylink_config *config)
 823 {
 824         struct mv88e6xxx_chip *chip = ds->priv;
 825
 826         chip->info->ops->phylink_get_caps(chip, port, config);
 827
 828         /* Internal ports need GMII for PHYLIB */
 829         if (mv88e6xxx_phy_is_internal(ds, port))
 830                 __set_bit(PHY_INTERFACE_MODE_GMII,
 831                           config->supported_interfaces);
 832 }
 833
 834 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 835                                  unsigned int mode,
 836                                  const struct phylink_link_state *state)
 837 {
 838         struct mv88e6xxx_chip *chip = ds->priv;
 839         struct mv88e6xxx_port *p;
 840         int err = 0;
 841
 842         p = &chip->ports[port];
 843
 844         mv88e6xxx_reg_lock(chip);
 845
 846         if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
 847                 /* In inband mode, the link may come up at any time while the
 848                  * link is not forced down. Force the link down while we
 849                  * reconfigure the interface mode.
 850                  */
 851                 if (mode == MLO_AN_INBAND &&
 852                     p->interface != state->interface &&
 853                     chip->info->ops->port_set_link)
 854                         chip->info->ops->port_set_link(chip, port,
 855                                                        LINK_FORCED_DOWN);
 856
 857                 err = mv88e6xxx_port_config_interface(chip, port,
 858                                                       state->interface);
 859                 if (err && err != -EOPNOTSUPP)
 860                         goto err_unlock;
 861
 862                 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
 863                                                   state->interface,
 864                                                   state->advertising);
 865                 /* FIXME: we should restart negotiation if something changed -
 866                  * which is something we get if we convert to using phylinks
 867                  * PCS operations.
 868                  */
 869                 if (err > 0)
 870                         err = 0;
 871         }
 872
 873         /* Undo the forced down state above after completing configuration
 874          * irrespective of its state on entry, which allows the link to come
 875          * up in the in-band case where there is no separate SERDES. Also
 876          * ensure that the link can come up if the PPU is in use and we are
 877          * in PHY mode (we treat the PPU as an effective in-band mechanism.)
 878          */
 879         if (chip->info->ops->port_set_link &&
 880             ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
 881              (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
 882                 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 883
 884         p->interface = state->interface;
 885
 886 err_unlock:
 887         mv88e6xxx_reg_unlock(chip);
 888
 889         if (err && err != -EOPNOTSUPP)
 890                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 891 }
 892
 893 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 894                                     unsigned int mode,
 895                                     phy_interface_t interface)
 896 {
 897         struct mv88e6xxx_chip *chip = ds->priv;
 898         const struct mv88e6xxx_ops *ops;
 899         int err = 0;
 900
 901         ops = chip->info->ops;
 902
 903         mv88e6xxx_reg_lock(chip);
 904         /* Force the link down if we know the port may not be automatically
 905          * updated by the switch or if we are using fixed-link mode.
 906          */
 907         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 908              mode == MLO_AN_FIXED) && ops->port_sync_link)
 909                 err = ops->port_sync_link(chip, port, mode, false);
 910
 911         if (!err && ops->port_set_speed_duplex)
 912                 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
 913                                                  DUPLEX_UNFORCED);
 914         mv88e6xxx_reg_unlock(chip);
 915
 916         if (err)
 917                 dev_err(chip->dev,
 918                         "p%d: failed to force MAC link down\n", port);
 919 }
 920
 921 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 922                                   unsigned int mode, phy_interface_t interface,
 923                                   struct phy_device *phydev,
 924                                   int speed, int duplex,
 925                                   bool tx_pause, bool rx_pause)
 926 {
 927         struct mv88e6xxx_chip *chip = ds->priv;
 928         const struct mv88e6xxx_ops *ops;
 929         int err = 0;
 930
 931         ops = chip->info->ops;
 932
 933         mv88e6xxx_reg_lock(chip);
 934         /* Configure and force the link up if we know that the port may not
 935          * automatically updated by the switch or if we are using fixed-link
 936          * mode.
 937          */
 938         if (!mv88e6xxx_port_ppu_updates(chip, port) ||
 939             mode == MLO_AN_FIXED) {
 940                 /* FIXME: for an automedia port, should we force the link
 941                  * down here - what if the link comes up due to "other" media
 942                  * while we're bringing the port up, how is the exclusivity
 943                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 944                  * shared between internal PHY and Serdes.
 945                  */
 946                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 947                                                    duplex);
 948                 if (err)
 949                         goto error;
 950
 951                 if (ops->port_set_speed_duplex) {
 952                         err = ops->port_set_speed_duplex(chip, port,
 953                                                          speed, duplex);
 954                         if (err && err != -EOPNOTSUPP)
 955                                 goto error;
 956                 }
 957
 958                 if (ops->port_sync_link)
 959                         err = ops->port_sync_link(chip, port, mode, true);
 960         }
 961 error:
 962         mv88e6xxx_reg_unlock(chip);
 963
 964         if (err && err != -EOPNOTSUPP)
 965                 dev_err(ds->dev,
 966                         "p%d: failed to configure MAC link up\n", port);
 967 }
 968
 969 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 970 {
 971         if (!chip->info->ops->stats_snapshot)
 972                 return -EOPNOTSUPP;
 973
 974         return chip->info->ops->stats_snapshot(chip, port);
 975 }
 976
 977 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 978         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 979         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 980         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 981         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 982         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 983         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 984         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 985         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 986         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 987         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 988         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 989         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 990         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 991         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 992         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 993         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 994         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 995         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 996         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 997         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 998         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 999         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
1000         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
1001         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
1002         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
1003         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
1004         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
1005         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
1006         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
1007         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
1008         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
1009         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
1010         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
1011         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
1012         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
1013         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
1014         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
1015         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
1016         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
1017         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
1018         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
1019         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
1020         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
1021         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
1022         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
1023         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
1024         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
1025         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
1026         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
1027         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
1028         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
1029         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
1030         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
1031         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
1032         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
1033         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
1034         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
1035         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
1036         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
1037 };
1038
1039 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1040                                             struct mv88e6xxx_hw_stat *s,
1041                                             int port, u16 bank1_select,
1042                                             u16 histogram)
1043 {
1044         u32 low;
1045         u32 high = 0;
1046         u16 reg = 0;
1047         int err;
1048         u64 value;
1049
1050         switch (s->type) {
1051         case STATS_TYPE_PORT:
1052                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1053                 if (err)
1054                         return U64_MAX;
1055
1056                 low = reg;
1057                 if (s->size == 4) {
1058                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1059                         if (err)
1060                                 return U64_MAX;
1061                         low |= ((u32)reg) << 16;
1062                 }
1063                 break;
1064         case STATS_TYPE_BANK1:
1065                 reg = bank1_select;
1066                 fallthrough;
1067         case STATS_TYPE_BANK0:
1068                 reg |= s->reg | histogram;
1069                 mv88e6xxx_g1_stats_read(chip, reg, &low);
1070                 if (s->size == 8)
1071                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1072                 break;
1073         default:
1074                 return U64_MAX;
1075         }
1076         value = (((u64)high) << 32) | low;
1077         return value;
1078 }
1079
1080 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1081                                        uint8_t *data, int types)
1082 {
1083         struct mv88e6xxx_hw_stat *stat;
1084         int i, j;
1085
1086         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1087                 stat = &mv88e6xxx_hw_stats[i];
1088                 if (stat->type & types) {
1089                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1090                                ETH_GSTRING_LEN);
1091                         j++;
1092                 }
1093         }
1094
1095         return j;
1096 }
1097
1098 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1099                                        uint8_t *data)
1100 {
1101         return mv88e6xxx_stats_get_strings(chip, data,
1102                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1103 }
1104
1105 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1106                                        uint8_t *data)
1107 {
1108         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1109 }
1110
1111 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1112                                        uint8_t *data)
1113 {
1114         return mv88e6xxx_stats_get_strings(chip, data,
1115                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1116 }
1117
1118 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1119         "atu_member_violation",
1120         "atu_miss_violation",
1121         "atu_full_violation",
1122         "vtu_member_violation",
1123         "vtu_miss_violation",
1124 };
1125
1126 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1127 {
1128         unsigned int i;
1129
1130         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1131                 strlcpy(data + i * ETH_GSTRING_LEN,
1132                         mv88e6xxx_atu_vtu_stats_strings[i],
1133                         ETH_GSTRING_LEN);
1134 }
1135
1136 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1137                                   u32 stringset, uint8_t *data)
1138 {
1139         struct mv88e6xxx_chip *chip = ds->priv;
1140         int count = 0;
1141
1142         if (stringset != ETH_SS_STATS)
1143                 return;
1144
1145         mv88e6xxx_reg_lock(chip);
1146
1147         if (chip->info->ops->stats_get_strings)
1148                 count = chip->info->ops->stats_get_strings(chip, data);
1149
1150         if (chip->info->ops->serdes_get_strings) {
1151                 data += count * ETH_GSTRING_LEN;
1152                 count = chip->info->ops->serdes_get_strings(chip, port, data);
1153         }
1154
1155         data += count * ETH_GSTRING_LEN;
1156         mv88e6xxx_atu_vtu_get_strings(data);
1157
1158         mv88e6xxx_reg_unlock(chip);
1159 }
1160
1161 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1162                                           int types)
1163 {
1164         struct mv88e6xxx_hw_stat *stat;
1165         int i, j;
1166
1167         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1168                 stat = &mv88e6xxx_hw_stats[i];
1169                 if (stat->type & types)
1170                         j++;
1171         }
1172         return j;
1173 }
1174
1175 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1176 {
1177         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1178                                               STATS_TYPE_PORT);
1179 }
1180
1181 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1182 {
1183         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1184 }
1185
1186 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1187 {
1188         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1189                                               STATS_TYPE_BANK1);
1190 }
1191
1192 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1193 {
1194         struct mv88e6xxx_chip *chip = ds->priv;
1195         int serdes_count = 0;
1196         int count = 0;
1197
1198         if (sset != ETH_SS_STATS)
1199                 return 0;
1200
1201         mv88e6xxx_reg_lock(chip);
1202         if (chip->info->ops->stats_get_sset_count)
1203                 count = chip->info->ops->stats_get_sset_count(chip);
1204         if (count < 0)
1205                 goto out;
1206
1207         if (chip->info->ops->serdes_get_sset_count)
1208                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1209                                                                       port);
1210         if (serdes_count < 0) {
1211                 count = serdes_count;
1212                 goto out;
1213         }
1214         count += serdes_count;
1215         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1216
1217 out:
1218         mv88e6xxx_reg_unlock(chip);
1219
1220         return count;
1221 }
1222
1223 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1224                                      uint64_t *data, int types,
1225                                      u16 bank1_select, u16 histogram)
1226 {
1227         struct mv88e6xxx_hw_stat *stat;
1228         int i, j;
1229
1230         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1231                 stat = &mv88e6xxx_hw_stats[i];
1232                 if (stat->type & types) {
1233                         mv88e6xxx_reg_lock(chip);
1234                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1235                                                               bank1_select,
1236                                                               histogram);
1237                         mv88e6xxx_reg_unlock(chip);
1238
1239                         j++;
1240                 }
1241         }
1242         return j;
1243 }
1244
1245 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1246                                      uint64_t *data)
1247 {
1248         return mv88e6xxx_stats_get_stats(chip, port, data,
1249                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1250                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1251 }
1252
1253 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1254                                      uint64_t *data)
1255 {
1256         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1257                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1258 }
1259
1260 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1261                                      uint64_t *data)
1262 {
1263         return mv88e6xxx_stats_get_stats(chip, port, data,
1264                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1265                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1266                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1267 }
1268
1269 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1270                                      uint64_t *data)
1271 {
1272         return mv88e6xxx_stats_get_stats(chip, port, data,
1273                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1274                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1275                                          0);
1276 }
1277
1278 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1279                                         uint64_t *data)
1280 {
1281         *data++ = chip->ports[port].atu_member_violation;
1282         *data++ = chip->ports[port].atu_miss_violation;
1283         *data++ = chip->ports[port].atu_full_violation;
1284         *data++ = chip->ports[port].vtu_member_violation;
1285         *data++ = chip->ports[port].vtu_miss_violation;
1286 }
1287
1288 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1289                                 uint64_t *data)
1290 {
1291         int count = 0;
1292
1293         if (chip->info->ops->stats_get_stats)
1294                 count = chip->info->ops->stats_get_stats(chip, port, data);
1295
1296         mv88e6xxx_reg_lock(chip);
1297         if (chip->info->ops->serdes_get_stats) {
1298                 data += count;
1299                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1300         }
1301         data += count;
1302         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1303         mv88e6xxx_reg_unlock(chip);
1304 }
1305
1306 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1307                                         uint64_t *data)
1308 {
1309         struct mv88e6xxx_chip *chip = ds->priv;
1310         int ret;
1311
1312         mv88e6xxx_reg_lock(chip);
1313
1314         ret = mv88e6xxx_stats_snapshot(chip, port);
1315         mv88e6xxx_reg_unlock(chip);
1316
1317         if (ret < 0)
1318                 return;
1319
1320         mv88e6xxx_get_stats(chip, port, data);
1321
1322 }
1323
1324 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1325 {
1326         struct mv88e6xxx_chip *chip = ds->priv;
1327         int len;
1328
1329         len = 32 * sizeof(u16);
1330         if (chip->info->ops->serdes_get_regs_len)
1331                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1332
1333         return len;
1334 }
1335
1336 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1337                                struct ethtool_regs *regs, void *_p)
1338 {
1339         struct mv88e6xxx_chip *chip = ds->priv;
1340         int err;
1341         u16 reg;
1342         u16 *p = _p;
1343         int i;
1344
1345         regs->version = chip->info->prod_num;
1346
1347         memset(p, 0xff, 32 * sizeof(u16));
1348
1349         mv88e6xxx_reg_lock(chip);
1350
1351         for (i = 0; i < 32; i++) {
1352
1353                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1354                 if (!err)
1355                         p[i] = reg;
1356         }
1357
1358         if (chip->info->ops->serdes_get_regs)
1359                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1360
1361         mv88e6xxx_reg_unlock(chip);
1362 }
1363
1364 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1365                                  struct ethtool_eee *e)
1366 {
1367         /* Nothing to do on the port's MAC */
1368         return 0;
1369 }
1370
1371 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1372                                  struct ethtool_eee *e)
1373 {
1374         /* Nothing to do on the port's MAC */
1375         return 0;
1376 }
1377
1378 /* Mask of the local ports allowed to receive frames from a given fabric port */
1379 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1380 {
1381         struct dsa_switch *ds = chip->ds;
1382         struct dsa_switch_tree *dst = ds->dst;
1383         struct dsa_port *dp, *other_dp;
1384         bool found = false;
1385         u16 pvlan;
1386
1387         /* dev is a physical switch */
1388         if (dev <= dst->last_switch) {
1389                 list_for_each_entry(dp, &dst->ports, list) {
1390                         if (dp->ds->index == dev && dp->index == port) {
1391                                 /* dp might be a DSA link or a user port, so it
1392                                  * might or might not have a bridge.
1393                                  * Use the "found" variable for both cases.
1394                                  */
1395                                 found = true;
1396                                 break;
1397                         }
1398                 }
1399         /* dev is a virtual bridge */
1400         } else {
1401                 list_for_each_entry(dp, &dst->ports, list) {
1402                         unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1403
1404                         if (!bridge_num)
1405                                 continue;
1406
1407                         if (bridge_num + dst->last_switch != dev)
1408                                 continue;
1409
1410                         found = true;
1411                         break;
1412                 }
1413         }
1414
1415         /* Prevent frames from unknown switch or virtual bridge */
1416         if (!found)
1417                 return 0;
1418
1419         /* Frames from DSA links and CPU ports can egress any local port */
1420         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1421                 return mv88e6xxx_port_mask(chip);
1422
1423         pvlan = 0;
1424
1425         /* Frames from standalone user ports can only egress on the
1426          * upstream port.
1427          */
1428         if (!dsa_port_bridge_dev_get(dp))
1429                 return BIT(dsa_switch_upstream_port(ds));
1430
1431         /* Frames from bridged user ports can egress any local DSA
1432          * links and CPU ports, as well as any local member of their
1433          * bridge group.
1434          */
1435         dsa_switch_for_each_port(other_dp, ds)
1436                 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1437                     other_dp->type == DSA_PORT_TYPE_DSA ||
1438                     dsa_port_bridge_same(dp, other_dp))
1439                         pvlan |= BIT(other_dp->index);
1440
1441         return pvlan;
1442 }
1443
1444 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1445 {
1446         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1447
1448         /* prevent frames from going back out of the port they came in on */
1449         output_ports &= ~BIT(port);
1450
1451         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1452 }
1453
1454 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1455                                          u8 state)
1456 {
1457         struct mv88e6xxx_chip *chip = ds->priv;
1458         int err;
1459
1460         mv88e6xxx_reg_lock(chip);
1461         err = mv88e6xxx_port_set_state(chip, port, state);
1462         mv88e6xxx_reg_unlock(chip);
1463
1464         if (err)
1465                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1466 }
1467
1468 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1469 {
1470         int err;
1471
1472         if (chip->info->ops->ieee_pri_map) {
1473                 err = chip->info->ops->ieee_pri_map(chip);
1474                 if (err)
1475                         return err;
1476         }
1477
1478         if (chip->info->ops->ip_pri_map) {
1479                 err = chip->info->ops->ip_pri_map(chip);
1480                 if (err)
1481                         return err;
1482         }
1483
1484         return 0;
1485 }
1486
1487 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1488 {
1489         struct dsa_switch *ds = chip->ds;
1490         int target, port;
1491         int err;
1492
1493         if (!chip->info->global2_addr)
1494                 return 0;
1495
1496         /* Initialize the routing port to the 32 possible target devices */
1497         for (target = 0; target < 32; target++) {
1498                 port = dsa_routing_port(ds, target);
1499                 if (port == ds->num_ports)
1500                         port = 0x1f;
1501
1502                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1503                 if (err)
1504                         return err;
1505         }
1506
1507         if (chip->info->ops->set_cascade_port) {
1508                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1509                 err = chip->info->ops->set_cascade_port(chip, port);
1510                 if (err)
1511                         return err;
1512         }
1513
1514         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1515         if (err)
1516                 return err;
1517
1518         return 0;
1519 }
1520
1521 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1522 {
1523         /* Clear all trunk masks and mapping */
1524         if (chip->info->global2_addr)
1525                 return mv88e6xxx_g2_trunk_clear(chip);
1526
1527         return 0;
1528 }
1529
1530 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1531 {
1532         if (chip->info->ops->rmu_disable)
1533                 return chip->info->ops->rmu_disable(chip);
1534
1535         return 0;
1536 }
1537
1538 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1539 {
1540         if (chip->info->ops->pot_clear)
1541                 return chip->info->ops->pot_clear(chip);
1542
1543         return 0;
1544 }
1545
1546 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1547 {
1548         if (chip->info->ops->mgmt_rsvd2cpu)
1549                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1550
1551         return 0;
1552 }
1553
1554 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1555 {
1556         int err;
1557
1558         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1559         if (err)
1560                 return err;
1561
1562         /* The chips that have a "learn2all" bit in Global1, ATU
1563          * Control are precisely those whose port registers have a
1564          * Message Port bit in Port Control 1 and hence implement
1565          * ->port_setup_message_port.
1566          */
1567         if (chip->info->ops->port_setup_message_port) {
1568                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1569                 if (err)
1570                         return err;
1571         }
1572
1573         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1574 }
1575
1576 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1577 {
1578         int port;
1579         int err;
1580
1581         if (!chip->info->ops->irl_init_all)
1582                 return 0;
1583
1584         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1585                 /* Disable ingress rate limiting by resetting all per port
1586                  * ingress rate limit resources to their initial state.
1587                  */
1588                 err = chip->info->ops->irl_init_all(chip, port);
1589                 if (err)
1590                         return err;
1591         }
1592
1593         return 0;
1594 }
1595
1596 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1597 {
1598         if (chip->info->ops->set_switch_mac) {
1599                 u8 addr[ETH_ALEN];
1600
1601                 eth_random_addr(addr);
1602
1603                 return chip->info->ops->set_switch_mac(chip, addr);
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1610 {
1611         struct dsa_switch_tree *dst = chip->ds->dst;
1612         struct dsa_switch *ds;
1613         struct dsa_port *dp;
1614         u16 pvlan = 0;
1615
1616         if (!mv88e6xxx_has_pvt(chip))
1617                 return 0;
1618
1619         /* Skip the local source device, which uses in-chip port VLAN */
1620         if (dev != chip->ds->index) {
1621                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1622
1623                 ds = dsa_switch_find(dst->index, dev);
1624                 dp = ds ? dsa_to_port(ds, port) : NULL;
1625                 if (dp && dp->lag) {
1626                         /* As the PVT is used to limit flooding of
1627                          * FORWARD frames, which use the LAG ID as the
1628                          * source port, we must translate dev/port to
1629                          * the special "LAG device" in the PVT, using
1630                          * the LAG ID (one-based) as the port number
1631                          * (zero-based).
1632                          */
1633                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1634                         port = dsa_port_lag_id_get(dp) - 1;
1635                 }
1636         }
1637
1638         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1639 }
1640
1641 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1642 {
1643         int dev, port;
1644         int err;
1645
1646         if (!mv88e6xxx_has_pvt(chip))
1647                 return 0;
1648
1649         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1650          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1651          */
1652         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1653         if (err)
1654                 return err;
1655
1656         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1657                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1658                         err = mv88e6xxx_pvt_map(chip, dev, port);
1659                         if (err)
1660                                 return err;
1661                 }
1662         }
1663
1664         return 0;
1665 }
1666
1667 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1668                                        u16 fid)
1669 {
1670         if (dsa_to_port(chip->ds, port)->lag)
1671                 /* Hardware is incapable of fast-aging a LAG through a
1672                  * regular ATU move operation. Until we have something
1673                  * more fancy in place this is a no-op.
1674                  */
1675                 return -EOPNOTSUPP;
1676
1677         return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1678 }
1679
1680 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1681 {
1682         struct mv88e6xxx_chip *chip = ds->priv;
1683         int err;
1684
1685         mv88e6xxx_reg_lock(chip);
1686         err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1687         mv88e6xxx_reg_unlock(chip);
1688
1689         if (err)
1690                 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1691                         port, err);
1692 }
1693
1694 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1695 {
1696         if (!mv88e6xxx_max_vid(chip))
1697                 return 0;
1698
1699         return mv88e6xxx_g1_vtu_flush(chip);
1700 }
1701
1702 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1703                              struct mv88e6xxx_vtu_entry *entry)
1704 {
1705         int err;
1706
1707         if (!chip->info->ops->vtu_getnext)
1708                 return -EOPNOTSUPP;
1709
1710         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1711         entry->valid = false;
1712
1713         err = chip->info->ops->vtu_getnext(chip, entry);
1714
1715         if (entry->vid != vid)
1716                 entry->valid = false;
1717
1718         return err;
1719 }
1720
1721 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1722                               int (*cb)(struct mv88e6xxx_chip *chip,
1723                                         const struct mv88e6xxx_vtu_entry *entry,
1724                                         void *priv),
1725                               void *priv)
1726 {
1727         struct mv88e6xxx_vtu_entry entry = {
1728                 .vid = mv88e6xxx_max_vid(chip),
1729                 .valid = false,
1730         };
1731         int err;
1732
1733         if (!chip->info->ops->vtu_getnext)
1734                 return -EOPNOTSUPP;
1735
1736         do {
1737                 err = chip->info->ops->vtu_getnext(chip, &entry);
1738                 if (err)
1739                         return err;
1740
1741                 if (!entry.valid)
1742                         break;
1743
1744                 err = cb(chip, &entry, priv);
1745                 if (err)
1746                         return err;
1747         } while (entry.vid < mv88e6xxx_max_vid(chip));
1748
1749         return 0;
1750 }
1751
1752 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1753                                    struct mv88e6xxx_vtu_entry *entry)
1754 {
1755         if (!chip->info->ops->vtu_loadpurge)
1756                 return -EOPNOTSUPP;
1757
1758         return chip->info->ops->vtu_loadpurge(chip, entry);
1759 }
1760
1761 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1762                                   const struct mv88e6xxx_vtu_entry *entry,
1763                                   void *_fid_bitmap)
1764 {
1765         unsigned long *fid_bitmap = _fid_bitmap;
1766
1767         set_bit(entry->fid, fid_bitmap);
1768         return 0;
1769 }
1770
1771 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1772 {
1773         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1774
1775         /* Every FID has an associated VID, so walking the VTU
1776          * will discover the full set of FIDs in use.
1777          */
1778         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1779 }
1780
1781 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1782 {
1783         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1784         int err;
1785
1786         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1787         if (err)
1788                 return err;
1789
1790         *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1791         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1792                 return -ENOSPC;
1793
1794         /* Clear the database */
1795         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1796 }
1797
1798 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1799                                    struct mv88e6xxx_stu_entry *entry)
1800 {
1801         if (!chip->info->ops->stu_loadpurge)
1802                 return -EOPNOTSUPP;
1803
1804         return chip->info->ops->stu_loadpurge(chip, entry);
1805 }
1806
1807 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1808 {
1809         struct mv88e6xxx_stu_entry stu = {
1810                 .valid = true,
1811                 .sid = 0
1812         };
1813
1814         if (!mv88e6xxx_has_stu(chip))
1815                 return 0;
1816
1817         /* Make sure that SID 0 is always valid. This is used by VTU
1818          * entries that do not make use of the STU, e.g. when creating
1819          * a VLAN upper on a port that is also part of a VLAN
1820          * filtering bridge.
1821          */
1822         return mv88e6xxx_stu_loadpurge(chip, &stu);
1823 }
1824
1825 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1826 {
1827         DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1828         struct mv88e6xxx_mst *mst;
1829
1830         __set_bit(0, busy);
1831
1832         list_for_each_entry(mst, &chip->msts, node)
1833                 __set_bit(mst->stu.sid, busy);
1834
1835         *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1836
1837         return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1838 }
1839
1840 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1841 {
1842         struct mv88e6xxx_mst *mst, *tmp;
1843         int err;
1844
1845         if (!sid)
1846                 return 0;
1847
1848         list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1849                 if (mst->stu.sid != sid)
1850                         continue;
1851
1852                 if (!refcount_dec_and_test(&mst->refcnt))
1853                         return 0;
1854
1855                 mst->stu.valid = false;
1856                 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1857                 if (err) {
1858                         refcount_set(&mst->refcnt, 1);
1859                         return err;
1860                 }
1861
1862                 list_del(&mst->node);
1863                 kfree(mst);
1864                 return 0;
1865         }
1866
1867         return -ENOENT;
1868 }
1869
1870 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1871                              u16 msti, u8 *sid)
1872 {
1873         struct mv88e6xxx_mst *mst;
1874         int err, i;
1875
1876         if (!mv88e6xxx_has_stu(chip)) {
1877                 err = -EOPNOTSUPP;
1878                 goto err;
1879         }
1880
1881         if (!msti) {
1882                 *sid = 0;
1883                 return 0;
1884         }
1885
1886         list_for_each_entry(mst, &chip->msts, node) {
1887                 if (mst->br == br && mst->msti == msti) {
1888                         refcount_inc(&mst->refcnt);
1889                         *sid = mst->stu.sid;
1890                         return 0;
1891                 }
1892         }
1893
1894         err = mv88e6xxx_sid_get(chip, sid);
1895         if (err)
1896                 goto err;
1897
1898         mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1899         if (!mst) {
1900                 err = -ENOMEM;
1901                 goto err;
1902         }
1903
1904         INIT_LIST_HEAD(&mst->node);
1905         refcount_set(&mst->refcnt, 1);
1906         mst->br = br;
1907         mst->msti = msti;
1908         mst->stu.valid = true;
1909         mst->stu.sid = *sid;
1910
1911         /* The bridge starts out all ports in the disabled state. But
1912          * a STU state of disabled means to go by the port-global
1913          * state. So we set all user port's initial state to blocking,
1914          * to match the bridge's behavior.
1915          */
1916         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1917                 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1918                         MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1919                         MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1920
1921         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1922         if (err)
1923                 goto err_free;
1924
1925         list_add_tail(&mst->node, &chip->msts);
1926         return 0;
1927
1928 err_free:
1929         kfree(mst);
1930 err:
1931         return err;
1932 }
1933
1934 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1935                                         const struct switchdev_mst_state *st)
1936 {
1937         struct dsa_port *dp = dsa_to_port(ds, port);
1938         struct mv88e6xxx_chip *chip = ds->priv;
1939         struct mv88e6xxx_mst *mst;
1940         u8 state;
1941         int err;
1942
1943         if (!mv88e6xxx_has_stu(chip))
1944                 return -EOPNOTSUPP;
1945
1946         switch (st->state) {
1947         case BR_STATE_DISABLED:
1948         case BR_STATE_BLOCKING:
1949         case BR_STATE_LISTENING:
1950                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1951                 break;
1952         case BR_STATE_LEARNING:
1953                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1954                 break;
1955         case BR_STATE_FORWARDING:
1956                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         list_for_each_entry(mst, &chip->msts, node) {
1963                 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1964                     mst->msti == st->msti) {
1965                         if (mst->stu.state[port] == state)
1966                                 return 0;
1967
1968                         mst->stu.state[port] = state;
1969                         mv88e6xxx_reg_lock(chip);
1970                         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1971                         mv88e6xxx_reg_unlock(chip);
1972                         return err;
1973                 }
1974         }
1975
1976         return -ENOENT;
1977 }
1978
1979 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1980                                         u16 vid)
1981 {
1982         struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1983         struct mv88e6xxx_chip *chip = ds->priv;
1984         struct mv88e6xxx_vtu_entry vlan;
1985         int err;
1986
1987         /* DSA and CPU ports have to be members of multiple vlans */
1988         if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
1989                 return 0;
1990
1991         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1992         if (err)
1993                 return err;
1994
1995         if (!vlan.valid)
1996                 return 0;
1997
1998         dsa_switch_for_each_user_port(other_dp, ds) {
1999                 struct net_device *other_br;
2000
2001                 if (vlan.member[other_dp->index] ==
2002                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2003                         continue;
2004
2005                 if (dsa_port_bridge_same(dp, other_dp))
2006                         break; /* same bridge, check next VLAN */
2007
2008                 other_br = dsa_port_bridge_dev_get(other_dp);
2009                 if (!other_br)
2010                         continue;
2011
2012                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2013                         port, vlan.vid, other_dp->index, netdev_name(other_br));
2014                 return -EOPNOTSUPP;
2015         }
2016
2017         return 0;
2018 }
2019
2020 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2021 {
2022         struct dsa_port *dp = dsa_to_port(chip->ds, port);
2023         struct net_device *br = dsa_port_bridge_dev_get(dp);
2024         struct mv88e6xxx_port *p = &chip->ports[port];
2025         u16 pvid = MV88E6XXX_VID_STANDALONE;
2026         bool drop_untagged = false;
2027         int err;
2028
2029         if (br) {
2030                 if (br_vlan_enabled(br)) {
2031                         pvid = p->bridge_pvid.vid;
2032                         drop_untagged = !p->bridge_pvid.valid;
2033                 } else {
2034                         pvid = MV88E6XXX_VID_BRIDGED;
2035                 }
2036         }
2037
2038         err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2039         if (err)
2040                 return err;
2041
2042         return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2043 }
2044
2045 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2046                                          bool vlan_filtering,
2047                                          struct netlink_ext_ack *extack)
2048 {
2049         struct mv88e6xxx_chip *chip = ds->priv;
2050         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2051                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2052         int err;
2053
2054         if (!mv88e6xxx_max_vid(chip))
2055                 return -EOPNOTSUPP;
2056
2057         mv88e6xxx_reg_lock(chip);
2058
2059         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2060         if (err)
2061                 goto unlock;
2062
2063         err = mv88e6xxx_port_commit_pvid(chip, port);
2064         if (err)
2065                 goto unlock;
2066
2067 unlock:
2068         mv88e6xxx_reg_unlock(chip);
2069
2070         return err;
2071 }
2072
2073 static int
2074 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2075                             const struct switchdev_obj_port_vlan *vlan)
2076 {
2077         struct mv88e6xxx_chip *chip = ds->priv;
2078         int err;
2079
2080         if (!mv88e6xxx_max_vid(chip))
2081                 return -EOPNOTSUPP;
2082
2083         /* If the requested port doesn't belong to the same bridge as the VLAN
2084          * members, do not support it (yet) and fallback to software VLAN.
2085          */
2086         mv88e6xxx_reg_lock(chip);
2087         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2088         mv88e6xxx_reg_unlock(chip);
2089
2090         return err;
2091 }
2092
2093 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2094                                         const unsigned char *addr, u16 vid,
2095                                         u8 state)
2096 {
2097         struct mv88e6xxx_atu_entry entry;
2098         struct mv88e6xxx_vtu_entry vlan;
2099         u16 fid;
2100         int err;
2101
2102         /* Ports have two private address databases: one for when the port is
2103          * standalone and one for when the port is under a bridge and the
2104          * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2105          * address database to remain 100% empty, so we never load an ATU entry
2106          * into a standalone port's database. Therefore, translate the null
2107          * VLAN ID into the port's database used for VLAN-unaware bridging.
2108          */
2109         if (vid == 0) {
2110                 fid = MV88E6XXX_FID_BRIDGED;
2111         } else {
2112                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2113                 if (err)
2114                         return err;
2115
2116                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2117                 if (!vlan.valid)
2118                         return -EOPNOTSUPP;
2119
2120                 fid = vlan.fid;
2121         }
2122
2123         entry.state = 0;
2124         ether_addr_copy(entry.mac, addr);
2125         eth_addr_dec(entry.mac);
2126
2127         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2128         if (err)
2129                 return err;
2130
2131         /* Initialize a fresh ATU entry if it isn't found */
2132         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2133                 memset(&entry, 0, sizeof(entry));
2134                 ether_addr_copy(entry.mac, addr);
2135         }
2136
2137         /* Purge the ATU entry only if no port is using it anymore */
2138         if (!state) {
2139                 entry.portvec &= ~BIT(port);
2140                 if (!entry.portvec)
2141                         entry.state = 0;
2142         } else {
2143                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2144                         entry.portvec = BIT(port);
2145                 else
2146                         entry.portvec |= BIT(port);
2147
2148                 entry.state = state;
2149         }
2150
2151         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2152 }
2153
2154 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2155                                   const struct mv88e6xxx_policy *policy)
2156 {
2157         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2158         enum mv88e6xxx_policy_action action = policy->action;
2159         const u8 *addr = policy->addr;
2160         u16 vid = policy->vid;
2161         u8 state;
2162         int err;
2163         int id;
2164
2165         if (!chip->info->ops->port_set_policy)
2166                 return -EOPNOTSUPP;
2167
2168         switch (mapping) {
2169         case MV88E6XXX_POLICY_MAPPING_DA:
2170         case MV88E6XXX_POLICY_MAPPING_SA:
2171                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2172                         state = 0; /* Dissociate the port and address */
2173                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2174                          is_multicast_ether_addr(addr))
2175                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2176                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2177                          is_unicast_ether_addr(addr))
2178                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2179                 else
2180                         return -EOPNOTSUPP;
2181
2182                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2183                                                    state);
2184                 if (err)
2185                         return err;
2186                 break;
2187         default:
2188                 return -EOPNOTSUPP;
2189         }
2190
2191         /* Skip the port's policy clearing if the mapping is still in use */
2192         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2193                 idr_for_each_entry(&chip->policies, policy, id)
2194                         if (policy->port == port &&
2195                             policy->mapping == mapping &&
2196                             policy->action != action)
2197                                 return 0;
2198
2199         return chip->info->ops->port_set_policy(chip, port, mapping, action);
2200 }
2201
2202 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2203                                    struct ethtool_rx_flow_spec *fs)
2204 {
2205         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2206         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2207         enum mv88e6xxx_policy_mapping mapping;
2208         enum mv88e6xxx_policy_action action;
2209         struct mv88e6xxx_policy *policy;
2210         u16 vid = 0;
2211         u8 *addr;
2212         int err;
2213         int id;
2214
2215         if (fs->location != RX_CLS_LOC_ANY)
2216                 return -EINVAL;
2217
2218         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2219                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2220         else
2221                 return -EOPNOTSUPP;
2222
2223         switch (fs->flow_type & ~FLOW_EXT) {
2224         case ETHER_FLOW:
2225                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2226                     is_zero_ether_addr(mac_mask->h_source)) {
2227                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
2228                         addr = mac_entry->h_dest;
2229                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2230                     !is_zero_ether_addr(mac_mask->h_source)) {
2231                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
2232                         addr = mac_entry->h_source;
2233                 } else {
2234                         /* Cannot support DA and SA mapping in the same rule */
2235                         return -EOPNOTSUPP;
2236                 }
2237                 break;
2238         default:
2239                 return -EOPNOTSUPP;
2240         }
2241
2242         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2243                 if (fs->m_ext.vlan_tci != htons(0xffff))
2244                         return -EOPNOTSUPP;
2245                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2246         }
2247
2248         idr_for_each_entry(&chip->policies, policy, id) {
2249                 if (policy->port == port && policy->mapping == mapping &&
2250                     policy->action == action && policy->vid == vid &&
2251                     ether_addr_equal(policy->addr, addr))
2252                         return -EEXIST;
2253         }
2254
2255         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2256         if (!policy)
2257                 return -ENOMEM;
2258
2259         fs->location = 0;
2260         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2261                             GFP_KERNEL);
2262         if (err) {
2263                 devm_kfree(chip->dev, policy);
2264                 return err;
2265         }
2266
2267         memcpy(&policy->fs, fs, sizeof(*fs));
2268         ether_addr_copy(policy->addr, addr);
2269         policy->mapping = mapping;
2270         policy->action = action;
2271         policy->port = port;
2272         policy->vid = vid;
2273
2274         err = mv88e6xxx_policy_apply(chip, port, policy);
2275         if (err) {
2276                 idr_remove(&chip->policies, fs->location);
2277                 devm_kfree(chip->dev, policy);
2278                 return err;
2279         }
2280
2281         return 0;
2282 }
2283
2284 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2285                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2286 {
2287         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2288         struct mv88e6xxx_chip *chip = ds->priv;
2289         struct mv88e6xxx_policy *policy;
2290         int err;
2291         int id;
2292
2293         mv88e6xxx_reg_lock(chip);
2294
2295         switch (rxnfc->cmd) {
2296         case ETHTOOL_GRXCLSRLCNT:
2297                 rxnfc->data = 0;
2298                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2299                 rxnfc->rule_cnt = 0;
2300                 idr_for_each_entry(&chip->policies, policy, id)
2301                         if (policy->port == port)
2302                                 rxnfc->rule_cnt++;
2303                 err = 0;
2304                 break;
2305         case ETHTOOL_GRXCLSRULE:
2306                 err = -ENOENT;
2307                 policy = idr_find(&chip->policies, fs->location);
2308                 if (policy) {
2309                         memcpy(fs, &policy->fs, sizeof(*fs));
2310                         err = 0;
2311                 }
2312                 break;
2313         case ETHTOOL_GRXCLSRLALL:
2314                 rxnfc->data = 0;
2315                 rxnfc->rule_cnt = 0;
2316                 idr_for_each_entry(&chip->policies, policy, id)
2317                         if (policy->port == port)
2318                                 rule_locs[rxnfc->rule_cnt++] = id;
2319                 err = 0;
2320                 break;
2321         default:
2322                 err = -EOPNOTSUPP;
2323                 break;
2324         }
2325
2326         mv88e6xxx_reg_unlock(chip);
2327
2328         return err;
2329 }
2330
2331 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2332                                struct ethtool_rxnfc *rxnfc)
2333 {
2334         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2335         struct mv88e6xxx_chip *chip = ds->priv;
2336         struct mv88e6xxx_policy *policy;
2337         int err;
2338
2339         mv88e6xxx_reg_lock(chip);
2340
2341         switch (rxnfc->cmd) {
2342         case ETHTOOL_SRXCLSRLINS:
2343                 err = mv88e6xxx_policy_insert(chip, port, fs);
2344                 break;
2345         case ETHTOOL_SRXCLSRLDEL:
2346                 err = -ENOENT;
2347                 policy = idr_remove(&chip->policies, fs->location);
2348                 if (policy) {
2349                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2350                         err = mv88e6xxx_policy_apply(chip, port, policy);
2351                         devm_kfree(chip->dev, policy);
2352                 }
2353                 break;
2354         default:
2355                 err = -EOPNOTSUPP;
2356                 break;
2357         }
2358
2359         mv88e6xxx_reg_unlock(chip);
2360
2361         return err;
2362 }
2363
2364 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2365                                         u16 vid)
2366 {
2367         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2368         u8 broadcast[ETH_ALEN];
2369
2370         eth_broadcast_addr(broadcast);
2371
2372         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2373 }
2374
2375 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2376 {
2377         int port;
2378         int err;
2379
2380         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2381                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2382                 struct net_device *brport;
2383
2384                 if (dsa_is_unused_port(chip->ds, port))
2385                         continue;
2386
2387                 brport = dsa_port_to_bridge_port(dp);
2388                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2389                         /* Skip bridged user ports where broadcast
2390                          * flooding is disabled.
2391                          */
2392                         continue;
2393
2394                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2395                 if (err)
2396                         return err;
2397         }
2398
2399         return 0;
2400 }
2401
2402 struct mv88e6xxx_port_broadcast_sync_ctx {
2403         int port;
2404         bool flood;
2405 };
2406
2407 static int
2408 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2409                                    const struct mv88e6xxx_vtu_entry *vlan,
2410                                    void *_ctx)
2411 {
2412         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2413         u8 broadcast[ETH_ALEN];
2414         u8 state;
2415
2416         if (ctx->flood)
2417                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2418         else
2419                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2420
2421         eth_broadcast_addr(broadcast);
2422
2423         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2424                                             vlan->vid, state);
2425 }
2426
2427 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2428                                          bool flood)
2429 {
2430         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2431                 .port = port,
2432                 .flood = flood,
2433         };
2434         struct mv88e6xxx_vtu_entry vid0 = {
2435                 .vid = 0,
2436         };
2437         int err;
2438
2439         /* Update the port's private database... */
2440         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2441         if (err)
2442                 return err;
2443
2444         /* ...and the database for all VLANs. */
2445         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2446                                   &ctx);
2447 }
2448
2449 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2450                                     u16 vid, u8 member, bool warn)
2451 {
2452         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2453         struct mv88e6xxx_vtu_entry vlan;
2454         int i, err;
2455
2456         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2457         if (err)
2458                 return err;
2459
2460         if (!vlan.valid) {
2461                 memset(&vlan, 0, sizeof(vlan));
2462
2463                 if (vid == MV88E6XXX_VID_STANDALONE)
2464                         vlan.policy = true;
2465
2466                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2467                 if (err)
2468                         return err;
2469
2470                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2471                         if (i == port)
2472                                 vlan.member[i] = member;
2473                         else
2474                                 vlan.member[i] = non_member;
2475
2476                 vlan.vid = vid;
2477                 vlan.valid = true;
2478
2479                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2480                 if (err)
2481                         return err;
2482
2483                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2484                 if (err)
2485                         return err;
2486         } else if (vlan.member[port] != member) {
2487                 vlan.member[port] = member;
2488
2489                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2490                 if (err)
2491                         return err;
2492         } else if (warn) {
2493                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2494                          port, vid);
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2501                                    const struct switchdev_obj_port_vlan *vlan,
2502                                    struct netlink_ext_ack *extack)
2503 {
2504         struct mv88e6xxx_chip *chip = ds->priv;
2505         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2506         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2507         struct mv88e6xxx_port *p = &chip->ports[port];
2508         bool warn;
2509         u8 member;
2510         int err;
2511
2512         if (!vlan->vid)
2513                 return 0;
2514
2515         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2516         if (err)
2517                 return err;
2518
2519         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2520                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2521         else if (untagged)
2522                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2523         else
2524                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2525
2526         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2527          * and then the CPU port. Do not warn for duplicates for the CPU port.
2528          */
2529         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2530
2531         mv88e6xxx_reg_lock(chip);
2532
2533         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2534         if (err) {
2535                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2536                         vlan->vid, untagged ? 'u' : 't');
2537                 goto out;
2538         }
2539
2540         if (pvid) {
2541                 p->bridge_pvid.vid = vlan->vid;
2542                 p->bridge_pvid.valid = true;
2543
2544                 err = mv88e6xxx_port_commit_pvid(chip, port);
2545                 if (err)
2546                         goto out;
2547         } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2548                 /* The old pvid was reinstalled as a non-pvid VLAN */
2549                 p->bridge_pvid.valid = false;
2550
2551                 err = mv88e6xxx_port_commit_pvid(chip, port);
2552                 if (err)
2553                         goto out;
2554         }
2555
2556 out:
2557         mv88e6xxx_reg_unlock(chip);
2558
2559         return err;
2560 }
2561
2562 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2563                                      int port, u16 vid)
2564 {
2565         struct mv88e6xxx_vtu_entry vlan;
2566         int i, err;
2567
2568         if (!vid)
2569                 return 0;
2570
2571         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2572         if (err)
2573                 return err;
2574
2575         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2576          * tell switchdev that this VLAN is likely handled in software.
2577          */
2578         if (!vlan.valid ||
2579             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2580                 return -EOPNOTSUPP;
2581
2582         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2583
2584         /* keep the VLAN unless all ports are excluded */
2585         vlan.valid = false;
2586         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2587                 if (vlan.member[i] !=
2588                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2589                         vlan.valid = true;
2590                         break;
2591                 }
2592         }
2593
2594         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2595         if (err)
2596                 return err;
2597
2598         if (!vlan.valid) {
2599                 err = mv88e6xxx_mst_put(chip, vlan.sid);
2600                 if (err)
2601                         return err;
2602         }
2603
2604         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2605 }
2606
2607 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2608                                    const struct switchdev_obj_port_vlan *vlan)
2609 {
2610         struct mv88e6xxx_chip *chip = ds->priv;
2611         struct mv88e6xxx_port *p = &chip->ports[port];
2612         int err = 0;
2613         u16 pvid;
2614
2615         if (!mv88e6xxx_max_vid(chip))
2616                 return -EOPNOTSUPP;
2617
2618         /* The ATU removal procedure needs the FID to be mapped in the VTU,
2619          * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2620          * switchdev workqueue to ensure that all FDB entries are deleted
2621          * before we remove the VLAN.
2622          */
2623         dsa_flush_workqueue();
2624
2625         mv88e6xxx_reg_lock(chip);
2626
2627         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2628         if (err)
2629                 goto unlock;
2630
2631         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2632         if (err)
2633                 goto unlock;
2634
2635         if (vlan->vid == pvid) {
2636                 p->bridge_pvid.valid = false;
2637
2638                 err = mv88e6xxx_port_commit_pvid(chip, port);
2639                 if (err)
2640                         goto unlock;
2641         }
2642
2643 unlock:
2644         mv88e6xxx_reg_unlock(chip);
2645
2646         return err;
2647 }
2648
2649 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2650 {
2651         struct mv88e6xxx_chip *chip = ds->priv;
2652         struct mv88e6xxx_vtu_entry vlan;
2653         int err;
2654
2655         mv88e6xxx_reg_lock(chip);
2656
2657         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2658         if (err)
2659                 goto unlock;
2660
2661         err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2662
2663 unlock:
2664         mv88e6xxx_reg_unlock(chip);
2665
2666         return err;
2667 }
2668
2669 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2670                                    struct dsa_bridge bridge,
2671                                    const struct switchdev_vlan_msti *msti)
2672 {
2673         struct mv88e6xxx_chip *chip = ds->priv;
2674         struct mv88e6xxx_vtu_entry vlan;
2675         u8 old_sid, new_sid;
2676         int err;
2677
2678         if (!mv88e6xxx_has_stu(chip))
2679                 return -EOPNOTSUPP;
2680
2681         mv88e6xxx_reg_lock(chip);
2682
2683         err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2684         if (err)
2685                 goto unlock;
2686
2687         if (!vlan.valid) {
2688                 err = -EINVAL;
2689                 goto unlock;
2690         }
2691
2692         old_sid = vlan.sid;
2693
2694         err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2695         if (err)
2696                 goto unlock;
2697
2698         if (new_sid != old_sid) {
2699                 vlan.sid = new_sid;
2700
2701                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2702                 if (err) {
2703                         mv88e6xxx_mst_put(chip, new_sid);
2704                         goto unlock;
2705                 }
2706         }
2707
2708         err = mv88e6xxx_mst_put(chip, old_sid);
2709
2710 unlock:
2711         mv88e6xxx_reg_unlock(chip);
2712         return err;
2713 }
2714
2715 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2716                                   const unsigned char *addr, u16 vid,
2717                                   struct dsa_db db)
2718 {
2719         struct mv88e6xxx_chip *chip = ds->priv;
2720         int err;
2721
2722         mv88e6xxx_reg_lock(chip);
2723         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2724                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2725         mv88e6xxx_reg_unlock(chip);
2726
2727         return err;
2728 }
2729
2730 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2731                                   const unsigned char *addr, u16 vid,
2732                                   struct dsa_db db)
2733 {
2734         struct mv88e6xxx_chip *chip = ds->priv;
2735         int err;
2736
2737         mv88e6xxx_reg_lock(chip);
2738         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2739         mv88e6xxx_reg_unlock(chip);
2740
2741         return err;
2742 }
2743
2744 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2745                                       u16 fid, u16 vid, int port,
2746                                       dsa_fdb_dump_cb_t *cb, void *data)
2747 {
2748         struct mv88e6xxx_atu_entry addr;
2749         bool is_static;
2750         int err;
2751
2752         addr.state = 0;
2753         eth_broadcast_addr(addr.mac);
2754
2755         do {
2756                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2757                 if (err)
2758                         return err;
2759
2760                 if (!addr.state)
2761                         break;
2762
2763                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2764                         continue;
2765
2766                 if (!is_unicast_ether_addr(addr.mac))
2767                         continue;
2768
2769                 is_static = (addr.state ==
2770                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2771                 err = cb(addr.mac, vid, is_static, data);
2772                 if (err)
2773                         return err;
2774         } while (!is_broadcast_ether_addr(addr.mac));
2775
2776         return err;
2777 }
2778
2779 struct mv88e6xxx_port_db_dump_vlan_ctx {
2780         int port;
2781         dsa_fdb_dump_cb_t *cb;
2782         void *data;
2783 };
2784
2785 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2786                                        const struct mv88e6xxx_vtu_entry *entry,
2787                                        void *_data)
2788 {
2789         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2790
2791         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2792                                           ctx->port, ctx->cb, ctx->data);
2793 }
2794
2795 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2796                                   dsa_fdb_dump_cb_t *cb, void *data)
2797 {
2798         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2799                 .port = port,
2800                 .cb = cb,
2801                 .data = data,
2802         };
2803         u16 fid;
2804         int err;
2805
2806         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2807         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2808         if (err)
2809                 return err;
2810
2811         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2812         if (err)
2813                 return err;
2814
2815         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2816 }
2817
2818 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2819                                    dsa_fdb_dump_cb_t *cb, void *data)
2820 {
2821         struct mv88e6xxx_chip *chip = ds->priv;
2822         int err;
2823
2824         mv88e6xxx_reg_lock(chip);
2825         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2826         mv88e6xxx_reg_unlock(chip);
2827
2828         return err;
2829 }
2830
2831 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2832                                 struct dsa_bridge bridge)
2833 {
2834         struct dsa_switch *ds = chip->ds;
2835         struct dsa_switch_tree *dst = ds->dst;
2836         struct dsa_port *dp;
2837         int err;
2838
2839         list_for_each_entry(dp, &dst->ports, list) {
2840                 if (dsa_port_offloads_bridge(dp, &bridge)) {
2841                         if (dp->ds == ds) {
2842                                 /* This is a local bridge group member,
2843                                  * remap its Port VLAN Map.
2844                                  */
2845                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2846                                 if (err)
2847                                         return err;
2848                         } else {
2849                                 /* This is an external bridge group member,
2850                                  * remap its cross-chip Port VLAN Table entry.
2851                                  */
2852                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2853                                                         dp->index);
2854                                 if (err)
2855                                         return err;
2856                         }
2857                 }
2858         }
2859
2860         return 0;
2861 }
2862
2863 /* Treat the software bridge as a virtual single-port switch behind the
2864  * CPU and map in the PVT. First dst->last_switch elements are taken by
2865  * physical switches, so start from beyond that range.
2866  */
2867 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2868                                                unsigned int bridge_num)
2869 {
2870         u8 dev = bridge_num + ds->dst->last_switch;
2871         struct mv88e6xxx_chip *chip = ds->priv;
2872
2873         return mv88e6xxx_pvt_map(chip, dev, 0);
2874 }
2875
2876 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2877                                       struct dsa_bridge bridge,
2878                                       bool *tx_fwd_offload,
2879                                       struct netlink_ext_ack *extack)
2880 {
2881         struct mv88e6xxx_chip *chip = ds->priv;
2882         int err;
2883
2884         mv88e6xxx_reg_lock(chip);
2885
2886         err = mv88e6xxx_bridge_map(chip, bridge);
2887         if (err)
2888                 goto unlock;
2889
2890         err = mv88e6xxx_port_set_map_da(chip, port, true);
2891         if (err)
2892                 goto unlock;
2893
2894         err = mv88e6xxx_port_commit_pvid(chip, port);
2895         if (err)
2896                 goto unlock;
2897
2898         if (mv88e6xxx_has_pvt(chip)) {
2899                 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2900                 if (err)
2901                         goto unlock;
2902
2903                 *tx_fwd_offload = true;
2904         }
2905
2906 unlock:
2907         mv88e6xxx_reg_unlock(chip);
2908
2909         return err;
2910 }
2911
2912 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2913                                         struct dsa_bridge bridge)
2914 {
2915         struct mv88e6xxx_chip *chip = ds->priv;
2916         int err;
2917
2918         mv88e6xxx_reg_lock(chip);
2919
2920         if (bridge.tx_fwd_offload &&
2921             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2922                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2923
2924         if (mv88e6xxx_bridge_map(chip, bridge) ||
2925             mv88e6xxx_port_vlan_map(chip, port))
2926                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2927
2928         err = mv88e6xxx_port_set_map_da(chip, port, false);
2929         if (err)
2930                 dev_err(ds->dev,
2931                         "port %d failed to restore map-DA: %pe\n",
2932                         port, ERR_PTR(err));
2933
2934         err = mv88e6xxx_port_commit_pvid(chip, port);
2935         if (err)
2936                 dev_err(ds->dev,
2937                         "port %d failed to restore standalone pvid: %pe\n",
2938                         port, ERR_PTR(err));
2939
2940         mv88e6xxx_reg_unlock(chip);
2941 }
2942
2943 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2944                                            int tree_index, int sw_index,
2945                                            int port, struct dsa_bridge bridge,
2946                                            struct netlink_ext_ack *extack)
2947 {
2948         struct mv88e6xxx_chip *chip = ds->priv;
2949         int err;
2950
2951         if (tree_index != ds->dst->index)
2952                 return 0;
2953
2954         mv88e6xxx_reg_lock(chip);
2955         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2956         err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2957         mv88e6xxx_reg_unlock(chip);
2958
2959         return err;
2960 }
2961
2962 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2963                                              int tree_index, int sw_index,
2964                                              int port, struct dsa_bridge bridge)
2965 {
2966         struct mv88e6xxx_chip *chip = ds->priv;
2967
2968         if (tree_index != ds->dst->index)
2969                 return;
2970
2971         mv88e6xxx_reg_lock(chip);
2972         if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2973             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2974                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2975         mv88e6xxx_reg_unlock(chip);
2976 }
2977
2978 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2979 {
2980         if (chip->info->ops->reset)
2981                 return chip->info->ops->reset(chip);
2982
2983         return 0;
2984 }
2985
2986 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2987 {
2988         struct gpio_desc *gpiod = chip->reset;
2989
2990         /* If there is a GPIO connected to the reset pin, toggle it */
2991         if (gpiod) {
2992                 gpiod_set_value_cansleep(gpiod, 1);
2993                 usleep_range(10000, 20000);
2994                 gpiod_set_value_cansleep(gpiod, 0);
2995                 usleep_range(10000, 20000);
2996
2997                 mv88e6xxx_g1_wait_eeprom_done(chip);
2998         }
2999 }
3000
3001 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3002 {
3003         int i, err;
3004
3005         /* Set all ports to the Disabled state */
3006         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3007                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3008                 if (err)
3009                         return err;
3010         }
3011
3012         /* Wait for transmit queues to drain,
3013          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3014          */
3015         usleep_range(2000, 4000);
3016
3017         return 0;
3018 }
3019
3020 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3021 {
3022         int err;
3023
3024         err = mv88e6xxx_disable_ports(chip);
3025         if (err)
3026                 return err;
3027
3028         mv88e6xxx_hardware_reset(chip);
3029
3030         return mv88e6xxx_software_reset(chip);
3031 }
3032
3033 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3034                                    enum mv88e6xxx_frame_mode frame,
3035                                    enum mv88e6xxx_egress_mode egress, u16 etype)
3036 {
3037         int err;
3038
3039         if (!chip->info->ops->port_set_frame_mode)
3040                 return -EOPNOTSUPP;
3041
3042         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3043         if (err)
3044                 return err;
3045
3046         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3047         if (err)
3048                 return err;
3049
3050         if (chip->info->ops->port_set_ether_type)
3051                 return chip->info->ops->port_set_ether_type(chip, port, etype);
3052
3053         return 0;
3054 }
3055
3056 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3057 {
3058         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3059                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3060                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3061 }
3062
3063 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3064 {
3065         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3066                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3067                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3068 }
3069
3070 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3071 {
3072         return mv88e6xxx_set_port_mode(chip, port,
3073                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
3074                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3075                                        ETH_P_EDSA);
3076 }
3077
3078 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3079 {
3080         if (dsa_is_dsa_port(chip->ds, port))
3081                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3082
3083         if (dsa_is_user_port(chip->ds, port))
3084                 return mv88e6xxx_set_port_mode_normal(chip, port);
3085
3086         /* Setup CPU port mode depending on its supported tag format */
3087         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3088                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3089
3090         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3091                 return mv88e6xxx_set_port_mode_edsa(chip, port);
3092
3093         return -EINVAL;
3094 }
3095
3096 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3097 {
3098         bool message = dsa_is_dsa_port(chip->ds, port);
3099
3100         return mv88e6xxx_port_set_message_port(chip, port, message);
3101 }
3102
3103 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3104 {
3105         int err;
3106
3107         if (chip->info->ops->port_set_ucast_flood) {
3108                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3109                 if (err)
3110                         return err;
3111         }
3112         if (chip->info->ops->port_set_mcast_flood) {
3113                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3114                 if (err)
3115                         return err;
3116         }
3117
3118         return 0;
3119 }
3120
3121 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
3122 {
3123         struct mv88e6xxx_port *mvp = dev_id;
3124         struct mv88e6xxx_chip *chip = mvp->chip;
3125         irqreturn_t ret = IRQ_NONE;
3126         int port = mvp->port;
3127         int lane;
3128
3129         mv88e6xxx_reg_lock(chip);
3130         lane = mv88e6xxx_serdes_get_lane(chip, port);
3131         if (lane >= 0)
3132                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
3133         mv88e6xxx_reg_unlock(chip);
3134
3135         return ret;
3136 }
3137
3138 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
3139                                         int lane)
3140 {
3141         struct mv88e6xxx_port *dev_id = &chip->ports[port];
3142         unsigned int irq;
3143         int err;
3144
3145         /* Nothing to request if this SERDES port has no IRQ */
3146         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
3147         if (!irq)
3148                 return 0;
3149
3150         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
3151                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
3152
3153         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
3154         mv88e6xxx_reg_unlock(chip);
3155         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
3156                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
3157                                    dev_id);
3158         mv88e6xxx_reg_lock(chip);
3159         if (err)
3160                 return err;
3161
3162         dev_id->serdes_irq = irq;
3163
3164         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
3165 }
3166
3167 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
3168                                      int lane)
3169 {
3170         struct mv88e6xxx_port *dev_id = &chip->ports[port];
3171         unsigned int irq = dev_id->serdes_irq;
3172         int err;
3173
3174         /* Nothing to free if no IRQ has been requested */
3175         if (!irq)
3176                 return 0;
3177
3178         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
3179
3180         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
3181         mv88e6xxx_reg_unlock(chip);
3182         free_irq(irq, dev_id);
3183         mv88e6xxx_reg_lock(chip);
3184
3185         dev_id->serdes_irq = 0;
3186
3187         return err;
3188 }
3189
3190 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
3191                                   bool on)
3192 {
3193         int lane;
3194         int err;
3195
3196         lane = mv88e6xxx_serdes_get_lane(chip, port);
3197         if (lane < 0)
3198                 return 0;
3199
3200         if (on) {
3201                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
3202                 if (err)
3203                         return err;
3204
3205                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
3206         } else {
3207                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
3208                 if (err)
3209                         return err;
3210
3211                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
3212         }
3213
3214         return err;
3215 }
3216
3217 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3218                                      enum mv88e6xxx_egress_direction direction,
3219                                      int port)
3220 {
3221         int err;
3222
3223         if (!chip->info->ops->set_egress_port)
3224                 return -EOPNOTSUPP;
3225
3226         err = chip->info->ops->set_egress_port(chip, direction, port);
3227         if (err)
3228                 return err;
3229
3230         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3231                 chip->ingress_dest_port = port;
3232         else
3233                 chip->egress_dest_port = port;
3234
3235         return 0;
3236 }
3237
3238 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3239 {
3240         struct dsa_switch *ds = chip->ds;
3241         int upstream_port;
3242         int err;
3243
3244         upstream_port = dsa_upstream_port(ds, port);
3245         if (chip->info->ops->port_set_upstream_port) {
3246                 err = chip->info->ops->port_set_upstream_port(chip, port,
3247                                                               upstream_port);
3248                 if (err)
3249                         return err;
3250         }
3251
3252         if (port == upstream_port) {
3253                 if (chip->info->ops->set_cpu_port) {
3254                         err = chip->info->ops->set_cpu_port(chip,
3255                                                             upstream_port);
3256                         if (err)
3257                                 return err;
3258                 }
3259
3260                 err = mv88e6xxx_set_egress_port(chip,
3261                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
3262                                                 upstream_port);
3263                 if (err && err != -EOPNOTSUPP)
3264                         return err;
3265
3266                 err = mv88e6xxx_set_egress_port(chip,
3267                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
3268                                                 upstream_port);
3269                 if (err && err != -EOPNOTSUPP)
3270                         return err;
3271         }
3272
3273         return 0;
3274 }
3275
3276 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3277 {
3278         struct device_node *phy_handle = NULL;
3279         struct dsa_switch *ds = chip->ds;
3280         phy_interface_t mode;
3281         struct dsa_port *dp;
3282         int tx_amp, speed;
3283         int err;
3284         u16 reg;
3285
3286         chip->ports[port].chip = chip;
3287         chip->ports[port].port = port;
3288
3289         dp = dsa_to_port(ds, port);
3290
3291         /* MAC Forcing register: don't force link, speed, duplex or flow control
3292          * state to any particular values on physical ports, but force the CPU
3293          * port and all DSA ports to their maximum bandwidth and full duplex.
3294          */
3295         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
3296                 unsigned long caps = dp->pl_config.mac_capabilities;
3297
3298                 if (chip->info->ops->port_max_speed_mode)
3299                         mode = chip->info->ops->port_max_speed_mode(port);
3300                 else
3301                         mode = PHY_INTERFACE_MODE_NA;
3302
3303                 if (caps & MAC_10000FD)
3304                         speed = SPEED_10000;
3305                 else if (caps & MAC_5000FD)
3306                         speed = SPEED_5000;
3307                 else if (caps & MAC_2500FD)
3308                         speed = SPEED_2500;
3309                 else if (caps & MAC_1000)
3310                         speed = SPEED_1000;
3311                 else if (caps & MAC_100)
3312                         speed = SPEED_100;
3313                 else
3314                         speed = SPEED_10;
3315
3316                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
3317                                                speed, DUPLEX_FULL,
3318                                                PAUSE_OFF, mode);
3319         } else {
3320                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3321                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
3322                                                PAUSE_ON,
3323                                                PHY_INTERFACE_MODE_NA);
3324         }
3325         if (err)
3326                 return err;
3327
3328         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3329          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3330          * tunneling, determine priority by looking at 802.1p and IP
3331          * priority fields (IP prio has precedence), and set STP state
3332          * to Forwarding.
3333          *
3334          * If this is the CPU link, use DSA or EDSA tagging depending
3335          * on which tagging mode was configured.
3336          *
3337          * If this is a link to another switch, use DSA tagging mode.
3338          *
3339          * If this is the upstream port for this switch, enable
3340          * forwarding of unknown unicasts and multicasts.
3341          */
3342         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
3343                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3344                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3345         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3346         if (err)
3347                 return err;
3348
3349         err = mv88e6xxx_setup_port_mode(chip, port);
3350         if (err)
3351                 return err;
3352
3353         err = mv88e6xxx_setup_egress_floods(chip, port);
3354         if (err)
3355                 return err;
3356
3357         /* Port Control 2: don't force a good FCS, set the MTU size to
3358          * 10222 bytes, disable 802.1q tags checking, don't discard
3359          * tagged or untagged frames on this port, skip destination
3360          * address lookup on user ports, disable ARP mirroring and don't
3361          * send a copy of all transmitted/received frames on this port
3362          * to the CPU.
3363          */
3364         err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3365         if (err)
3366                 return err;
3367
3368         err = mv88e6xxx_setup_upstream_port(chip, port);
3369         if (err)
3370                 return err;
3371
3372         /* On chips that support it, set all downstream DSA ports'
3373          * VLAN policy to TRAP. In combination with loading
3374          * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3375          * provides a better isolation barrier between standalone
3376          * ports, as the ATU is bypassed on any intermediate switches
3377          * between the incoming port and the CPU.
3378          */
3379         if (dsa_is_downstream_port(ds, port) &&
3380             chip->info->ops->port_set_policy) {
3381                 err = chip->info->ops->port_set_policy(chip, port,
3382                                                 MV88E6XXX_POLICY_MAPPING_VTU,
3383                                                 MV88E6XXX_POLICY_ACTION_TRAP);
3384                 if (err)
3385                         return err;
3386         }
3387
3388         /* User ports start out in standalone mode and 802.1Q is
3389          * therefore disabled. On DSA ports, all valid VIDs are always
3390          * loaded in the VTU - therefore, enable 802.1Q in order to take
3391          * advantage of VLAN policy on chips that supports it.
3392          */
3393         err = mv88e6xxx_port_set_8021q_mode(chip, port,
3394                                 dsa_is_user_port(ds, port) ?
3395                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3396                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3397         if (err)
3398                 return err;
3399
3400         /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3401          * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3402          * the first free FID. This will be used as the private PVID for
3403          * unbridged ports. Shared (DSA and CPU) ports must also be
3404          * members of this VID, in order to trap all frames assigned to
3405          * it to the CPU.
3406          */
3407         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3408                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3409                                        false);
3410         if (err)
3411                 return err;
3412
3413         /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3414          * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3415          * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3416          * as the private PVID on ports under a VLAN-unaware bridge.
3417          * Shared (DSA and CPU) ports must also be members of it, to translate
3418          * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3419          * relying on their port default FID.
3420          */
3421         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3422                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3423                                        false);
3424         if (err)
3425                 return err;
3426
3427         if (chip->info->ops->port_set_jumbo_size) {
3428                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3429                 if (err)
3430                         return err;
3431         }
3432
3433         /* Port Association Vector: disable automatic address learning
3434          * on all user ports since they start out in standalone
3435          * mode. When joining a bridge, learning will be configured to
3436          * match the bridge port settings. Enable learning on all
3437          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3438          * learning process.
3439          *
3440          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3441          * and RefreshLocked. I.e. setup standard automatic learning.
3442          */
3443         if (dsa_is_user_port(ds, port))
3444                 reg = 0;
3445         else
3446                 reg = 1 << port;
3447
3448         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3449                                    reg);
3450         if (err)
3451                 return err;
3452
3453         /* Egress rate control 2: disable egress rate control. */
3454         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3455                                    0x0000);
3456         if (err)
3457                 return err;
3458
3459         if (chip->info->ops->port_pause_limit) {
3460                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3461                 if (err)
3462                         return err;
3463         }
3464
3465         if (chip->info->ops->port_disable_learn_limit) {
3466                 err = chip->info->ops->port_disable_learn_limit(chip, port);
3467                 if (err)
3468                         return err;
3469         }
3470
3471         if (chip->info->ops->port_disable_pri_override) {
3472                 err = chip->info->ops->port_disable_pri_override(chip, port);
3473                 if (err)
3474                         return err;
3475         }
3476
3477         if (chip->info->ops->port_tag_remap) {
3478                 err = chip->info->ops->port_tag_remap(chip, port);
3479                 if (err)
3480                         return err;
3481         }
3482
3483         if (chip->info->ops->port_egress_rate_limiting) {
3484                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3485                 if (err)
3486                         return err;
3487         }
3488
3489         if (chip->info->ops->port_setup_message_port) {
3490                 err = chip->info->ops->port_setup_message_port(chip, port);
3491                 if (err)
3492                         return err;
3493         }
3494
3495         if (chip->info->ops->serdes_set_tx_amplitude) {
3496                 if (dp)
3497                         phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3498
3499                 if (phy_handle && !of_property_read_u32(phy_handle,
3500                                                         "tx-p2p-microvolt",
3501                                                         &tx_amp))
3502                         err = chip->info->ops->serdes_set_tx_amplitude(chip,
3503                                                                 port, tx_amp);
3504                 if (phy_handle) {
3505                         of_node_put(phy_handle);
3506                         if (err)
3507                                 return err;
3508                 }
3509         }
3510
3511         /* Port based VLAN map: give each port the same default address
3512          * database, and allow bidirectional communication between the
3513          * CPU and DSA port(s), and the other ports.
3514          */
3515         err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3516         if (err)
3517                 return err;
3518
3519         err = mv88e6xxx_port_vlan_map(chip, port);
3520         if (err)
3521                 return err;
3522
3523         /* Default VLAN ID and priority: don't set a default VLAN
3524          * ID, and set the default packet priority to zero.
3525          */
3526         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3527 }
3528
3529 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3530 {
3531         struct mv88e6xxx_chip *chip = ds->priv;
3532
3533         if (chip->info->ops->port_set_jumbo_size)
3534                 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3535         else if (chip->info->ops->set_max_frame_size)
3536                 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3537         return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3538 }
3539
3540 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3541 {
3542         struct mv88e6xxx_chip *chip = ds->priv;
3543         int ret = 0;
3544
3545         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3546                 new_mtu += EDSA_HLEN;
3547
3548         mv88e6xxx_reg_lock(chip);
3549         if (chip->info->ops->port_set_jumbo_size)
3550                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3551         else if (chip->info->ops->set_max_frame_size)
3552                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3553         else
3554                 if (new_mtu > 1522)
3555                         ret = -EINVAL;
3556         mv88e6xxx_reg_unlock(chip);
3557
3558         return ret;
3559 }
3560
3561 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3562                                  struct phy_device *phydev)
3563 {
3564         struct mv88e6xxx_chip *chip = ds->priv;
3565         int err;
3566
3567         mv88e6xxx_reg_lock(chip);
3568         err = mv88e6xxx_serdes_power(chip, port, true);
3569         mv88e6xxx_reg_unlock(chip);
3570
3571         return err;
3572 }
3573
3574 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3575 {
3576         struct mv88e6xxx_chip *chip = ds->priv;
3577
3578         mv88e6xxx_reg_lock(chip);
3579         if (mv88e6xxx_serdes_power(chip, port, false))
3580                 dev_err(chip->dev, "failed to power off SERDES\n");
3581         mv88e6xxx_reg_unlock(chip);
3582 }
3583
3584 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3585                                      unsigned int ageing_time)
3586 {
3587         struct mv88e6xxx_chip *chip = ds->priv;
3588         int err;
3589
3590         mv88e6xxx_reg_lock(chip);
3591         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3592         mv88e6xxx_reg_unlock(chip);
3593
3594         return err;
3595 }
3596
3597 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3598 {
3599         int err;
3600
3601         /* Initialize the statistics unit */
3602         if (chip->info->ops->stats_set_histogram) {
3603                 err = chip->info->ops->stats_set_histogram(chip);
3604                 if (err)
3605                         return err;
3606         }
3607
3608         return mv88e6xxx_g1_stats_clear(chip);
3609 }
3610
3611 /* Check if the errata has already been applied. */
3612 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3613 {
3614         int port;
3615         int err;
3616         u16 val;
3617
3618         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3619                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3620                 if (err) {
3621                         dev_err(chip->dev,
3622                                 "Error reading hidden register: %d\n", err);
3623                         return false;
3624                 }
3625                 if (val != 0x01c0)
3626                         return false;
3627         }
3628
3629         return true;
3630 }
3631
3632 /* The 6390 copper ports have an errata which require poking magic
3633  * values into undocumented hidden registers and then performing a
3634  * software reset.
3635  */
3636 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3637 {
3638         int port;
3639         int err;
3640
3641         if (mv88e6390_setup_errata_applied(chip))
3642                 return 0;
3643
3644         /* Set the ports into blocking mode */
3645         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3646                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3647                 if (err)
3648                         return err;
3649         }
3650
3651         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3652                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3653                 if (err)
3654                         return err;
3655         }
3656
3657         return mv88e6xxx_software_reset(chip);
3658 }
3659
3660 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3661 {
3662         mv88e6xxx_teardown_devlink_params(ds);
3663         dsa_devlink_resources_unregister(ds);
3664         mv88e6xxx_teardown_devlink_regions_global(ds);
3665 }
3666
3667 static int mv88e6xxx_setup(struct dsa_switch *ds)
3668 {
3669         struct mv88e6xxx_chip *chip = ds->priv;
3670         u8 cmode;
3671         int err;
3672         int i;
3673
3674         chip->ds = ds;
3675         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3676
3677         /* Since virtual bridges are mapped in the PVT, the number we support
3678          * depends on the physical switch topology. We need to let DSA figure
3679          * that out and therefore we cannot set this at dsa_register_switch()
3680          * time.
3681          */
3682         if (mv88e6xxx_has_pvt(chip))
3683                 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3684                                       ds->dst->last_switch - 1;
3685
3686         mv88e6xxx_reg_lock(chip);
3687
3688         if (chip->info->ops->setup_errata) {
3689                 err = chip->info->ops->setup_errata(chip);
3690                 if (err)
3691                         goto unlock;
3692         }
3693
3694         /* Cache the cmode of each port. */
3695         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3696                 if (chip->info->ops->port_get_cmode) {
3697                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3698                         if (err)
3699                                 goto unlock;
3700
3701                         chip->ports[i].cmode = cmode;
3702                 }
3703         }
3704
3705         err = mv88e6xxx_vtu_setup(chip);
3706         if (err)
3707                 goto unlock;
3708
3709         /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3710          * VTU, thereby also flushing the STU).
3711          */
3712         err = mv88e6xxx_stu_setup(chip);
3713         if (err)
3714                 goto unlock;
3715
3716         /* Setup Switch Port Registers */
3717         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3718                 if (dsa_is_unused_port(ds, i))
3719                         continue;
3720
3721                 /* Prevent the use of an invalid port. */
3722                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3723                         dev_err(chip->dev, "port %d is invalid\n", i);
3724                         err = -EINVAL;
3725                         goto unlock;
3726                 }
3727
3728                 err = mv88e6xxx_setup_port(chip, i);
3729                 if (err)
3730                         goto unlock;
3731         }
3732
3733         err = mv88e6xxx_irl_setup(chip);
3734         if (err)
3735                 goto unlock;
3736
3737         err = mv88e6xxx_mac_setup(chip);
3738         if (err)
3739                 goto unlock;
3740
3741         err = mv88e6xxx_phy_setup(chip);
3742         if (err)
3743                 goto unlock;
3744
3745         err = mv88e6xxx_pvt_setup(chip);
3746         if (err)
3747                 goto unlock;
3748
3749         err = mv88e6xxx_atu_setup(chip);
3750         if (err)
3751                 goto unlock;
3752
3753         err = mv88e6xxx_broadcast_setup(chip, 0);
3754         if (err)
3755                 goto unlock;
3756
3757         err = mv88e6xxx_pot_setup(chip);
3758         if (err)
3759                 goto unlock;
3760
3761         err = mv88e6xxx_rmu_setup(chip);
3762         if (err)
3763                 goto unlock;
3764
3765         err = mv88e6xxx_rsvd2cpu_setup(chip);
3766         if (err)
3767                 goto unlock;
3768
3769         err = mv88e6xxx_trunk_setup(chip);
3770         if (err)
3771                 goto unlock;
3772
3773         err = mv88e6xxx_devmap_setup(chip);
3774         if (err)
3775                 goto unlock;
3776
3777         err = mv88e6xxx_pri_setup(chip);
3778         if (err)
3779                 goto unlock;
3780
3781         /* Setup PTP Hardware Clock and timestamping */
3782         if (chip->info->ptp_support) {
3783                 err = mv88e6xxx_ptp_setup(chip);
3784                 if (err)
3785                         goto unlock;
3786
3787                 err = mv88e6xxx_hwtstamp_setup(chip);
3788                 if (err)
3789                         goto unlock;
3790         }
3791
3792         err = mv88e6xxx_stats_setup(chip);
3793         if (err)
3794                 goto unlock;
3795
3796 unlock:
3797         mv88e6xxx_reg_unlock(chip);
3798
3799         if (err)
3800                 return err;
3801
3802         /* Have to be called without holding the register lock, since
3803          * they take the devlink lock, and we later take the locks in
3804          * the reverse order when getting/setting parameters or
3805          * resource occupancy.
3806          */
3807         err = mv88e6xxx_setup_devlink_resources(ds);
3808         if (err)
3809                 return err;
3810
3811         err = mv88e6xxx_setup_devlink_params(ds);
3812         if (err)
3813                 goto out_resources;
3814
3815         err = mv88e6xxx_setup_devlink_regions_global(ds);
3816         if (err)
3817                 goto out_params;
3818
3819         return 0;
3820
3821 out_params:
3822         mv88e6xxx_teardown_devlink_params(ds);
3823 out_resources:
3824         dsa_devlink_resources_unregister(ds);
3825
3826         return err;
3827 }
3828
3829 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3830 {
3831         return mv88e6xxx_setup_devlink_regions_port(ds, port);
3832 }
3833
3834 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3835 {
3836         mv88e6xxx_teardown_devlink_regions_port(ds, port);
3837 }
3838
3839 /* prod_id for switch families which do not have a PHY model number */
3840 static const u16 family_prod_id_table[] = {
3841         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3842         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3843         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3844 };
3845
3846 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3847 {
3848         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3849         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3850         u16 prod_id;
3851         u16 val;
3852         int err;
3853
3854         if (!chip->info->ops->phy_read)
3855                 return -EOPNOTSUPP;
3856
3857         mv88e6xxx_reg_lock(chip);
3858         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3859         mv88e6xxx_reg_unlock(chip);
3860
3861         /* Some internal PHYs don't have a model number. */
3862         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3863             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3864                 prod_id = family_prod_id_table[chip->info->family];
3865                 if (prod_id)
3866                         val |= prod_id >> 4;
3867         }
3868
3869         return err ? err : val;
3870 }
3871
3872 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3873 {
3874         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3875         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3876         int err;
3877
3878         if (!chip->info->ops->phy_write)
3879                 return -EOPNOTSUPP;
3880
3881         mv88e6xxx_reg_lock(chip);
3882         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3883         mv88e6xxx_reg_unlock(chip);
3884
3885         return err;
3886 }
3887
3888 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3889                                    struct device_node *np,
3890                                    bool external)
3891 {
3892         static int index;
3893         struct mv88e6xxx_mdio_bus *mdio_bus;
3894         struct mii_bus *bus;
3895         int err;
3896
3897         if (external) {
3898                 mv88e6xxx_reg_lock(chip);
3899                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3900                 mv88e6xxx_reg_unlock(chip);
3901
3902                 if (err)
3903                         return err;
3904         }
3905
3906         bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3907         if (!bus)
3908                 return -ENOMEM;
3909
3910         mdio_bus = bus->priv;
3911         mdio_bus->bus = bus;
3912         mdio_bus->chip = chip;
3913         INIT_LIST_HEAD(&mdio_bus->list);
3914         mdio_bus->external = external;
3915
3916         if (np) {
3917                 bus->name = np->full_name;
3918                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3919         } else {
3920                 bus->name = "mv88e6xxx SMI";
3921                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3922         }
3923
3924         bus->read = mv88e6xxx_mdio_read;
3925         bus->write = mv88e6xxx_mdio_write;
3926         bus->parent = chip->dev;
3927
3928         if (!external) {
3929                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3930                 if (err)
3931                         goto out;
3932         }
3933
3934         err = of_mdiobus_register(bus, np);
3935         if (err) {
3936                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3937                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3938                 goto out;
3939         }
3940
3941         if (external)
3942                 list_add_tail(&mdio_bus->list, &chip->mdios);
3943         else
3944                 list_add(&mdio_bus->list, &chip->mdios);
3945
3946         return 0;
3947
3948 out:
3949         mdiobus_free(bus);
3950         return err;
3951 }
3952
3953 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3954
3955 {
3956         struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3957         struct mii_bus *bus;
3958
3959         list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3960                 bus = mdio_bus->bus;
3961
3962                 if (!mdio_bus->external)
3963                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3964
3965                 mdiobus_unregister(bus);
3966                 mdiobus_free(bus);
3967         }
3968 }
3969
3970 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3971                                     struct device_node *np)
3972 {
3973         struct device_node *child;
3974         int err;
3975
3976         /* Always register one mdio bus for the internal/default mdio
3977          * bus. This maybe represented in the device tree, but is
3978          * optional.
3979          */
3980         child = of_get_child_by_name(np, "mdio");
3981         err = mv88e6xxx_mdio_register(chip, child, false);
3982         of_node_put(child);
3983         if (err)
3984                 return err;
3985
3986         /* Walk the device tree, and see if there are any other nodes
3987          * which say they are compatible with the external mdio
3988          * bus.
3989          */
3990         for_each_available_child_of_node(np, child) {
3991                 if (of_device_is_compatible(
3992                             child, "marvell,mv88e6xxx-mdio-external")) {
3993                         err = mv88e6xxx_mdio_register(chip, child, true);
3994                         if (err) {
3995                                 mv88e6xxx_mdios_unregister(chip);
3996                                 of_node_put(child);
3997                                 return err;
3998                         }
3999                 }
4000         }
4001
4002         return 0;
4003 }
4004
4005 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4006 {
4007         struct mv88e6xxx_chip *chip = ds->priv;
4008
4009         return chip->eeprom_len;
4010 }
4011
4012 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4013                                 struct ethtool_eeprom *eeprom, u8 *data)
4014 {
4015         struct mv88e6xxx_chip *chip = ds->priv;
4016         int err;
4017
4018         if (!chip->info->ops->get_eeprom)
4019                 return -EOPNOTSUPP;
4020
4021         mv88e6xxx_reg_lock(chip);
4022         err = chip->info->ops->get_eeprom(chip, eeprom, data);
4023         mv88e6xxx_reg_unlock(chip);
4024
4025         if (err)
4026                 return err;
4027
4028         eeprom->magic = 0xc3ec4951;
4029
4030         return 0;
4031 }
4032
4033 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4034                                 struct ethtool_eeprom *eeprom, u8 *data)
4035 {
4036         struct mv88e6xxx_chip *chip = ds->priv;
4037         int err;
4038
4039         if (!chip->info->ops->set_eeprom)
4040                 return -EOPNOTSUPP;
4041
4042         if (eeprom->magic != 0xc3ec4951)
4043                 return -EINVAL;
4044
4045         mv88e6xxx_reg_lock(chip);
4046         err = chip->info->ops->set_eeprom(chip, eeprom, data);
4047         mv88e6xxx_reg_unlock(chip);
4048
4049         return err;
4050 }
4051
4052 static const struct mv88e6xxx_ops mv88e6085_ops = {
4053         /* MV88E6XXX_FAMILY_6097 */
4054         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4055         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4056         .irl_init_all = mv88e6352_g2_irl_init_all,
4057         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4058         .phy_read = mv88e6185_phy_ppu_read,
4059         .phy_write = mv88e6185_phy_ppu_write,
4060         .port_set_link = mv88e6xxx_port_set_link,
4061         .port_sync_link = mv88e6xxx_port_sync_link,
4062         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4063         .port_tag_remap = mv88e6095_port_tag_remap,
4064         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4065         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4066         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4067         .port_set_ether_type = mv88e6351_port_set_ether_type,
4068         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4069         .port_pause_limit = mv88e6097_port_pause_limit,
4070         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4071         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4072         .port_get_cmode = mv88e6185_port_get_cmode,
4073         .port_setup_message_port = mv88e6xxx_setup_message_port,
4074         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4075         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4076         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4077         .stats_get_strings = mv88e6095_stats_get_strings,
4078         .stats_get_stats = mv88e6095_stats_get_stats,
4079         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4080         .set_egress_port = mv88e6095_g1_set_egress_port,
4081         .watchdog_ops = &mv88e6097_watchdog_ops,
4082         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4083         .pot_clear = mv88e6xxx_g2_pot_clear,
4084         .ppu_enable = mv88e6185_g1_ppu_enable,
4085         .ppu_disable = mv88e6185_g1_ppu_disable,
4086         .reset = mv88e6185_g1_reset,
4087         .rmu_disable = mv88e6085_g1_rmu_disable,
4088         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4089         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4090         .stu_getnext = mv88e6352_g1_stu_getnext,
4091         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4092         .phylink_get_caps = mv88e6185_phylink_get_caps,
4093         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4094 };
4095
4096 static const struct mv88e6xxx_ops mv88e6095_ops = {
4097         /* MV88E6XXX_FAMILY_6095 */
4098         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4099         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4100         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4101         .phy_read = mv88e6185_phy_ppu_read,
4102         .phy_write = mv88e6185_phy_ppu_write,
4103         .port_set_link = mv88e6xxx_port_set_link,
4104         .port_sync_link = mv88e6185_port_sync_link,
4105         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4106         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4107         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4108         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4109         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4110         .port_get_cmode = mv88e6185_port_get_cmode,
4111         .port_setup_message_port = mv88e6xxx_setup_message_port,
4112         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4113         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4114         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4115         .stats_get_strings = mv88e6095_stats_get_strings,
4116         .stats_get_stats = mv88e6095_stats_get_stats,
4117         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4118         .serdes_power = mv88e6185_serdes_power,
4119         .serdes_get_lane = mv88e6185_serdes_get_lane,
4120         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4121         .ppu_enable = mv88e6185_g1_ppu_enable,
4122         .ppu_disable = mv88e6185_g1_ppu_disable,
4123         .reset = mv88e6185_g1_reset,
4124         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4125         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4126         .phylink_get_caps = mv88e6095_phylink_get_caps,
4127         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4128 };
4129
4130 static const struct mv88e6xxx_ops mv88e6097_ops = {
4131         /* MV88E6XXX_FAMILY_6097 */
4132         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4133         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4134         .irl_init_all = mv88e6352_g2_irl_init_all,
4135         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4136         .phy_read = mv88e6xxx_g2_smi_phy_read,
4137         .phy_write = mv88e6xxx_g2_smi_phy_write,
4138         .port_set_link = mv88e6xxx_port_set_link,
4139         .port_sync_link = mv88e6185_port_sync_link,
4140         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4141         .port_tag_remap = mv88e6095_port_tag_remap,
4142         .port_set_policy = mv88e6352_port_set_policy,
4143         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4144         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4145         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4146         .port_set_ether_type = mv88e6351_port_set_ether_type,
4147         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4148         .port_pause_limit = mv88e6097_port_pause_limit,
4149         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4150         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4151         .port_get_cmode = mv88e6185_port_get_cmode,
4152         .port_setup_message_port = mv88e6xxx_setup_message_port,
4153         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4154         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4155         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4156         .stats_get_strings = mv88e6095_stats_get_strings,
4157         .stats_get_stats = mv88e6095_stats_get_stats,
4158         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4159         .set_egress_port = mv88e6095_g1_set_egress_port,
4160         .watchdog_ops = &mv88e6097_watchdog_ops,
4161         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4162         .serdes_power = mv88e6185_serdes_power,
4163         .serdes_get_lane = mv88e6185_serdes_get_lane,
4164         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4165         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4166         .serdes_irq_enable = mv88e6097_serdes_irq_enable,
4167         .serdes_irq_status = mv88e6097_serdes_irq_status,
4168         .pot_clear = mv88e6xxx_g2_pot_clear,
4169         .reset = mv88e6352_g1_reset,
4170         .rmu_disable = mv88e6085_g1_rmu_disable,
4171         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4172         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4173         .phylink_get_caps = mv88e6095_phylink_get_caps,
4174         .stu_getnext = mv88e6352_g1_stu_getnext,
4175         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4176         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4177 };
4178
4179 static const struct mv88e6xxx_ops mv88e6123_ops = {
4180         /* MV88E6XXX_FAMILY_6165 */
4181         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4182         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4183         .irl_init_all = mv88e6352_g2_irl_init_all,
4184         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4185         .phy_read = mv88e6xxx_g2_smi_phy_read,
4186         .phy_write = mv88e6xxx_g2_smi_phy_write,
4187         .port_set_link = mv88e6xxx_port_set_link,
4188         .port_sync_link = mv88e6xxx_port_sync_link,
4189         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4190         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4191         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4192         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4193         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4194         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4195         .port_get_cmode = mv88e6185_port_get_cmode,
4196         .port_setup_message_port = mv88e6xxx_setup_message_port,
4197         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4198         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4199         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4200         .stats_get_strings = mv88e6095_stats_get_strings,
4201         .stats_get_stats = mv88e6095_stats_get_stats,
4202         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4203         .set_egress_port = mv88e6095_g1_set_egress_port,
4204         .watchdog_ops = &mv88e6097_watchdog_ops,
4205         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4206         .pot_clear = mv88e6xxx_g2_pot_clear,
4207         .reset = mv88e6352_g1_reset,
4208         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4209         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4210         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4211         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4212         .stu_getnext = mv88e6352_g1_stu_getnext,
4213         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4214         .phylink_get_caps = mv88e6185_phylink_get_caps,
4215         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4216 };
4217
4218 static const struct mv88e6xxx_ops mv88e6131_ops = {
4219         /* MV88E6XXX_FAMILY_6185 */
4220         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4221         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4222         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4223         .phy_read = mv88e6185_phy_ppu_read,
4224         .phy_write = mv88e6185_phy_ppu_write,
4225         .port_set_link = mv88e6xxx_port_set_link,
4226         .port_sync_link = mv88e6xxx_port_sync_link,
4227         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4228         .port_tag_remap = mv88e6095_port_tag_remap,
4229         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4230         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4231         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4232         .port_set_ether_type = mv88e6351_port_set_ether_type,
4233         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4234         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4235         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4236         .port_pause_limit = mv88e6097_port_pause_limit,
4237         .port_set_pause = mv88e6185_port_set_pause,
4238         .port_get_cmode = mv88e6185_port_get_cmode,
4239         .port_setup_message_port = mv88e6xxx_setup_message_port,
4240         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4241         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4242         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4243         .stats_get_strings = mv88e6095_stats_get_strings,
4244         .stats_get_stats = mv88e6095_stats_get_stats,
4245         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4246         .set_egress_port = mv88e6095_g1_set_egress_port,
4247         .watchdog_ops = &mv88e6097_watchdog_ops,
4248         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4249         .ppu_enable = mv88e6185_g1_ppu_enable,
4250         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4251         .ppu_disable = mv88e6185_g1_ppu_disable,
4252         .reset = mv88e6185_g1_reset,
4253         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4254         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4255         .phylink_get_caps = mv88e6185_phylink_get_caps,
4256 };
4257
4258 static const struct mv88e6xxx_ops mv88e6141_ops = {
4259         /* MV88E6XXX_FAMILY_6341 */
4260         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4261         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4262         .irl_init_all = mv88e6352_g2_irl_init_all,
4263         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4264         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4265         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4266         .phy_read = mv88e6xxx_g2_smi_phy_read,
4267         .phy_write = mv88e6xxx_g2_smi_phy_write,
4268         .port_set_link = mv88e6xxx_port_set_link,
4269         .port_sync_link = mv88e6xxx_port_sync_link,
4270         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4271         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4272         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4273         .port_tag_remap = mv88e6095_port_tag_remap,
4274         .port_set_policy = mv88e6352_port_set_policy,
4275         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4276         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4277         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4278         .port_set_ether_type = mv88e6351_port_set_ether_type,
4279         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4280         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4281         .port_pause_limit = mv88e6097_port_pause_limit,
4282         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4283         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4284         .port_get_cmode = mv88e6352_port_get_cmode,
4285         .port_set_cmode = mv88e6341_port_set_cmode,
4286         .port_setup_message_port = mv88e6xxx_setup_message_port,
4287         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4288         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4289         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4290         .stats_get_strings = mv88e6320_stats_get_strings,
4291         .stats_get_stats = mv88e6390_stats_get_stats,
4292         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4293         .set_egress_port = mv88e6390_g1_set_egress_port,
4294         .watchdog_ops = &mv88e6390_watchdog_ops,
4295         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4296         .pot_clear = mv88e6xxx_g2_pot_clear,
4297         .reset = mv88e6352_g1_reset,
4298         .rmu_disable = mv88e6390_g1_rmu_disable,
4299         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4300         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4301         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4302         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4303         .stu_getnext = mv88e6352_g1_stu_getnext,
4304         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4305         .serdes_power = mv88e6390_serdes_power,
4306         .serdes_get_lane = mv88e6341_serdes_get_lane,
4307         /* Check status register pause & lpa register */
4308         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4309         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4310         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4311         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4312         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4313         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4314         .serdes_irq_status = mv88e6390_serdes_irq_status,
4315         .gpio_ops = &mv88e6352_gpio_ops,
4316         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4317         .serdes_get_strings = mv88e6390_serdes_get_strings,
4318         .serdes_get_stats = mv88e6390_serdes_get_stats,
4319         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4320         .serdes_get_regs = mv88e6390_serdes_get_regs,
4321         .phylink_get_caps = mv88e6341_phylink_get_caps,
4322 };
4323
4324 static const struct mv88e6xxx_ops mv88e6161_ops = {
4325         /* MV88E6XXX_FAMILY_6165 */
4326         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4327         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4328         .irl_init_all = mv88e6352_g2_irl_init_all,
4329         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4330         .phy_read = mv88e6xxx_g2_smi_phy_read,
4331         .phy_write = mv88e6xxx_g2_smi_phy_write,
4332         .port_set_link = mv88e6xxx_port_set_link,
4333         .port_sync_link = mv88e6xxx_port_sync_link,
4334         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4335         .port_tag_remap = mv88e6095_port_tag_remap,
4336         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4337         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4338         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4339         .port_set_ether_type = mv88e6351_port_set_ether_type,
4340         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4341         .port_pause_limit = mv88e6097_port_pause_limit,
4342         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4343         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4344         .port_get_cmode = mv88e6185_port_get_cmode,
4345         .port_setup_message_port = mv88e6xxx_setup_message_port,
4346         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4347         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4348         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4349         .stats_get_strings = mv88e6095_stats_get_strings,
4350         .stats_get_stats = mv88e6095_stats_get_stats,
4351         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4352         .set_egress_port = mv88e6095_g1_set_egress_port,
4353         .watchdog_ops = &mv88e6097_watchdog_ops,
4354         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4355         .pot_clear = mv88e6xxx_g2_pot_clear,
4356         .reset = mv88e6352_g1_reset,
4357         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4358         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4359         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4360         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4361         .stu_getnext = mv88e6352_g1_stu_getnext,
4362         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4363         .avb_ops = &mv88e6165_avb_ops,
4364         .ptp_ops = &mv88e6165_ptp_ops,
4365         .phylink_get_caps = mv88e6185_phylink_get_caps,
4366         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4367 };
4368
4369 static const struct mv88e6xxx_ops mv88e6165_ops = {
4370         /* MV88E6XXX_FAMILY_6165 */
4371         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4372         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4373         .irl_init_all = mv88e6352_g2_irl_init_all,
4374         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4375         .phy_read = mv88e6165_phy_read,
4376         .phy_write = mv88e6165_phy_write,
4377         .port_set_link = mv88e6xxx_port_set_link,
4378         .port_sync_link = mv88e6xxx_port_sync_link,
4379         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4380         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4381         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4382         .port_get_cmode = mv88e6185_port_get_cmode,
4383         .port_setup_message_port = mv88e6xxx_setup_message_port,
4384         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4385         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4386         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4387         .stats_get_strings = mv88e6095_stats_get_strings,
4388         .stats_get_stats = mv88e6095_stats_get_stats,
4389         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4390         .set_egress_port = mv88e6095_g1_set_egress_port,
4391         .watchdog_ops = &mv88e6097_watchdog_ops,
4392         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4393         .pot_clear = mv88e6xxx_g2_pot_clear,
4394         .reset = mv88e6352_g1_reset,
4395         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4396         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4397         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4398         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4399         .stu_getnext = mv88e6352_g1_stu_getnext,
4400         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4401         .avb_ops = &mv88e6165_avb_ops,
4402         .ptp_ops = &mv88e6165_ptp_ops,
4403         .phylink_get_caps = mv88e6185_phylink_get_caps,
4404 };
4405
4406 static const struct mv88e6xxx_ops mv88e6171_ops = {
4407         /* MV88E6XXX_FAMILY_6351 */
4408         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4409         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4410         .irl_init_all = mv88e6352_g2_irl_init_all,
4411         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4412         .phy_read = mv88e6xxx_g2_smi_phy_read,
4413         .phy_write = mv88e6xxx_g2_smi_phy_write,
4414         .port_set_link = mv88e6xxx_port_set_link,
4415         .port_sync_link = mv88e6xxx_port_sync_link,
4416         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4417         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4418         .port_tag_remap = mv88e6095_port_tag_remap,
4419         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4420         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4421         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4422         .port_set_ether_type = mv88e6351_port_set_ether_type,
4423         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4424         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4425         .port_pause_limit = mv88e6097_port_pause_limit,
4426         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4427         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4428         .port_get_cmode = mv88e6352_port_get_cmode,
4429         .port_setup_message_port = mv88e6xxx_setup_message_port,
4430         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4431         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4432         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4433         .stats_get_strings = mv88e6095_stats_get_strings,
4434         .stats_get_stats = mv88e6095_stats_get_stats,
4435         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4436         .set_egress_port = mv88e6095_g1_set_egress_port,
4437         .watchdog_ops = &mv88e6097_watchdog_ops,
4438         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4439         .pot_clear = mv88e6xxx_g2_pot_clear,
4440         .reset = mv88e6352_g1_reset,
4441         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4442         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4443         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4444         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4445         .stu_getnext = mv88e6352_g1_stu_getnext,
4446         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4447         .phylink_get_caps = mv88e6185_phylink_get_caps,
4448 };
4449
4450 static const struct mv88e6xxx_ops mv88e6172_ops = {
4451         /* MV88E6XXX_FAMILY_6352 */
4452         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4453         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4454         .irl_init_all = mv88e6352_g2_irl_init_all,
4455         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4456         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4457         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4458         .phy_read = mv88e6xxx_g2_smi_phy_read,
4459         .phy_write = mv88e6xxx_g2_smi_phy_write,
4460         .port_set_link = mv88e6xxx_port_set_link,
4461         .port_sync_link = mv88e6xxx_port_sync_link,
4462         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4463         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4464         .port_tag_remap = mv88e6095_port_tag_remap,
4465         .port_set_policy = mv88e6352_port_set_policy,
4466         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4467         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4468         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4469         .port_set_ether_type = mv88e6351_port_set_ether_type,
4470         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4471         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4472         .port_pause_limit = mv88e6097_port_pause_limit,
4473         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4474         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4475         .port_get_cmode = mv88e6352_port_get_cmode,
4476         .port_setup_message_port = mv88e6xxx_setup_message_port,
4477         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4478         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4479         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4480         .stats_get_strings = mv88e6095_stats_get_strings,
4481         .stats_get_stats = mv88e6095_stats_get_stats,
4482         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4483         .set_egress_port = mv88e6095_g1_set_egress_port,
4484         .watchdog_ops = &mv88e6097_watchdog_ops,
4485         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4486         .pot_clear = mv88e6xxx_g2_pot_clear,
4487         .reset = mv88e6352_g1_reset,
4488         .rmu_disable = mv88e6352_g1_rmu_disable,
4489         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4490         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4491         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4492         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4493         .stu_getnext = mv88e6352_g1_stu_getnext,
4494         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4495         .serdes_get_lane = mv88e6352_serdes_get_lane,
4496         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4497         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4498         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4499         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4500         .serdes_power = mv88e6352_serdes_power,
4501         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4502         .serdes_get_regs = mv88e6352_serdes_get_regs,
4503         .gpio_ops = &mv88e6352_gpio_ops,
4504         .phylink_get_caps = mv88e6352_phylink_get_caps,
4505 };
4506
4507 static const struct mv88e6xxx_ops mv88e6175_ops = {
4508         /* MV88E6XXX_FAMILY_6351 */
4509         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4510         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4511         .irl_init_all = mv88e6352_g2_irl_init_all,
4512         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4513         .phy_read = mv88e6xxx_g2_smi_phy_read,
4514         .phy_write = mv88e6xxx_g2_smi_phy_write,
4515         .port_set_link = mv88e6xxx_port_set_link,
4516         .port_sync_link = mv88e6xxx_port_sync_link,
4517         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4518         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4519         .port_tag_remap = mv88e6095_port_tag_remap,
4520         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4521         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4522         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4523         .port_set_ether_type = mv88e6351_port_set_ether_type,
4524         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4525         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4526         .port_pause_limit = mv88e6097_port_pause_limit,
4527         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4528         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4529         .port_get_cmode = mv88e6352_port_get_cmode,
4530         .port_setup_message_port = mv88e6xxx_setup_message_port,
4531         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4532         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4533         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4534         .stats_get_strings = mv88e6095_stats_get_strings,
4535         .stats_get_stats = mv88e6095_stats_get_stats,
4536         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4537         .set_egress_port = mv88e6095_g1_set_egress_port,
4538         .watchdog_ops = &mv88e6097_watchdog_ops,
4539         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4540         .pot_clear = mv88e6xxx_g2_pot_clear,
4541         .reset = mv88e6352_g1_reset,
4542         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4543         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4544         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4545         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4546         .stu_getnext = mv88e6352_g1_stu_getnext,
4547         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4548         .phylink_get_caps = mv88e6185_phylink_get_caps,
4549 };
4550
4551 static const struct mv88e6xxx_ops mv88e6176_ops = {
4552         /* MV88E6XXX_FAMILY_6352 */
4553         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4554         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4555         .irl_init_all = mv88e6352_g2_irl_init_all,
4556         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4557         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4558         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4559         .phy_read = mv88e6xxx_g2_smi_phy_read,
4560         .phy_write = mv88e6xxx_g2_smi_phy_write,
4561         .port_set_link = mv88e6xxx_port_set_link,
4562         .port_sync_link = mv88e6xxx_port_sync_link,
4563         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4564         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4565         .port_tag_remap = mv88e6095_port_tag_remap,
4566         .port_set_policy = mv88e6352_port_set_policy,
4567         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4568         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4569         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4570         .port_set_ether_type = mv88e6351_port_set_ether_type,
4571         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4572         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4573         .port_pause_limit = mv88e6097_port_pause_limit,
4574         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4575         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4576         .port_get_cmode = mv88e6352_port_get_cmode,
4577         .port_setup_message_port = mv88e6xxx_setup_message_port,
4578         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4579         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4580         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4581         .stats_get_strings = mv88e6095_stats_get_strings,
4582         .stats_get_stats = mv88e6095_stats_get_stats,
4583         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4584         .set_egress_port = mv88e6095_g1_set_egress_port,
4585         .watchdog_ops = &mv88e6097_watchdog_ops,
4586         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4587         .pot_clear = mv88e6xxx_g2_pot_clear,
4588         .reset = mv88e6352_g1_reset,
4589         .rmu_disable = mv88e6352_g1_rmu_disable,
4590         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4591         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4592         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4593         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4594         .stu_getnext = mv88e6352_g1_stu_getnext,
4595         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4596         .serdes_get_lane = mv88e6352_serdes_get_lane,
4597         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4598         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4599         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4600         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4601         .serdes_power = mv88e6352_serdes_power,
4602         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4603         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4604         .serdes_irq_status = mv88e6352_serdes_irq_status,
4605         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4606         .serdes_get_regs = mv88e6352_serdes_get_regs,
4607         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4608         .gpio_ops = &mv88e6352_gpio_ops,
4609         .phylink_get_caps = mv88e6352_phylink_get_caps,
4610 };
4611
4612 static const struct mv88e6xxx_ops mv88e6185_ops = {
4613         /* MV88E6XXX_FAMILY_6185 */
4614         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4615         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4616         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4617         .phy_read = mv88e6185_phy_ppu_read,
4618         .phy_write = mv88e6185_phy_ppu_write,
4619         .port_set_link = mv88e6xxx_port_set_link,
4620         .port_sync_link = mv88e6185_port_sync_link,
4621         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4622         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4623         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4624         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4625         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4626         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4627         .port_set_pause = mv88e6185_port_set_pause,
4628         .port_get_cmode = mv88e6185_port_get_cmode,
4629         .port_setup_message_port = mv88e6xxx_setup_message_port,
4630         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4631         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4632         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4633         .stats_get_strings = mv88e6095_stats_get_strings,
4634         .stats_get_stats = mv88e6095_stats_get_stats,
4635         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4636         .set_egress_port = mv88e6095_g1_set_egress_port,
4637         .watchdog_ops = &mv88e6097_watchdog_ops,
4638         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4639         .serdes_power = mv88e6185_serdes_power,
4640         .serdes_get_lane = mv88e6185_serdes_get_lane,
4641         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4642         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4643         .ppu_enable = mv88e6185_g1_ppu_enable,
4644         .ppu_disable = mv88e6185_g1_ppu_disable,
4645         .reset = mv88e6185_g1_reset,
4646         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4647         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4648         .phylink_get_caps = mv88e6185_phylink_get_caps,
4649         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4650 };
4651
4652 static const struct mv88e6xxx_ops mv88e6190_ops = {
4653         /* MV88E6XXX_FAMILY_6390 */
4654         .setup_errata = mv88e6390_setup_errata,
4655         .irl_init_all = mv88e6390_g2_irl_init_all,
4656         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4657         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4658         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4659         .phy_read = mv88e6xxx_g2_smi_phy_read,
4660         .phy_write = mv88e6xxx_g2_smi_phy_write,
4661         .port_set_link = mv88e6xxx_port_set_link,
4662         .port_sync_link = mv88e6xxx_port_sync_link,
4663         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4664         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4665         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4666         .port_tag_remap = mv88e6390_port_tag_remap,
4667         .port_set_policy = mv88e6352_port_set_policy,
4668         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4669         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4670         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4671         .port_set_ether_type = mv88e6351_port_set_ether_type,
4672         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4673         .port_pause_limit = mv88e6390_port_pause_limit,
4674         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4675         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4676         .port_get_cmode = mv88e6352_port_get_cmode,
4677         .port_set_cmode = mv88e6390_port_set_cmode,
4678         .port_setup_message_port = mv88e6xxx_setup_message_port,
4679         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4680         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4681         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4682         .stats_get_strings = mv88e6320_stats_get_strings,
4683         .stats_get_stats = mv88e6390_stats_get_stats,
4684         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4685         .set_egress_port = mv88e6390_g1_set_egress_port,
4686         .watchdog_ops = &mv88e6390_watchdog_ops,
4687         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4688         .pot_clear = mv88e6xxx_g2_pot_clear,
4689         .reset = mv88e6352_g1_reset,
4690         .rmu_disable = mv88e6390_g1_rmu_disable,
4691         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4692         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4693         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4694         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4695         .stu_getnext = mv88e6390_g1_stu_getnext,
4696         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4697         .serdes_power = mv88e6390_serdes_power,
4698         .serdes_get_lane = mv88e6390_serdes_get_lane,
4699         /* Check status register pause & lpa register */
4700         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4701         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4702         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4703         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4704         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4705         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4706         .serdes_irq_status = mv88e6390_serdes_irq_status,
4707         .serdes_get_strings = mv88e6390_serdes_get_strings,
4708         .serdes_get_stats = mv88e6390_serdes_get_stats,
4709         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4710         .serdes_get_regs = mv88e6390_serdes_get_regs,
4711         .gpio_ops = &mv88e6352_gpio_ops,
4712         .phylink_get_caps = mv88e6390_phylink_get_caps,
4713 };
4714
4715 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4716         /* MV88E6XXX_FAMILY_6390 */
4717         .setup_errata = mv88e6390_setup_errata,
4718         .irl_init_all = mv88e6390_g2_irl_init_all,
4719         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4720         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4721         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4722         .phy_read = mv88e6xxx_g2_smi_phy_read,
4723         .phy_write = mv88e6xxx_g2_smi_phy_write,
4724         .port_set_link = mv88e6xxx_port_set_link,
4725         .port_sync_link = mv88e6xxx_port_sync_link,
4726         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4727         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4728         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4729         .port_tag_remap = mv88e6390_port_tag_remap,
4730         .port_set_policy = mv88e6352_port_set_policy,
4731         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4732         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4733         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4734         .port_set_ether_type = mv88e6351_port_set_ether_type,
4735         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4736         .port_pause_limit = mv88e6390_port_pause_limit,
4737         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4738         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4739         .port_get_cmode = mv88e6352_port_get_cmode,
4740         .port_set_cmode = mv88e6390x_port_set_cmode,
4741         .port_setup_message_port = mv88e6xxx_setup_message_port,
4742         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4743         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4744         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4745         .stats_get_strings = mv88e6320_stats_get_strings,
4746         .stats_get_stats = mv88e6390_stats_get_stats,
4747         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4748         .set_egress_port = mv88e6390_g1_set_egress_port,
4749         .watchdog_ops = &mv88e6390_watchdog_ops,
4750         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4751         .pot_clear = mv88e6xxx_g2_pot_clear,
4752         .reset = mv88e6352_g1_reset,
4753         .rmu_disable = mv88e6390_g1_rmu_disable,
4754         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4755         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4756         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4757         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4758         .stu_getnext = mv88e6390_g1_stu_getnext,
4759         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4760         .serdes_power = mv88e6390_serdes_power,
4761         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4762         /* Check status register pause & lpa register */
4763         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4764         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4765         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4766         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4767         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4768         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4769         .serdes_irq_status = mv88e6390_serdes_irq_status,
4770         .serdes_get_strings = mv88e6390_serdes_get_strings,
4771         .serdes_get_stats = mv88e6390_serdes_get_stats,
4772         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4773         .serdes_get_regs = mv88e6390_serdes_get_regs,
4774         .gpio_ops = &mv88e6352_gpio_ops,
4775         .phylink_get_caps = mv88e6390x_phylink_get_caps,
4776 };
4777
4778 static const struct mv88e6xxx_ops mv88e6191_ops = {
4779         /* MV88E6XXX_FAMILY_6390 */
4780         .setup_errata = mv88e6390_setup_errata,
4781         .irl_init_all = mv88e6390_g2_irl_init_all,
4782         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4783         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4784         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4785         .phy_read = mv88e6xxx_g2_smi_phy_read,
4786         .phy_write = mv88e6xxx_g2_smi_phy_write,
4787         .port_set_link = mv88e6xxx_port_set_link,
4788         .port_sync_link = mv88e6xxx_port_sync_link,
4789         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4790         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4791         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4792         .port_tag_remap = mv88e6390_port_tag_remap,
4793         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4794         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4795         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4796         .port_set_ether_type = mv88e6351_port_set_ether_type,
4797         .port_pause_limit = mv88e6390_port_pause_limit,
4798         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4799         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4800         .port_get_cmode = mv88e6352_port_get_cmode,
4801         .port_set_cmode = mv88e6390_port_set_cmode,
4802         .port_setup_message_port = mv88e6xxx_setup_message_port,
4803         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4804         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4805         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4806         .stats_get_strings = mv88e6320_stats_get_strings,
4807         .stats_get_stats = mv88e6390_stats_get_stats,
4808         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4809         .set_egress_port = mv88e6390_g1_set_egress_port,
4810         .watchdog_ops = &mv88e6390_watchdog_ops,
4811         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4812         .pot_clear = mv88e6xxx_g2_pot_clear,
4813         .reset = mv88e6352_g1_reset,
4814         .rmu_disable = mv88e6390_g1_rmu_disable,
4815         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4816         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4817         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4818         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4819         .stu_getnext = mv88e6390_g1_stu_getnext,
4820         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4821         .serdes_power = mv88e6390_serdes_power,
4822         .serdes_get_lane = mv88e6390_serdes_get_lane,
4823         /* Check status register pause & lpa register */
4824         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4825         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4826         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4827         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4828         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4829         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4830         .serdes_irq_status = mv88e6390_serdes_irq_status,
4831         .serdes_get_strings = mv88e6390_serdes_get_strings,
4832         .serdes_get_stats = mv88e6390_serdes_get_stats,
4833         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4834         .serdes_get_regs = mv88e6390_serdes_get_regs,
4835         .avb_ops = &mv88e6390_avb_ops,
4836         .ptp_ops = &mv88e6352_ptp_ops,
4837         .phylink_get_caps = mv88e6390_phylink_get_caps,
4838 };
4839
4840 static const struct mv88e6xxx_ops mv88e6240_ops = {
4841         /* MV88E6XXX_FAMILY_6352 */
4842         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4843         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4844         .irl_init_all = mv88e6352_g2_irl_init_all,
4845         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4846         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4847         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4848         .phy_read = mv88e6xxx_g2_smi_phy_read,
4849         .phy_write = mv88e6xxx_g2_smi_phy_write,
4850         .port_set_link = mv88e6xxx_port_set_link,
4851         .port_sync_link = mv88e6xxx_port_sync_link,
4852         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4853         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4854         .port_tag_remap = mv88e6095_port_tag_remap,
4855         .port_set_policy = mv88e6352_port_set_policy,
4856         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4857         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4858         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4859         .port_set_ether_type = mv88e6351_port_set_ether_type,
4860         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4861         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4862         .port_pause_limit = mv88e6097_port_pause_limit,
4863         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4864         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4865         .port_get_cmode = mv88e6352_port_get_cmode,
4866         .port_setup_message_port = mv88e6xxx_setup_message_port,
4867         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4868         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4869         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4870         .stats_get_strings = mv88e6095_stats_get_strings,
4871         .stats_get_stats = mv88e6095_stats_get_stats,
4872         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4873         .set_egress_port = mv88e6095_g1_set_egress_port,
4874         .watchdog_ops = &mv88e6097_watchdog_ops,
4875         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4876         .pot_clear = mv88e6xxx_g2_pot_clear,
4877         .reset = mv88e6352_g1_reset,
4878         .rmu_disable = mv88e6352_g1_rmu_disable,
4879         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4880         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4881         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4882         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4883         .stu_getnext = mv88e6352_g1_stu_getnext,
4884         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4885         .serdes_get_lane = mv88e6352_serdes_get_lane,
4886         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4887         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4888         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4889         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4890         .serdes_power = mv88e6352_serdes_power,
4891         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4892         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4893         .serdes_irq_status = mv88e6352_serdes_irq_status,
4894         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4895         .serdes_get_regs = mv88e6352_serdes_get_regs,
4896         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4897         .gpio_ops = &mv88e6352_gpio_ops,
4898         .avb_ops = &mv88e6352_avb_ops,
4899         .ptp_ops = &mv88e6352_ptp_ops,
4900         .phylink_get_caps = mv88e6352_phylink_get_caps,
4901 };
4902
4903 static const struct mv88e6xxx_ops mv88e6250_ops = {
4904         /* MV88E6XXX_FAMILY_6250 */
4905         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4906         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4907         .irl_init_all = mv88e6352_g2_irl_init_all,
4908         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4909         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4910         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4911         .phy_read = mv88e6xxx_g2_smi_phy_read,
4912         .phy_write = mv88e6xxx_g2_smi_phy_write,
4913         .port_set_link = mv88e6xxx_port_set_link,
4914         .port_sync_link = mv88e6xxx_port_sync_link,
4915         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4916         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4917         .port_tag_remap = mv88e6095_port_tag_remap,
4918         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4919         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4920         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4921         .port_set_ether_type = mv88e6351_port_set_ether_type,
4922         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4923         .port_pause_limit = mv88e6097_port_pause_limit,
4924         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4925         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4926         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4927         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4928         .stats_get_strings = mv88e6250_stats_get_strings,
4929         .stats_get_stats = mv88e6250_stats_get_stats,
4930         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4931         .set_egress_port = mv88e6095_g1_set_egress_port,
4932         .watchdog_ops = &mv88e6250_watchdog_ops,
4933         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4934         .pot_clear = mv88e6xxx_g2_pot_clear,
4935         .reset = mv88e6250_g1_reset,
4936         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4937         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4938         .avb_ops = &mv88e6352_avb_ops,
4939         .ptp_ops = &mv88e6250_ptp_ops,
4940         .phylink_get_caps = mv88e6250_phylink_get_caps,
4941 };
4942
4943 static const struct mv88e6xxx_ops mv88e6290_ops = {
4944         /* MV88E6XXX_FAMILY_6390 */
4945         .setup_errata = mv88e6390_setup_errata,
4946         .irl_init_all = mv88e6390_g2_irl_init_all,
4947         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4948         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4949         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4950         .phy_read = mv88e6xxx_g2_smi_phy_read,
4951         .phy_write = mv88e6xxx_g2_smi_phy_write,
4952         .port_set_link = mv88e6xxx_port_set_link,
4953         .port_sync_link = mv88e6xxx_port_sync_link,
4954         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4955         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4956         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4957         .port_tag_remap = mv88e6390_port_tag_remap,
4958         .port_set_policy = mv88e6352_port_set_policy,
4959         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4960         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4961         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4962         .port_set_ether_type = mv88e6351_port_set_ether_type,
4963         .port_pause_limit = mv88e6390_port_pause_limit,
4964         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4965         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4966         .port_get_cmode = mv88e6352_port_get_cmode,
4967         .port_set_cmode = mv88e6390_port_set_cmode,
4968         .port_setup_message_port = mv88e6xxx_setup_message_port,
4969         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4970         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4971         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4972         .stats_get_strings = mv88e6320_stats_get_strings,
4973         .stats_get_stats = mv88e6390_stats_get_stats,
4974         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4975         .set_egress_port = mv88e6390_g1_set_egress_port,
4976         .watchdog_ops = &mv88e6390_watchdog_ops,
4977         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4978         .pot_clear = mv88e6xxx_g2_pot_clear,
4979         .reset = mv88e6352_g1_reset,
4980         .rmu_disable = mv88e6390_g1_rmu_disable,
4981         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4982         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4983         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4984         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4985         .stu_getnext = mv88e6390_g1_stu_getnext,
4986         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4987         .serdes_power = mv88e6390_serdes_power,
4988         .serdes_get_lane = mv88e6390_serdes_get_lane,
4989         /* Check status register pause & lpa register */
4990         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4991         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4992         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4993         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4994         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4995         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4996         .serdes_irq_status = mv88e6390_serdes_irq_status,
4997         .serdes_get_strings = mv88e6390_serdes_get_strings,
4998         .serdes_get_stats = mv88e6390_serdes_get_stats,
4999         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5000         .serdes_get_regs = mv88e6390_serdes_get_regs,
5001         .gpio_ops = &mv88e6352_gpio_ops,
5002         .avb_ops = &mv88e6390_avb_ops,
5003         .ptp_ops = &mv88e6352_ptp_ops,
5004         .phylink_get_caps = mv88e6390_phylink_get_caps,
5005 };
5006
5007 static const struct mv88e6xxx_ops mv88e6320_ops = {
5008         /* MV88E6XXX_FAMILY_6320 */
5009         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5010         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5011         .irl_init_all = mv88e6352_g2_irl_init_all,
5012         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5013         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5014         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5015         .phy_read = mv88e6xxx_g2_smi_phy_read,
5016         .phy_write = mv88e6xxx_g2_smi_phy_write,
5017         .port_set_link = mv88e6xxx_port_set_link,
5018         .port_sync_link = mv88e6xxx_port_sync_link,
5019         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5020         .port_tag_remap = mv88e6095_port_tag_remap,
5021         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5022         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5023         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5024         .port_set_ether_type = mv88e6351_port_set_ether_type,
5025         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5026         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5027         .port_pause_limit = mv88e6097_port_pause_limit,
5028         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5029         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5030         .port_get_cmode = mv88e6352_port_get_cmode,
5031         .port_setup_message_port = mv88e6xxx_setup_message_port,
5032         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5033         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5034         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5035         .stats_get_strings = mv88e6320_stats_get_strings,
5036         .stats_get_stats = mv88e6320_stats_get_stats,
5037         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5038         .set_egress_port = mv88e6095_g1_set_egress_port,
5039         .watchdog_ops = &mv88e6390_watchdog_ops,
5040         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5041         .pot_clear = mv88e6xxx_g2_pot_clear,
5042         .reset = mv88e6352_g1_reset,
5043         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5044         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5045         .gpio_ops = &mv88e6352_gpio_ops,
5046         .avb_ops = &mv88e6352_avb_ops,
5047         .ptp_ops = &mv88e6352_ptp_ops,
5048         .phylink_get_caps = mv88e6185_phylink_get_caps,
5049 };
5050
5051 static const struct mv88e6xxx_ops mv88e6321_ops = {
5052         /* MV88E6XXX_FAMILY_6320 */
5053         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5054         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5055         .irl_init_all = mv88e6352_g2_irl_init_all,
5056         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5057         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5058         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5059         .phy_read = mv88e6xxx_g2_smi_phy_read,
5060         .phy_write = mv88e6xxx_g2_smi_phy_write,
5061         .port_set_link = mv88e6xxx_port_set_link,
5062         .port_sync_link = mv88e6xxx_port_sync_link,
5063         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5064         .port_tag_remap = mv88e6095_port_tag_remap,
5065         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5066         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5067         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5068         .port_set_ether_type = mv88e6351_port_set_ether_type,
5069         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5070         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5071         .port_pause_limit = mv88e6097_port_pause_limit,
5072         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5073         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5074         .port_get_cmode = mv88e6352_port_get_cmode,
5075         .port_setup_message_port = mv88e6xxx_setup_message_port,
5076         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5077         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5078         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5079         .stats_get_strings = mv88e6320_stats_get_strings,
5080         .stats_get_stats = mv88e6320_stats_get_stats,
5081         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5082         .set_egress_port = mv88e6095_g1_set_egress_port,
5083         .watchdog_ops = &mv88e6390_watchdog_ops,
5084         .reset = mv88e6352_g1_reset,
5085         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5086         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5087         .gpio_ops = &mv88e6352_gpio_ops,
5088         .avb_ops = &mv88e6352_avb_ops,
5089         .ptp_ops = &mv88e6352_ptp_ops,
5090         .phylink_get_caps = mv88e6185_phylink_get_caps,
5091 };
5092
5093 static const struct mv88e6xxx_ops mv88e6341_ops = {
5094         /* MV88E6XXX_FAMILY_6341 */
5095         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5096         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5097         .irl_init_all = mv88e6352_g2_irl_init_all,
5098         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5099         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5100         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5101         .phy_read = mv88e6xxx_g2_smi_phy_read,
5102         .phy_write = mv88e6xxx_g2_smi_phy_write,
5103         .port_set_link = mv88e6xxx_port_set_link,
5104         .port_sync_link = mv88e6xxx_port_sync_link,
5105         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5106         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5107         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5108         .port_tag_remap = mv88e6095_port_tag_remap,
5109         .port_set_policy = mv88e6352_port_set_policy,
5110         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5111         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5112         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5113         .port_set_ether_type = mv88e6351_port_set_ether_type,
5114         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5115         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5116         .port_pause_limit = mv88e6097_port_pause_limit,
5117         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5118         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5119         .port_get_cmode = mv88e6352_port_get_cmode,
5120         .port_set_cmode = mv88e6341_port_set_cmode,
5121         .port_setup_message_port = mv88e6xxx_setup_message_port,
5122         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5123         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5124         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5125         .stats_get_strings = mv88e6320_stats_get_strings,
5126         .stats_get_stats = mv88e6390_stats_get_stats,
5127         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5128         .set_egress_port = mv88e6390_g1_set_egress_port,
5129         .watchdog_ops = &mv88e6390_watchdog_ops,
5130         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5131         .pot_clear = mv88e6xxx_g2_pot_clear,
5132         .reset = mv88e6352_g1_reset,
5133         .rmu_disable = mv88e6390_g1_rmu_disable,
5134         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5135         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5136         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5137         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5138         .stu_getnext = mv88e6352_g1_stu_getnext,
5139         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5140         .serdes_power = mv88e6390_serdes_power,
5141         .serdes_get_lane = mv88e6341_serdes_get_lane,
5142         /* Check status register pause & lpa register */
5143         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5144         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5145         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5146         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5147         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5148         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5149         .serdes_irq_status = mv88e6390_serdes_irq_status,
5150         .gpio_ops = &mv88e6352_gpio_ops,
5151         .avb_ops = &mv88e6390_avb_ops,
5152         .ptp_ops = &mv88e6352_ptp_ops,
5153         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5154         .serdes_get_strings = mv88e6390_serdes_get_strings,
5155         .serdes_get_stats = mv88e6390_serdes_get_stats,
5156         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5157         .serdes_get_regs = mv88e6390_serdes_get_regs,
5158         .phylink_get_caps = mv88e6341_phylink_get_caps,
5159 };
5160
5161 static const struct mv88e6xxx_ops mv88e6350_ops = {
5162         /* MV88E6XXX_FAMILY_6351 */
5163         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5164         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5165         .irl_init_all = mv88e6352_g2_irl_init_all,
5166         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5167         .phy_read = mv88e6xxx_g2_smi_phy_read,
5168         .phy_write = mv88e6xxx_g2_smi_phy_write,
5169         .port_set_link = mv88e6xxx_port_set_link,
5170         .port_sync_link = mv88e6xxx_port_sync_link,
5171         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5172         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5173         .port_tag_remap = mv88e6095_port_tag_remap,
5174         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5175         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5176         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5177         .port_set_ether_type = mv88e6351_port_set_ether_type,
5178         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5179         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5180         .port_pause_limit = mv88e6097_port_pause_limit,
5181         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5182         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5183         .port_get_cmode = mv88e6352_port_get_cmode,
5184         .port_setup_message_port = mv88e6xxx_setup_message_port,
5185         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5186         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5187         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5188         .stats_get_strings = mv88e6095_stats_get_strings,
5189         .stats_get_stats = mv88e6095_stats_get_stats,
5190         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5191         .set_egress_port = mv88e6095_g1_set_egress_port,
5192         .watchdog_ops = &mv88e6097_watchdog_ops,
5193         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5194         .pot_clear = mv88e6xxx_g2_pot_clear,
5195         .reset = mv88e6352_g1_reset,
5196         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5197         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5198         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5199         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5200         .stu_getnext = mv88e6352_g1_stu_getnext,
5201         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5202         .phylink_get_caps = mv88e6185_phylink_get_caps,
5203 };
5204
5205 static const struct mv88e6xxx_ops mv88e6351_ops = {
5206         /* MV88E6XXX_FAMILY_6351 */
5207         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5208         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5209         .irl_init_all = mv88e6352_g2_irl_init_all,
5210         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5211         .phy_read = mv88e6xxx_g2_smi_phy_read,
5212         .phy_write = mv88e6xxx_g2_smi_phy_write,
5213         .port_set_link = mv88e6xxx_port_set_link,
5214         .port_sync_link = mv88e6xxx_port_sync_link,
5215         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5216         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5217         .port_tag_remap = mv88e6095_port_tag_remap,
5218         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5219         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5220         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5221         .port_set_ether_type = mv88e6351_port_set_ether_type,
5222         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5223         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5224         .port_pause_limit = mv88e6097_port_pause_limit,
5225         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5226         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5227         .port_get_cmode = mv88e6352_port_get_cmode,
5228         .port_setup_message_port = mv88e6xxx_setup_message_port,
5229         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5230         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5231         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5232         .stats_get_strings = mv88e6095_stats_get_strings,
5233         .stats_get_stats = mv88e6095_stats_get_stats,
5234         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5235         .set_egress_port = mv88e6095_g1_set_egress_port,
5236         .watchdog_ops = &mv88e6097_watchdog_ops,
5237         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5238         .pot_clear = mv88e6xxx_g2_pot_clear,
5239         .reset = mv88e6352_g1_reset,
5240         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5241         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5242         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5243         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5244         .stu_getnext = mv88e6352_g1_stu_getnext,
5245         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5246         .avb_ops = &mv88e6352_avb_ops,
5247         .ptp_ops = &mv88e6352_ptp_ops,
5248         .phylink_get_caps = mv88e6185_phylink_get_caps,
5249 };
5250
5251 static const struct mv88e6xxx_ops mv88e6352_ops = {
5252         /* MV88E6XXX_FAMILY_6352 */
5253         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5254         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5255         .irl_init_all = mv88e6352_g2_irl_init_all,
5256         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5257         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5258         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5259         .phy_read = mv88e6xxx_g2_smi_phy_read,
5260         .phy_write = mv88e6xxx_g2_smi_phy_write,
5261         .port_set_link = mv88e6xxx_port_set_link,
5262         .port_sync_link = mv88e6xxx_port_sync_link,
5263         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5264         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5265         .port_tag_remap = mv88e6095_port_tag_remap,
5266         .port_set_policy = mv88e6352_port_set_policy,
5267         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5268         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5269         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5270         .port_set_ether_type = mv88e6351_port_set_ether_type,
5271         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5272         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5273         .port_pause_limit = mv88e6097_port_pause_limit,
5274         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5275         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5276         .port_get_cmode = mv88e6352_port_get_cmode,
5277         .port_setup_message_port = mv88e6xxx_setup_message_port,
5278         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5279         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5280         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5281         .stats_get_strings = mv88e6095_stats_get_strings,
5282         .stats_get_stats = mv88e6095_stats_get_stats,
5283         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5284         .set_egress_port = mv88e6095_g1_set_egress_port,
5285         .watchdog_ops = &mv88e6097_watchdog_ops,
5286         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5287         .pot_clear = mv88e6xxx_g2_pot_clear,
5288         .reset = mv88e6352_g1_reset,
5289         .rmu_disable = mv88e6352_g1_rmu_disable,
5290         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5291         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5292         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5293         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5294         .stu_getnext = mv88e6352_g1_stu_getnext,
5295         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5296         .serdes_get_lane = mv88e6352_serdes_get_lane,
5297         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
5298         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
5299         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
5300         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
5301         .serdes_power = mv88e6352_serdes_power,
5302         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5303         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
5304         .serdes_irq_status = mv88e6352_serdes_irq_status,
5305         .gpio_ops = &mv88e6352_gpio_ops,
5306         .avb_ops = &mv88e6352_avb_ops,
5307         .ptp_ops = &mv88e6352_ptp_ops,
5308         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5309         .serdes_get_strings = mv88e6352_serdes_get_strings,
5310         .serdes_get_stats = mv88e6352_serdes_get_stats,
5311         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5312         .serdes_get_regs = mv88e6352_serdes_get_regs,
5313         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5314         .phylink_get_caps = mv88e6352_phylink_get_caps,
5315 };
5316
5317 static const struct mv88e6xxx_ops mv88e6390_ops = {
5318         /* MV88E6XXX_FAMILY_6390 */
5319         .setup_errata = mv88e6390_setup_errata,
5320         .irl_init_all = mv88e6390_g2_irl_init_all,
5321         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5322         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5323         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5324         .phy_read = mv88e6xxx_g2_smi_phy_read,
5325         .phy_write = mv88e6xxx_g2_smi_phy_write,
5326         .port_set_link = mv88e6xxx_port_set_link,
5327         .port_sync_link = mv88e6xxx_port_sync_link,
5328         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5329         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5330         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5331         .port_tag_remap = mv88e6390_port_tag_remap,
5332         .port_set_policy = mv88e6352_port_set_policy,
5333         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5334         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5335         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5336         .port_set_ether_type = mv88e6351_port_set_ether_type,
5337         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5338         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5339         .port_pause_limit = mv88e6390_port_pause_limit,
5340         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5341         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5342         .port_get_cmode = mv88e6352_port_get_cmode,
5343         .port_set_cmode = mv88e6390_port_set_cmode,
5344         .port_setup_message_port = mv88e6xxx_setup_message_port,
5345         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5346         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5347         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5348         .stats_get_strings = mv88e6320_stats_get_strings,
5349         .stats_get_stats = mv88e6390_stats_get_stats,
5350         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5351         .set_egress_port = mv88e6390_g1_set_egress_port,
5352         .watchdog_ops = &mv88e6390_watchdog_ops,
5353         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5354         .pot_clear = mv88e6xxx_g2_pot_clear,
5355         .reset = mv88e6352_g1_reset,
5356         .rmu_disable = mv88e6390_g1_rmu_disable,
5357         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5358         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5359         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5360         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5361         .stu_getnext = mv88e6390_g1_stu_getnext,
5362         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5363         .serdes_power = mv88e6390_serdes_power,
5364         .serdes_get_lane = mv88e6390_serdes_get_lane,
5365         /* Check status register pause & lpa register */
5366         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5367         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5368         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5369         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5370         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5371         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5372         .serdes_irq_status = mv88e6390_serdes_irq_status,
5373         .gpio_ops = &mv88e6352_gpio_ops,
5374         .avb_ops = &mv88e6390_avb_ops,
5375         .ptp_ops = &mv88e6352_ptp_ops,
5376         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5377         .serdes_get_strings = mv88e6390_serdes_get_strings,
5378         .serdes_get_stats = mv88e6390_serdes_get_stats,
5379         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5380         .serdes_get_regs = mv88e6390_serdes_get_regs,
5381         .phylink_get_caps = mv88e6390_phylink_get_caps,
5382 };
5383
5384 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5385         /* MV88E6XXX_FAMILY_6390 */
5386         .setup_errata = mv88e6390_setup_errata,
5387         .irl_init_all = mv88e6390_g2_irl_init_all,
5388         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5389         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5390         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5391         .phy_read = mv88e6xxx_g2_smi_phy_read,
5392         .phy_write = mv88e6xxx_g2_smi_phy_write,
5393         .port_set_link = mv88e6xxx_port_set_link,
5394         .port_sync_link = mv88e6xxx_port_sync_link,
5395         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5396         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5397         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5398         .port_tag_remap = mv88e6390_port_tag_remap,
5399         .port_set_policy = mv88e6352_port_set_policy,
5400         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5401         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5402         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5403         .port_set_ether_type = mv88e6351_port_set_ether_type,
5404         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5405         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5406         .port_pause_limit = mv88e6390_port_pause_limit,
5407         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5408         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5409         .port_get_cmode = mv88e6352_port_get_cmode,
5410         .port_set_cmode = mv88e6390x_port_set_cmode,
5411         .port_setup_message_port = mv88e6xxx_setup_message_port,
5412         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5413         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5414         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5415         .stats_get_strings = mv88e6320_stats_get_strings,
5416         .stats_get_stats = mv88e6390_stats_get_stats,
5417         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5418         .set_egress_port = mv88e6390_g1_set_egress_port,
5419         .watchdog_ops = &mv88e6390_watchdog_ops,
5420         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5421         .pot_clear = mv88e6xxx_g2_pot_clear,
5422         .reset = mv88e6352_g1_reset,
5423         .rmu_disable = mv88e6390_g1_rmu_disable,
5424         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5425         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5426         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5427         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5428         .stu_getnext = mv88e6390_g1_stu_getnext,
5429         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5430         .serdes_power = mv88e6390_serdes_power,
5431         .serdes_get_lane = mv88e6390x_serdes_get_lane,
5432         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5433         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5434         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5435         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5436         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5437         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5438         .serdes_irq_status = mv88e6390_serdes_irq_status,
5439         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5440         .serdes_get_strings = mv88e6390_serdes_get_strings,
5441         .serdes_get_stats = mv88e6390_serdes_get_stats,
5442         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5443         .serdes_get_regs = mv88e6390_serdes_get_regs,
5444         .gpio_ops = &mv88e6352_gpio_ops,
5445         .avb_ops = &mv88e6390_avb_ops,
5446         .ptp_ops = &mv88e6352_ptp_ops,
5447         .phylink_get_caps = mv88e6390x_phylink_get_caps,
5448 };
5449
5450 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5451         /* MV88E6XXX_FAMILY_6393 */
5452         .setup_errata = mv88e6393x_serdes_setup_errata,
5453         .irl_init_all = mv88e6390_g2_irl_init_all,
5454         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5455         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5456         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5457         .phy_read = mv88e6xxx_g2_smi_phy_read,
5458         .phy_write = mv88e6xxx_g2_smi_phy_write,
5459         .port_set_link = mv88e6xxx_port_set_link,
5460         .port_sync_link = mv88e6xxx_port_sync_link,
5461         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5462         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5463         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5464         .port_tag_remap = mv88e6390_port_tag_remap,
5465         .port_set_policy = mv88e6393x_port_set_policy,
5466         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5467         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5468         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5469         .port_set_ether_type = mv88e6393x_port_set_ether_type,
5470         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5471         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5472         .port_pause_limit = mv88e6390_port_pause_limit,
5473         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5474         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5475         .port_get_cmode = mv88e6352_port_get_cmode,
5476         .port_set_cmode = mv88e6393x_port_set_cmode,
5477         .port_setup_message_port = mv88e6xxx_setup_message_port,
5478         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5479         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5480         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5481         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5482         .stats_get_strings = mv88e6320_stats_get_strings,
5483         .stats_get_stats = mv88e6390_stats_get_stats,
5484         /* .set_cpu_port is missing because this family does not support a global
5485          * CPU port, only per port CPU port which is set via
5486          * .port_set_upstream_port method.
5487          */
5488         .set_egress_port = mv88e6393x_set_egress_port,
5489         .watchdog_ops = &mv88e6390_watchdog_ops,
5490         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5491         .pot_clear = mv88e6xxx_g2_pot_clear,
5492         .reset = mv88e6352_g1_reset,
5493         .rmu_disable = mv88e6390_g1_rmu_disable,
5494         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5495         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5496         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5497         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5498         .stu_getnext = mv88e6390_g1_stu_getnext,
5499         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5500         .serdes_power = mv88e6393x_serdes_power,
5501         .serdes_get_lane = mv88e6393x_serdes_get_lane,
5502         .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
5503         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5504         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5505         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5506         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5507         .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
5508         .serdes_irq_status = mv88e6393x_serdes_irq_status,
5509         /* TODO: serdes stats */
5510         .gpio_ops = &mv88e6352_gpio_ops,
5511         .avb_ops = &mv88e6390_avb_ops,
5512         .ptp_ops = &mv88e6352_ptp_ops,
5513         .phylink_get_caps = mv88e6393x_phylink_get_caps,
5514 };
5515
5516 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5517         [MV88E6085] = {
5518                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5519                 .family = MV88E6XXX_FAMILY_6097,
5520                 .name = "Marvell 88E6085",
5521                 .num_databases = 4096,
5522                 .num_macs = 8192,
5523                 .num_ports = 10,
5524                 .num_internal_phys = 5,
5525                 .max_vid = 4095,
5526                 .max_sid = 63,
5527                 .port_base_addr = 0x10,
5528                 .phy_base_addr = 0x0,
5529                 .global1_addr = 0x1b,
5530                 .global2_addr = 0x1c,
5531                 .age_time_coeff = 15000,
5532                 .g1_irqs = 8,
5533                 .g2_irqs = 10,
5534                 .atu_move_port_mask = 0xf,
5535                 .pvt = true,
5536                 .multi_chip = true,
5537                 .ops = &mv88e6085_ops,
5538         },
5539
5540         [MV88E6095] = {
5541                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5542                 .family = MV88E6XXX_FAMILY_6095,
5543                 .name = "Marvell 88E6095/88E6095F",
5544                 .num_databases = 256,
5545                 .num_macs = 8192,
5546                 .num_ports = 11,
5547                 .num_internal_phys = 0,
5548                 .max_vid = 4095,
5549                 .port_base_addr = 0x10,
5550                 .phy_base_addr = 0x0,
5551                 .global1_addr = 0x1b,
5552                 .global2_addr = 0x1c,
5553                 .age_time_coeff = 15000,
5554                 .g1_irqs = 8,
5555                 .atu_move_port_mask = 0xf,
5556                 .multi_chip = true,
5557                 .ops = &mv88e6095_ops,
5558         },
5559
5560         [MV88E6097] = {
5561                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5562                 .family = MV88E6XXX_FAMILY_6097,
5563                 .name = "Marvell 88E6097/88E6097F",
5564                 .num_databases = 4096,
5565                 .num_macs = 8192,
5566                 .num_ports = 11,
5567                 .num_internal_phys = 8,
5568                 .max_vid = 4095,
5569                 .max_sid = 63,
5570                 .port_base_addr = 0x10,
5571                 .phy_base_addr = 0x0,
5572                 .global1_addr = 0x1b,
5573                 .global2_addr = 0x1c,
5574                 .age_time_coeff = 15000,
5575                 .g1_irqs = 8,
5576                 .g2_irqs = 10,
5577                 .atu_move_port_mask = 0xf,
5578                 .pvt = true,
5579                 .multi_chip = true,
5580                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5581                 .ops = &mv88e6097_ops,
5582         },
5583
5584         [MV88E6123] = {
5585                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5586                 .family = MV88E6XXX_FAMILY_6165,
5587                 .name = "Marvell 88E6123",
5588                 .num_databases = 4096,
5589                 .num_macs = 1024,
5590                 .num_ports = 3,
5591                 .num_internal_phys = 5,
5592                 .max_vid = 4095,
5593                 .max_sid = 63,
5594                 .port_base_addr = 0x10,
5595                 .phy_base_addr = 0x0,
5596                 .global1_addr = 0x1b,
5597                 .global2_addr = 0x1c,
5598                 .age_time_coeff = 15000,
5599                 .g1_irqs = 9,
5600                 .g2_irqs = 10,
5601                 .atu_move_port_mask = 0xf,
5602                 .pvt = true,
5603                 .multi_chip = true,
5604                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5605                 .ops = &mv88e6123_ops,
5606         },
5607
5608         [MV88E6131] = {
5609                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5610                 .family = MV88E6XXX_FAMILY_6185,
5611                 .name = "Marvell 88E6131",
5612                 .num_databases = 256,
5613                 .num_macs = 8192,
5614                 .num_ports = 8,
5615                 .num_internal_phys = 0,
5616                 .max_vid = 4095,
5617                 .port_base_addr = 0x10,
5618                 .phy_base_addr = 0x0,
5619                 .global1_addr = 0x1b,
5620                 .global2_addr = 0x1c,
5621                 .age_time_coeff = 15000,
5622                 .g1_irqs = 9,
5623                 .atu_move_port_mask = 0xf,
5624                 .multi_chip = true,
5625                 .ops = &mv88e6131_ops,
5626         },
5627
5628         [MV88E6141] = {
5629                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5630                 .family = MV88E6XXX_FAMILY_6341,
5631                 .name = "Marvell 88E6141",
5632                 .num_databases = 4096,
5633                 .num_macs = 2048,
5634                 .num_ports = 6,
5635                 .num_internal_phys = 5,
5636                 .num_gpio = 11,
5637                 .max_vid = 4095,
5638                 .max_sid = 63,
5639                 .port_base_addr = 0x10,
5640                 .phy_base_addr = 0x10,
5641                 .global1_addr = 0x1b,
5642                 .global2_addr = 0x1c,
5643                 .age_time_coeff = 3750,
5644                 .atu_move_port_mask = 0x1f,
5645                 .g1_irqs = 9,
5646                 .g2_irqs = 10,
5647                 .pvt = true,
5648                 .multi_chip = true,
5649                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5650                 .ops = &mv88e6141_ops,
5651         },
5652
5653         [MV88E6161] = {
5654                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5655                 .family = MV88E6XXX_FAMILY_6165,
5656                 .name = "Marvell 88E6161",
5657                 .num_databases = 4096,
5658                 .num_macs = 1024,
5659                 .num_ports = 6,
5660                 .num_internal_phys = 5,
5661                 .max_vid = 4095,
5662                 .max_sid = 63,
5663                 .port_base_addr = 0x10,
5664                 .phy_base_addr = 0x0,
5665                 .global1_addr = 0x1b,
5666                 .global2_addr = 0x1c,
5667                 .age_time_coeff = 15000,
5668                 .g1_irqs = 9,
5669                 .g2_irqs = 10,
5670                 .atu_move_port_mask = 0xf,
5671                 .pvt = true,
5672                 .multi_chip = true,
5673                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5674                 .ptp_support = true,
5675                 .ops = &mv88e6161_ops,
5676         },
5677
5678         [MV88E6165] = {
5679                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5680                 .family = MV88E6XXX_FAMILY_6165,
5681                 .name = "Marvell 88E6165",
5682                 .num_databases = 4096,
5683                 .num_macs = 8192,
5684                 .num_ports = 6,
5685                 .num_internal_phys = 0,
5686                 .max_vid = 4095,
5687                 .max_sid = 63,
5688                 .port_base_addr = 0x10,
5689                 .phy_base_addr = 0x0,
5690                 .global1_addr = 0x1b,
5691                 .global2_addr = 0x1c,
5692                 .age_time_coeff = 15000,
5693                 .g1_irqs = 9,
5694                 .g2_irqs = 10,
5695                 .atu_move_port_mask = 0xf,
5696                 .pvt = true,
5697                 .multi_chip = true,
5698                 .ptp_support = true,
5699                 .ops = &mv88e6165_ops,
5700         },
5701
5702         [MV88E6171] = {
5703                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5704                 .family = MV88E6XXX_FAMILY_6351,
5705                 .name = "Marvell 88E6171",
5706                 .num_databases = 4096,
5707                 .num_macs = 8192,
5708                 .num_ports = 7,
5709                 .num_internal_phys = 5,
5710                 .max_vid = 4095,
5711                 .max_sid = 63,
5712                 .port_base_addr = 0x10,
5713                 .phy_base_addr = 0x0,
5714                 .global1_addr = 0x1b,
5715                 .global2_addr = 0x1c,
5716                 .age_time_coeff = 15000,
5717                 .g1_irqs = 9,
5718                 .g2_irqs = 10,
5719                 .atu_move_port_mask = 0xf,
5720                 .pvt = true,
5721                 .multi_chip = true,
5722                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5723                 .ops = &mv88e6171_ops,
5724         },
5725
5726         [MV88E6172] = {
5727                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5728                 .family = MV88E6XXX_FAMILY_6352,
5729                 .name = "Marvell 88E6172",
5730                 .num_databases = 4096,
5731                 .num_macs = 8192,
5732                 .num_ports = 7,
5733                 .num_internal_phys = 5,
5734                 .num_gpio = 15,
5735                 .max_vid = 4095,
5736                 .max_sid = 63,
5737                 .port_base_addr = 0x10,
5738                 .phy_base_addr = 0x0,
5739                 .global1_addr = 0x1b,
5740                 .global2_addr = 0x1c,
5741                 .age_time_coeff = 15000,
5742                 .g1_irqs = 9,
5743                 .g2_irqs = 10,
5744                 .atu_move_port_mask = 0xf,
5745                 .pvt = true,
5746                 .multi_chip = true,
5747                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5748                 .ops = &mv88e6172_ops,
5749         },
5750
5751         [MV88E6175] = {
5752                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5753                 .family = MV88E6XXX_FAMILY_6351,
5754                 .name = "Marvell 88E6175",
5755                 .num_databases = 4096,
5756                 .num_macs = 8192,
5757                 .num_ports = 7,
5758                 .num_internal_phys = 5,
5759                 .max_vid = 4095,
5760                 .max_sid = 63,
5761                 .port_base_addr = 0x10,
5762                 .phy_base_addr = 0x0,
5763                 .global1_addr = 0x1b,
5764                 .global2_addr = 0x1c,
5765                 .age_time_coeff = 15000,
5766                 .g1_irqs = 9,
5767                 .g2_irqs = 10,
5768                 .atu_move_port_mask = 0xf,
5769                 .pvt = true,
5770                 .multi_chip = true,
5771                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5772                 .ops = &mv88e6175_ops,
5773         },
5774
5775         [MV88E6176] = {
5776                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5777                 .family = MV88E6XXX_FAMILY_6352,
5778                 .name = "Marvell 88E6176",
5779                 .num_databases = 4096,
5780                 .num_macs = 8192,
5781                 .num_ports = 7,
5782                 .num_internal_phys = 5,
5783                 .num_gpio = 15,
5784                 .max_vid = 4095,
5785                 .max_sid = 63,
5786                 .port_base_addr = 0x10,
5787                 .phy_base_addr = 0x0,
5788                 .global1_addr = 0x1b,
5789                 .global2_addr = 0x1c,
5790                 .age_time_coeff = 15000,
5791                 .g1_irqs = 9,
5792                 .g2_irqs = 10,
5793                 .atu_move_port_mask = 0xf,
5794                 .pvt = true,
5795                 .multi_chip = true,
5796                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5797                 .ops = &mv88e6176_ops,
5798         },
5799
5800         [MV88E6185] = {
5801                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5802                 .family = MV88E6XXX_FAMILY_6185,
5803                 .name = "Marvell 88E6185",
5804                 .num_databases = 256,
5805                 .num_macs = 8192,
5806                 .num_ports = 10,
5807                 .num_internal_phys = 0,
5808                 .max_vid = 4095,
5809                 .port_base_addr = 0x10,
5810                 .phy_base_addr = 0x0,
5811                 .global1_addr = 0x1b,
5812                 .global2_addr = 0x1c,
5813                 .age_time_coeff = 15000,
5814                 .g1_irqs = 8,
5815                 .atu_move_port_mask = 0xf,
5816                 .multi_chip = true,
5817                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5818                 .ops = &mv88e6185_ops,
5819         },
5820
5821         [MV88E6190] = {
5822                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5823                 .family = MV88E6XXX_FAMILY_6390,
5824                 .name = "Marvell 88E6190",
5825                 .num_databases = 4096,
5826                 .num_macs = 16384,
5827                 .num_ports = 11,        /* 10 + Z80 */
5828                 .num_internal_phys = 9,
5829                 .num_gpio = 16,
5830                 .max_vid = 8191,
5831                 .max_sid = 63,
5832                 .port_base_addr = 0x0,
5833                 .phy_base_addr = 0x0,
5834                 .global1_addr = 0x1b,
5835                 .global2_addr = 0x1c,
5836                 .age_time_coeff = 3750,
5837                 .g1_irqs = 9,
5838                 .g2_irqs = 14,
5839                 .pvt = true,
5840                 .multi_chip = true,
5841                 .atu_move_port_mask = 0x1f,
5842                 .ops = &mv88e6190_ops,
5843         },
5844
5845         [MV88E6190X] = {
5846                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5847                 .family = MV88E6XXX_FAMILY_6390,
5848                 .name = "Marvell 88E6190X",
5849                 .num_databases = 4096,
5850                 .num_macs = 16384,
5851                 .num_ports = 11,        /* 10 + Z80 */
5852                 .num_internal_phys = 9,
5853                 .num_gpio = 16,
5854                 .max_vid = 8191,
5855                 .max_sid = 63,
5856                 .port_base_addr = 0x0,
5857                 .phy_base_addr = 0x0,
5858                 .global1_addr = 0x1b,
5859                 .global2_addr = 0x1c,
5860                 .age_time_coeff = 3750,
5861                 .g1_irqs = 9,
5862                 .g2_irqs = 14,
5863                 .atu_move_port_mask = 0x1f,
5864                 .pvt = true,
5865                 .multi_chip = true,
5866                 .ops = &mv88e6190x_ops,
5867         },
5868
5869         [MV88E6191] = {
5870                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5871                 .family = MV88E6XXX_FAMILY_6390,
5872                 .name = "Marvell 88E6191",
5873                 .num_databases = 4096,
5874                 .num_macs = 16384,
5875                 .num_ports = 11,        /* 10 + Z80 */
5876                 .num_internal_phys = 9,
5877                 .max_vid = 8191,
5878                 .max_sid = 63,
5879                 .port_base_addr = 0x0,
5880                 .phy_base_addr = 0x0,
5881                 .global1_addr = 0x1b,
5882                 .global2_addr = 0x1c,
5883                 .age_time_coeff = 3750,
5884                 .g1_irqs = 9,
5885                 .g2_irqs = 14,
5886                 .atu_move_port_mask = 0x1f,
5887                 .pvt = true,
5888                 .multi_chip = true,
5889                 .ptp_support = true,
5890                 .ops = &mv88e6191_ops,
5891         },
5892
5893         [MV88E6191X] = {
5894                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5895                 .family = MV88E6XXX_FAMILY_6393,
5896                 .name = "Marvell 88E6191X",
5897                 .num_databases = 4096,
5898                 .num_ports = 11,        /* 10 + Z80 */
5899                 .num_internal_phys = 9,
5900                 .max_vid = 8191,
5901                 .max_sid = 63,
5902                 .port_base_addr = 0x0,
5903                 .phy_base_addr = 0x0,
5904                 .global1_addr = 0x1b,
5905                 .global2_addr = 0x1c,
5906                 .age_time_coeff = 3750,
5907                 .g1_irqs = 10,
5908                 .g2_irqs = 14,
5909                 .atu_move_port_mask = 0x1f,
5910                 .pvt = true,
5911                 .multi_chip = true,
5912                 .ptp_support = true,
5913                 .ops = &mv88e6393x_ops,
5914         },
5915
5916         [MV88E6193X] = {
5917                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5918                 .family = MV88E6XXX_FAMILY_6393,
5919                 .name = "Marvell 88E6193X",
5920                 .num_databases = 4096,
5921                 .num_ports = 11,        /* 10 + Z80 */
5922                 .num_internal_phys = 9,
5923                 .max_vid = 8191,
5924                 .max_sid = 63,
5925                 .port_base_addr = 0x0,
5926                 .phy_base_addr = 0x0,
5927                 .global1_addr = 0x1b,
5928                 .global2_addr = 0x1c,
5929                 .age_time_coeff = 3750,
5930                 .g1_irqs = 10,
5931                 .g2_irqs = 14,
5932                 .atu_move_port_mask = 0x1f,
5933                 .pvt = true,
5934                 .multi_chip = true,
5935                 .ptp_support = true,
5936                 .ops = &mv88e6393x_ops,
5937         },
5938
5939         [MV88E6220] = {
5940                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5941                 .family = MV88E6XXX_FAMILY_6250,
5942                 .name = "Marvell 88E6220",
5943                 .num_databases = 64,
5944
5945                 /* Ports 2-4 are not routed to pins
5946                  * => usable ports 0, 1, 5, 6
5947                  */
5948                 .num_ports = 7,
5949                 .num_internal_phys = 2,
5950                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5951                 .max_vid = 4095,
5952                 .port_base_addr = 0x08,
5953                 .phy_base_addr = 0x00,
5954                 .global1_addr = 0x0f,
5955                 .global2_addr = 0x07,
5956                 .age_time_coeff = 15000,
5957                 .g1_irqs = 9,
5958                 .g2_irqs = 10,
5959                 .atu_move_port_mask = 0xf,
5960                 .dual_chip = true,
5961                 .ptp_support = true,
5962                 .ops = &mv88e6250_ops,
5963         },
5964
5965         [MV88E6240] = {
5966                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5967                 .family = MV88E6XXX_FAMILY_6352,
5968                 .name = "Marvell 88E6240",
5969                 .num_databases = 4096,
5970                 .num_macs = 8192,
5971                 .num_ports = 7,
5972                 .num_internal_phys = 5,
5973                 .num_gpio = 15,
5974                 .max_vid = 4095,
5975                 .max_sid = 63,
5976                 .port_base_addr = 0x10,
5977                 .phy_base_addr = 0x0,
5978                 .global1_addr = 0x1b,
5979                 .global2_addr = 0x1c,
5980                 .age_time_coeff = 15000,
5981                 .g1_irqs = 9,
5982                 .g2_irqs = 10,
5983                 .atu_move_port_mask = 0xf,
5984                 .pvt = true,
5985                 .multi_chip = true,
5986                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5987                 .ptp_support = true,
5988                 .ops = &mv88e6240_ops,
5989         },
5990
5991         [MV88E6250] = {
5992                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5993                 .family = MV88E6XXX_FAMILY_6250,
5994                 .name = "Marvell 88E6250",
5995                 .num_databases = 64,
5996                 .num_ports = 7,
5997                 .num_internal_phys = 5,
5998                 .max_vid = 4095,
5999                 .port_base_addr = 0x08,
6000                 .phy_base_addr = 0x00,
6001                 .global1_addr = 0x0f,
6002                 .global2_addr = 0x07,
6003                 .age_time_coeff = 15000,
6004                 .g1_irqs = 9,
6005                 .g2_irqs = 10,
6006                 .atu_move_port_mask = 0xf,
6007                 .dual_chip = true,
6008                 .ptp_support = true,
6009                 .ops = &mv88e6250_ops,
6010         },
6011
6012         [MV88E6290] = {
6013                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6014                 .family = MV88E6XXX_FAMILY_6390,
6015                 .name = "Marvell 88E6290",
6016                 .num_databases = 4096,
6017                 .num_ports = 11,        /* 10 + Z80 */
6018                 .num_internal_phys = 9,
6019                 .num_gpio = 16,
6020                 .max_vid = 8191,
6021                 .max_sid = 63,
6022                 .port_base_addr = 0x0,
6023                 .phy_base_addr = 0x0,
6024                 .global1_addr = 0x1b,
6025                 .global2_addr = 0x1c,
6026                 .age_time_coeff = 3750,
6027                 .g1_irqs = 9,
6028                 .g2_irqs = 14,
6029                 .atu_move_port_mask = 0x1f,
6030                 .pvt = true,
6031                 .multi_chip = true,
6032                 .ptp_support = true,
6033                 .ops = &mv88e6290_ops,
6034         },
6035
6036         [MV88E6320] = {
6037                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6038                 .family = MV88E6XXX_FAMILY_6320,
6039                 .name = "Marvell 88E6320",
6040                 .num_databases = 4096,
6041                 .num_macs = 8192,
6042                 .num_ports = 7,
6043                 .num_internal_phys = 5,
6044                 .num_gpio = 15,
6045                 .max_vid = 4095,
6046                 .port_base_addr = 0x10,
6047                 .phy_base_addr = 0x0,
6048                 .global1_addr = 0x1b,
6049                 .global2_addr = 0x1c,
6050                 .age_time_coeff = 15000,
6051                 .g1_irqs = 8,
6052                 .g2_irqs = 10,
6053                 .atu_move_port_mask = 0xf,
6054                 .pvt = true,
6055                 .multi_chip = true,
6056                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6057                 .ptp_support = true,
6058                 .ops = &mv88e6320_ops,
6059         },
6060
6061         [MV88E6321] = {
6062                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6063                 .family = MV88E6XXX_FAMILY_6320,
6064                 .name = "Marvell 88E6321",
6065                 .num_databases = 4096,
6066                 .num_macs = 8192,
6067                 .num_ports = 7,
6068                 .num_internal_phys = 5,
6069                 .num_gpio = 15,
6070                 .max_vid = 4095,
6071                 .port_base_addr = 0x10,
6072                 .phy_base_addr = 0x0,
6073                 .global1_addr = 0x1b,
6074                 .global2_addr = 0x1c,
6075                 .age_time_coeff = 15000,
6076                 .g1_irqs = 8,
6077                 .g2_irqs = 10,
6078                 .atu_move_port_mask = 0xf,
6079                 .multi_chip = true,
6080                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6081                 .ptp_support = true,
6082                 .ops = &mv88e6321_ops,
6083         },
6084
6085         [MV88E6341] = {
6086                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6087                 .family = MV88E6XXX_FAMILY_6341,
6088                 .name = "Marvell 88E6341",
6089                 .num_databases = 4096,
6090                 .num_macs = 2048,
6091                 .num_internal_phys = 5,
6092                 .num_ports = 6,
6093                 .num_gpio = 11,
6094                 .max_vid = 4095,
6095                 .max_sid = 63,
6096                 .port_base_addr = 0x10,
6097                 .phy_base_addr = 0x10,
6098                 .global1_addr = 0x1b,
6099                 .global2_addr = 0x1c,
6100                 .age_time_coeff = 3750,
6101                 .atu_move_port_mask = 0x1f,
6102                 .g1_irqs = 9,
6103                 .g2_irqs = 10,
6104                 .pvt = true,
6105                 .multi_chip = true,
6106                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6107                 .ptp_support = true,
6108                 .ops = &mv88e6341_ops,
6109         },
6110
6111         [MV88E6350] = {
6112                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6113                 .family = MV88E6XXX_FAMILY_6351,
6114                 .name = "Marvell 88E6350",
6115                 .num_databases = 4096,
6116                 .num_macs = 8192,
6117                 .num_ports = 7,
6118                 .num_internal_phys = 5,
6119                 .max_vid = 4095,
6120                 .max_sid = 63,
6121                 .port_base_addr = 0x10,
6122                 .phy_base_addr = 0x0,
6123                 .global1_addr = 0x1b,
6124                 .global2_addr = 0x1c,
6125                 .age_time_coeff = 15000,
6126                 .g1_irqs = 9,
6127                 .g2_irqs = 10,
6128                 .atu_move_port_mask = 0xf,
6129                 .pvt = true,
6130                 .multi_chip = true,
6131                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6132                 .ops = &mv88e6350_ops,
6133         },
6134
6135         [MV88E6351] = {
6136                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6137                 .family = MV88E6XXX_FAMILY_6351,
6138                 .name = "Marvell 88E6351",
6139                 .num_databases = 4096,
6140                 .num_macs = 8192,
6141                 .num_ports = 7,
6142                 .num_internal_phys = 5,
6143                 .max_vid = 4095,
6144                 .max_sid = 63,
6145                 .port_base_addr = 0x10,
6146                 .phy_base_addr = 0x0,
6147                 .global1_addr = 0x1b,
6148                 .global2_addr = 0x1c,
6149                 .age_time_coeff = 15000,
6150                 .g1_irqs = 9,
6151                 .g2_irqs = 10,
6152                 .atu_move_port_mask = 0xf,
6153                 .pvt = true,
6154                 .multi_chip = true,
6155                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6156                 .ops = &mv88e6351_ops,
6157         },
6158
6159         [MV88E6352] = {
6160                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6161                 .family = MV88E6XXX_FAMILY_6352,
6162                 .name = "Marvell 88E6352",
6163                 .num_databases = 4096,
6164                 .num_macs = 8192,
6165                 .num_ports = 7,
6166                 .num_internal_phys = 5,
6167                 .num_gpio = 15,
6168                 .max_vid = 4095,
6169                 .max_sid = 63,
6170                 .port_base_addr = 0x10,
6171                 .phy_base_addr = 0x0,
6172                 .global1_addr = 0x1b,
6173                 .global2_addr = 0x1c,
6174                 .age_time_coeff = 15000,
6175                 .g1_irqs = 9,
6176                 .g2_irqs = 10,
6177                 .atu_move_port_mask = 0xf,
6178                 .pvt = true,
6179                 .multi_chip = true,
6180                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6181                 .ptp_support = true,
6182                 .ops = &mv88e6352_ops,
6183         },
6184         [MV88E6390] = {
6185                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6186                 .family = MV88E6XXX_FAMILY_6390,
6187                 .name = "Marvell 88E6390",
6188                 .num_databases = 4096,
6189                 .num_macs = 16384,
6190                 .num_ports = 11,        /* 10 + Z80 */
6191                 .num_internal_phys = 9,
6192                 .num_gpio = 16,
6193                 .max_vid = 8191,
6194                 .max_sid = 63,
6195                 .port_base_addr = 0x0,
6196                 .phy_base_addr = 0x0,
6197                 .global1_addr = 0x1b,
6198                 .global2_addr = 0x1c,
6199                 .age_time_coeff = 3750,
6200                 .g1_irqs = 9,
6201                 .g2_irqs = 14,
6202                 .atu_move_port_mask = 0x1f,
6203                 .pvt = true,
6204                 .multi_chip = true,
6205                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6206                 .ptp_support = true,
6207                 .ops = &mv88e6390_ops,
6208         },
6209         [MV88E6390X] = {
6210                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6211                 .family = MV88E6XXX_FAMILY_6390,
6212                 .name = "Marvell 88E6390X",
6213                 .num_databases = 4096,
6214                 .num_macs = 16384,
6215                 .num_ports = 11,        /* 10 + Z80 */
6216                 .num_internal_phys = 9,
6217                 .num_gpio = 16,
6218                 .max_vid = 8191,
6219                 .max_sid = 63,
6220                 .port_base_addr = 0x0,
6221                 .phy_base_addr = 0x0,
6222                 .global1_addr = 0x1b,
6223                 .global2_addr = 0x1c,
6224                 .age_time_coeff = 3750,
6225                 .g1_irqs = 9,
6226                 .g2_irqs = 14,
6227                 .atu_move_port_mask = 0x1f,
6228                 .pvt = true,
6229                 .multi_chip = true,
6230                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6231                 .ptp_support = true,
6232                 .ops = &mv88e6390x_ops,
6233         },
6234
6235         [MV88E6393X] = {
6236                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6237                 .family = MV88E6XXX_FAMILY_6393,
6238                 .name = "Marvell 88E6393X",
6239                 .num_databases = 4096,
6240                 .num_ports = 11,        /* 10 + Z80 */
6241                 .num_internal_phys = 9,
6242                 .max_vid = 8191,
6243                 .max_sid = 63,
6244                 .port_base_addr = 0x0,
6245                 .phy_base_addr = 0x0,
6246                 .global1_addr = 0x1b,
6247                 .global2_addr = 0x1c,
6248                 .age_time_coeff = 3750,
6249                 .g1_irqs = 10,
6250                 .g2_irqs = 14,
6251                 .atu_move_port_mask = 0x1f,
6252                 .pvt = true,
6253                 .multi_chip = true,
6254                 .ptp_support = true,
6255                 .ops = &mv88e6393x_ops,
6256         },
6257 };
6258
6259 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6260 {
6261         int i;
6262
6263         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6264                 if (mv88e6xxx_table[i].prod_num == prod_num)
6265                         return &mv88e6xxx_table[i];
6266
6267         return NULL;
6268 }
6269
6270 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6271 {
6272         const struct mv88e6xxx_info *info;
6273         unsigned int prod_num, rev;
6274         u16 id;
6275         int err;
6276
6277         mv88e6xxx_reg_lock(chip);
6278         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6279         mv88e6xxx_reg_unlock(chip);
6280         if (err)
6281                 return err;
6282
6283         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6284         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6285
6286         info = mv88e6xxx_lookup_info(prod_num);
6287         if (!info)
6288                 return -ENODEV;
6289
6290         /* Update the compatible info with the probed one */
6291         chip->info = info;
6292
6293         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6294                  chip->info->prod_num, chip->info->name, rev);
6295
6296         return 0;
6297 }
6298
6299 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6300                                         struct mdio_device *mdiodev)
6301 {
6302         int err;
6303
6304         /* dual_chip takes precedence over single/multi-chip modes */
6305         if (chip->info->dual_chip)
6306                 return -EINVAL;
6307
6308         /* If the mdio addr is 16 indicating the first port address of a switch
6309          * (e.g. mv88e6*41) in single chip addressing mode the device may be
6310          * configured in single chip addressing mode. Setup the smi access as
6311          * single chip addressing mode and attempt to detect the model of the
6312          * switch, if this fails the device is not configured in single chip
6313          * addressing mode.
6314          */
6315         if (mdiodev->addr != 16)
6316                 return -EINVAL;
6317
6318         err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6319         if (err)
6320                 return err;
6321
6322         return mv88e6xxx_detect(chip);
6323 }
6324
6325 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6326 {
6327         struct mv88e6xxx_chip *chip;
6328
6329         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6330         if (!chip)
6331                 return NULL;
6332
6333         chip->dev = dev;
6334
6335         mutex_init(&chip->reg_lock);
6336         INIT_LIST_HEAD(&chip->mdios);
6337         idr_init(&chip->policies);
6338         INIT_LIST_HEAD(&chip->msts);
6339
6340         return chip;
6341 }
6342
6343 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6344                                                         int port,
6345                                                         enum dsa_tag_protocol m)
6346 {
6347         struct mv88e6xxx_chip *chip = ds->priv;
6348
6349         return chip->tag_protocol;
6350 }
6351
6352 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6353                                          enum dsa_tag_protocol proto)
6354 {
6355         struct mv88e6xxx_chip *chip = ds->priv;
6356         enum dsa_tag_protocol old_protocol;
6357         struct dsa_port *cpu_dp;
6358         int err;
6359
6360         switch (proto) {
6361         case DSA_TAG_PROTO_EDSA:
6362                 switch (chip->info->edsa_support) {
6363                 case MV88E6XXX_EDSA_UNSUPPORTED:
6364                         return -EPROTONOSUPPORT;
6365                 case MV88E6XXX_EDSA_UNDOCUMENTED:
6366                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6367                         fallthrough;
6368                 case MV88E6XXX_EDSA_SUPPORTED:
6369                         break;
6370                 }
6371                 break;
6372         case DSA_TAG_PROTO_DSA:
6373                 break;
6374         default:
6375                 return -EPROTONOSUPPORT;
6376         }
6377
6378         old_protocol = chip->tag_protocol;
6379         chip->tag_protocol = proto;
6380
6381         mv88e6xxx_reg_lock(chip);
6382         dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6383                 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6384                 if (err) {
6385                         mv88e6xxx_reg_unlock(chip);
6386                         goto unwind;
6387                 }
6388         }
6389         mv88e6xxx_reg_unlock(chip);
6390
6391         return 0;
6392
6393 unwind:
6394         chip->tag_protocol = old_protocol;
6395
6396         mv88e6xxx_reg_lock(chip);
6397         dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6398                 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6399         mv88e6xxx_reg_unlock(chip);
6400
6401         return err;
6402 }
6403
6404 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6405                                   const struct switchdev_obj_port_mdb *mdb,
6406                                   struct dsa_db db)
6407 {
6408         struct mv88e6xxx_chip *chip = ds->priv;
6409         int err;
6410
6411         mv88e6xxx_reg_lock(chip);
6412         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6413                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6414         mv88e6xxx_reg_unlock(chip);
6415
6416         return err;
6417 }
6418
6419 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6420                                   const struct switchdev_obj_port_mdb *mdb,
6421                                   struct dsa_db db)
6422 {
6423         struct mv88e6xxx_chip *chip = ds->priv;
6424         int err;
6425
6426         mv88e6xxx_reg_lock(chip);
6427         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6428         mv88e6xxx_reg_unlock(chip);
6429
6430         return err;
6431 }
6432
6433 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6434                                      struct dsa_mall_mirror_tc_entry *mirror,
6435                                      bool ingress,
6436                                      struct netlink_ext_ack *extack)
6437 {
6438         enum mv88e6xxx_egress_direction direction = ingress ?
6439                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6440                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6441         struct mv88e6xxx_chip *chip = ds->priv;
6442         bool other_mirrors = false;
6443         int i;
6444         int err;
6445
6446         mutex_lock(&chip->reg_lock);
6447         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6448             mirror->to_local_port) {
6449                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6450                         other_mirrors |= ingress ?
6451                                          chip->ports[i].mirror_ingress :
6452                                          chip->ports[i].mirror_egress;
6453
6454                 /* Can't change egress port when other mirror is active */
6455                 if (other_mirrors) {
6456                         err = -EBUSY;
6457                         goto out;
6458                 }
6459
6460                 err = mv88e6xxx_set_egress_port(chip, direction,
6461                                                 mirror->to_local_port);
6462                 if (err)
6463                         goto out;
6464         }
6465
6466         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6467 out:
6468         mutex_unlock(&chip->reg_lock);
6469
6470         return err;
6471 }
6472
6473 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6474                                       struct dsa_mall_mirror_tc_entry *mirror)
6475 {
6476         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6477                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6478                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6479         struct mv88e6xxx_chip *chip = ds->priv;
6480         bool other_mirrors = false;
6481         int i;
6482
6483         mutex_lock(&chip->reg_lock);
6484         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6485                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6486
6487         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6488                 other_mirrors |= mirror->ingress ?
6489                                  chip->ports[i].mirror_ingress :
6490                                  chip->ports[i].mirror_egress;
6491
6492         /* Reset egress port when no other mirror is active */
6493         if (!other_mirrors) {
6494                 if (mv88e6xxx_set_egress_port(chip, direction,
6495                                               dsa_upstream_port(ds, port)))
6496                         dev_err(ds->dev, "failed to set egress port\n");
6497         }
6498
6499         mutex_unlock(&chip->reg_lock);
6500 }
6501
6502 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6503                                            struct switchdev_brport_flags flags,
6504                                            struct netlink_ext_ack *extack)
6505 {
6506         struct mv88e6xxx_chip *chip = ds->priv;
6507         const struct mv88e6xxx_ops *ops;
6508
6509         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6510                            BR_BCAST_FLOOD | BR_PORT_LOCKED))
6511                 return -EINVAL;
6512
6513         ops = chip->info->ops;
6514
6515         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6516                 return -EINVAL;
6517
6518         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6519                 return -EINVAL;
6520
6521         return 0;
6522 }
6523
6524 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6525                                        struct switchdev_brport_flags flags,
6526                                        struct netlink_ext_ack *extack)
6527 {
6528         struct mv88e6xxx_chip *chip = ds->priv;
6529         int err = -EOPNOTSUPP;
6530
6531         mv88e6xxx_reg_lock(chip);
6532
6533         if (flags.mask & BR_LEARNING) {
6534                 bool learning = !!(flags.val & BR_LEARNING);
6535                 u16 pav = learning ? (1 << port) : 0;
6536
6537                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6538                 if (err)
6539                         goto out;
6540         }
6541
6542         if (flags.mask & BR_FLOOD) {
6543                 bool unicast = !!(flags.val & BR_FLOOD);
6544
6545                 err = chip->info->ops->port_set_ucast_flood(chip, port,
6546                                                             unicast);
6547                 if (err)
6548                         goto out;
6549         }
6550
6551         if (flags.mask & BR_MCAST_FLOOD) {
6552                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6553
6554                 err = chip->info->ops->port_set_mcast_flood(chip, port,
6555                                                             multicast);
6556                 if (err)
6557                         goto out;
6558         }
6559
6560         if (flags.mask & BR_BCAST_FLOOD) {
6561                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6562
6563                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6564                 if (err)
6565                         goto out;
6566         }
6567
6568         if (flags.mask & BR_PORT_LOCKED) {
6569                 bool locked = !!(flags.val & BR_PORT_LOCKED);
6570
6571                 err = mv88e6xxx_port_set_lock(chip, port, locked);
6572                 if (err)
6573                         goto out;
6574         }
6575 out:
6576         mv88e6xxx_reg_unlock(chip);
6577
6578         return err;
6579 }
6580
6581 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6582                                       struct dsa_lag lag,
6583                                       struct netdev_lag_upper_info *info)
6584 {
6585         struct mv88e6xxx_chip *chip = ds->priv;
6586         struct dsa_port *dp;
6587         int members = 0;
6588
6589         if (!mv88e6xxx_has_lag(chip))
6590                 return false;
6591
6592         if (!lag.id)
6593                 return false;
6594
6595         dsa_lag_foreach_port(dp, ds->dst, &lag)
6596                 /* Includes the port joining the LAG */
6597                 members++;
6598
6599         if (members > 8)
6600                 return false;
6601
6602         /* We could potentially relax this to include active
6603          * backup in the future.
6604          */
6605         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
6606                 return false;
6607
6608         /* Ideally we would also validate that the hash type matches
6609          * the hardware. Alas, this is always set to unknown on team
6610          * interfaces.
6611          */
6612         return true;
6613 }
6614
6615 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6616 {
6617         struct mv88e6xxx_chip *chip = ds->priv;
6618         struct dsa_port *dp;
6619         u16 map = 0;
6620         int id;
6621
6622         /* DSA LAG IDs are one-based, hardware is zero-based */
6623         id = lag.id - 1;
6624
6625         /* Build the map of all ports to distribute flows destined for
6626          * this LAG. This can be either a local user port, or a DSA
6627          * port if the LAG port is on a remote chip.
6628          */
6629         dsa_lag_foreach_port(dp, ds->dst, &lag)
6630                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6631
6632         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6633 }
6634
6635 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6636         /* Row number corresponds to the number of active members in a
6637          * LAG. Each column states which of the eight hash buckets are
6638          * mapped to the column:th port in the LAG.
6639          *
6640          * Example: In a LAG with three active ports, the second port
6641          * ([2][1]) would be selected for traffic mapped to buckets
6642          * 3,4,5 (0x38).
6643          */
6644         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
6645         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6646         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6647         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6648         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6649         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6650         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6651         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6652 };
6653
6654 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6655                                         int num_tx, int nth)
6656 {
6657         u8 active = 0;
6658         int i;
6659
6660         num_tx = num_tx <= 8 ? num_tx : 8;
6661         if (nth < num_tx)
6662                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6663
6664         for (i = 0; i < 8; i++) {
6665                 if (BIT(i) & active)
6666                         mask[i] |= BIT(port);
6667         }
6668 }
6669
6670 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6671 {
6672         struct mv88e6xxx_chip *chip = ds->priv;
6673         unsigned int id, num_tx;
6674         struct dsa_port *dp;
6675         struct dsa_lag *lag;
6676         int i, err, nth;
6677         u16 mask[8];
6678         u16 ivec;
6679
6680         /* Assume no port is a member of any LAG. */
6681         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6682
6683         /* Disable all masks for ports that _are_ members of a LAG. */
6684         dsa_switch_for_each_port(dp, ds) {
6685                 if (!dp->lag)
6686                         continue;
6687
6688                 ivec &= ~BIT(dp->index);
6689         }
6690
6691         for (i = 0; i < 8; i++)
6692                 mask[i] = ivec;
6693
6694         /* Enable the correct subset of masks for all LAG ports that
6695          * are in the Tx set.
6696          */
6697         dsa_lags_foreach_id(id, ds->dst) {
6698                 lag = dsa_lag_by_id(ds->dst, id);
6699                 if (!lag)
6700                         continue;
6701
6702                 num_tx = 0;
6703                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6704                         if (dp->lag_tx_enabled)
6705                                 num_tx++;
6706                 }
6707
6708                 if (!num_tx)
6709                         continue;
6710
6711                 nth = 0;
6712                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6713                         if (!dp->lag_tx_enabled)
6714                                 continue;
6715
6716                         if (dp->ds == ds)
6717                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6718                                                             num_tx, nth);
6719
6720                         nth++;
6721                 }
6722         }
6723
6724         for (i = 0; i < 8; i++) {
6725                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6726                 if (err)
6727                         return err;
6728         }
6729
6730         return 0;
6731 }
6732
6733 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6734                                         struct dsa_lag lag)
6735 {
6736         int err;
6737
6738         err = mv88e6xxx_lag_sync_masks(ds);
6739
6740         if (!err)
6741                 err = mv88e6xxx_lag_sync_map(ds, lag);
6742
6743         return err;
6744 }
6745
6746 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6747 {
6748         struct mv88e6xxx_chip *chip = ds->priv;
6749         int err;
6750
6751         mv88e6xxx_reg_lock(chip);
6752         err = mv88e6xxx_lag_sync_masks(ds);
6753         mv88e6xxx_reg_unlock(chip);
6754         return err;
6755 }
6756
6757 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6758                                    struct dsa_lag lag,
6759                                    struct netdev_lag_upper_info *info)
6760 {
6761         struct mv88e6xxx_chip *chip = ds->priv;
6762         int err, id;
6763
6764         if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6765                 return -EOPNOTSUPP;
6766
6767         /* DSA LAG IDs are one-based */
6768         id = lag.id - 1;
6769
6770         mv88e6xxx_reg_lock(chip);
6771
6772         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6773         if (err)
6774                 goto err_unlock;
6775
6776         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6777         if (err)
6778                 goto err_clear_trunk;
6779
6780         mv88e6xxx_reg_unlock(chip);
6781         return 0;
6782
6783 err_clear_trunk:
6784         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6785 err_unlock:
6786         mv88e6xxx_reg_unlock(chip);
6787         return err;
6788 }
6789
6790 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6791                                     struct dsa_lag lag)
6792 {
6793         struct mv88e6xxx_chip *chip = ds->priv;
6794         int err_sync, err_trunk;
6795
6796         mv88e6xxx_reg_lock(chip);
6797         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6798         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6799         mv88e6xxx_reg_unlock(chip);
6800         return err_sync ? : err_trunk;
6801 }
6802
6803 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6804                                           int port)
6805 {
6806         struct mv88e6xxx_chip *chip = ds->priv;
6807         int err;
6808
6809         mv88e6xxx_reg_lock(chip);
6810         err = mv88e6xxx_lag_sync_masks(ds);
6811         mv88e6xxx_reg_unlock(chip);
6812         return err;
6813 }
6814
6815 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6816                                         int port, struct dsa_lag lag,
6817                                         struct netdev_lag_upper_info *info)
6818 {
6819         struct mv88e6xxx_chip *chip = ds->priv;
6820         int err;
6821
6822         if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6823                 return -EOPNOTSUPP;
6824
6825         mv88e6xxx_reg_lock(chip);
6826
6827         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6828         if (err)
6829                 goto unlock;
6830
6831         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6832
6833 unlock:
6834         mv88e6xxx_reg_unlock(chip);
6835         return err;
6836 }
6837
6838 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6839                                          int port, struct dsa_lag lag)
6840 {
6841         struct mv88e6xxx_chip *chip = ds->priv;
6842         int err_sync, err_pvt;
6843
6844         mv88e6xxx_reg_lock(chip);
6845         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6846         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6847         mv88e6xxx_reg_unlock(chip);
6848         return err_sync ? : err_pvt;
6849 }
6850
6851 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6852         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6853         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6854         .setup                  = mv88e6xxx_setup,
6855         .teardown               = mv88e6xxx_teardown,
6856         .port_setup             = mv88e6xxx_port_setup,
6857         .port_teardown          = mv88e6xxx_port_teardown,
6858         .phylink_get_caps       = mv88e6xxx_get_caps,
6859         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6860         .phylink_mac_config     = mv88e6xxx_mac_config,
6861         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6862         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6863         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6864         .get_strings            = mv88e6xxx_get_strings,
6865         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6866         .get_sset_count         = mv88e6xxx_get_sset_count,
6867         .port_enable            = mv88e6xxx_port_enable,
6868         .port_disable           = mv88e6xxx_port_disable,
6869         .port_max_mtu           = mv88e6xxx_get_max_mtu,
6870         .port_change_mtu        = mv88e6xxx_change_mtu,
6871         .get_mac_eee            = mv88e6xxx_get_mac_eee,
6872         .set_mac_eee            = mv88e6xxx_set_mac_eee,
6873         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
6874         .get_eeprom             = mv88e6xxx_get_eeprom,
6875         .set_eeprom             = mv88e6xxx_set_eeprom,
6876         .get_regs_len           = mv88e6xxx_get_regs_len,
6877         .get_regs               = mv88e6xxx_get_regs,
6878         .get_rxnfc              = mv88e6xxx_get_rxnfc,
6879         .set_rxnfc              = mv88e6xxx_set_rxnfc,
6880         .set_ageing_time        = mv88e6xxx_set_ageing_time,
6881         .port_bridge_join       = mv88e6xxx_port_bridge_join,
6882         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
6883         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
6884         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
6885         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
6886         .port_mst_state_set     = mv88e6xxx_port_mst_state_set,
6887         .port_fast_age          = mv88e6xxx_port_fast_age,
6888         .port_vlan_fast_age     = mv88e6xxx_port_vlan_fast_age,
6889         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
6890         .port_vlan_add          = mv88e6xxx_port_vlan_add,
6891         .port_vlan_del          = mv88e6xxx_port_vlan_del,
6892         .vlan_msti_set          = mv88e6xxx_vlan_msti_set,
6893         .port_fdb_add           = mv88e6xxx_port_fdb_add,
6894         .port_fdb_del           = mv88e6xxx_port_fdb_del,
6895         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
6896         .port_mdb_add           = mv88e6xxx_port_mdb_add,
6897         .port_mdb_del           = mv88e6xxx_port_mdb_del,
6898         .port_mirror_add        = mv88e6xxx_port_mirror_add,
6899         .port_mirror_del        = mv88e6xxx_port_mirror_del,
6900         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
6901         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6902         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
6903         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
6904         .port_txtstamp          = mv88e6xxx_port_txtstamp,
6905         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
6906         .get_ts_info            = mv88e6xxx_get_ts_info,
6907         .devlink_param_get      = mv88e6xxx_devlink_param_get,
6908         .devlink_param_set      = mv88e6xxx_devlink_param_set,
6909         .devlink_info_get       = mv88e6xxx_devlink_info_get,
6910         .port_lag_change        = mv88e6xxx_port_lag_change,
6911         .port_lag_join          = mv88e6xxx_port_lag_join,
6912         .port_lag_leave         = mv88e6xxx_port_lag_leave,
6913         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
6914         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
6915         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
6916 };
6917
6918 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6919 {
6920         struct device *dev = chip->dev;
6921         struct dsa_switch *ds;
6922
6923         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6924         if (!ds)
6925                 return -ENOMEM;
6926
6927         ds->dev = dev;
6928         ds->num_ports = mv88e6xxx_num_ports(chip);
6929         ds->priv = chip;
6930         ds->dev = dev;
6931         ds->ops = &mv88e6xxx_switch_ops;
6932         ds->ageing_time_min = chip->info->age_time_coeff;
6933         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6934
6935         /* Some chips support up to 32, but that requires enabling the
6936          * 5-bit port mode, which we do not support. 640k^W16 ought to
6937          * be enough for anyone.
6938          */
6939         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6940
6941         dev_set_drvdata(dev, ds);
6942
6943         return dsa_register_switch(ds);
6944 }
6945
6946 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6947 {
6948         dsa_unregister_switch(chip->ds);
6949 }
6950
6951 static const void *pdata_device_get_match_data(struct device *dev)
6952 {
6953         const struct of_device_id *matches = dev->driver->of_match_table;
6954         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6955
6956         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6957              matches++) {
6958                 if (!strcmp(pdata->compatible, matches->compatible))
6959                         return matches->data;
6960         }
6961         return NULL;
6962 }
6963
6964 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6965  * would be lost after a power cycle so prevent it to be suspended.
6966  */
6967 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6968 {
6969         return -EOPNOTSUPP;
6970 }
6971
6972 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6973 {
6974         return 0;
6975 }
6976
6977 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6978
6979 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6980 {
6981         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6982         const struct mv88e6xxx_info *compat_info = NULL;
6983         struct device *dev = &mdiodev->dev;
6984         struct device_node *np = dev->of_node;
6985         struct mv88e6xxx_chip *chip;
6986         int port;
6987         int err;
6988
6989         if (!np && !pdata)
6990                 return -EINVAL;
6991
6992         if (np)
6993                 compat_info = of_device_get_match_data(dev);
6994
6995         if (pdata) {
6996                 compat_info = pdata_device_get_match_data(dev);
6997
6998                 if (!pdata->netdev)
6999                         return -EINVAL;
7000
7001                 for (port = 0; port < DSA_MAX_PORTS; port++) {
7002                         if (!(pdata->enabled_ports & (1 << port)))
7003                                 continue;
7004                         if (strcmp(pdata->cd.port_names[port], "cpu"))
7005                                 continue;
7006                         pdata->cd.netdev[port] = &pdata->netdev->dev;
7007                         break;
7008                 }
7009         }
7010
7011         if (!compat_info)
7012                 return -EINVAL;
7013
7014         chip = mv88e6xxx_alloc_chip(dev);
7015         if (!chip) {
7016                 err = -ENOMEM;
7017                 goto out;
7018         }
7019
7020         chip->info = compat_info;
7021
7022         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7023         if (IS_ERR(chip->reset)) {
7024                 err = PTR_ERR(chip->reset);
7025                 goto out;
7026         }
7027         if (chip->reset)
7028                 usleep_range(1000, 2000);
7029
7030         /* Detect if the device is configured in single chip addressing mode,
7031          * otherwise continue with address specific smi init/detection.
7032          */
7033         err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7034         if (err) {
7035                 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7036                 if (err)
7037                         goto out;
7038
7039                 err = mv88e6xxx_detect(chip);
7040                 if (err)
7041                         goto out;
7042         }
7043
7044         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7045                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7046         else
7047                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7048
7049         mv88e6xxx_phy_init(chip);
7050
7051         if (chip->info->ops->get_eeprom) {
7052                 if (np)
7053                         of_property_read_u32(np, "eeprom-length",
7054                                              &chip->eeprom_len);
7055                 else
7056                         chip->eeprom_len = pdata->eeprom_len;
7057         }
7058
7059         mv88e6xxx_reg_lock(chip);
7060         err = mv88e6xxx_switch_reset(chip);
7061         mv88e6xxx_reg_unlock(chip);
7062         if (err)
7063                 goto out;
7064
7065         if (np) {
7066                 chip->irq = of_irq_get(np, 0);
7067                 if (chip->irq == -EPROBE_DEFER) {
7068                         err = chip->irq;
7069                         goto out;
7070                 }
7071         }
7072
7073         if (pdata)
7074                 chip->irq = pdata->irq;
7075
7076         /* Has to be performed before the MDIO bus is created, because
7077          * the PHYs will link their interrupts to these interrupt
7078          * controllers
7079          */
7080         mv88e6xxx_reg_lock(chip);
7081         if (chip->irq > 0)
7082                 err = mv88e6xxx_g1_irq_setup(chip);
7083         else
7084                 err = mv88e6xxx_irq_poll_setup(chip);
7085         mv88e6xxx_reg_unlock(chip);
7086
7087         if (err)
7088                 goto out;
7089
7090         if (chip->info->g2_irqs > 0) {
7091                 err = mv88e6xxx_g2_irq_setup(chip);
7092                 if (err)
7093                         goto out_g1_irq;
7094         }
7095
7096         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7097         if (err)
7098                 goto out_g2_irq;
7099
7100         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7101         if (err)
7102                 goto out_g1_atu_prob_irq;
7103
7104         err = mv88e6xxx_mdios_register(chip, np);
7105         if (err)
7106                 goto out_g1_vtu_prob_irq;
7107
7108         err = mv88e6xxx_register_switch(chip);
7109         if (err)
7110                 goto out_mdio;
7111
7112         return 0;
7113
7114 out_mdio:
7115         mv88e6xxx_mdios_unregister(chip);
7116 out_g1_vtu_prob_irq:
7117         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7118 out_g1_atu_prob_irq:
7119         mv88e6xxx_g1_atu_prob_irq_free(chip);
7120 out_g2_irq:
7121         if (chip->info->g2_irqs > 0)
7122                 mv88e6xxx_g2_irq_free(chip);
7123 out_g1_irq:
7124         if (chip->irq > 0)
7125                 mv88e6xxx_g1_irq_free(chip);
7126         else
7127                 mv88e6xxx_irq_poll_free(chip);
7128 out:
7129         if (pdata)
7130                 dev_put(pdata->netdev);
7131
7132         return err;
7133 }
7134
7135 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7136 {
7137         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7138         struct mv88e6xxx_chip *chip;
7139
7140         if (!ds)
7141                 return;
7142
7143         chip = ds->priv;
7144
7145         if (chip->info->ptp_support) {
7146                 mv88e6xxx_hwtstamp_free(chip);
7147                 mv88e6xxx_ptp_free(chip);
7148         }
7149
7150         mv88e6xxx_phy_destroy(chip);
7151         mv88e6xxx_unregister_switch(chip);
7152         mv88e6xxx_mdios_unregister(chip);
7153
7154         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7155         mv88e6xxx_g1_atu_prob_irq_free(chip);
7156
7157         if (chip->info->g2_irqs > 0)
7158                 mv88e6xxx_g2_irq_free(chip);
7159
7160         if (chip->irq > 0)
7161                 mv88e6xxx_g1_irq_free(chip);
7162         else
7163                 mv88e6xxx_irq_poll_free(chip);
7164
7165         dev_set_drvdata(&mdiodev->dev, NULL);
7166 }
7167
7168 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7169 {
7170         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7171
7172         if (!ds)
7173                 return;
7174
7175         dsa_switch_shutdown(ds);
7176
7177         dev_set_drvdata(&mdiodev->dev, NULL);
7178 }
7179
7180 static const struct of_device_id mv88e6xxx_of_match[] = {
7181         {
7182                 .compatible = "marvell,mv88e6085",
7183                 .data = &mv88e6xxx_table[MV88E6085],
7184         },
7185         {
7186                 .compatible = "marvell,mv88e6190",
7187                 .data = &mv88e6xxx_table[MV88E6190],
7188         },
7189         {
7190                 .compatible = "marvell,mv88e6250",
7191                 .data = &mv88e6xxx_table[MV88E6250],
7192         },
7193         { /* sentinel */ },
7194 };
7195
7196 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7197
7198 static struct mdio_driver mv88e6xxx_driver = {
7199         .probe  = mv88e6xxx_probe,
7200         .remove = mv88e6xxx_remove,
7201         .shutdown = mv88e6xxx_shutdown,
7202         .mdiodrv.driver = {
7203                 .name = "mv88e6085",
7204                 .of_match_table = mv88e6xxx_of_match,
7205                 .pm = &mv88e6xxx_pm_ops,
7206         },
7207 };
7208
7209 mdio_module_driver(mv88e6xxx_driver);
7210
7211 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7212 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7213 MODULE_LICENSE("GPL");