1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
57 assert_reg_lock(chip);
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
73 assert_reg_lock(chip);
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
98 if ((data & mask) == val)
101 usleep_range(1000, 2000);
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
117 struct mv88e6xxx_mdio_bus *mdio_bus;
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
124 return mdio_bus->bus;
127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
132 chip->g1_irq.masked |= (1 << n);
135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
140 chip->g1_irq.masked &= ~(1 << n);
143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
164 handle_nested_irq(sub_irq);
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
175 mv88e6xxx_reg_unlock(chip);
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
187 struct mv88e6xxx_chip *chip = dev_id;
189 return mv88e6xxx_g1_irq_thread_work(chip);
192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196 mv88e6xxx_reg_lock(chip);
199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
211 reg |= (~chip->g1_irq.masked & mask);
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
218 mv88e6xxx_reg_unlock(chip);
221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
231 irq_hw_number_t hwirq)
233 struct mv88e6xxx_chip *chip = d->host_data;
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
247 /* To be called with reg_lock held */
248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
259 irq_dispose_mapping(virq);
262 irq_domain_remove(chip->g1_irq.domain);
265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
271 free_irq(chip->irq, chip);
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
306 /* Reading the interrupt status clears (most of) them */
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
323 irq_domain_remove(chip->g1_irq.domain);
328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
334 err = mv88e6xxx_g1_irq_setup_common(chip);
338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
350 IRQF_ONESHOT | IRQF_SHARED,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
354 mv88e6xxx_g1_irq_free_common(chip);
359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
364 mv88e6xxx_g1_irq_thread_work(chip);
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
374 err = mv88e6xxx_g1_irq_setup_common(chip);
378 kthread_init_delayed_work(&chip->irq_poll_work,
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
409 if (err && err != -EOPNOTSUPP)
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
416 if (err && err != -EOPNOTSUPP)
423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
429 if (!chip->info->ops->port_set_link)
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
440 if (err && err != -EOPNOTSUPP)
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
463 struct mv88e6xxx_chip *chip = ds->priv;
465 return port < chip->info->num_internal_phys;
468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
476 "p%d: %s: failed to read port status\n",
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
487 struct mv88e6xxx_chip *chip = ds->priv;
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
498 mv88e6xxx_reg_unlock(chip);
503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
505 phy_interface_t interface,
506 const unsigned long *advertise)
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
528 ops = chip->info->ops;
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
544 int speed, int duplex)
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
552 return ops->serdes_pcs_link_up(chip, port, lane,
559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
561 struct phylink_link_state *state)
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
574 struct phylink_link_state *state)
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
582 mv88e6065_phylink_validate(chip, port, mask, state);
585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
587 struct phylink_link_state *state)
590 phylink_set(mask, 2500baseX_Full);
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
596 mv88e6065_phylink_validate(chip, port, mask, state);
599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
601 struct phylink_link_state *state)
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
607 mv88e6065_phylink_validate(chip, port, mask, state);
610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
612 struct phylink_link_state *state)
615 phylink_set(mask, 2500baseX_Full);
616 phylink_set(mask, 2500baseT_Full);
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
623 mv88e6065_phylink_validate(chip, port, mask, state);
626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
628 struct phylink_link_state *state)
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
635 mv88e6390_phylink_validate(chip, port, mask, state);
638 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
640 struct phylink_link_state *state)
642 if (port == 0 || port == 9 || port == 10) {
643 phylink_set(mask, 10000baseT_Full);
644 phylink_set(mask, 10000baseKR_Full);
645 phylink_set(mask, 10000baseCR_Full);
646 phylink_set(mask, 10000baseSR_Full);
647 phylink_set(mask, 10000baseLR_Full);
648 phylink_set(mask, 10000baseLRM_Full);
649 phylink_set(mask, 10000baseER_Full);
650 phylink_set(mask, 5000baseT_Full);
651 phylink_set(mask, 2500baseX_Full);
652 phylink_set(mask, 2500baseT_Full);
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
658 mv88e6065_phylink_validate(chip, port, mask, state);
661 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
662 unsigned long *supported,
663 struct phylink_link_state *state)
665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
666 struct mv88e6xxx_chip *chip = ds->priv;
668 /* Allow all the expected bits */
669 phylink_set(mask, Autoneg);
670 phylink_set(mask, Pause);
671 phylink_set_port_modes(mask);
673 if (chip->info->ops->phylink_validate)
674 chip->info->ops->phylink_validate(chip, port, mask, state);
676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
677 bitmap_and(state->advertising, state->advertising, mask,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
680 /* We can only operate at 2500BaseX or 1000BaseX. If requested
681 * to advertise both, only report advertising at 2500BaseX.
683 phylink_helper_basex_speed(state);
686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
688 const struct phylink_link_state *state)
690 struct mv88e6xxx_chip *chip = ds->priv;
691 struct mv88e6xxx_port *p;
694 p = &chip->ports[port];
696 /* FIXME: is this the correct test? If we're in fixed mode on an
697 * internal port, why should we process this any different from
698 * PHY mode? On the other hand, the port may be automedia between
699 * an internal PHY and the serdes...
701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
704 mv88e6xxx_reg_lock(chip);
705 /* In inband mode, the link may come up at any time while the link
706 * is not forced down. Force the link down while we reconfigure the
709 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
710 chip->info->ops->port_set_link)
711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
713 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
714 if (err && err != -EOPNOTSUPP)
717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
719 /* FIXME: we should restart negotiation if something changed - which
720 * is something we get if we convert to using phylinks PCS operations.
725 /* Undo the forced down state above after completing configuration
726 * irrespective of its state on entry, which allows the link to come up.
728 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
729 chip->info->ops->port_set_link)
730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
732 p->interface = state->interface;
735 mv88e6xxx_reg_unlock(chip);
737 if (err && err != -EOPNOTSUPP)
738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
743 phy_interface_t interface)
745 struct mv88e6xxx_chip *chip = ds->priv;
746 const struct mv88e6xxx_ops *ops;
749 ops = chip->info->ops;
751 mv88e6xxx_reg_lock(chip);
752 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
753 mode == MLO_AN_FIXED) && ops->port_sync_link)
754 err = ops->port_sync_link(chip, port, mode, false);
755 mv88e6xxx_reg_unlock(chip);
759 "p%d: failed to force MAC link down\n", port);
762 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
763 unsigned int mode, phy_interface_t interface,
764 struct phy_device *phydev,
765 int speed, int duplex,
766 bool tx_pause, bool rx_pause)
768 struct mv88e6xxx_chip *chip = ds->priv;
769 const struct mv88e6xxx_ops *ops;
772 ops = chip->info->ops;
774 mv88e6xxx_reg_lock(chip);
775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
776 /* FIXME: for an automedia port, should we force the link
777 * down here - what if the link comes up due to "other" media
778 * while we're bringing the port up, how is the exclusivity
779 * handled in the Marvell hardware? E.g. port 2 on 88E6390
780 * shared between internal PHY and Serdes.
782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
787 if (ops->port_set_speed_duplex) {
788 err = ops->port_set_speed_duplex(chip, port,
790 if (err && err != -EOPNOTSUPP)
794 if (ops->port_sync_link)
795 err = ops->port_sync_link(chip, port, mode, true);
798 mv88e6xxx_reg_unlock(chip);
800 if (err && err != -EOPNOTSUPP)
802 "p%d: failed to configure MAC link up\n", port);
805 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
807 if (!chip->info->ops->stats_snapshot)
810 return chip->info->ops->stats_snapshot(chip, port);
813 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
834 { "single", 4, 0x14, STATS_TYPE_BANK0, },
835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
837 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
875 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
876 struct mv88e6xxx_hw_stat *s,
877 int port, u16 bank1_select,
887 case STATS_TYPE_PORT:
888 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
897 low |= ((u32)reg) << 16;
900 case STATS_TYPE_BANK1:
903 case STATS_TYPE_BANK0:
904 reg |= s->reg | histogram;
905 mv88e6xxx_g1_stats_read(chip, reg, &low);
907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
912 value = (((u64)high) << 32) | low;
916 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
917 uint8_t *data, int types)
919 struct mv88e6xxx_hw_stat *stat;
922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
923 stat = &mv88e6xxx_hw_stats[i];
924 if (stat->type & types) {
925 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
934 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
937 return mv88e6xxx_stats_get_strings(chip, data,
938 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
941 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
947 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
950 return mv88e6xxx_stats_get_strings(chip, data,
951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
954 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
955 "atu_member_violation",
956 "atu_miss_violation",
957 "atu_full_violation",
958 "vtu_member_violation",
959 "vtu_miss_violation",
962 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
967 strlcpy(data + i * ETH_GSTRING_LEN,
968 mv88e6xxx_atu_vtu_stats_strings[i],
972 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
973 u32 stringset, uint8_t *data)
975 struct mv88e6xxx_chip *chip = ds->priv;
978 if (stringset != ETH_SS_STATS)
981 mv88e6xxx_reg_lock(chip);
983 if (chip->info->ops->stats_get_strings)
984 count = chip->info->ops->stats_get_strings(chip, data);
986 if (chip->info->ops->serdes_get_strings) {
987 data += count * ETH_GSTRING_LEN;
988 count = chip->info->ops->serdes_get_strings(chip, port, data);
991 data += count * ETH_GSTRING_LEN;
992 mv88e6xxx_atu_vtu_get_strings(data);
994 mv88e6xxx_reg_unlock(chip);
997 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1000 struct mv88e6xxx_hw_stat *stat;
1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1004 stat = &mv88e6xxx_hw_stats[i];
1005 if (stat->type & types)
1011 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1017 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1022 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1028 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1030 struct mv88e6xxx_chip *chip = ds->priv;
1031 int serdes_count = 0;
1034 if (sset != ETH_SS_STATS)
1037 mv88e6xxx_reg_lock(chip);
1038 if (chip->info->ops->stats_get_sset_count)
1039 count = chip->info->ops->stats_get_sset_count(chip);
1043 if (chip->info->ops->serdes_get_sset_count)
1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1046 if (serdes_count < 0) {
1047 count = serdes_count;
1050 count += serdes_count;
1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1054 mv88e6xxx_reg_unlock(chip);
1059 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1060 uint64_t *data, int types,
1061 u16 bank1_select, u16 histogram)
1063 struct mv88e6xxx_hw_stat *stat;
1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1067 stat = &mv88e6xxx_hw_stats[i];
1068 if (stat->type & types) {
1069 mv88e6xxx_reg_lock(chip);
1070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1073 mv88e6xxx_reg_unlock(chip);
1081 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1084 return mv88e6xxx_stats_get_stats(chip, port, data,
1085 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1089 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1096 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1099 return mv88e6xxx_stats_get_stats(chip, port, data,
1100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1105 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1108 return mv88e6xxx_stats_get_stats(chip, port, data,
1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1114 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1117 *data++ = chip->ports[port].atu_member_violation;
1118 *data++ = chip->ports[port].atu_miss_violation;
1119 *data++ = chip->ports[port].atu_full_violation;
1120 *data++ = chip->ports[port].vtu_member_violation;
1121 *data++ = chip->ports[port].vtu_miss_violation;
1124 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1129 if (chip->info->ops->stats_get_stats)
1130 count = chip->info->ops->stats_get_stats(chip, port, data);
1132 mv88e6xxx_reg_lock(chip);
1133 if (chip->info->ops->serdes_get_stats) {
1135 count = chip->info->ops->serdes_get_stats(chip, port, data);
1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1139 mv88e6xxx_reg_unlock(chip);
1142 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1145 struct mv88e6xxx_chip *chip = ds->priv;
1148 mv88e6xxx_reg_lock(chip);
1150 ret = mv88e6xxx_stats_snapshot(chip, port);
1151 mv88e6xxx_reg_unlock(chip);
1156 mv88e6xxx_get_stats(chip, port, data);
1160 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1162 struct mv88e6xxx_chip *chip = ds->priv;
1165 len = 32 * sizeof(u16);
1166 if (chip->info->ops->serdes_get_regs_len)
1167 len += chip->info->ops->serdes_get_regs_len(chip, port);
1172 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1173 struct ethtool_regs *regs, void *_p)
1175 struct mv88e6xxx_chip *chip = ds->priv;
1181 regs->version = chip->info->prod_num;
1183 memset(p, 0xff, 32 * sizeof(u16));
1185 mv88e6xxx_reg_lock(chip);
1187 for (i = 0; i < 32; i++) {
1189 err = mv88e6xxx_port_read(chip, port, i, ®);
1194 if (chip->info->ops->serdes_get_regs)
1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1197 mv88e6xxx_reg_unlock(chip);
1200 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1201 struct ethtool_eee *e)
1203 /* Nothing to do on the port's MAC */
1207 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1208 struct ethtool_eee *e)
1210 /* Nothing to do on the port's MAC */
1214 /* Mask of the local ports allowed to receive frames from a given fabric port */
1215 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1217 struct dsa_switch *ds = chip->ds;
1218 struct dsa_switch_tree *dst = ds->dst;
1219 struct net_device *br;
1220 struct dsa_port *dp;
1224 list_for_each_entry(dp, &dst->ports, list) {
1225 if (dp->ds->index == dev && dp->index == port) {
1231 /* Prevent frames from unknown switch or port */
1235 /* Frames from DSA links and CPU ports can egress any local port */
1236 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1237 return mv88e6xxx_port_mask(chip);
1239 br = dp->bridge_dev;
1242 /* Frames from user ports can egress any local DSA links and CPU ports,
1243 * as well as any local member of their bridge group.
1245 list_for_each_entry(dp, &dst->ports, list)
1247 (dp->type == DSA_PORT_TYPE_CPU ||
1248 dp->type == DSA_PORT_TYPE_DSA ||
1249 (br && dp->bridge_dev == br)))
1250 pvlan |= BIT(dp->index);
1255 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1257 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1259 /* prevent frames from going back out of the port they came in on */
1260 output_ports &= ~BIT(port);
1262 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1265 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1268 struct mv88e6xxx_chip *chip = ds->priv;
1271 mv88e6xxx_reg_lock(chip);
1272 err = mv88e6xxx_port_set_state(chip, port, state);
1273 mv88e6xxx_reg_unlock(chip);
1276 dev_err(ds->dev, "p%d: failed to update state\n", port);
1279 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1283 if (chip->info->ops->ieee_pri_map) {
1284 err = chip->info->ops->ieee_pri_map(chip);
1289 if (chip->info->ops->ip_pri_map) {
1290 err = chip->info->ops->ip_pri_map(chip);
1298 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1300 struct dsa_switch *ds = chip->ds;
1304 if (!chip->info->global2_addr)
1307 /* Initialize the routing port to the 32 possible target devices */
1308 for (target = 0; target < 32; target++) {
1309 port = dsa_routing_port(ds, target);
1310 if (port == ds->num_ports)
1313 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1318 if (chip->info->ops->set_cascade_port) {
1319 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1320 err = chip->info->ops->set_cascade_port(chip, port);
1325 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1332 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1334 /* Clear all trunk masks and mapping */
1335 if (chip->info->global2_addr)
1336 return mv88e6xxx_g2_trunk_clear(chip);
1341 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1343 if (chip->info->ops->rmu_disable)
1344 return chip->info->ops->rmu_disable(chip);
1349 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1351 if (chip->info->ops->pot_clear)
1352 return chip->info->ops->pot_clear(chip);
1357 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1359 if (chip->info->ops->mgmt_rsvd2cpu)
1360 return chip->info->ops->mgmt_rsvd2cpu(chip);
1365 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1369 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1373 /* The chips that have a "learn2all" bit in Global1, ATU
1374 * Control are precisely those whose port registers have a
1375 * Message Port bit in Port Control 1 and hence implement
1376 * ->port_setup_message_port.
1378 if (chip->info->ops->port_setup_message_port) {
1379 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1384 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1387 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1392 if (!chip->info->ops->irl_init_all)
1395 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1396 /* Disable ingress rate limiting by resetting all per port
1397 * ingress rate limit resources to their initial state.
1399 err = chip->info->ops->irl_init_all(chip, port);
1407 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1409 if (chip->info->ops->set_switch_mac) {
1412 eth_random_addr(addr);
1414 return chip->info->ops->set_switch_mac(chip, addr);
1420 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1422 struct dsa_switch_tree *dst = chip->ds->dst;
1423 struct dsa_switch *ds;
1424 struct dsa_port *dp;
1427 if (!mv88e6xxx_has_pvt(chip))
1430 /* Skip the local source device, which uses in-chip port VLAN */
1431 if (dev != chip->ds->index) {
1432 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1434 ds = dsa_switch_find(dst->index, dev);
1435 dp = ds ? dsa_to_port(ds, port) : NULL;
1436 if (dp && dp->lag_dev) {
1437 /* As the PVT is used to limit flooding of
1438 * FORWARD frames, which use the LAG ID as the
1439 * source port, we must translate dev/port to
1440 * the special "LAG device" in the PVT, using
1441 * the LAG ID as the port number.
1443 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1444 port = dsa_lag_id(dst, dp->lag_dev);
1448 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1451 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1456 if (!mv88e6xxx_has_pvt(chip))
1459 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1460 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1462 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1466 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1467 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1468 err = mv88e6xxx_pvt_map(chip, dev, port);
1477 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1479 struct mv88e6xxx_chip *chip = ds->priv;
1482 if (dsa_to_port(ds, port)->lag_dev)
1483 /* Hardware is incapable of fast-aging a LAG through a
1484 * regular ATU move operation. Until we have something
1485 * more fancy in place this is a no-op.
1489 mv88e6xxx_reg_lock(chip);
1490 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1491 mv88e6xxx_reg_unlock(chip);
1494 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1497 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1499 if (!mv88e6xxx_max_vid(chip))
1502 return mv88e6xxx_g1_vtu_flush(chip);
1505 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1506 struct mv88e6xxx_vtu_entry *entry)
1510 if (!chip->info->ops->vtu_getnext)
1513 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1514 entry->valid = false;
1516 err = chip->info->ops->vtu_getnext(chip, entry);
1518 if (entry->vid != vid)
1519 entry->valid = false;
1524 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1525 int (*cb)(struct mv88e6xxx_chip *chip,
1526 const struct mv88e6xxx_vtu_entry *entry,
1530 struct mv88e6xxx_vtu_entry entry = {
1531 .vid = mv88e6xxx_max_vid(chip),
1536 if (!chip->info->ops->vtu_getnext)
1540 err = chip->info->ops->vtu_getnext(chip, &entry);
1547 err = cb(chip, &entry, priv);
1550 } while (entry.vid < mv88e6xxx_max_vid(chip));
1555 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1556 struct mv88e6xxx_vtu_entry *entry)
1558 if (!chip->info->ops->vtu_loadpurge)
1561 return chip->info->ops->vtu_loadpurge(chip, entry);
1564 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1565 const struct mv88e6xxx_vtu_entry *entry,
1568 unsigned long *fid_bitmap = _fid_bitmap;
1570 set_bit(entry->fid, fid_bitmap);
1574 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1579 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1581 /* Set every FID bit used by the (un)bridged ports */
1582 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1583 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1587 set_bit(fid, fid_bitmap);
1590 /* Set every FID bit used by the VLAN entries */
1591 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1594 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1596 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1599 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1603 /* The reset value 0x000 is used to indicate that multiple address
1604 * databases are not needed. Return the next positive available.
1606 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1607 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1610 /* Clear the database */
1611 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1614 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1617 struct mv88e6xxx_chip *chip = ds->priv;
1618 struct mv88e6xxx_vtu_entry vlan;
1621 /* DSA and CPU ports have to be members of multiple vlans */
1622 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1625 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1632 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1633 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1636 if (!dsa_to_port(ds, i)->slave)
1639 if (vlan.member[i] ==
1640 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1643 if (dsa_to_port(ds, i)->bridge_dev ==
1644 dsa_to_port(ds, port)->bridge_dev)
1645 break; /* same bridge, check next VLAN */
1647 if (!dsa_to_port(ds, i)->bridge_dev)
1650 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1652 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1659 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1660 bool vlan_filtering,
1661 struct netlink_ext_ack *extack)
1663 struct mv88e6xxx_chip *chip = ds->priv;
1664 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1665 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1668 if (!mv88e6xxx_max_vid(chip))
1671 mv88e6xxx_reg_lock(chip);
1672 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1673 mv88e6xxx_reg_unlock(chip);
1679 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1680 const struct switchdev_obj_port_vlan *vlan)
1682 struct mv88e6xxx_chip *chip = ds->priv;
1685 if (!mv88e6xxx_max_vid(chip))
1688 /* If the requested port doesn't belong to the same bridge as the VLAN
1689 * members, do not support it (yet) and fallback to software VLAN.
1691 mv88e6xxx_reg_lock(chip);
1692 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
1693 mv88e6xxx_reg_unlock(chip);
1698 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1699 const unsigned char *addr, u16 vid,
1702 struct mv88e6xxx_atu_entry entry;
1703 struct mv88e6xxx_vtu_entry vlan;
1707 /* Null VLAN ID corresponds to the port private database */
1709 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1713 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1717 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1725 ether_addr_copy(entry.mac, addr);
1726 eth_addr_dec(entry.mac);
1728 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1732 /* Initialize a fresh ATU entry if it isn't found */
1733 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1734 memset(&entry, 0, sizeof(entry));
1735 ether_addr_copy(entry.mac, addr);
1738 /* Purge the ATU entry only if no port is using it anymore */
1740 entry.portvec &= ~BIT(port);
1744 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1745 entry.portvec = BIT(port);
1747 entry.portvec |= BIT(port);
1749 entry.state = state;
1752 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1755 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1756 const struct mv88e6xxx_policy *policy)
1758 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1759 enum mv88e6xxx_policy_action action = policy->action;
1760 const u8 *addr = policy->addr;
1761 u16 vid = policy->vid;
1766 if (!chip->info->ops->port_set_policy)
1770 case MV88E6XXX_POLICY_MAPPING_DA:
1771 case MV88E6XXX_POLICY_MAPPING_SA:
1772 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1773 state = 0; /* Dissociate the port and address */
1774 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1775 is_multicast_ether_addr(addr))
1776 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1777 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1778 is_unicast_ether_addr(addr))
1779 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1783 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1792 /* Skip the port's policy clearing if the mapping is still in use */
1793 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1794 idr_for_each_entry(&chip->policies, policy, id)
1795 if (policy->port == port &&
1796 policy->mapping == mapping &&
1797 policy->action != action)
1800 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1803 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1804 struct ethtool_rx_flow_spec *fs)
1806 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1807 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1808 enum mv88e6xxx_policy_mapping mapping;
1809 enum mv88e6xxx_policy_action action;
1810 struct mv88e6xxx_policy *policy;
1816 if (fs->location != RX_CLS_LOC_ANY)
1819 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1820 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1824 switch (fs->flow_type & ~FLOW_EXT) {
1826 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1827 is_zero_ether_addr(mac_mask->h_source)) {
1828 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1829 addr = mac_entry->h_dest;
1830 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1831 !is_zero_ether_addr(mac_mask->h_source)) {
1832 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1833 addr = mac_entry->h_source;
1835 /* Cannot support DA and SA mapping in the same rule */
1843 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1844 if (fs->m_ext.vlan_tci != htons(0xffff))
1846 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1849 idr_for_each_entry(&chip->policies, policy, id) {
1850 if (policy->port == port && policy->mapping == mapping &&
1851 policy->action == action && policy->vid == vid &&
1852 ether_addr_equal(policy->addr, addr))
1856 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1861 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1864 devm_kfree(chip->dev, policy);
1868 memcpy(&policy->fs, fs, sizeof(*fs));
1869 ether_addr_copy(policy->addr, addr);
1870 policy->mapping = mapping;
1871 policy->action = action;
1872 policy->port = port;
1875 err = mv88e6xxx_policy_apply(chip, port, policy);
1877 idr_remove(&chip->policies, fs->location);
1878 devm_kfree(chip->dev, policy);
1885 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1886 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1888 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1889 struct mv88e6xxx_chip *chip = ds->priv;
1890 struct mv88e6xxx_policy *policy;
1894 mv88e6xxx_reg_lock(chip);
1896 switch (rxnfc->cmd) {
1897 case ETHTOOL_GRXCLSRLCNT:
1899 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1900 rxnfc->rule_cnt = 0;
1901 idr_for_each_entry(&chip->policies, policy, id)
1902 if (policy->port == port)
1906 case ETHTOOL_GRXCLSRULE:
1908 policy = idr_find(&chip->policies, fs->location);
1910 memcpy(fs, &policy->fs, sizeof(*fs));
1914 case ETHTOOL_GRXCLSRLALL:
1916 rxnfc->rule_cnt = 0;
1917 idr_for_each_entry(&chip->policies, policy, id)
1918 if (policy->port == port)
1919 rule_locs[rxnfc->rule_cnt++] = id;
1927 mv88e6xxx_reg_unlock(chip);
1932 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1933 struct ethtool_rxnfc *rxnfc)
1935 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1936 struct mv88e6xxx_chip *chip = ds->priv;
1937 struct mv88e6xxx_policy *policy;
1940 mv88e6xxx_reg_lock(chip);
1942 switch (rxnfc->cmd) {
1943 case ETHTOOL_SRXCLSRLINS:
1944 err = mv88e6xxx_policy_insert(chip, port, fs);
1946 case ETHTOOL_SRXCLSRLDEL:
1948 policy = idr_remove(&chip->policies, fs->location);
1950 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1951 err = mv88e6xxx_policy_apply(chip, port, policy);
1952 devm_kfree(chip->dev, policy);
1960 mv88e6xxx_reg_unlock(chip);
1965 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1968 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1969 u8 broadcast[ETH_ALEN];
1971 eth_broadcast_addr(broadcast);
1973 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1976 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1981 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1982 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1983 struct net_device *brport;
1985 if (dsa_is_unused_port(chip->ds, port))
1988 brport = dsa_port_to_bridge_port(dp);
1989 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
1990 /* Skip bridged user ports where broadcast
1991 * flooding is disabled.
1995 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2003 struct mv88e6xxx_port_broadcast_sync_ctx {
2009 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2010 const struct mv88e6xxx_vtu_entry *vlan,
2013 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2014 u8 broadcast[ETH_ALEN];
2018 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2020 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2022 eth_broadcast_addr(broadcast);
2024 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2028 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2031 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2035 struct mv88e6xxx_vtu_entry vid0 = {
2040 /* Update the port's private database... */
2041 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2045 /* ...and the database for all VLANs. */
2046 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2050 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2051 u16 vid, u8 member, bool warn)
2053 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2054 struct mv88e6xxx_vtu_entry vlan;
2057 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2062 memset(&vlan, 0, sizeof(vlan));
2064 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2068 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2070 vlan.member[i] = member;
2072 vlan.member[i] = non_member;
2077 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2081 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2084 } else if (vlan.member[port] != member) {
2085 vlan.member[port] = member;
2087 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2091 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2098 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2099 const struct switchdev_obj_port_vlan *vlan,
2100 struct netlink_ext_ack *extack)
2102 struct mv88e6xxx_chip *chip = ds->priv;
2103 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2104 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2112 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2116 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2117 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2119 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2121 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2123 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2124 * and then the CPU port. Do not warn for duplicates for the CPU port.
2126 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2128 mv88e6xxx_reg_lock(chip);
2130 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2132 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2133 vlan->vid, untagged ? 'u' : 't');
2138 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2140 dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2146 mv88e6xxx_reg_unlock(chip);
2151 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2154 struct mv88e6xxx_vtu_entry vlan;
2160 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2164 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2165 * tell switchdev that this VLAN is likely handled in software.
2168 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2171 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2173 /* keep the VLAN unless all ports are excluded */
2175 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2176 if (vlan.member[i] !=
2177 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2183 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2187 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2190 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2191 const struct switchdev_obj_port_vlan *vlan)
2193 struct mv88e6xxx_chip *chip = ds->priv;
2197 if (!mv88e6xxx_max_vid(chip))
2200 mv88e6xxx_reg_lock(chip);
2202 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2206 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2210 if (vlan->vid == pvid) {
2211 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2217 mv88e6xxx_reg_unlock(chip);
2222 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2223 const unsigned char *addr, u16 vid)
2225 struct mv88e6xxx_chip *chip = ds->priv;
2228 mv88e6xxx_reg_lock(chip);
2229 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2230 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2231 mv88e6xxx_reg_unlock(chip);
2236 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2237 const unsigned char *addr, u16 vid)
2239 struct mv88e6xxx_chip *chip = ds->priv;
2242 mv88e6xxx_reg_lock(chip);
2243 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2244 mv88e6xxx_reg_unlock(chip);
2249 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2250 u16 fid, u16 vid, int port,
2251 dsa_fdb_dump_cb_t *cb, void *data)
2253 struct mv88e6xxx_atu_entry addr;
2258 eth_broadcast_addr(addr.mac);
2261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2268 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2271 if (!is_unicast_ether_addr(addr.mac))
2274 is_static = (addr.state ==
2275 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2276 err = cb(addr.mac, vid, is_static, data);
2279 } while (!is_broadcast_ether_addr(addr.mac));
2284 struct mv88e6xxx_port_db_dump_vlan_ctx {
2286 dsa_fdb_dump_cb_t *cb;
2290 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2291 const struct mv88e6xxx_vtu_entry *entry,
2294 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2296 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2297 ctx->port, ctx->cb, ctx->data);
2300 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2301 dsa_fdb_dump_cb_t *cb, void *data)
2303 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2311 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2312 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2316 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2320 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2323 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2324 dsa_fdb_dump_cb_t *cb, void *data)
2326 struct mv88e6xxx_chip *chip = ds->priv;
2329 mv88e6xxx_reg_lock(chip);
2330 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2331 mv88e6xxx_reg_unlock(chip);
2336 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2337 struct net_device *br)
2339 struct dsa_switch *ds = chip->ds;
2340 struct dsa_switch_tree *dst = ds->dst;
2341 struct dsa_port *dp;
2344 list_for_each_entry(dp, &dst->ports, list) {
2345 if (dp->bridge_dev == br) {
2347 /* This is a local bridge group member,
2348 * remap its Port VLAN Map.
2350 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2354 /* This is an external bridge group member,
2355 * remap its cross-chip Port VLAN Table entry.
2357 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2368 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2369 struct net_device *br)
2371 struct mv88e6xxx_chip *chip = ds->priv;
2374 mv88e6xxx_reg_lock(chip);
2375 err = mv88e6xxx_bridge_map(chip, br);
2376 mv88e6xxx_reg_unlock(chip);
2381 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2382 struct net_device *br)
2384 struct mv88e6xxx_chip *chip = ds->priv;
2386 mv88e6xxx_reg_lock(chip);
2387 if (mv88e6xxx_bridge_map(chip, br) ||
2388 mv88e6xxx_port_vlan_map(chip, port))
2389 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2390 mv88e6xxx_reg_unlock(chip);
2393 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2394 int tree_index, int sw_index,
2395 int port, struct net_device *br)
2397 struct mv88e6xxx_chip *chip = ds->priv;
2400 if (tree_index != ds->dst->index)
2403 mv88e6xxx_reg_lock(chip);
2404 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2405 mv88e6xxx_reg_unlock(chip);
2410 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2411 int tree_index, int sw_index,
2412 int port, struct net_device *br)
2414 struct mv88e6xxx_chip *chip = ds->priv;
2416 if (tree_index != ds->dst->index)
2419 mv88e6xxx_reg_lock(chip);
2420 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2421 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2422 mv88e6xxx_reg_unlock(chip);
2425 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2427 if (chip->info->ops->reset)
2428 return chip->info->ops->reset(chip);
2433 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2435 struct gpio_desc *gpiod = chip->reset;
2437 /* If there is a GPIO connected to the reset pin, toggle it */
2439 gpiod_set_value_cansleep(gpiod, 1);
2440 usleep_range(10000, 20000);
2441 gpiod_set_value_cansleep(gpiod, 0);
2442 usleep_range(10000, 20000);
2444 mv88e6xxx_g1_wait_eeprom_done(chip);
2448 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2452 /* Set all ports to the Disabled state */
2453 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2454 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2459 /* Wait for transmit queues to drain,
2460 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2462 usleep_range(2000, 4000);
2467 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2471 err = mv88e6xxx_disable_ports(chip);
2475 mv88e6xxx_hardware_reset(chip);
2477 return mv88e6xxx_software_reset(chip);
2480 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2481 enum mv88e6xxx_frame_mode frame,
2482 enum mv88e6xxx_egress_mode egress, u16 etype)
2486 if (!chip->info->ops->port_set_frame_mode)
2489 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2493 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2497 if (chip->info->ops->port_set_ether_type)
2498 return chip->info->ops->port_set_ether_type(chip, port, etype);
2503 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2505 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2506 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2507 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2510 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2512 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2513 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2514 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2517 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2519 return mv88e6xxx_set_port_mode(chip, port,
2520 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2521 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2525 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2527 if (dsa_is_dsa_port(chip->ds, port))
2528 return mv88e6xxx_set_port_mode_dsa(chip, port);
2530 if (dsa_is_user_port(chip->ds, port))
2531 return mv88e6xxx_set_port_mode_normal(chip, port);
2533 /* Setup CPU port mode depending on its supported tag format */
2534 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
2535 return mv88e6xxx_set_port_mode_dsa(chip, port);
2537 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
2538 return mv88e6xxx_set_port_mode_edsa(chip, port);
2543 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2545 bool message = dsa_is_dsa_port(chip->ds, port);
2547 return mv88e6xxx_port_set_message_port(chip, port, message);
2550 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2554 if (chip->info->ops->port_set_ucast_flood) {
2555 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
2559 if (chip->info->ops->port_set_mcast_flood) {
2560 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
2568 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2570 struct mv88e6xxx_port *mvp = dev_id;
2571 struct mv88e6xxx_chip *chip = mvp->chip;
2572 irqreturn_t ret = IRQ_NONE;
2573 int port = mvp->port;
2576 mv88e6xxx_reg_lock(chip);
2577 lane = mv88e6xxx_serdes_get_lane(chip, port);
2579 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2580 mv88e6xxx_reg_unlock(chip);
2585 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2588 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2592 /* Nothing to request if this SERDES port has no IRQ */
2593 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2597 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2598 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2600 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2601 mv88e6xxx_reg_unlock(chip);
2602 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2603 IRQF_ONESHOT, dev_id->serdes_irq_name,
2605 mv88e6xxx_reg_lock(chip);
2609 dev_id->serdes_irq = irq;
2611 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2614 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2617 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2618 unsigned int irq = dev_id->serdes_irq;
2621 /* Nothing to free if no IRQ has been requested */
2625 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2627 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2628 mv88e6xxx_reg_unlock(chip);
2629 free_irq(irq, dev_id);
2630 mv88e6xxx_reg_lock(chip);
2632 dev_id->serdes_irq = 0;
2637 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2643 lane = mv88e6xxx_serdes_get_lane(chip, port);
2648 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2652 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2654 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2658 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2664 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2665 enum mv88e6xxx_egress_direction direction,
2670 if (!chip->info->ops->set_egress_port)
2673 err = chip->info->ops->set_egress_port(chip, direction, port);
2677 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2678 chip->ingress_dest_port = port;
2680 chip->egress_dest_port = port;
2685 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2687 struct dsa_switch *ds = chip->ds;
2691 upstream_port = dsa_upstream_port(ds, port);
2692 if (chip->info->ops->port_set_upstream_port) {
2693 err = chip->info->ops->port_set_upstream_port(chip, port,
2699 if (port == upstream_port) {
2700 if (chip->info->ops->set_cpu_port) {
2701 err = chip->info->ops->set_cpu_port(chip,
2707 err = mv88e6xxx_set_egress_port(chip,
2708 MV88E6XXX_EGRESS_DIR_INGRESS,
2710 if (err && err != -EOPNOTSUPP)
2713 err = mv88e6xxx_set_egress_port(chip,
2714 MV88E6XXX_EGRESS_DIR_EGRESS,
2716 if (err && err != -EOPNOTSUPP)
2723 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2725 struct dsa_switch *ds = chip->ds;
2729 chip->ports[port].chip = chip;
2730 chip->ports[port].port = port;
2732 /* MAC Forcing register: don't force link, speed, duplex or flow control
2733 * state to any particular values on physical ports, but force the CPU
2734 * port and all DSA ports to their maximum bandwidth and full duplex.
2736 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2737 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2738 SPEED_MAX, DUPLEX_FULL,
2740 PHY_INTERFACE_MODE_NA);
2742 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2743 SPEED_UNFORCED, DUPLEX_UNFORCED,
2745 PHY_INTERFACE_MODE_NA);
2749 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2750 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2751 * tunneling, determine priority by looking at 802.1p and IP
2752 * priority fields (IP prio has precedence), and set STP state
2755 * If this is the CPU link, use DSA or EDSA tagging depending
2756 * on which tagging mode was configured.
2758 * If this is a link to another switch, use DSA tagging mode.
2760 * If this is the upstream port for this switch, enable
2761 * forwarding of unknown unicasts and multicasts.
2763 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2764 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2765 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2766 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2770 err = mv88e6xxx_setup_port_mode(chip, port);
2774 err = mv88e6xxx_setup_egress_floods(chip, port);
2778 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2779 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2780 * untagged frames on this port, do a destination address lookup on all
2781 * received packets as usual, disable ARP mirroring and don't send a
2782 * copy of all transmitted/received frames on this port to the CPU.
2784 err = mv88e6xxx_port_set_map_da(chip, port);
2788 err = mv88e6xxx_setup_upstream_port(chip, port);
2792 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2793 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2797 if (chip->info->ops->port_set_jumbo_size) {
2798 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2803 /* Port Association Vector: disable automatic address learning
2804 * on all user ports since they start out in standalone
2805 * mode. When joining a bridge, learning will be configured to
2806 * match the bridge port settings. Enable learning on all
2807 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2810 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2811 * and RefreshLocked. I.e. setup standard automatic learning.
2813 if (dsa_is_user_port(ds, port))
2818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2823 /* Egress rate control 2: disable egress rate control. */
2824 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2829 if (chip->info->ops->port_pause_limit) {
2830 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2835 if (chip->info->ops->port_disable_learn_limit) {
2836 err = chip->info->ops->port_disable_learn_limit(chip, port);
2841 if (chip->info->ops->port_disable_pri_override) {
2842 err = chip->info->ops->port_disable_pri_override(chip, port);
2847 if (chip->info->ops->port_tag_remap) {
2848 err = chip->info->ops->port_tag_remap(chip, port);
2853 if (chip->info->ops->port_egress_rate_limiting) {
2854 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2859 if (chip->info->ops->port_setup_message_port) {
2860 err = chip->info->ops->port_setup_message_port(chip, port);
2865 /* Port based VLAN map: give each port the same default address
2866 * database, and allow bidirectional communication between the
2867 * CPU and DSA port(s), and the other ports.
2869 err = mv88e6xxx_port_set_fid(chip, port, 0);
2873 err = mv88e6xxx_port_vlan_map(chip, port);
2877 /* Default VLAN ID and priority: don't set a default VLAN
2878 * ID, and set the default packet priority to zero.
2880 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2883 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2885 struct mv88e6xxx_chip *chip = ds->priv;
2887 if (chip->info->ops->port_set_jumbo_size)
2889 else if (chip->info->ops->set_max_frame_size)
2894 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2896 struct mv88e6xxx_chip *chip = ds->priv;
2899 mv88e6xxx_reg_lock(chip);
2900 if (chip->info->ops->port_set_jumbo_size)
2901 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2902 else if (chip->info->ops->set_max_frame_size)
2903 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2907 mv88e6xxx_reg_unlock(chip);
2912 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2913 struct phy_device *phydev)
2915 struct mv88e6xxx_chip *chip = ds->priv;
2918 mv88e6xxx_reg_lock(chip);
2919 err = mv88e6xxx_serdes_power(chip, port, true);
2920 mv88e6xxx_reg_unlock(chip);
2925 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2927 struct mv88e6xxx_chip *chip = ds->priv;
2929 mv88e6xxx_reg_lock(chip);
2930 if (mv88e6xxx_serdes_power(chip, port, false))
2931 dev_err(chip->dev, "failed to power off SERDES\n");
2932 mv88e6xxx_reg_unlock(chip);
2935 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2936 unsigned int ageing_time)
2938 struct mv88e6xxx_chip *chip = ds->priv;
2941 mv88e6xxx_reg_lock(chip);
2942 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2943 mv88e6xxx_reg_unlock(chip);
2948 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2952 /* Initialize the statistics unit */
2953 if (chip->info->ops->stats_set_histogram) {
2954 err = chip->info->ops->stats_set_histogram(chip);
2959 return mv88e6xxx_g1_stats_clear(chip);
2962 /* Check if the errata has already been applied. */
2963 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2969 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2970 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2973 "Error reading hidden register: %d\n", err);
2983 /* The 6390 copper ports have an errata which require poking magic
2984 * values into undocumented hidden registers and then performing a
2987 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2992 if (mv88e6390_setup_errata_applied(chip))
2995 /* Set the ports into blocking mode */
2996 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2997 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3003 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3008 return mv88e6xxx_software_reset(chip);
3011 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3013 mv88e6xxx_teardown_devlink_params(ds);
3014 dsa_devlink_resources_unregister(ds);
3015 mv88e6xxx_teardown_devlink_regions(ds);
3018 static int mv88e6xxx_setup(struct dsa_switch *ds)
3020 struct mv88e6xxx_chip *chip = ds->priv;
3026 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3028 mv88e6xxx_reg_lock(chip);
3030 if (chip->info->ops->setup_errata) {
3031 err = chip->info->ops->setup_errata(chip);
3036 /* Cache the cmode of each port. */
3037 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3038 if (chip->info->ops->port_get_cmode) {
3039 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3043 chip->ports[i].cmode = cmode;
3047 /* Setup Switch Port Registers */
3048 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3049 if (dsa_is_unused_port(ds, i))
3052 /* Prevent the use of an invalid port. */
3053 if (mv88e6xxx_is_invalid_port(chip, i)) {
3054 dev_err(chip->dev, "port %d is invalid\n", i);
3059 err = mv88e6xxx_setup_port(chip, i);
3064 err = mv88e6xxx_irl_setup(chip);
3068 err = mv88e6xxx_mac_setup(chip);
3072 err = mv88e6xxx_phy_setup(chip);
3076 err = mv88e6xxx_vtu_setup(chip);
3080 err = mv88e6xxx_pvt_setup(chip);
3084 err = mv88e6xxx_atu_setup(chip);
3088 err = mv88e6xxx_broadcast_setup(chip, 0);
3092 err = mv88e6xxx_pot_setup(chip);
3096 err = mv88e6xxx_rmu_setup(chip);
3100 err = mv88e6xxx_rsvd2cpu_setup(chip);
3104 err = mv88e6xxx_trunk_setup(chip);
3108 err = mv88e6xxx_devmap_setup(chip);
3112 err = mv88e6xxx_pri_setup(chip);
3116 /* Setup PTP Hardware Clock and timestamping */
3117 if (chip->info->ptp_support) {
3118 err = mv88e6xxx_ptp_setup(chip);
3122 err = mv88e6xxx_hwtstamp_setup(chip);
3127 err = mv88e6xxx_stats_setup(chip);
3132 mv88e6xxx_reg_unlock(chip);
3137 /* Have to be called without holding the register lock, since
3138 * they take the devlink lock, and we later take the locks in
3139 * the reverse order when getting/setting parameters or
3140 * resource occupancy.
3142 err = mv88e6xxx_setup_devlink_resources(ds);
3146 err = mv88e6xxx_setup_devlink_params(ds);
3150 err = mv88e6xxx_setup_devlink_regions(ds);
3157 mv88e6xxx_teardown_devlink_params(ds);
3159 dsa_devlink_resources_unregister(ds);
3164 /* prod_id for switch families which do not have a PHY model number */
3165 static const u16 family_prod_id_table[] = {
3166 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3167 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3168 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3171 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3173 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3174 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3179 if (!chip->info->ops->phy_read)
3182 mv88e6xxx_reg_lock(chip);
3183 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3184 mv88e6xxx_reg_unlock(chip);
3186 /* Some internal PHYs don't have a model number. */
3187 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3188 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3189 prod_id = family_prod_id_table[chip->info->family];
3191 val |= prod_id >> 4;
3194 return err ? err : val;
3197 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3199 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3200 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3203 if (!chip->info->ops->phy_write)
3206 mv88e6xxx_reg_lock(chip);
3207 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3208 mv88e6xxx_reg_unlock(chip);
3213 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3214 struct device_node *np,
3218 struct mv88e6xxx_mdio_bus *mdio_bus;
3219 struct mii_bus *bus;
3223 mv88e6xxx_reg_lock(chip);
3224 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3225 mv88e6xxx_reg_unlock(chip);
3231 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3235 mdio_bus = bus->priv;
3236 mdio_bus->bus = bus;
3237 mdio_bus->chip = chip;
3238 INIT_LIST_HEAD(&mdio_bus->list);
3239 mdio_bus->external = external;
3242 bus->name = np->full_name;
3243 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3245 bus->name = "mv88e6xxx SMI";
3246 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3249 bus->read = mv88e6xxx_mdio_read;
3250 bus->write = mv88e6xxx_mdio_write;
3251 bus->parent = chip->dev;
3254 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3259 err = of_mdiobus_register(bus, np);
3261 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3262 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3267 list_add_tail(&mdio_bus->list, &chip->mdios);
3269 list_add(&mdio_bus->list, &chip->mdios);
3274 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3277 struct mv88e6xxx_mdio_bus *mdio_bus;
3278 struct mii_bus *bus;
3280 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3281 bus = mdio_bus->bus;
3283 if (!mdio_bus->external)
3284 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3286 mdiobus_unregister(bus);
3290 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3291 struct device_node *np)
3293 struct device_node *child;
3296 /* Always register one mdio bus for the internal/default mdio
3297 * bus. This maybe represented in the device tree, but is
3300 child = of_get_child_by_name(np, "mdio");
3301 err = mv88e6xxx_mdio_register(chip, child, false);
3305 /* Walk the device tree, and see if there are any other nodes
3306 * which say they are compatible with the external mdio
3309 for_each_available_child_of_node(np, child) {
3310 if (of_device_is_compatible(
3311 child, "marvell,mv88e6xxx-mdio-external")) {
3312 err = mv88e6xxx_mdio_register(chip, child, true);
3314 mv88e6xxx_mdios_unregister(chip);
3324 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3326 struct mv88e6xxx_chip *chip = ds->priv;
3328 return chip->eeprom_len;
3331 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3332 struct ethtool_eeprom *eeprom, u8 *data)
3334 struct mv88e6xxx_chip *chip = ds->priv;
3337 if (!chip->info->ops->get_eeprom)
3340 mv88e6xxx_reg_lock(chip);
3341 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3342 mv88e6xxx_reg_unlock(chip);
3347 eeprom->magic = 0xc3ec4951;
3352 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3353 struct ethtool_eeprom *eeprom, u8 *data)
3355 struct mv88e6xxx_chip *chip = ds->priv;
3358 if (!chip->info->ops->set_eeprom)
3361 if (eeprom->magic != 0xc3ec4951)
3364 mv88e6xxx_reg_lock(chip);
3365 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3366 mv88e6xxx_reg_unlock(chip);
3371 static const struct mv88e6xxx_ops mv88e6085_ops = {
3372 /* MV88E6XXX_FAMILY_6097 */
3373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3375 .irl_init_all = mv88e6352_g2_irl_init_all,
3376 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3377 .phy_read = mv88e6185_phy_ppu_read,
3378 .phy_write = mv88e6185_phy_ppu_write,
3379 .port_set_link = mv88e6xxx_port_set_link,
3380 .port_sync_link = mv88e6xxx_port_sync_link,
3381 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3382 .port_tag_remap = mv88e6095_port_tag_remap,
3383 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3385 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3386 .port_set_ether_type = mv88e6351_port_set_ether_type,
3387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388 .port_pause_limit = mv88e6097_port_pause_limit,
3389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391 .port_get_cmode = mv88e6185_port_get_cmode,
3392 .port_setup_message_port = mv88e6xxx_setup_message_port,
3393 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3394 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3395 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3396 .stats_get_strings = mv88e6095_stats_get_strings,
3397 .stats_get_stats = mv88e6095_stats_get_stats,
3398 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3399 .set_egress_port = mv88e6095_g1_set_egress_port,
3400 .watchdog_ops = &mv88e6097_watchdog_ops,
3401 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3402 .pot_clear = mv88e6xxx_g2_pot_clear,
3403 .ppu_enable = mv88e6185_g1_ppu_enable,
3404 .ppu_disable = mv88e6185_g1_ppu_disable,
3405 .reset = mv88e6185_g1_reset,
3406 .rmu_disable = mv88e6085_g1_rmu_disable,
3407 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3408 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3409 .phylink_validate = mv88e6185_phylink_validate,
3410 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3413 static const struct mv88e6xxx_ops mv88e6095_ops = {
3414 /* MV88E6XXX_FAMILY_6095 */
3415 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3416 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3417 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3418 .phy_read = mv88e6185_phy_ppu_read,
3419 .phy_write = mv88e6185_phy_ppu_write,
3420 .port_set_link = mv88e6xxx_port_set_link,
3421 .port_sync_link = mv88e6185_port_sync_link,
3422 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3423 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3424 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3425 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3426 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3427 .port_get_cmode = mv88e6185_port_get_cmode,
3428 .port_setup_message_port = mv88e6xxx_setup_message_port,
3429 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3431 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3432 .stats_get_strings = mv88e6095_stats_get_strings,
3433 .stats_get_stats = mv88e6095_stats_get_stats,
3434 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3435 .serdes_power = mv88e6185_serdes_power,
3436 .serdes_get_lane = mv88e6185_serdes_get_lane,
3437 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3438 .ppu_enable = mv88e6185_g1_ppu_enable,
3439 .ppu_disable = mv88e6185_g1_ppu_disable,
3440 .reset = mv88e6185_g1_reset,
3441 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3442 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3443 .phylink_validate = mv88e6185_phylink_validate,
3444 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3447 static const struct mv88e6xxx_ops mv88e6097_ops = {
3448 /* MV88E6XXX_FAMILY_6097 */
3449 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3450 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3451 .irl_init_all = mv88e6352_g2_irl_init_all,
3452 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453 .phy_read = mv88e6xxx_g2_smi_phy_read,
3454 .phy_write = mv88e6xxx_g2_smi_phy_write,
3455 .port_set_link = mv88e6xxx_port_set_link,
3456 .port_sync_link = mv88e6185_port_sync_link,
3457 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3458 .port_tag_remap = mv88e6095_port_tag_remap,
3459 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3460 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3461 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3462 .port_set_ether_type = mv88e6351_port_set_ether_type,
3463 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3464 .port_pause_limit = mv88e6097_port_pause_limit,
3465 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3466 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3467 .port_get_cmode = mv88e6185_port_get_cmode,
3468 .port_setup_message_port = mv88e6xxx_setup_message_port,
3469 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3470 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3471 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3472 .stats_get_strings = mv88e6095_stats_get_strings,
3473 .stats_get_stats = mv88e6095_stats_get_stats,
3474 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3475 .set_egress_port = mv88e6095_g1_set_egress_port,
3476 .watchdog_ops = &mv88e6097_watchdog_ops,
3477 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3478 .serdes_power = mv88e6185_serdes_power,
3479 .serdes_get_lane = mv88e6185_serdes_get_lane,
3480 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3481 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3482 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3483 .serdes_irq_status = mv88e6097_serdes_irq_status,
3484 .pot_clear = mv88e6xxx_g2_pot_clear,
3485 .reset = mv88e6352_g1_reset,
3486 .rmu_disable = mv88e6085_g1_rmu_disable,
3487 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3489 .phylink_validate = mv88e6185_phylink_validate,
3490 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3493 static const struct mv88e6xxx_ops mv88e6123_ops = {
3494 /* MV88E6XXX_FAMILY_6165 */
3495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3496 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3497 .irl_init_all = mv88e6352_g2_irl_init_all,
3498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3499 .phy_read = mv88e6xxx_g2_smi_phy_read,
3500 .phy_write = mv88e6xxx_g2_smi_phy_write,
3501 .port_set_link = mv88e6xxx_port_set_link,
3502 .port_sync_link = mv88e6xxx_port_sync_link,
3503 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3504 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3505 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3506 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3507 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3508 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3509 .port_get_cmode = mv88e6185_port_get_cmode,
3510 .port_setup_message_port = mv88e6xxx_setup_message_port,
3511 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3513 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3514 .stats_get_strings = mv88e6095_stats_get_strings,
3515 .stats_get_stats = mv88e6095_stats_get_stats,
3516 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3517 .set_egress_port = mv88e6095_g1_set_egress_port,
3518 .watchdog_ops = &mv88e6097_watchdog_ops,
3519 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3520 .pot_clear = mv88e6xxx_g2_pot_clear,
3521 .reset = mv88e6352_g1_reset,
3522 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3523 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3524 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3525 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3526 .phylink_validate = mv88e6185_phylink_validate,
3527 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3530 static const struct mv88e6xxx_ops mv88e6131_ops = {
3531 /* MV88E6XXX_FAMILY_6185 */
3532 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3533 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3534 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3535 .phy_read = mv88e6185_phy_ppu_read,
3536 .phy_write = mv88e6185_phy_ppu_write,
3537 .port_set_link = mv88e6xxx_port_set_link,
3538 .port_sync_link = mv88e6xxx_port_sync_link,
3539 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3540 .port_tag_remap = mv88e6095_port_tag_remap,
3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3543 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3544 .port_set_ether_type = mv88e6351_port_set_ether_type,
3545 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3546 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3547 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3548 .port_pause_limit = mv88e6097_port_pause_limit,
3549 .port_set_pause = mv88e6185_port_set_pause,
3550 .port_get_cmode = mv88e6185_port_get_cmode,
3551 .port_setup_message_port = mv88e6xxx_setup_message_port,
3552 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3553 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3554 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3555 .stats_get_strings = mv88e6095_stats_get_strings,
3556 .stats_get_stats = mv88e6095_stats_get_stats,
3557 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3558 .set_egress_port = mv88e6095_g1_set_egress_port,
3559 .watchdog_ops = &mv88e6097_watchdog_ops,
3560 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3561 .ppu_enable = mv88e6185_g1_ppu_enable,
3562 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3563 .ppu_disable = mv88e6185_g1_ppu_disable,
3564 .reset = mv88e6185_g1_reset,
3565 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3566 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3567 .phylink_validate = mv88e6185_phylink_validate,
3570 static const struct mv88e6xxx_ops mv88e6141_ops = {
3571 /* MV88E6XXX_FAMILY_6341 */
3572 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3573 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3574 .irl_init_all = mv88e6352_g2_irl_init_all,
3575 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3576 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3577 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3578 .phy_read = mv88e6xxx_g2_smi_phy_read,
3579 .phy_write = mv88e6xxx_g2_smi_phy_write,
3580 .port_set_link = mv88e6xxx_port_set_link,
3581 .port_sync_link = mv88e6xxx_port_sync_link,
3582 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3583 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3584 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3585 .port_tag_remap = mv88e6095_port_tag_remap,
3586 .port_set_policy = mv88e6352_port_set_policy,
3587 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3588 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3589 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3590 .port_set_ether_type = mv88e6351_port_set_ether_type,
3591 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3592 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3593 .port_pause_limit = mv88e6097_port_pause_limit,
3594 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3595 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3596 .port_get_cmode = mv88e6352_port_get_cmode,
3597 .port_set_cmode = mv88e6341_port_set_cmode,
3598 .port_setup_message_port = mv88e6xxx_setup_message_port,
3599 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3600 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3601 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3602 .stats_get_strings = mv88e6320_stats_get_strings,
3603 .stats_get_stats = mv88e6390_stats_get_stats,
3604 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3605 .set_egress_port = mv88e6390_g1_set_egress_port,
3606 .watchdog_ops = &mv88e6390_watchdog_ops,
3607 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3608 .pot_clear = mv88e6xxx_g2_pot_clear,
3609 .reset = mv88e6352_g1_reset,
3610 .rmu_disable = mv88e6390_g1_rmu_disable,
3611 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3612 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3613 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3614 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3615 .serdes_power = mv88e6390_serdes_power,
3616 .serdes_get_lane = mv88e6341_serdes_get_lane,
3617 /* Check status register pause & lpa register */
3618 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3619 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3620 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3621 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3622 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3623 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3624 .serdes_irq_status = mv88e6390_serdes_irq_status,
3625 .gpio_ops = &mv88e6352_gpio_ops,
3626 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3627 .serdes_get_strings = mv88e6390_serdes_get_strings,
3628 .serdes_get_stats = mv88e6390_serdes_get_stats,
3629 .phylink_validate = mv88e6341_phylink_validate,
3632 static const struct mv88e6xxx_ops mv88e6161_ops = {
3633 /* MV88E6XXX_FAMILY_6165 */
3634 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3635 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3636 .irl_init_all = mv88e6352_g2_irl_init_all,
3637 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3638 .phy_read = mv88e6xxx_g2_smi_phy_read,
3639 .phy_write = mv88e6xxx_g2_smi_phy_write,
3640 .port_set_link = mv88e6xxx_port_set_link,
3641 .port_sync_link = mv88e6xxx_port_sync_link,
3642 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3643 .port_tag_remap = mv88e6095_port_tag_remap,
3644 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3645 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3646 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3647 .port_set_ether_type = mv88e6351_port_set_ether_type,
3648 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3649 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3650 .port_pause_limit = mv88e6097_port_pause_limit,
3651 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3652 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3653 .port_get_cmode = mv88e6185_port_get_cmode,
3654 .port_setup_message_port = mv88e6xxx_setup_message_port,
3655 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3656 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3657 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3658 .stats_get_strings = mv88e6095_stats_get_strings,
3659 .stats_get_stats = mv88e6095_stats_get_stats,
3660 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3661 .set_egress_port = mv88e6095_g1_set_egress_port,
3662 .watchdog_ops = &mv88e6097_watchdog_ops,
3663 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3664 .pot_clear = mv88e6xxx_g2_pot_clear,
3665 .reset = mv88e6352_g1_reset,
3666 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3667 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3668 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3669 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3670 .avb_ops = &mv88e6165_avb_ops,
3671 .ptp_ops = &mv88e6165_ptp_ops,
3672 .phylink_validate = mv88e6185_phylink_validate,
3675 static const struct mv88e6xxx_ops mv88e6165_ops = {
3676 /* MV88E6XXX_FAMILY_6165 */
3677 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3678 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3679 .irl_init_all = mv88e6352_g2_irl_init_all,
3680 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3681 .phy_read = mv88e6165_phy_read,
3682 .phy_write = mv88e6165_phy_write,
3683 .port_set_link = mv88e6xxx_port_set_link,
3684 .port_sync_link = mv88e6xxx_port_sync_link,
3685 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3686 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3687 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3688 .port_get_cmode = mv88e6185_port_get_cmode,
3689 .port_setup_message_port = mv88e6xxx_setup_message_port,
3690 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3692 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3693 .stats_get_strings = mv88e6095_stats_get_strings,
3694 .stats_get_stats = mv88e6095_stats_get_stats,
3695 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3696 .set_egress_port = mv88e6095_g1_set_egress_port,
3697 .watchdog_ops = &mv88e6097_watchdog_ops,
3698 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3699 .pot_clear = mv88e6xxx_g2_pot_clear,
3700 .reset = mv88e6352_g1_reset,
3701 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3702 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3703 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3704 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3705 .avb_ops = &mv88e6165_avb_ops,
3706 .ptp_ops = &mv88e6165_ptp_ops,
3707 .phylink_validate = mv88e6185_phylink_validate,
3710 static const struct mv88e6xxx_ops mv88e6171_ops = {
3711 /* MV88E6XXX_FAMILY_6351 */
3712 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3713 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3714 .irl_init_all = mv88e6352_g2_irl_init_all,
3715 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3716 .phy_read = mv88e6xxx_g2_smi_phy_read,
3717 .phy_write = mv88e6xxx_g2_smi_phy_write,
3718 .port_set_link = mv88e6xxx_port_set_link,
3719 .port_sync_link = mv88e6xxx_port_sync_link,
3720 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3721 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3722 .port_tag_remap = mv88e6095_port_tag_remap,
3723 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3724 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3725 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3726 .port_set_ether_type = mv88e6351_port_set_ether_type,
3727 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3728 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3729 .port_pause_limit = mv88e6097_port_pause_limit,
3730 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3731 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3732 .port_get_cmode = mv88e6352_port_get_cmode,
3733 .port_setup_message_port = mv88e6xxx_setup_message_port,
3734 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3735 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3736 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3737 .stats_get_strings = mv88e6095_stats_get_strings,
3738 .stats_get_stats = mv88e6095_stats_get_stats,
3739 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3740 .set_egress_port = mv88e6095_g1_set_egress_port,
3741 .watchdog_ops = &mv88e6097_watchdog_ops,
3742 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3743 .pot_clear = mv88e6xxx_g2_pot_clear,
3744 .reset = mv88e6352_g1_reset,
3745 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3746 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3747 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3748 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3749 .phylink_validate = mv88e6185_phylink_validate,
3752 static const struct mv88e6xxx_ops mv88e6172_ops = {
3753 /* MV88E6XXX_FAMILY_6352 */
3754 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3755 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3756 .irl_init_all = mv88e6352_g2_irl_init_all,
3757 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3758 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3759 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3760 .phy_read = mv88e6xxx_g2_smi_phy_read,
3761 .phy_write = mv88e6xxx_g2_smi_phy_write,
3762 .port_set_link = mv88e6xxx_port_set_link,
3763 .port_sync_link = mv88e6xxx_port_sync_link,
3764 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3765 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3766 .port_tag_remap = mv88e6095_port_tag_remap,
3767 .port_set_policy = mv88e6352_port_set_policy,
3768 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3769 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3770 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3771 .port_set_ether_type = mv88e6351_port_set_ether_type,
3772 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3773 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3774 .port_pause_limit = mv88e6097_port_pause_limit,
3775 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3776 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3777 .port_get_cmode = mv88e6352_port_get_cmode,
3778 .port_setup_message_port = mv88e6xxx_setup_message_port,
3779 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3780 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3781 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3782 .stats_get_strings = mv88e6095_stats_get_strings,
3783 .stats_get_stats = mv88e6095_stats_get_stats,
3784 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3785 .set_egress_port = mv88e6095_g1_set_egress_port,
3786 .watchdog_ops = &mv88e6097_watchdog_ops,
3787 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3788 .pot_clear = mv88e6xxx_g2_pot_clear,
3789 .reset = mv88e6352_g1_reset,
3790 .rmu_disable = mv88e6352_g1_rmu_disable,
3791 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3792 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3793 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3794 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3795 .serdes_get_lane = mv88e6352_serdes_get_lane,
3796 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3797 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3798 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3799 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3800 .serdes_power = mv88e6352_serdes_power,
3801 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3802 .serdes_get_regs = mv88e6352_serdes_get_regs,
3803 .gpio_ops = &mv88e6352_gpio_ops,
3804 .phylink_validate = mv88e6352_phylink_validate,
3807 static const struct mv88e6xxx_ops mv88e6175_ops = {
3808 /* MV88E6XXX_FAMILY_6351 */
3809 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3810 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3811 .irl_init_all = mv88e6352_g2_irl_init_all,
3812 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3813 .phy_read = mv88e6xxx_g2_smi_phy_read,
3814 .phy_write = mv88e6xxx_g2_smi_phy_write,
3815 .port_set_link = mv88e6xxx_port_set_link,
3816 .port_sync_link = mv88e6xxx_port_sync_link,
3817 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3818 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3819 .port_tag_remap = mv88e6095_port_tag_remap,
3820 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3821 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3822 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3823 .port_set_ether_type = mv88e6351_port_set_ether_type,
3824 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3825 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3826 .port_pause_limit = mv88e6097_port_pause_limit,
3827 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3828 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3829 .port_get_cmode = mv88e6352_port_get_cmode,
3830 .port_setup_message_port = mv88e6xxx_setup_message_port,
3831 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3832 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3833 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3834 .stats_get_strings = mv88e6095_stats_get_strings,
3835 .stats_get_stats = mv88e6095_stats_get_stats,
3836 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3837 .set_egress_port = mv88e6095_g1_set_egress_port,
3838 .watchdog_ops = &mv88e6097_watchdog_ops,
3839 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3840 .pot_clear = mv88e6xxx_g2_pot_clear,
3841 .reset = mv88e6352_g1_reset,
3842 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3843 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3844 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3845 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3846 .phylink_validate = mv88e6185_phylink_validate,
3849 static const struct mv88e6xxx_ops mv88e6176_ops = {
3850 /* MV88E6XXX_FAMILY_6352 */
3851 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3852 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3853 .irl_init_all = mv88e6352_g2_irl_init_all,
3854 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3855 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3856 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3857 .phy_read = mv88e6xxx_g2_smi_phy_read,
3858 .phy_write = mv88e6xxx_g2_smi_phy_write,
3859 .port_set_link = mv88e6xxx_port_set_link,
3860 .port_sync_link = mv88e6xxx_port_sync_link,
3861 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3862 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3863 .port_tag_remap = mv88e6095_port_tag_remap,
3864 .port_set_policy = mv88e6352_port_set_policy,
3865 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3866 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3867 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3868 .port_set_ether_type = mv88e6351_port_set_ether_type,
3869 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3870 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3871 .port_pause_limit = mv88e6097_port_pause_limit,
3872 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3873 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3874 .port_get_cmode = mv88e6352_port_get_cmode,
3875 .port_setup_message_port = mv88e6xxx_setup_message_port,
3876 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3877 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3878 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3879 .stats_get_strings = mv88e6095_stats_get_strings,
3880 .stats_get_stats = mv88e6095_stats_get_stats,
3881 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3882 .set_egress_port = mv88e6095_g1_set_egress_port,
3883 .watchdog_ops = &mv88e6097_watchdog_ops,
3884 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3885 .pot_clear = mv88e6xxx_g2_pot_clear,
3886 .reset = mv88e6352_g1_reset,
3887 .rmu_disable = mv88e6352_g1_rmu_disable,
3888 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3889 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3890 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3891 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3892 .serdes_get_lane = mv88e6352_serdes_get_lane,
3893 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3894 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3895 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3896 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3897 .serdes_power = mv88e6352_serdes_power,
3898 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3899 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3900 .serdes_irq_status = mv88e6352_serdes_irq_status,
3901 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3902 .serdes_get_regs = mv88e6352_serdes_get_regs,
3903 .gpio_ops = &mv88e6352_gpio_ops,
3904 .phylink_validate = mv88e6352_phylink_validate,
3907 static const struct mv88e6xxx_ops mv88e6185_ops = {
3908 /* MV88E6XXX_FAMILY_6185 */
3909 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3910 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3911 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3912 .phy_read = mv88e6185_phy_ppu_read,
3913 .phy_write = mv88e6185_phy_ppu_write,
3914 .port_set_link = mv88e6xxx_port_set_link,
3915 .port_sync_link = mv88e6185_port_sync_link,
3916 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3917 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3918 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3919 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3920 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3921 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3922 .port_set_pause = mv88e6185_port_set_pause,
3923 .port_get_cmode = mv88e6185_port_get_cmode,
3924 .port_setup_message_port = mv88e6xxx_setup_message_port,
3925 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3926 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3927 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3928 .stats_get_strings = mv88e6095_stats_get_strings,
3929 .stats_get_stats = mv88e6095_stats_get_stats,
3930 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3931 .set_egress_port = mv88e6095_g1_set_egress_port,
3932 .watchdog_ops = &mv88e6097_watchdog_ops,
3933 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3934 .serdes_power = mv88e6185_serdes_power,
3935 .serdes_get_lane = mv88e6185_serdes_get_lane,
3936 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3937 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3938 .ppu_enable = mv88e6185_g1_ppu_enable,
3939 .ppu_disable = mv88e6185_g1_ppu_disable,
3940 .reset = mv88e6185_g1_reset,
3941 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3942 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3943 .phylink_validate = mv88e6185_phylink_validate,
3944 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3947 static const struct mv88e6xxx_ops mv88e6190_ops = {
3948 /* MV88E6XXX_FAMILY_6390 */
3949 .setup_errata = mv88e6390_setup_errata,
3950 .irl_init_all = mv88e6390_g2_irl_init_all,
3951 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3952 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3953 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3954 .phy_read = mv88e6xxx_g2_smi_phy_read,
3955 .phy_write = mv88e6xxx_g2_smi_phy_write,
3956 .port_set_link = mv88e6xxx_port_set_link,
3957 .port_sync_link = mv88e6xxx_port_sync_link,
3958 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3959 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3960 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3961 .port_tag_remap = mv88e6390_port_tag_remap,
3962 .port_set_policy = mv88e6352_port_set_policy,
3963 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3964 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3965 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3966 .port_set_ether_type = mv88e6351_port_set_ether_type,
3967 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3968 .port_pause_limit = mv88e6390_port_pause_limit,
3969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3971 .port_get_cmode = mv88e6352_port_get_cmode,
3972 .port_set_cmode = mv88e6390_port_set_cmode,
3973 .port_setup_message_port = mv88e6xxx_setup_message_port,
3974 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3975 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3976 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3977 .stats_get_strings = mv88e6320_stats_get_strings,
3978 .stats_get_stats = mv88e6390_stats_get_stats,
3979 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3980 .set_egress_port = mv88e6390_g1_set_egress_port,
3981 .watchdog_ops = &mv88e6390_watchdog_ops,
3982 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3983 .pot_clear = mv88e6xxx_g2_pot_clear,
3984 .reset = mv88e6352_g1_reset,
3985 .rmu_disable = mv88e6390_g1_rmu_disable,
3986 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3987 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3988 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3989 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3990 .serdes_power = mv88e6390_serdes_power,
3991 .serdes_get_lane = mv88e6390_serdes_get_lane,
3992 /* Check status register pause & lpa register */
3993 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3994 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3995 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3996 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3997 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3998 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3999 .serdes_irq_status = mv88e6390_serdes_irq_status,
4000 .serdes_get_strings = mv88e6390_serdes_get_strings,
4001 .serdes_get_stats = mv88e6390_serdes_get_stats,
4002 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4003 .serdes_get_regs = mv88e6390_serdes_get_regs,
4004 .gpio_ops = &mv88e6352_gpio_ops,
4005 .phylink_validate = mv88e6390_phylink_validate,
4008 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4009 /* MV88E6XXX_FAMILY_6390 */
4010 .setup_errata = mv88e6390_setup_errata,
4011 .irl_init_all = mv88e6390_g2_irl_init_all,
4012 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4013 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4014 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4015 .phy_read = mv88e6xxx_g2_smi_phy_read,
4016 .phy_write = mv88e6xxx_g2_smi_phy_write,
4017 .port_set_link = mv88e6xxx_port_set_link,
4018 .port_sync_link = mv88e6xxx_port_sync_link,
4019 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4020 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4021 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4022 .port_tag_remap = mv88e6390_port_tag_remap,
4023 .port_set_policy = mv88e6352_port_set_policy,
4024 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4025 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4026 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4027 .port_set_ether_type = mv88e6351_port_set_ether_type,
4028 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4029 .port_pause_limit = mv88e6390_port_pause_limit,
4030 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4031 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4032 .port_get_cmode = mv88e6352_port_get_cmode,
4033 .port_set_cmode = mv88e6390x_port_set_cmode,
4034 .port_setup_message_port = mv88e6xxx_setup_message_port,
4035 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4036 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4037 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4038 .stats_get_strings = mv88e6320_stats_get_strings,
4039 .stats_get_stats = mv88e6390_stats_get_stats,
4040 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4041 .set_egress_port = mv88e6390_g1_set_egress_port,
4042 .watchdog_ops = &mv88e6390_watchdog_ops,
4043 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4044 .pot_clear = mv88e6xxx_g2_pot_clear,
4045 .reset = mv88e6352_g1_reset,
4046 .rmu_disable = mv88e6390_g1_rmu_disable,
4047 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4048 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4049 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4050 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4051 .serdes_power = mv88e6390_serdes_power,
4052 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4053 /* Check status register pause & lpa register */
4054 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4055 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4056 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4057 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4058 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4059 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4060 .serdes_irq_status = mv88e6390_serdes_irq_status,
4061 .serdes_get_strings = mv88e6390_serdes_get_strings,
4062 .serdes_get_stats = mv88e6390_serdes_get_stats,
4063 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4064 .serdes_get_regs = mv88e6390_serdes_get_regs,
4065 .gpio_ops = &mv88e6352_gpio_ops,
4066 .phylink_validate = mv88e6390x_phylink_validate,
4069 static const struct mv88e6xxx_ops mv88e6191_ops = {
4070 /* MV88E6XXX_FAMILY_6390 */
4071 .setup_errata = mv88e6390_setup_errata,
4072 .irl_init_all = mv88e6390_g2_irl_init_all,
4073 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4074 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4075 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4076 .phy_read = mv88e6xxx_g2_smi_phy_read,
4077 .phy_write = mv88e6xxx_g2_smi_phy_write,
4078 .port_set_link = mv88e6xxx_port_set_link,
4079 .port_sync_link = mv88e6xxx_port_sync_link,
4080 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4081 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4082 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4083 .port_tag_remap = mv88e6390_port_tag_remap,
4084 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4085 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4086 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4087 .port_set_ether_type = mv88e6351_port_set_ether_type,
4088 .port_pause_limit = mv88e6390_port_pause_limit,
4089 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4090 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4091 .port_get_cmode = mv88e6352_port_get_cmode,
4092 .port_set_cmode = mv88e6390_port_set_cmode,
4093 .port_setup_message_port = mv88e6xxx_setup_message_port,
4094 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4095 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4096 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4097 .stats_get_strings = mv88e6320_stats_get_strings,
4098 .stats_get_stats = mv88e6390_stats_get_stats,
4099 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4100 .set_egress_port = mv88e6390_g1_set_egress_port,
4101 .watchdog_ops = &mv88e6390_watchdog_ops,
4102 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4103 .pot_clear = mv88e6xxx_g2_pot_clear,
4104 .reset = mv88e6352_g1_reset,
4105 .rmu_disable = mv88e6390_g1_rmu_disable,
4106 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4107 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4108 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4109 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4110 .serdes_power = mv88e6390_serdes_power,
4111 .serdes_get_lane = mv88e6390_serdes_get_lane,
4112 /* Check status register pause & lpa register */
4113 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4114 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4115 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4116 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4117 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4118 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4119 .serdes_irq_status = mv88e6390_serdes_irq_status,
4120 .serdes_get_strings = mv88e6390_serdes_get_strings,
4121 .serdes_get_stats = mv88e6390_serdes_get_stats,
4122 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4123 .serdes_get_regs = mv88e6390_serdes_get_regs,
4124 .avb_ops = &mv88e6390_avb_ops,
4125 .ptp_ops = &mv88e6352_ptp_ops,
4126 .phylink_validate = mv88e6390_phylink_validate,
4129 static const struct mv88e6xxx_ops mv88e6240_ops = {
4130 /* MV88E6XXX_FAMILY_6352 */
4131 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4132 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4133 .irl_init_all = mv88e6352_g2_irl_init_all,
4134 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4135 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4136 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4137 .phy_read = mv88e6xxx_g2_smi_phy_read,
4138 .phy_write = mv88e6xxx_g2_smi_phy_write,
4139 .port_set_link = mv88e6xxx_port_set_link,
4140 .port_sync_link = mv88e6xxx_port_sync_link,
4141 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4142 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4143 .port_tag_remap = mv88e6095_port_tag_remap,
4144 .port_set_policy = mv88e6352_port_set_policy,
4145 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4146 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4147 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4148 .port_set_ether_type = mv88e6351_port_set_ether_type,
4149 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4150 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4151 .port_pause_limit = mv88e6097_port_pause_limit,
4152 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4153 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4154 .port_get_cmode = mv88e6352_port_get_cmode,
4155 .port_setup_message_port = mv88e6xxx_setup_message_port,
4156 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4157 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4158 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4159 .stats_get_strings = mv88e6095_stats_get_strings,
4160 .stats_get_stats = mv88e6095_stats_get_stats,
4161 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4162 .set_egress_port = mv88e6095_g1_set_egress_port,
4163 .watchdog_ops = &mv88e6097_watchdog_ops,
4164 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4165 .pot_clear = mv88e6xxx_g2_pot_clear,
4166 .reset = mv88e6352_g1_reset,
4167 .rmu_disable = mv88e6352_g1_rmu_disable,
4168 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4169 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4170 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4171 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4172 .serdes_get_lane = mv88e6352_serdes_get_lane,
4173 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4174 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4175 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4176 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4177 .serdes_power = mv88e6352_serdes_power,
4178 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4179 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4180 .serdes_irq_status = mv88e6352_serdes_irq_status,
4181 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4182 .serdes_get_regs = mv88e6352_serdes_get_regs,
4183 .gpio_ops = &mv88e6352_gpio_ops,
4184 .avb_ops = &mv88e6352_avb_ops,
4185 .ptp_ops = &mv88e6352_ptp_ops,
4186 .phylink_validate = mv88e6352_phylink_validate,
4189 static const struct mv88e6xxx_ops mv88e6250_ops = {
4190 /* MV88E6XXX_FAMILY_6250 */
4191 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4192 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4193 .irl_init_all = mv88e6352_g2_irl_init_all,
4194 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4195 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4196 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4197 .phy_read = mv88e6xxx_g2_smi_phy_read,
4198 .phy_write = mv88e6xxx_g2_smi_phy_write,
4199 .port_set_link = mv88e6xxx_port_set_link,
4200 .port_sync_link = mv88e6xxx_port_sync_link,
4201 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4202 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4203 .port_tag_remap = mv88e6095_port_tag_remap,
4204 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4205 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4206 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4207 .port_set_ether_type = mv88e6351_port_set_ether_type,
4208 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4209 .port_pause_limit = mv88e6097_port_pause_limit,
4210 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4211 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4212 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4213 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4214 .stats_get_strings = mv88e6250_stats_get_strings,
4215 .stats_get_stats = mv88e6250_stats_get_stats,
4216 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4217 .set_egress_port = mv88e6095_g1_set_egress_port,
4218 .watchdog_ops = &mv88e6250_watchdog_ops,
4219 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4220 .pot_clear = mv88e6xxx_g2_pot_clear,
4221 .reset = mv88e6250_g1_reset,
4222 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4223 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4224 .avb_ops = &mv88e6352_avb_ops,
4225 .ptp_ops = &mv88e6250_ptp_ops,
4226 .phylink_validate = mv88e6065_phylink_validate,
4229 static const struct mv88e6xxx_ops mv88e6290_ops = {
4230 /* MV88E6XXX_FAMILY_6390 */
4231 .setup_errata = mv88e6390_setup_errata,
4232 .irl_init_all = mv88e6390_g2_irl_init_all,
4233 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4234 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4236 .phy_read = mv88e6xxx_g2_smi_phy_read,
4237 .phy_write = mv88e6xxx_g2_smi_phy_write,
4238 .port_set_link = mv88e6xxx_port_set_link,
4239 .port_sync_link = mv88e6xxx_port_sync_link,
4240 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4241 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4242 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4243 .port_tag_remap = mv88e6390_port_tag_remap,
4244 .port_set_policy = mv88e6352_port_set_policy,
4245 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4246 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4247 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4248 .port_set_ether_type = mv88e6351_port_set_ether_type,
4249 .port_pause_limit = mv88e6390_port_pause_limit,
4250 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4251 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4252 .port_get_cmode = mv88e6352_port_get_cmode,
4253 .port_set_cmode = mv88e6390_port_set_cmode,
4254 .port_setup_message_port = mv88e6xxx_setup_message_port,
4255 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4256 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4257 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4258 .stats_get_strings = mv88e6320_stats_get_strings,
4259 .stats_get_stats = mv88e6390_stats_get_stats,
4260 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4261 .set_egress_port = mv88e6390_g1_set_egress_port,
4262 .watchdog_ops = &mv88e6390_watchdog_ops,
4263 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4264 .pot_clear = mv88e6xxx_g2_pot_clear,
4265 .reset = mv88e6352_g1_reset,
4266 .rmu_disable = mv88e6390_g1_rmu_disable,
4267 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4268 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4269 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4270 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4271 .serdes_power = mv88e6390_serdes_power,
4272 .serdes_get_lane = mv88e6390_serdes_get_lane,
4273 /* Check status register pause & lpa register */
4274 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4275 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4276 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4277 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4278 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4279 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4280 .serdes_irq_status = mv88e6390_serdes_irq_status,
4281 .serdes_get_strings = mv88e6390_serdes_get_strings,
4282 .serdes_get_stats = mv88e6390_serdes_get_stats,
4283 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4284 .serdes_get_regs = mv88e6390_serdes_get_regs,
4285 .gpio_ops = &mv88e6352_gpio_ops,
4286 .avb_ops = &mv88e6390_avb_ops,
4287 .ptp_ops = &mv88e6352_ptp_ops,
4288 .phylink_validate = mv88e6390_phylink_validate,
4291 static const struct mv88e6xxx_ops mv88e6320_ops = {
4292 /* MV88E6XXX_FAMILY_6320 */
4293 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4294 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4295 .irl_init_all = mv88e6352_g2_irl_init_all,
4296 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4297 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4299 .phy_read = mv88e6xxx_g2_smi_phy_read,
4300 .phy_write = mv88e6xxx_g2_smi_phy_write,
4301 .port_set_link = mv88e6xxx_port_set_link,
4302 .port_sync_link = mv88e6xxx_port_sync_link,
4303 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4304 .port_tag_remap = mv88e6095_port_tag_remap,
4305 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4306 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4307 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4308 .port_set_ether_type = mv88e6351_port_set_ether_type,
4309 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4310 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4311 .port_pause_limit = mv88e6097_port_pause_limit,
4312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4314 .port_get_cmode = mv88e6352_port_get_cmode,
4315 .port_setup_message_port = mv88e6xxx_setup_message_port,
4316 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4318 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4319 .stats_get_strings = mv88e6320_stats_get_strings,
4320 .stats_get_stats = mv88e6320_stats_get_stats,
4321 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4322 .set_egress_port = mv88e6095_g1_set_egress_port,
4323 .watchdog_ops = &mv88e6390_watchdog_ops,
4324 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4325 .pot_clear = mv88e6xxx_g2_pot_clear,
4326 .reset = mv88e6352_g1_reset,
4327 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4328 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4329 .gpio_ops = &mv88e6352_gpio_ops,
4330 .avb_ops = &mv88e6352_avb_ops,
4331 .ptp_ops = &mv88e6352_ptp_ops,
4332 .phylink_validate = mv88e6185_phylink_validate,
4335 static const struct mv88e6xxx_ops mv88e6321_ops = {
4336 /* MV88E6XXX_FAMILY_6320 */
4337 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4338 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4339 .irl_init_all = mv88e6352_g2_irl_init_all,
4340 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4341 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4343 .phy_read = mv88e6xxx_g2_smi_phy_read,
4344 .phy_write = mv88e6xxx_g2_smi_phy_write,
4345 .port_set_link = mv88e6xxx_port_set_link,
4346 .port_sync_link = mv88e6xxx_port_sync_link,
4347 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4348 .port_tag_remap = mv88e6095_port_tag_remap,
4349 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4350 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4351 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4352 .port_set_ether_type = mv88e6351_port_set_ether_type,
4353 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4354 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4355 .port_pause_limit = mv88e6097_port_pause_limit,
4356 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4357 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4358 .port_get_cmode = mv88e6352_port_get_cmode,
4359 .port_setup_message_port = mv88e6xxx_setup_message_port,
4360 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4361 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4362 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4363 .stats_get_strings = mv88e6320_stats_get_strings,
4364 .stats_get_stats = mv88e6320_stats_get_stats,
4365 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4366 .set_egress_port = mv88e6095_g1_set_egress_port,
4367 .watchdog_ops = &mv88e6390_watchdog_ops,
4368 .reset = mv88e6352_g1_reset,
4369 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4370 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4371 .gpio_ops = &mv88e6352_gpio_ops,
4372 .avb_ops = &mv88e6352_avb_ops,
4373 .ptp_ops = &mv88e6352_ptp_ops,
4374 .phylink_validate = mv88e6185_phylink_validate,
4377 static const struct mv88e6xxx_ops mv88e6341_ops = {
4378 /* MV88E6XXX_FAMILY_6341 */
4379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4380 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4381 .irl_init_all = mv88e6352_g2_irl_init_all,
4382 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4383 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4385 .phy_read = mv88e6xxx_g2_smi_phy_read,
4386 .phy_write = mv88e6xxx_g2_smi_phy_write,
4387 .port_set_link = mv88e6xxx_port_set_link,
4388 .port_sync_link = mv88e6xxx_port_sync_link,
4389 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4390 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4391 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4392 .port_tag_remap = mv88e6095_port_tag_remap,
4393 .port_set_policy = mv88e6352_port_set_policy,
4394 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4395 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4396 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4397 .port_set_ether_type = mv88e6351_port_set_ether_type,
4398 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4399 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4400 .port_pause_limit = mv88e6097_port_pause_limit,
4401 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4402 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4403 .port_get_cmode = mv88e6352_port_get_cmode,
4404 .port_set_cmode = mv88e6341_port_set_cmode,
4405 .port_setup_message_port = mv88e6xxx_setup_message_port,
4406 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4407 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4408 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4409 .stats_get_strings = mv88e6320_stats_get_strings,
4410 .stats_get_stats = mv88e6390_stats_get_stats,
4411 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4412 .set_egress_port = mv88e6390_g1_set_egress_port,
4413 .watchdog_ops = &mv88e6390_watchdog_ops,
4414 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4415 .pot_clear = mv88e6xxx_g2_pot_clear,
4416 .reset = mv88e6352_g1_reset,
4417 .rmu_disable = mv88e6390_g1_rmu_disable,
4418 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4419 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4420 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4421 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4422 .serdes_power = mv88e6390_serdes_power,
4423 .serdes_get_lane = mv88e6341_serdes_get_lane,
4424 /* Check status register pause & lpa register */
4425 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4426 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4427 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4428 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4429 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4430 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4431 .serdes_irq_status = mv88e6390_serdes_irq_status,
4432 .gpio_ops = &mv88e6352_gpio_ops,
4433 .avb_ops = &mv88e6390_avb_ops,
4434 .ptp_ops = &mv88e6352_ptp_ops,
4435 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4436 .serdes_get_strings = mv88e6390_serdes_get_strings,
4437 .serdes_get_stats = mv88e6390_serdes_get_stats,
4438 .phylink_validate = mv88e6341_phylink_validate,
4441 static const struct mv88e6xxx_ops mv88e6350_ops = {
4442 /* MV88E6XXX_FAMILY_6351 */
4443 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4444 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4445 .irl_init_all = mv88e6352_g2_irl_init_all,
4446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4447 .phy_read = mv88e6xxx_g2_smi_phy_read,
4448 .phy_write = mv88e6xxx_g2_smi_phy_write,
4449 .port_set_link = mv88e6xxx_port_set_link,
4450 .port_sync_link = mv88e6xxx_port_sync_link,
4451 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4452 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4453 .port_tag_remap = mv88e6095_port_tag_remap,
4454 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4455 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4456 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4457 .port_set_ether_type = mv88e6351_port_set_ether_type,
4458 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4460 .port_pause_limit = mv88e6097_port_pause_limit,
4461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4463 .port_get_cmode = mv88e6352_port_get_cmode,
4464 .port_setup_message_port = mv88e6xxx_setup_message_port,
4465 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4466 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4467 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4468 .stats_get_strings = mv88e6095_stats_get_strings,
4469 .stats_get_stats = mv88e6095_stats_get_stats,
4470 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4471 .set_egress_port = mv88e6095_g1_set_egress_port,
4472 .watchdog_ops = &mv88e6097_watchdog_ops,
4473 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4474 .pot_clear = mv88e6xxx_g2_pot_clear,
4475 .reset = mv88e6352_g1_reset,
4476 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4477 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4478 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4479 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4480 .phylink_validate = mv88e6185_phylink_validate,
4483 static const struct mv88e6xxx_ops mv88e6351_ops = {
4484 /* MV88E6XXX_FAMILY_6351 */
4485 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4486 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4487 .irl_init_all = mv88e6352_g2_irl_init_all,
4488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4489 .phy_read = mv88e6xxx_g2_smi_phy_read,
4490 .phy_write = mv88e6xxx_g2_smi_phy_write,
4491 .port_set_link = mv88e6xxx_port_set_link,
4492 .port_sync_link = mv88e6xxx_port_sync_link,
4493 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4494 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4495 .port_tag_remap = mv88e6095_port_tag_remap,
4496 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4497 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4498 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4499 .port_set_ether_type = mv88e6351_port_set_ether_type,
4500 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4501 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4502 .port_pause_limit = mv88e6097_port_pause_limit,
4503 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4504 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4505 .port_get_cmode = mv88e6352_port_get_cmode,
4506 .port_setup_message_port = mv88e6xxx_setup_message_port,
4507 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4508 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4509 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4510 .stats_get_strings = mv88e6095_stats_get_strings,
4511 .stats_get_stats = mv88e6095_stats_get_stats,
4512 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4513 .set_egress_port = mv88e6095_g1_set_egress_port,
4514 .watchdog_ops = &mv88e6097_watchdog_ops,
4515 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4516 .pot_clear = mv88e6xxx_g2_pot_clear,
4517 .reset = mv88e6352_g1_reset,
4518 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4519 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4520 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4521 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4522 .avb_ops = &mv88e6352_avb_ops,
4523 .ptp_ops = &mv88e6352_ptp_ops,
4524 .phylink_validate = mv88e6185_phylink_validate,
4527 static const struct mv88e6xxx_ops mv88e6352_ops = {
4528 /* MV88E6XXX_FAMILY_6352 */
4529 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4530 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4531 .irl_init_all = mv88e6352_g2_irl_init_all,
4532 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4533 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4534 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4535 .phy_read = mv88e6xxx_g2_smi_phy_read,
4536 .phy_write = mv88e6xxx_g2_smi_phy_write,
4537 .port_set_link = mv88e6xxx_port_set_link,
4538 .port_sync_link = mv88e6xxx_port_sync_link,
4539 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4540 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4541 .port_tag_remap = mv88e6095_port_tag_remap,
4542 .port_set_policy = mv88e6352_port_set_policy,
4543 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4544 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4545 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4546 .port_set_ether_type = mv88e6351_port_set_ether_type,
4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4549 .port_pause_limit = mv88e6097_port_pause_limit,
4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4552 .port_get_cmode = mv88e6352_port_get_cmode,
4553 .port_setup_message_port = mv88e6xxx_setup_message_port,
4554 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4555 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4556 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4557 .stats_get_strings = mv88e6095_stats_get_strings,
4558 .stats_get_stats = mv88e6095_stats_get_stats,
4559 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4560 .set_egress_port = mv88e6095_g1_set_egress_port,
4561 .watchdog_ops = &mv88e6097_watchdog_ops,
4562 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4563 .pot_clear = mv88e6xxx_g2_pot_clear,
4564 .reset = mv88e6352_g1_reset,
4565 .rmu_disable = mv88e6352_g1_rmu_disable,
4566 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4567 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4568 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4569 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4570 .serdes_get_lane = mv88e6352_serdes_get_lane,
4571 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4572 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4573 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4574 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4575 .serdes_power = mv88e6352_serdes_power,
4576 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4577 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4578 .serdes_irq_status = mv88e6352_serdes_irq_status,
4579 .gpio_ops = &mv88e6352_gpio_ops,
4580 .avb_ops = &mv88e6352_avb_ops,
4581 .ptp_ops = &mv88e6352_ptp_ops,
4582 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4583 .serdes_get_strings = mv88e6352_serdes_get_strings,
4584 .serdes_get_stats = mv88e6352_serdes_get_stats,
4585 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4586 .serdes_get_regs = mv88e6352_serdes_get_regs,
4587 .phylink_validate = mv88e6352_phylink_validate,
4590 static const struct mv88e6xxx_ops mv88e6390_ops = {
4591 /* MV88E6XXX_FAMILY_6390 */
4592 .setup_errata = mv88e6390_setup_errata,
4593 .irl_init_all = mv88e6390_g2_irl_init_all,
4594 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4595 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4596 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4597 .phy_read = mv88e6xxx_g2_smi_phy_read,
4598 .phy_write = mv88e6xxx_g2_smi_phy_write,
4599 .port_set_link = mv88e6xxx_port_set_link,
4600 .port_sync_link = mv88e6xxx_port_sync_link,
4601 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4602 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4603 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4604 .port_tag_remap = mv88e6390_port_tag_remap,
4605 .port_set_policy = mv88e6352_port_set_policy,
4606 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4607 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4608 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4609 .port_set_ether_type = mv88e6351_port_set_ether_type,
4610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4611 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4612 .port_pause_limit = mv88e6390_port_pause_limit,
4613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4615 .port_get_cmode = mv88e6352_port_get_cmode,
4616 .port_set_cmode = mv88e6390_port_set_cmode,
4617 .port_setup_message_port = mv88e6xxx_setup_message_port,
4618 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4619 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4620 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4621 .stats_get_strings = mv88e6320_stats_get_strings,
4622 .stats_get_stats = mv88e6390_stats_get_stats,
4623 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4624 .set_egress_port = mv88e6390_g1_set_egress_port,
4625 .watchdog_ops = &mv88e6390_watchdog_ops,
4626 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4627 .pot_clear = mv88e6xxx_g2_pot_clear,
4628 .reset = mv88e6352_g1_reset,
4629 .rmu_disable = mv88e6390_g1_rmu_disable,
4630 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4631 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4632 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4633 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4634 .serdes_power = mv88e6390_serdes_power,
4635 .serdes_get_lane = mv88e6390_serdes_get_lane,
4636 /* Check status register pause & lpa register */
4637 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4638 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4639 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4640 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4641 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4642 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4643 .serdes_irq_status = mv88e6390_serdes_irq_status,
4644 .gpio_ops = &mv88e6352_gpio_ops,
4645 .avb_ops = &mv88e6390_avb_ops,
4646 .ptp_ops = &mv88e6352_ptp_ops,
4647 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4648 .serdes_get_strings = mv88e6390_serdes_get_strings,
4649 .serdes_get_stats = mv88e6390_serdes_get_stats,
4650 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4651 .serdes_get_regs = mv88e6390_serdes_get_regs,
4652 .phylink_validate = mv88e6390_phylink_validate,
4655 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4656 /* MV88E6XXX_FAMILY_6390 */
4657 .setup_errata = mv88e6390_setup_errata,
4658 .irl_init_all = mv88e6390_g2_irl_init_all,
4659 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4660 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4661 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4662 .phy_read = mv88e6xxx_g2_smi_phy_read,
4663 .phy_write = mv88e6xxx_g2_smi_phy_write,
4664 .port_set_link = mv88e6xxx_port_set_link,
4665 .port_sync_link = mv88e6xxx_port_sync_link,
4666 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4667 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4668 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4669 .port_tag_remap = mv88e6390_port_tag_remap,
4670 .port_set_policy = mv88e6352_port_set_policy,
4671 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4672 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4673 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4674 .port_set_ether_type = mv88e6351_port_set_ether_type,
4675 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4676 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4677 .port_pause_limit = mv88e6390_port_pause_limit,
4678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4680 .port_get_cmode = mv88e6352_port_get_cmode,
4681 .port_set_cmode = mv88e6390x_port_set_cmode,
4682 .port_setup_message_port = mv88e6xxx_setup_message_port,
4683 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4684 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4685 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4686 .stats_get_strings = mv88e6320_stats_get_strings,
4687 .stats_get_stats = mv88e6390_stats_get_stats,
4688 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4689 .set_egress_port = mv88e6390_g1_set_egress_port,
4690 .watchdog_ops = &mv88e6390_watchdog_ops,
4691 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4692 .pot_clear = mv88e6xxx_g2_pot_clear,
4693 .reset = mv88e6352_g1_reset,
4694 .rmu_disable = mv88e6390_g1_rmu_disable,
4695 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4696 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4697 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4698 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4699 .serdes_power = mv88e6390_serdes_power,
4700 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4701 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4702 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4703 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4704 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4705 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4706 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4707 .serdes_irq_status = mv88e6390_serdes_irq_status,
4708 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4709 .serdes_get_strings = mv88e6390_serdes_get_strings,
4710 .serdes_get_stats = mv88e6390_serdes_get_stats,
4711 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4712 .serdes_get_regs = mv88e6390_serdes_get_regs,
4713 .gpio_ops = &mv88e6352_gpio_ops,
4714 .avb_ops = &mv88e6390_avb_ops,
4715 .ptp_ops = &mv88e6352_ptp_ops,
4716 .phylink_validate = mv88e6390x_phylink_validate,
4719 static const struct mv88e6xxx_ops mv88e6393x_ops = {
4720 /* MV88E6XXX_FAMILY_6393 */
4721 .setup_errata = mv88e6393x_serdes_setup_errata,
4722 .irl_init_all = mv88e6390_g2_irl_init_all,
4723 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4724 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4726 .phy_read = mv88e6xxx_g2_smi_phy_read,
4727 .phy_write = mv88e6xxx_g2_smi_phy_write,
4728 .port_set_link = mv88e6xxx_port_set_link,
4729 .port_sync_link = mv88e6xxx_port_sync_link,
4730 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4731 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4732 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4733 .port_tag_remap = mv88e6390_port_tag_remap,
4734 .port_set_policy = mv88e6393x_port_set_policy,
4735 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4736 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4737 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4738 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4739 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4740 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4741 .port_pause_limit = mv88e6390_port_pause_limit,
4742 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4743 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4744 .port_get_cmode = mv88e6352_port_get_cmode,
4745 .port_set_cmode = mv88e6393x_port_set_cmode,
4746 .port_setup_message_port = mv88e6xxx_setup_message_port,
4747 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4748 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4749 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4750 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4751 .stats_get_strings = mv88e6320_stats_get_strings,
4752 .stats_get_stats = mv88e6390_stats_get_stats,
4753 /* .set_cpu_port is missing because this family does not support a global
4754 * CPU port, only per port CPU port which is set via
4755 * .port_set_upstream_port method.
4757 .set_egress_port = mv88e6393x_set_egress_port,
4758 .watchdog_ops = &mv88e6390_watchdog_ops,
4759 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4760 .pot_clear = mv88e6xxx_g2_pot_clear,
4761 .reset = mv88e6352_g1_reset,
4762 .rmu_disable = mv88e6390_g1_rmu_disable,
4763 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4764 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4765 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4766 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4767 .serdes_power = mv88e6393x_serdes_power,
4768 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4769 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4770 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4771 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4772 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4773 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4774 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4775 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4776 /* TODO: serdes stats */
4777 .gpio_ops = &mv88e6352_gpio_ops,
4778 .avb_ops = &mv88e6390_avb_ops,
4779 .ptp_ops = &mv88e6352_ptp_ops,
4780 .phylink_validate = mv88e6393x_phylink_validate,
4783 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4785 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4786 .family = MV88E6XXX_FAMILY_6097,
4787 .name = "Marvell 88E6085",
4788 .num_databases = 4096,
4791 .num_internal_phys = 5,
4793 .port_base_addr = 0x10,
4794 .phy_base_addr = 0x0,
4795 .global1_addr = 0x1b,
4796 .global2_addr = 0x1c,
4797 .age_time_coeff = 15000,
4800 .atu_move_port_mask = 0xf,
4803 .ops = &mv88e6085_ops,
4807 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4808 .family = MV88E6XXX_FAMILY_6095,
4809 .name = "Marvell 88E6095/88E6095F",
4810 .num_databases = 256,
4813 .num_internal_phys = 0,
4815 .port_base_addr = 0x10,
4816 .phy_base_addr = 0x0,
4817 .global1_addr = 0x1b,
4818 .global2_addr = 0x1c,
4819 .age_time_coeff = 15000,
4821 .atu_move_port_mask = 0xf,
4823 .ops = &mv88e6095_ops,
4827 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4828 .family = MV88E6XXX_FAMILY_6097,
4829 .name = "Marvell 88E6097/88E6097F",
4830 .num_databases = 4096,
4833 .num_internal_phys = 8,
4835 .port_base_addr = 0x10,
4836 .phy_base_addr = 0x0,
4837 .global1_addr = 0x1b,
4838 .global2_addr = 0x1c,
4839 .age_time_coeff = 15000,
4842 .atu_move_port_mask = 0xf,
4845 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4846 .ops = &mv88e6097_ops,
4850 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4851 .family = MV88E6XXX_FAMILY_6165,
4852 .name = "Marvell 88E6123",
4853 .num_databases = 4096,
4856 .num_internal_phys = 5,
4858 .port_base_addr = 0x10,
4859 .phy_base_addr = 0x0,
4860 .global1_addr = 0x1b,
4861 .global2_addr = 0x1c,
4862 .age_time_coeff = 15000,
4865 .atu_move_port_mask = 0xf,
4868 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4869 .ops = &mv88e6123_ops,
4873 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4874 .family = MV88E6XXX_FAMILY_6185,
4875 .name = "Marvell 88E6131",
4876 .num_databases = 256,
4879 .num_internal_phys = 0,
4881 .port_base_addr = 0x10,
4882 .phy_base_addr = 0x0,
4883 .global1_addr = 0x1b,
4884 .global2_addr = 0x1c,
4885 .age_time_coeff = 15000,
4887 .atu_move_port_mask = 0xf,
4889 .ops = &mv88e6131_ops,
4893 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4894 .family = MV88E6XXX_FAMILY_6341,
4895 .name = "Marvell 88E6141",
4896 .num_databases = 4096,
4899 .num_internal_phys = 5,
4902 .port_base_addr = 0x10,
4903 .phy_base_addr = 0x10,
4904 .global1_addr = 0x1b,
4905 .global2_addr = 0x1c,
4906 .age_time_coeff = 3750,
4907 .atu_move_port_mask = 0x1f,
4912 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4913 .ops = &mv88e6141_ops,
4917 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4918 .family = MV88E6XXX_FAMILY_6165,
4919 .name = "Marvell 88E6161",
4920 .num_databases = 4096,
4923 .num_internal_phys = 5,
4925 .port_base_addr = 0x10,
4926 .phy_base_addr = 0x0,
4927 .global1_addr = 0x1b,
4928 .global2_addr = 0x1c,
4929 .age_time_coeff = 15000,
4932 .atu_move_port_mask = 0xf,
4935 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4936 .ptp_support = true,
4937 .ops = &mv88e6161_ops,
4941 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4942 .family = MV88E6XXX_FAMILY_6165,
4943 .name = "Marvell 88E6165",
4944 .num_databases = 4096,
4947 .num_internal_phys = 0,
4949 .port_base_addr = 0x10,
4950 .phy_base_addr = 0x0,
4951 .global1_addr = 0x1b,
4952 .global2_addr = 0x1c,
4953 .age_time_coeff = 15000,
4956 .atu_move_port_mask = 0xf,
4959 .ptp_support = true,
4960 .ops = &mv88e6165_ops,
4964 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4965 .family = MV88E6XXX_FAMILY_6351,
4966 .name = "Marvell 88E6171",
4967 .num_databases = 4096,
4970 .num_internal_phys = 5,
4972 .port_base_addr = 0x10,
4973 .phy_base_addr = 0x0,
4974 .global1_addr = 0x1b,
4975 .global2_addr = 0x1c,
4976 .age_time_coeff = 15000,
4979 .atu_move_port_mask = 0xf,
4982 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4983 .ops = &mv88e6171_ops,
4987 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4988 .family = MV88E6XXX_FAMILY_6352,
4989 .name = "Marvell 88E6172",
4990 .num_databases = 4096,
4993 .num_internal_phys = 5,
4996 .port_base_addr = 0x10,
4997 .phy_base_addr = 0x0,
4998 .global1_addr = 0x1b,
4999 .global2_addr = 0x1c,
5000 .age_time_coeff = 15000,
5003 .atu_move_port_mask = 0xf,
5006 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5007 .ops = &mv88e6172_ops,
5011 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5012 .family = MV88E6XXX_FAMILY_6351,
5013 .name = "Marvell 88E6175",
5014 .num_databases = 4096,
5017 .num_internal_phys = 5,
5019 .port_base_addr = 0x10,
5020 .phy_base_addr = 0x0,
5021 .global1_addr = 0x1b,
5022 .global2_addr = 0x1c,
5023 .age_time_coeff = 15000,
5026 .atu_move_port_mask = 0xf,
5029 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5030 .ops = &mv88e6175_ops,
5034 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5035 .family = MV88E6XXX_FAMILY_6352,
5036 .name = "Marvell 88E6176",
5037 .num_databases = 4096,
5040 .num_internal_phys = 5,
5043 .port_base_addr = 0x10,
5044 .phy_base_addr = 0x0,
5045 .global1_addr = 0x1b,
5046 .global2_addr = 0x1c,
5047 .age_time_coeff = 15000,
5050 .atu_move_port_mask = 0xf,
5053 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5054 .ops = &mv88e6176_ops,
5058 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5059 .family = MV88E6XXX_FAMILY_6185,
5060 .name = "Marvell 88E6185",
5061 .num_databases = 256,
5064 .num_internal_phys = 0,
5066 .port_base_addr = 0x10,
5067 .phy_base_addr = 0x0,
5068 .global1_addr = 0x1b,
5069 .global2_addr = 0x1c,
5070 .age_time_coeff = 15000,
5072 .atu_move_port_mask = 0xf,
5074 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5075 .ops = &mv88e6185_ops,
5079 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5080 .family = MV88E6XXX_FAMILY_6390,
5081 .name = "Marvell 88E6190",
5082 .num_databases = 4096,
5084 .num_ports = 11, /* 10 + Z80 */
5085 .num_internal_phys = 9,
5088 .port_base_addr = 0x0,
5089 .phy_base_addr = 0x0,
5090 .global1_addr = 0x1b,
5091 .global2_addr = 0x1c,
5092 .age_time_coeff = 3750,
5097 .atu_move_port_mask = 0x1f,
5098 .ops = &mv88e6190_ops,
5102 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5103 .family = MV88E6XXX_FAMILY_6390,
5104 .name = "Marvell 88E6190X",
5105 .num_databases = 4096,
5107 .num_ports = 11, /* 10 + Z80 */
5108 .num_internal_phys = 9,
5111 .port_base_addr = 0x0,
5112 .phy_base_addr = 0x0,
5113 .global1_addr = 0x1b,
5114 .global2_addr = 0x1c,
5115 .age_time_coeff = 3750,
5118 .atu_move_port_mask = 0x1f,
5121 .ops = &mv88e6190x_ops,
5125 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5126 .family = MV88E6XXX_FAMILY_6390,
5127 .name = "Marvell 88E6191",
5128 .num_databases = 4096,
5130 .num_ports = 11, /* 10 + Z80 */
5131 .num_internal_phys = 9,
5133 .port_base_addr = 0x0,
5134 .phy_base_addr = 0x0,
5135 .global1_addr = 0x1b,
5136 .global2_addr = 0x1c,
5137 .age_time_coeff = 3750,
5140 .atu_move_port_mask = 0x1f,
5143 .ptp_support = true,
5144 .ops = &mv88e6191_ops,
5148 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5149 .family = MV88E6XXX_FAMILY_6393,
5150 .name = "Marvell 88E6191X",
5151 .num_databases = 4096,
5152 .num_ports = 11, /* 10 + Z80 */
5153 .num_internal_phys = 9,
5155 .port_base_addr = 0x0,
5156 .phy_base_addr = 0x0,
5157 .global1_addr = 0x1b,
5158 .global2_addr = 0x1c,
5159 .age_time_coeff = 3750,
5162 .atu_move_port_mask = 0x1f,
5165 .ptp_support = true,
5166 .ops = &mv88e6393x_ops,
5170 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5171 .family = MV88E6XXX_FAMILY_6393,
5172 .name = "Marvell 88E6193X",
5173 .num_databases = 4096,
5174 .num_ports = 11, /* 10 + Z80 */
5175 .num_internal_phys = 9,
5177 .port_base_addr = 0x0,
5178 .phy_base_addr = 0x0,
5179 .global1_addr = 0x1b,
5180 .global2_addr = 0x1c,
5181 .age_time_coeff = 3750,
5184 .atu_move_port_mask = 0x1f,
5187 .ptp_support = true,
5188 .ops = &mv88e6393x_ops,
5192 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5193 .family = MV88E6XXX_FAMILY_6250,
5194 .name = "Marvell 88E6220",
5195 .num_databases = 64,
5197 /* Ports 2-4 are not routed to pins
5198 * => usable ports 0, 1, 5, 6
5201 .num_internal_phys = 2,
5202 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5204 .port_base_addr = 0x08,
5205 .phy_base_addr = 0x00,
5206 .global1_addr = 0x0f,
5207 .global2_addr = 0x07,
5208 .age_time_coeff = 15000,
5211 .atu_move_port_mask = 0xf,
5213 .ptp_support = true,
5214 .ops = &mv88e6250_ops,
5218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5219 .family = MV88E6XXX_FAMILY_6352,
5220 .name = "Marvell 88E6240",
5221 .num_databases = 4096,
5224 .num_internal_phys = 5,
5227 .port_base_addr = 0x10,
5228 .phy_base_addr = 0x0,
5229 .global1_addr = 0x1b,
5230 .global2_addr = 0x1c,
5231 .age_time_coeff = 15000,
5234 .atu_move_port_mask = 0xf,
5237 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5238 .ptp_support = true,
5239 .ops = &mv88e6240_ops,
5243 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5244 .family = MV88E6XXX_FAMILY_6250,
5245 .name = "Marvell 88E6250",
5246 .num_databases = 64,
5248 .num_internal_phys = 5,
5250 .port_base_addr = 0x08,
5251 .phy_base_addr = 0x00,
5252 .global1_addr = 0x0f,
5253 .global2_addr = 0x07,
5254 .age_time_coeff = 15000,
5257 .atu_move_port_mask = 0xf,
5259 .ptp_support = true,
5260 .ops = &mv88e6250_ops,
5264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5265 .family = MV88E6XXX_FAMILY_6390,
5266 .name = "Marvell 88E6290",
5267 .num_databases = 4096,
5268 .num_ports = 11, /* 10 + Z80 */
5269 .num_internal_phys = 9,
5272 .port_base_addr = 0x0,
5273 .phy_base_addr = 0x0,
5274 .global1_addr = 0x1b,
5275 .global2_addr = 0x1c,
5276 .age_time_coeff = 3750,
5279 .atu_move_port_mask = 0x1f,
5282 .ptp_support = true,
5283 .ops = &mv88e6290_ops,
5287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5288 .family = MV88E6XXX_FAMILY_6320,
5289 .name = "Marvell 88E6320",
5290 .num_databases = 4096,
5293 .num_internal_phys = 5,
5296 .port_base_addr = 0x10,
5297 .phy_base_addr = 0x0,
5298 .global1_addr = 0x1b,
5299 .global2_addr = 0x1c,
5300 .age_time_coeff = 15000,
5303 .atu_move_port_mask = 0xf,
5306 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5307 .ptp_support = true,
5308 .ops = &mv88e6320_ops,
5312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5313 .family = MV88E6XXX_FAMILY_6320,
5314 .name = "Marvell 88E6321",
5315 .num_databases = 4096,
5318 .num_internal_phys = 5,
5321 .port_base_addr = 0x10,
5322 .phy_base_addr = 0x0,
5323 .global1_addr = 0x1b,
5324 .global2_addr = 0x1c,
5325 .age_time_coeff = 15000,
5328 .atu_move_port_mask = 0xf,
5330 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5331 .ptp_support = true,
5332 .ops = &mv88e6321_ops,
5336 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5337 .family = MV88E6XXX_FAMILY_6341,
5338 .name = "Marvell 88E6341",
5339 .num_databases = 4096,
5341 .num_internal_phys = 5,
5345 .port_base_addr = 0x10,
5346 .phy_base_addr = 0x10,
5347 .global1_addr = 0x1b,
5348 .global2_addr = 0x1c,
5349 .age_time_coeff = 3750,
5350 .atu_move_port_mask = 0x1f,
5355 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5356 .ptp_support = true,
5357 .ops = &mv88e6341_ops,
5361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5362 .family = MV88E6XXX_FAMILY_6351,
5363 .name = "Marvell 88E6350",
5364 .num_databases = 4096,
5367 .num_internal_phys = 5,
5369 .port_base_addr = 0x10,
5370 .phy_base_addr = 0x0,
5371 .global1_addr = 0x1b,
5372 .global2_addr = 0x1c,
5373 .age_time_coeff = 15000,
5376 .atu_move_port_mask = 0xf,
5379 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5380 .ops = &mv88e6350_ops,
5384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5385 .family = MV88E6XXX_FAMILY_6351,
5386 .name = "Marvell 88E6351",
5387 .num_databases = 4096,
5390 .num_internal_phys = 5,
5392 .port_base_addr = 0x10,
5393 .phy_base_addr = 0x0,
5394 .global1_addr = 0x1b,
5395 .global2_addr = 0x1c,
5396 .age_time_coeff = 15000,
5399 .atu_move_port_mask = 0xf,
5402 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5403 .ops = &mv88e6351_ops,
5407 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5408 .family = MV88E6XXX_FAMILY_6352,
5409 .name = "Marvell 88E6352",
5410 .num_databases = 4096,
5413 .num_internal_phys = 5,
5416 .port_base_addr = 0x10,
5417 .phy_base_addr = 0x0,
5418 .global1_addr = 0x1b,
5419 .global2_addr = 0x1c,
5420 .age_time_coeff = 15000,
5423 .atu_move_port_mask = 0xf,
5426 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5427 .ptp_support = true,
5428 .ops = &mv88e6352_ops,
5431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5432 .family = MV88E6XXX_FAMILY_6390,
5433 .name = "Marvell 88E6390",
5434 .num_databases = 4096,
5436 .num_ports = 11, /* 10 + Z80 */
5437 .num_internal_phys = 9,
5440 .port_base_addr = 0x0,
5441 .phy_base_addr = 0x0,
5442 .global1_addr = 0x1b,
5443 .global2_addr = 0x1c,
5444 .age_time_coeff = 3750,
5447 .atu_move_port_mask = 0x1f,
5450 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5451 .ptp_support = true,
5452 .ops = &mv88e6390_ops,
5455 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5456 .family = MV88E6XXX_FAMILY_6390,
5457 .name = "Marvell 88E6390X",
5458 .num_databases = 4096,
5460 .num_ports = 11, /* 10 + Z80 */
5461 .num_internal_phys = 9,
5464 .port_base_addr = 0x0,
5465 .phy_base_addr = 0x0,
5466 .global1_addr = 0x1b,
5467 .global2_addr = 0x1c,
5468 .age_time_coeff = 3750,
5471 .atu_move_port_mask = 0x1f,
5474 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5475 .ptp_support = true,
5476 .ops = &mv88e6390x_ops,
5480 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5481 .family = MV88E6XXX_FAMILY_6393,
5482 .name = "Marvell 88E6393X",
5483 .num_databases = 4096,
5484 .num_ports = 11, /* 10 + Z80 */
5485 .num_internal_phys = 9,
5487 .port_base_addr = 0x0,
5488 .phy_base_addr = 0x0,
5489 .global1_addr = 0x1b,
5490 .global2_addr = 0x1c,
5491 .age_time_coeff = 3750,
5494 .atu_move_port_mask = 0x1f,
5497 .ptp_support = true,
5498 .ops = &mv88e6393x_ops,
5502 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5506 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5507 if (mv88e6xxx_table[i].prod_num == prod_num)
5508 return &mv88e6xxx_table[i];
5513 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5515 const struct mv88e6xxx_info *info;
5516 unsigned int prod_num, rev;
5520 mv88e6xxx_reg_lock(chip);
5521 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5522 mv88e6xxx_reg_unlock(chip);
5526 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5527 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5529 info = mv88e6xxx_lookup_info(prod_num);
5533 /* Update the compatible info with the probed one */
5536 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5537 chip->info->prod_num, chip->info->name, rev);
5542 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5544 struct mv88e6xxx_chip *chip;
5546 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5552 mutex_init(&chip->reg_lock);
5553 INIT_LIST_HEAD(&chip->mdios);
5554 idr_init(&chip->policies);
5559 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5561 enum dsa_tag_protocol m)
5563 struct mv88e6xxx_chip *chip = ds->priv;
5565 return chip->tag_protocol;
5568 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5569 enum dsa_tag_protocol proto)
5571 struct mv88e6xxx_chip *chip = ds->priv;
5572 enum dsa_tag_protocol old_protocol;
5576 case DSA_TAG_PROTO_EDSA:
5577 switch (chip->info->edsa_support) {
5578 case MV88E6XXX_EDSA_UNSUPPORTED:
5579 return -EPROTONOSUPPORT;
5580 case MV88E6XXX_EDSA_UNDOCUMENTED:
5581 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5583 case MV88E6XXX_EDSA_SUPPORTED:
5587 case DSA_TAG_PROTO_DSA:
5590 return -EPROTONOSUPPORT;
5593 old_protocol = chip->tag_protocol;
5594 chip->tag_protocol = proto;
5596 mv88e6xxx_reg_lock(chip);
5597 err = mv88e6xxx_setup_port_mode(chip, port);
5598 mv88e6xxx_reg_unlock(chip);
5601 chip->tag_protocol = old_protocol;
5606 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5607 const struct switchdev_obj_port_mdb *mdb)
5609 struct mv88e6xxx_chip *chip = ds->priv;
5612 mv88e6xxx_reg_lock(chip);
5613 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5614 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
5615 mv88e6xxx_reg_unlock(chip);
5620 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5621 const struct switchdev_obj_port_mdb *mdb)
5623 struct mv88e6xxx_chip *chip = ds->priv;
5626 mv88e6xxx_reg_lock(chip);
5627 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5628 mv88e6xxx_reg_unlock(chip);
5633 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5634 struct dsa_mall_mirror_tc_entry *mirror,
5637 enum mv88e6xxx_egress_direction direction = ingress ?
5638 MV88E6XXX_EGRESS_DIR_INGRESS :
5639 MV88E6XXX_EGRESS_DIR_EGRESS;
5640 struct mv88e6xxx_chip *chip = ds->priv;
5641 bool other_mirrors = false;
5645 mutex_lock(&chip->reg_lock);
5646 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5647 mirror->to_local_port) {
5648 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5649 other_mirrors |= ingress ?
5650 chip->ports[i].mirror_ingress :
5651 chip->ports[i].mirror_egress;
5653 /* Can't change egress port when other mirror is active */
5654 if (other_mirrors) {
5659 err = mv88e6xxx_set_egress_port(chip, direction,
5660 mirror->to_local_port);
5665 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5667 mutex_unlock(&chip->reg_lock);
5672 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5673 struct dsa_mall_mirror_tc_entry *mirror)
5675 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5676 MV88E6XXX_EGRESS_DIR_INGRESS :
5677 MV88E6XXX_EGRESS_DIR_EGRESS;
5678 struct mv88e6xxx_chip *chip = ds->priv;
5679 bool other_mirrors = false;
5682 mutex_lock(&chip->reg_lock);
5683 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5684 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5686 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5687 other_mirrors |= mirror->ingress ?
5688 chip->ports[i].mirror_ingress :
5689 chip->ports[i].mirror_egress;
5691 /* Reset egress port when no other mirror is active */
5692 if (!other_mirrors) {
5693 if (mv88e6xxx_set_egress_port(chip, direction,
5694 dsa_upstream_port(ds, port)))
5695 dev_err(ds->dev, "failed to set egress port\n");
5698 mutex_unlock(&chip->reg_lock);
5701 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5702 struct switchdev_brport_flags flags,
5703 struct netlink_ext_ack *extack)
5705 struct mv88e6xxx_chip *chip = ds->priv;
5706 const struct mv88e6xxx_ops *ops;
5708 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5712 ops = chip->info->ops;
5714 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5717 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5723 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5724 struct switchdev_brport_flags flags,
5725 struct netlink_ext_ack *extack)
5727 struct mv88e6xxx_chip *chip = ds->priv;
5728 bool do_fast_age = false;
5729 int err = -EOPNOTSUPP;
5731 mv88e6xxx_reg_lock(chip);
5733 if (flags.mask & BR_LEARNING) {
5734 bool learning = !!(flags.val & BR_LEARNING);
5735 u16 pav = learning ? (1 << port) : 0;
5737 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5745 if (flags.mask & BR_FLOOD) {
5746 bool unicast = !!(flags.val & BR_FLOOD);
5748 err = chip->info->ops->port_set_ucast_flood(chip, port,
5754 if (flags.mask & BR_MCAST_FLOOD) {
5755 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5757 err = chip->info->ops->port_set_mcast_flood(chip, port,
5763 if (flags.mask & BR_BCAST_FLOOD) {
5764 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5766 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5772 mv88e6xxx_reg_unlock(chip);
5775 mv88e6xxx_port_fast_age(ds, port);
5780 static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port,
5782 struct netlink_ext_ack *extack)
5784 struct mv88e6xxx_chip *chip = ds->priv;
5787 if (!chip->info->ops->port_set_mcast_flood)
5790 mv88e6xxx_reg_lock(chip);
5791 err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter);
5792 mv88e6xxx_reg_unlock(chip);
5797 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5798 struct net_device *lag,
5799 struct netdev_lag_upper_info *info)
5801 struct mv88e6xxx_chip *chip = ds->priv;
5802 struct dsa_port *dp;
5803 int id, members = 0;
5805 if (!mv88e6xxx_has_lag(chip))
5808 id = dsa_lag_id(ds->dst, lag);
5809 if (id < 0 || id >= ds->num_lag_ids)
5812 dsa_lag_foreach_port(dp, ds->dst, lag)
5813 /* Includes the port joining the LAG */
5819 /* We could potentially relax this to include active
5820 * backup in the future.
5822 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5825 /* Ideally we would also validate that the hash type matches
5826 * the hardware. Alas, this is always set to unknown on team
5832 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5834 struct mv88e6xxx_chip *chip = ds->priv;
5835 struct dsa_port *dp;
5839 id = dsa_lag_id(ds->dst, lag);
5841 /* Build the map of all ports to distribute flows destined for
5842 * this LAG. This can be either a local user port, or a DSA
5843 * port if the LAG port is on a remote chip.
5845 dsa_lag_foreach_port(dp, ds->dst, lag)
5846 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5848 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5851 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5852 /* Row number corresponds to the number of active members in a
5853 * LAG. Each column states which of the eight hash buckets are
5854 * mapped to the column:th port in the LAG.
5856 * Example: In a LAG with three active ports, the second port
5857 * ([2][1]) would be selected for traffic mapped to buckets
5860 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
5861 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
5862 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
5863 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
5864 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
5865 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
5866 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
5867 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5870 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5871 int num_tx, int nth)
5876 num_tx = num_tx <= 8 ? num_tx : 8;
5878 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5880 for (i = 0; i < 8; i++) {
5881 if (BIT(i) & active)
5882 mask[i] |= BIT(port);
5886 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5888 struct mv88e6xxx_chip *chip = ds->priv;
5889 unsigned int id, num_tx;
5890 struct net_device *lag;
5891 struct dsa_port *dp;
5896 /* Assume no port is a member of any LAG. */
5897 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5899 /* Disable all masks for ports that _are_ members of a LAG. */
5900 list_for_each_entry(dp, &ds->dst->ports, list) {
5901 if (!dp->lag_dev || dp->ds != ds)
5904 ivec &= ~BIT(dp->index);
5907 for (i = 0; i < 8; i++)
5910 /* Enable the correct subset of masks for all LAG ports that
5911 * are in the Tx set.
5913 dsa_lags_foreach_id(id, ds->dst) {
5914 lag = dsa_lag_dev(ds->dst, id);
5919 dsa_lag_foreach_port(dp, ds->dst, lag) {
5920 if (dp->lag_tx_enabled)
5928 dsa_lag_foreach_port(dp, ds->dst, lag) {
5929 if (!dp->lag_tx_enabled)
5933 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5940 for (i = 0; i < 8; i++) {
5941 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
5949 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
5950 struct net_device *lag)
5954 err = mv88e6xxx_lag_sync_masks(ds);
5957 err = mv88e6xxx_lag_sync_map(ds, lag);
5962 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
5964 struct mv88e6xxx_chip *chip = ds->priv;
5967 mv88e6xxx_reg_lock(chip);
5968 err = mv88e6xxx_lag_sync_masks(ds);
5969 mv88e6xxx_reg_unlock(chip);
5973 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
5974 struct net_device *lag,
5975 struct netdev_lag_upper_info *info)
5977 struct mv88e6xxx_chip *chip = ds->priv;
5980 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
5983 id = dsa_lag_id(ds->dst, lag);
5985 mv88e6xxx_reg_lock(chip);
5987 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
5991 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
5993 goto err_clear_trunk;
5995 mv88e6xxx_reg_unlock(chip);
5999 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6001 mv88e6xxx_reg_unlock(chip);
6005 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6006 struct net_device *lag)
6008 struct mv88e6xxx_chip *chip = ds->priv;
6009 int err_sync, err_trunk;
6011 mv88e6xxx_reg_lock(chip);
6012 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6013 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6014 mv88e6xxx_reg_unlock(chip);
6015 return err_sync ? : err_trunk;
6018 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6021 struct mv88e6xxx_chip *chip = ds->priv;
6024 mv88e6xxx_reg_lock(chip);
6025 err = mv88e6xxx_lag_sync_masks(ds);
6026 mv88e6xxx_reg_unlock(chip);
6030 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6031 int port, struct net_device *lag,
6032 struct netdev_lag_upper_info *info)
6034 struct mv88e6xxx_chip *chip = ds->priv;
6037 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6040 mv88e6xxx_reg_lock(chip);
6042 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6046 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6049 mv88e6xxx_reg_unlock(chip);
6053 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6054 int port, struct net_device *lag)
6056 struct mv88e6xxx_chip *chip = ds->priv;
6057 int err_sync, err_pvt;
6059 mv88e6xxx_reg_lock(chip);
6060 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6061 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6062 mv88e6xxx_reg_unlock(chip);
6063 return err_sync ? : err_pvt;
6066 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6067 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6068 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6069 .setup = mv88e6xxx_setup,
6070 .teardown = mv88e6xxx_teardown,
6071 .phylink_validate = mv88e6xxx_validate,
6072 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6073 .phylink_mac_config = mv88e6xxx_mac_config,
6074 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6075 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6076 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6077 .get_strings = mv88e6xxx_get_strings,
6078 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6079 .get_sset_count = mv88e6xxx_get_sset_count,
6080 .port_enable = mv88e6xxx_port_enable,
6081 .port_disable = mv88e6xxx_port_disable,
6082 .port_max_mtu = mv88e6xxx_get_max_mtu,
6083 .port_change_mtu = mv88e6xxx_change_mtu,
6084 .get_mac_eee = mv88e6xxx_get_mac_eee,
6085 .set_mac_eee = mv88e6xxx_set_mac_eee,
6086 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6087 .get_eeprom = mv88e6xxx_get_eeprom,
6088 .set_eeprom = mv88e6xxx_set_eeprom,
6089 .get_regs_len = mv88e6xxx_get_regs_len,
6090 .get_regs = mv88e6xxx_get_regs,
6091 .get_rxnfc = mv88e6xxx_get_rxnfc,
6092 .set_rxnfc = mv88e6xxx_set_rxnfc,
6093 .set_ageing_time = mv88e6xxx_set_ageing_time,
6094 .port_bridge_join = mv88e6xxx_port_bridge_join,
6095 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6096 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6097 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6098 .port_set_mrouter = mv88e6xxx_port_set_mrouter,
6099 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6100 .port_fast_age = mv88e6xxx_port_fast_age,
6101 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6102 .port_vlan_add = mv88e6xxx_port_vlan_add,
6103 .port_vlan_del = mv88e6xxx_port_vlan_del,
6104 .port_fdb_add = mv88e6xxx_port_fdb_add,
6105 .port_fdb_del = mv88e6xxx_port_fdb_del,
6106 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6107 .port_mdb_add = mv88e6xxx_port_mdb_add,
6108 .port_mdb_del = mv88e6xxx_port_mdb_del,
6109 .port_mirror_add = mv88e6xxx_port_mirror_add,
6110 .port_mirror_del = mv88e6xxx_port_mirror_del,
6111 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6112 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6113 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6114 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6115 .port_txtstamp = mv88e6xxx_port_txtstamp,
6116 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6117 .get_ts_info = mv88e6xxx_get_ts_info,
6118 .devlink_param_get = mv88e6xxx_devlink_param_get,
6119 .devlink_param_set = mv88e6xxx_devlink_param_set,
6120 .devlink_info_get = mv88e6xxx_devlink_info_get,
6121 .port_lag_change = mv88e6xxx_port_lag_change,
6122 .port_lag_join = mv88e6xxx_port_lag_join,
6123 .port_lag_leave = mv88e6xxx_port_lag_leave,
6124 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6125 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6126 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6129 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6131 struct device *dev = chip->dev;
6132 struct dsa_switch *ds;
6134 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6139 ds->num_ports = mv88e6xxx_num_ports(chip);
6142 ds->ops = &mv88e6xxx_switch_ops;
6143 ds->ageing_time_min = chip->info->age_time_coeff;
6144 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6146 /* Some chips support up to 32, but that requires enabling the
6147 * 5-bit port mode, which we do not support. 640k^W16 ought to
6148 * be enough for anyone.
6150 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6152 dev_set_drvdata(dev, ds);
6154 return dsa_register_switch(ds);
6157 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6159 dsa_unregister_switch(chip->ds);
6162 static const void *pdata_device_get_match_data(struct device *dev)
6164 const struct of_device_id *matches = dev->driver->of_match_table;
6165 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6167 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6169 if (!strcmp(pdata->compatible, matches->compatible))
6170 return matches->data;
6175 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6176 * would be lost after a power cycle so prevent it to be suspended.
6178 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6183 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6188 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6190 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6192 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6193 const struct mv88e6xxx_info *compat_info = NULL;
6194 struct device *dev = &mdiodev->dev;
6195 struct device_node *np = dev->of_node;
6196 struct mv88e6xxx_chip *chip;
6204 compat_info = of_device_get_match_data(dev);
6207 compat_info = pdata_device_get_match_data(dev);
6212 for (port = 0; port < DSA_MAX_PORTS; port++) {
6213 if (!(pdata->enabled_ports & (1 << port)))
6215 if (strcmp(pdata->cd.port_names[port], "cpu"))
6217 pdata->cd.netdev[port] = &pdata->netdev->dev;
6225 chip = mv88e6xxx_alloc_chip(dev);
6231 chip->info = compat_info;
6233 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6237 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6238 if (IS_ERR(chip->reset)) {
6239 err = PTR_ERR(chip->reset);
6243 usleep_range(1000, 2000);
6245 err = mv88e6xxx_detect(chip);
6249 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6250 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6252 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6254 mv88e6xxx_phy_init(chip);
6256 if (chip->info->ops->get_eeprom) {
6258 of_property_read_u32(np, "eeprom-length",
6261 chip->eeprom_len = pdata->eeprom_len;
6264 mv88e6xxx_reg_lock(chip);
6265 err = mv88e6xxx_switch_reset(chip);
6266 mv88e6xxx_reg_unlock(chip);
6271 chip->irq = of_irq_get(np, 0);
6272 if (chip->irq == -EPROBE_DEFER) {
6279 chip->irq = pdata->irq;
6281 /* Has to be performed before the MDIO bus is created, because
6282 * the PHYs will link their interrupts to these interrupt
6285 mv88e6xxx_reg_lock(chip);
6287 err = mv88e6xxx_g1_irq_setup(chip);
6289 err = mv88e6xxx_irq_poll_setup(chip);
6290 mv88e6xxx_reg_unlock(chip);
6295 if (chip->info->g2_irqs > 0) {
6296 err = mv88e6xxx_g2_irq_setup(chip);
6301 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6305 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6307 goto out_g1_atu_prob_irq;
6309 err = mv88e6xxx_mdios_register(chip, np);
6311 goto out_g1_vtu_prob_irq;
6313 err = mv88e6xxx_register_switch(chip);
6320 mv88e6xxx_mdios_unregister(chip);
6321 out_g1_vtu_prob_irq:
6322 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6323 out_g1_atu_prob_irq:
6324 mv88e6xxx_g1_atu_prob_irq_free(chip);
6326 if (chip->info->g2_irqs > 0)
6327 mv88e6xxx_g2_irq_free(chip);
6330 mv88e6xxx_g1_irq_free(chip);
6332 mv88e6xxx_irq_poll_free(chip);
6335 dev_put(pdata->netdev);
6340 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6342 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6343 struct mv88e6xxx_chip *chip = ds->priv;
6345 if (chip->info->ptp_support) {
6346 mv88e6xxx_hwtstamp_free(chip);
6347 mv88e6xxx_ptp_free(chip);
6350 mv88e6xxx_phy_destroy(chip);
6351 mv88e6xxx_unregister_switch(chip);
6352 mv88e6xxx_mdios_unregister(chip);
6354 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6355 mv88e6xxx_g1_atu_prob_irq_free(chip);
6357 if (chip->info->g2_irqs > 0)
6358 mv88e6xxx_g2_irq_free(chip);
6361 mv88e6xxx_g1_irq_free(chip);
6363 mv88e6xxx_irq_poll_free(chip);
6366 static const struct of_device_id mv88e6xxx_of_match[] = {
6368 .compatible = "marvell,mv88e6085",
6369 .data = &mv88e6xxx_table[MV88E6085],
6372 .compatible = "marvell,mv88e6190",
6373 .data = &mv88e6xxx_table[MV88E6190],
6376 .compatible = "marvell,mv88e6250",
6377 .data = &mv88e6xxx_table[MV88E6250],
6382 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6384 static struct mdio_driver mv88e6xxx_driver = {
6385 .probe = mv88e6xxx_probe,
6386 .remove = mv88e6xxx_remove,
6388 .name = "mv88e6085",
6389 .of_match_table = mv88e6xxx_of_match,
6390 .pm = &mv88e6xxx_pm_ops,
6394 mdio_module_driver(mv88e6xxx_driver);
6396 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6397 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6398 MODULE_LICENSE("GPL");