1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
58 assert_reg_lock(chip);
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
74 assert_reg_lock(chip);
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
103 if ((data & mask) == val)
109 usleep_range(1000, 2000);
112 dev_err(chip->dev, "Timeout while waiting for switch\n");
116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
120 val ? BIT(bit) : 0x0000);
123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
125 struct mv88e6xxx_mdio_bus *mdio_bus;
127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
132 return mdio_bus->bus;
135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
140 chip->g1_irq.masked |= (1 << n);
143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 unsigned int n = d->hwirq;
148 chip->g1_irq.masked &= ~(1 << n);
151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
153 unsigned int nhandled = 0;
154 unsigned int sub_irq;
160 mv88e6xxx_reg_lock(chip);
161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
162 mv88e6xxx_reg_unlock(chip);
168 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
169 if (reg & (1 << n)) {
170 sub_irq = irq_find_mapping(chip->g1_irq.domain,
172 handle_nested_irq(sub_irq);
177 mv88e6xxx_reg_lock(chip);
178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
183 mv88e6xxx_reg_unlock(chip);
186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
187 } while (reg & ctl1);
190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
195 struct mv88e6xxx_chip *chip = dev_id;
197 return mv88e6xxx_g1_irq_thread_work(chip);
200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
204 mv88e6xxx_reg_lock(chip);
207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
219 reg |= (~chip->g1_irq.masked & mask);
221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
226 mv88e6xxx_reg_unlock(chip);
229 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
230 .name = "mv88e6xxx-g1",
231 .irq_mask = mv88e6xxx_g1_irq_mask,
232 .irq_unmask = mv88e6xxx_g1_irq_unmask,
233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
239 irq_hw_number_t hwirq)
241 struct mv88e6xxx_chip *chip = d->host_data;
243 irq_set_chip_data(irq, d->host_data);
244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
245 irq_set_noprobe(irq);
250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
251 .map = mv88e6xxx_g1_irq_domain_map,
252 .xlate = irq_domain_xlate_twocell,
255 /* To be called with reg_lock held */
256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
266 virq = irq_find_mapping(chip->g1_irq.domain, irq);
267 irq_dispose_mapping(virq);
270 irq_domain_remove(chip->g1_irq.domain);
273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
276 * free_irq must be called without reg_lock taken because the irq
277 * handler takes this lock, too.
279 free_irq(chip->irq, chip);
281 mv88e6xxx_reg_lock(chip);
282 mv88e6xxx_g1_irq_free_common(chip);
283 mv88e6xxx_reg_unlock(chip);
286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
291 chip->g1_irq.nirqs = chip->info->g1_irqs;
292 chip->g1_irq.domain = irq_domain_add_simple(
293 NULL, chip->g1_irq.nirqs, 0,
294 &mv88e6xxx_g1_irq_domain_ops, chip);
295 if (!chip->g1_irq.domain)
298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
299 irq_create_mapping(chip->g1_irq.domain, irq);
301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
302 chip->g1_irq.masked = ~0;
304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
314 /* Reading the interrupt status clears (most of) them */
315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
326 for (irq = 0; irq < 16; irq++) {
327 virq = irq_find_mapping(chip->g1_irq.domain, irq);
328 irq_dispose_mapping(virq);
331 irq_domain_remove(chip->g1_irq.domain);
336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
338 static struct lock_class_key lock_key;
339 static struct lock_class_key request_key;
342 err = mv88e6xxx_g1_irq_setup_common(chip);
346 /* These lock classes tells lockdep that global 1 irqs are in
347 * a different category than their parent GPIO, so it won't
348 * report false recursion.
350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
352 snprintf(chip->irq_name, sizeof(chip->irq_name),
353 "mv88e6xxx-%s", dev_name(chip->dev));
355 mv88e6xxx_reg_unlock(chip);
356 err = request_threaded_irq(chip->irq, NULL,
357 mv88e6xxx_g1_irq_thread_fn,
358 IRQF_ONESHOT | IRQF_SHARED,
359 chip->irq_name, chip);
360 mv88e6xxx_reg_lock(chip);
362 mv88e6xxx_g1_irq_free_common(chip);
367 static void mv88e6xxx_irq_poll(struct kthread_work *work)
369 struct mv88e6xxx_chip *chip = container_of(work,
370 struct mv88e6xxx_chip,
372 mv88e6xxx_g1_irq_thread_work(chip);
374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
375 msecs_to_jiffies(100));
378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
382 err = mv88e6xxx_g1_irq_setup_common(chip);
386 kthread_init_delayed_work(&chip->irq_poll_work,
389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
390 if (IS_ERR(chip->kworker))
391 return PTR_ERR(chip->kworker);
393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
394 msecs_to_jiffies(100));
399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
402 kthread_destroy_worker(chip->kworker);
404 mv88e6xxx_reg_lock(chip);
405 mv88e6xxx_g1_irq_free_common(chip);
406 mv88e6xxx_reg_unlock(chip);
409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
410 int port, phy_interface_t interface)
414 if (chip->info->ops->port_set_rgmii_delay) {
415 err = chip->info->ops->port_set_rgmii_delay(chip, port,
417 if (err && err != -EOPNOTSUPP)
421 if (chip->info->ops->port_set_cmode) {
422 err = chip->info->ops->port_set_cmode(chip, port,
424 if (err && err != -EOPNOTSUPP)
431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
432 int link, int speed, int duplex, int pause,
433 phy_interface_t mode)
437 if (!chip->info->ops->port_set_link)
440 /* Port's MAC control must not be changed unless the link is down */
441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
445 if (chip->info->ops->port_set_speed_duplex) {
446 err = chip->info->ops->port_set_speed_duplex(chip, port,
448 if (err && err != -EOPNOTSUPP)
452 if (chip->info->ops->port_set_pause) {
453 err = chip->info->ops->port_set_pause(chip, port, pause);
458 err = mv88e6xxx_port_config_interface(chip, port, mode);
460 if (chip->info->ops->port_set_link(chip, port, link))
461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
468 struct mv88e6xxx_chip *chip = ds->priv;
470 return port < chip->info->num_internal_phys;
473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
478 /* The 88e6250 family does not have the PHY detect bit. Instead,
479 * report whether the port is internal.
481 if (chip->info->family == MV88E6XXX_FAMILY_6250)
482 return port < chip->info->num_internal_phys;
484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
487 "p%d: %s: failed to read port status\n",
492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
496 struct phylink_link_state *state)
498 struct mv88e6xxx_chip *chip = ds->priv;
502 mv88e6xxx_reg_lock(chip);
503 lane = mv88e6xxx_serdes_get_lane(chip, port);
504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
509 mv88e6xxx_reg_unlock(chip);
514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
516 phy_interface_t interface,
517 const unsigned long *advertise)
519 const struct mv88e6xxx_ops *ops = chip->info->ops;
522 if (ops->serdes_pcs_config) {
523 lane = mv88e6xxx_serdes_get_lane(chip, port);
525 return ops->serdes_pcs_config(chip, port, lane, mode,
526 interface, advertise);
532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
534 struct mv88e6xxx_chip *chip = ds->priv;
535 const struct mv88e6xxx_ops *ops;
539 ops = chip->info->ops;
541 if (ops->serdes_pcs_an_restart) {
542 mv88e6xxx_reg_lock(chip);
543 lane = mv88e6xxx_serdes_get_lane(chip, port);
545 err = ops->serdes_pcs_an_restart(chip, port, lane);
546 mv88e6xxx_reg_unlock(chip);
549 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
555 int speed, int duplex)
557 const struct mv88e6xxx_ops *ops = chip->info->ops;
560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
561 lane = mv88e6xxx_serdes_get_lane(chip, port);
563 return ops->serdes_pcs_link_up(chip, port, lane,
570 static const u8 mv88e6185_phy_interface_modes[] = {
571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
581 struct phylink_config *config)
583 u8 cmode = chip->ports[port].cmode;
585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
591 mv88e6185_phy_interface_modes[cmode])
592 __set_bit(mv88e6185_phy_interface_modes[cmode],
593 config->supported_interfaces);
595 config->mac_capabilities |= MAC_1000FD;
599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
600 struct phylink_config *config)
602 u8 cmode = chip->ports[port].cmode;
604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
605 mv88e6185_phy_interface_modes[cmode])
606 __set_bit(mv88e6185_phy_interface_modes[cmode],
607 config->supported_interfaces);
609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
613 static const u8 mv88e6xxx_phy_interface_modes[] = {
614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
622 /* higher interface modes are not needed here, since ports supporting
623 * them are writable, and so the supported interfaces are filled in the
624 * corresponding .phylink_set_interfaces() implementation below
628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
631 mv88e6xxx_phy_interface_modes[cmode])
632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
634 phy_interface_set_rgmii(supported);
637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
638 struct phylink_config *config)
640 unsigned long *supported = config->supported_interfaces;
642 /* Translate the default cmode */
643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
657 /* If PHY_DETECT is zero, then we are not in auto-media mode */
658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
670 /* Restore PHY_DETECT value */
671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
675 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
679 struct phylink_config *config)
681 unsigned long *supported = config->supported_interfaces;
684 /* Translate the default cmode */
685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
690 /* Port 4 supports automedia if the serdes is associated with it. */
692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
694 dev_err(chip->dev, "p%d: failed to read scratch\n",
699 cmode = mv88e6352_get_port4_serdes_cmode(chip);
701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
704 mv88e6xxx_translate_cmode(cmode, supported);
708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
709 struct phylink_config *config)
711 unsigned long *supported = config->supported_interfaces;
713 /* Translate the default cmode */
714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
716 /* No ethtool bits for 200Mbps */
717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
720 /* The C_Mode field is programmable on port 5 */
722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
726 config->mac_capabilities |= MAC_2500FD;
730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
731 struct phylink_config *config)
733 unsigned long *supported = config->supported_interfaces;
735 /* Translate the default cmode */
736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
738 /* No ethtool bits for 200Mbps */
739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
742 /* The C_Mode field is programmable on ports 9 and 10 */
743 if (port == 9 || port == 10) {
744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
748 config->mac_capabilities |= MAC_2500FD;
752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
753 struct phylink_config *config)
755 unsigned long *supported = config->supported_interfaces;
757 mv88e6390_phylink_get_caps(chip, port, config);
759 /* For the 6x90X, ports 2-7 can be in automedia mode.
760 * (Note that 6x90 doesn't support RXAUI nor XAUI).
762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
763 * configured for 1000BASE-X, SGMII or 2500BASE-X.
764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
768 * configured for 1000BASE-X, SGMII or 2500BASE-X.
769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
772 * For now, be permissive (as the old code was) and allow 1000BASE-X
775 if (port >= 2 && port <= 7)
776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
778 /* The C_Mode field can also be programmed for 10G speeds */
779 if (port == 9 || port == 10) {
780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
783 config->mac_capabilities |= MAC_10000FD;
787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
788 struct phylink_config *config)
790 unsigned long *supported = config->supported_interfaces;
792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
794 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
796 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
799 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
800 if (port == 0 || port == 9 || port == 10) {
801 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
802 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
804 /* 6191X supports >1G modes only on port 10 */
805 if (!is_6191x || port == 10) {
806 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
807 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
808 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
809 /* FIXME: USXGMII is not supported yet */
810 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
812 config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
818 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
819 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
820 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
821 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
822 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
826 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
827 struct phylink_config *config)
829 struct mv88e6xxx_chip *chip = ds->priv;
831 mv88e6xxx_reg_lock(chip);
832 chip->info->ops->phylink_get_caps(chip, port, config);
833 mv88e6xxx_reg_unlock(chip);
835 if (mv88e6xxx_phy_is_internal(ds, port)) {
836 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
837 config->supported_interfaces);
838 /* Internal ports with no phy-mode need GMII for PHYLIB */
839 __set_bit(PHY_INTERFACE_MODE_GMII,
840 config->supported_interfaces);
844 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
846 const struct phylink_link_state *state)
848 struct mv88e6xxx_chip *chip = ds->priv;
849 struct mv88e6xxx_port *p;
852 p = &chip->ports[port];
854 mv88e6xxx_reg_lock(chip);
856 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
857 /* In inband mode, the link may come up at any time while the
858 * link is not forced down. Force the link down while we
859 * reconfigure the interface mode.
861 if (mode == MLO_AN_INBAND &&
862 p->interface != state->interface &&
863 chip->info->ops->port_set_link)
864 chip->info->ops->port_set_link(chip, port,
867 err = mv88e6xxx_port_config_interface(chip, port,
869 if (err && err != -EOPNOTSUPP)
872 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
875 /* FIXME: we should restart negotiation if something changed -
876 * which is something we get if we convert to using phylinks
883 /* Undo the forced down state above after completing configuration
884 * irrespective of its state on entry, which allows the link to come
885 * up in the in-band case where there is no separate SERDES. Also
886 * ensure that the link can come up if the PPU is in use and we are
887 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
889 if (chip->info->ops->port_set_link &&
890 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
891 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
892 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
894 p->interface = state->interface;
897 mv88e6xxx_reg_unlock(chip);
899 if (err && err != -EOPNOTSUPP)
900 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
903 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
905 phy_interface_t interface)
907 struct mv88e6xxx_chip *chip = ds->priv;
908 const struct mv88e6xxx_ops *ops;
911 ops = chip->info->ops;
913 mv88e6xxx_reg_lock(chip);
914 /* Force the link down if we know the port may not be automatically
915 * updated by the switch or if we are using fixed-link mode.
917 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
918 mode == MLO_AN_FIXED) && ops->port_sync_link)
919 err = ops->port_sync_link(chip, port, mode, false);
921 if (!err && ops->port_set_speed_duplex)
922 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
924 mv88e6xxx_reg_unlock(chip);
928 "p%d: failed to force MAC link down\n", port);
931 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
932 unsigned int mode, phy_interface_t interface,
933 struct phy_device *phydev,
934 int speed, int duplex,
935 bool tx_pause, bool rx_pause)
937 struct mv88e6xxx_chip *chip = ds->priv;
938 const struct mv88e6xxx_ops *ops;
941 ops = chip->info->ops;
943 mv88e6xxx_reg_lock(chip);
944 /* Configure and force the link up if we know that the port may not
945 * automatically updated by the switch or if we are using fixed-link
948 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
949 mode == MLO_AN_FIXED) {
950 /* FIXME: for an automedia port, should we force the link
951 * down here - what if the link comes up due to "other" media
952 * while we're bringing the port up, how is the exclusivity
953 * handled in the Marvell hardware? E.g. port 2 on 88E6390
954 * shared between internal PHY and Serdes.
956 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
961 if (ops->port_set_speed_duplex) {
962 err = ops->port_set_speed_duplex(chip, port,
964 if (err && err != -EOPNOTSUPP)
968 if (ops->port_sync_link)
969 err = ops->port_sync_link(chip, port, mode, true);
972 mv88e6xxx_reg_unlock(chip);
974 if (err && err != -EOPNOTSUPP)
976 "p%d: failed to configure MAC link up\n", port);
979 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
981 if (!chip->info->ops->stats_snapshot)
984 return chip->info->ops->stats_snapshot(chip, port);
987 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
988 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
989 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
990 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
991 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
992 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
993 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
994 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
995 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
996 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
997 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
998 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
999 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1000 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1001 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1002 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1003 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1004 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1005 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1006 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1007 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1008 { "single", 4, 0x14, STATS_TYPE_BANK0, },
1009 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1010 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1011 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1012 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1013 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1014 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1015 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1016 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1017 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1018 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1019 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1020 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1021 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1022 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1023 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1024 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1025 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1026 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1027 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1028 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1029 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1030 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1031 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1032 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1033 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1034 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1035 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1036 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1037 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1038 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1039 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1040 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1041 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1042 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1043 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1044 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1045 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1046 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1049 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1050 struct mv88e6xxx_hw_stat *s,
1051 int port, u16 bank1_select,
1061 case STATS_TYPE_PORT:
1062 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1068 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1071 low |= ((u32)reg) << 16;
1074 case STATS_TYPE_BANK1:
1077 case STATS_TYPE_BANK0:
1078 reg |= s->reg | histogram;
1079 mv88e6xxx_g1_stats_read(chip, reg, &low);
1081 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1086 value = (((u64)high) << 32) | low;
1090 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1091 uint8_t *data, int types)
1093 struct mv88e6xxx_hw_stat *stat;
1096 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1097 stat = &mv88e6xxx_hw_stats[i];
1098 if (stat->type & types) {
1099 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1108 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1111 return mv88e6xxx_stats_get_strings(chip, data,
1112 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1115 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1118 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1121 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1124 return mv88e6xxx_stats_get_strings(chip, data,
1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1128 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1129 "atu_member_violation",
1130 "atu_miss_violation",
1131 "atu_full_violation",
1132 "vtu_member_violation",
1133 "vtu_miss_violation",
1136 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1140 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1141 strscpy(data + i * ETH_GSTRING_LEN,
1142 mv88e6xxx_atu_vtu_stats_strings[i],
1146 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1147 u32 stringset, uint8_t *data)
1149 struct mv88e6xxx_chip *chip = ds->priv;
1152 if (stringset != ETH_SS_STATS)
1155 mv88e6xxx_reg_lock(chip);
1157 if (chip->info->ops->stats_get_strings)
1158 count = chip->info->ops->stats_get_strings(chip, data);
1160 if (chip->info->ops->serdes_get_strings) {
1161 data += count * ETH_GSTRING_LEN;
1162 count = chip->info->ops->serdes_get_strings(chip, port, data);
1165 data += count * ETH_GSTRING_LEN;
1166 mv88e6xxx_atu_vtu_get_strings(data);
1168 mv88e6xxx_reg_unlock(chip);
1171 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1174 struct mv88e6xxx_hw_stat *stat;
1177 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1178 stat = &mv88e6xxx_hw_stats[i];
1179 if (stat->type & types)
1185 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1187 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1191 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1193 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1196 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1198 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1202 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1204 struct mv88e6xxx_chip *chip = ds->priv;
1205 int serdes_count = 0;
1208 if (sset != ETH_SS_STATS)
1211 mv88e6xxx_reg_lock(chip);
1212 if (chip->info->ops->stats_get_sset_count)
1213 count = chip->info->ops->stats_get_sset_count(chip);
1217 if (chip->info->ops->serdes_get_sset_count)
1218 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1220 if (serdes_count < 0) {
1221 count = serdes_count;
1224 count += serdes_count;
1225 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1228 mv88e6xxx_reg_unlock(chip);
1233 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1234 uint64_t *data, int types,
1235 u16 bank1_select, u16 histogram)
1237 struct mv88e6xxx_hw_stat *stat;
1240 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1241 stat = &mv88e6xxx_hw_stats[i];
1242 if (stat->type & types) {
1243 mv88e6xxx_reg_lock(chip);
1244 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1247 mv88e6xxx_reg_unlock(chip);
1255 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1258 return mv88e6xxx_stats_get_stats(chip, port, data,
1259 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1263 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1266 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1267 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1270 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1273 return mv88e6xxx_stats_get_stats(chip, port, data,
1274 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1275 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1276 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1279 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1282 return mv88e6xxx_stats_get_stats(chip, port, data,
1283 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1284 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1288 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1291 *data++ = chip->ports[port].atu_member_violation;
1292 *data++ = chip->ports[port].atu_miss_violation;
1293 *data++ = chip->ports[port].atu_full_violation;
1294 *data++ = chip->ports[port].vtu_member_violation;
1295 *data++ = chip->ports[port].vtu_miss_violation;
1298 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1303 if (chip->info->ops->stats_get_stats)
1304 count = chip->info->ops->stats_get_stats(chip, port, data);
1306 mv88e6xxx_reg_lock(chip);
1307 if (chip->info->ops->serdes_get_stats) {
1309 count = chip->info->ops->serdes_get_stats(chip, port, data);
1312 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1313 mv88e6xxx_reg_unlock(chip);
1316 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1319 struct mv88e6xxx_chip *chip = ds->priv;
1322 mv88e6xxx_reg_lock(chip);
1324 ret = mv88e6xxx_stats_snapshot(chip, port);
1325 mv88e6xxx_reg_unlock(chip);
1330 mv88e6xxx_get_stats(chip, port, data);
1334 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1336 struct mv88e6xxx_chip *chip = ds->priv;
1339 len = 32 * sizeof(u16);
1340 if (chip->info->ops->serdes_get_regs_len)
1341 len += chip->info->ops->serdes_get_regs_len(chip, port);
1346 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1347 struct ethtool_regs *regs, void *_p)
1349 struct mv88e6xxx_chip *chip = ds->priv;
1355 regs->version = chip->info->prod_num;
1357 memset(p, 0xff, 32 * sizeof(u16));
1359 mv88e6xxx_reg_lock(chip);
1361 for (i = 0; i < 32; i++) {
1363 err = mv88e6xxx_port_read(chip, port, i, ®);
1368 if (chip->info->ops->serdes_get_regs)
1369 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1371 mv88e6xxx_reg_unlock(chip);
1374 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1375 struct ethtool_eee *e)
1377 /* Nothing to do on the port's MAC */
1381 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1382 struct ethtool_eee *e)
1384 /* Nothing to do on the port's MAC */
1388 /* Mask of the local ports allowed to receive frames from a given fabric port */
1389 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1391 struct dsa_switch *ds = chip->ds;
1392 struct dsa_switch_tree *dst = ds->dst;
1393 struct dsa_port *dp, *other_dp;
1397 /* dev is a physical switch */
1398 if (dev <= dst->last_switch) {
1399 list_for_each_entry(dp, &dst->ports, list) {
1400 if (dp->ds->index == dev && dp->index == port) {
1401 /* dp might be a DSA link or a user port, so it
1402 * might or might not have a bridge.
1403 * Use the "found" variable for both cases.
1409 /* dev is a virtual bridge */
1411 list_for_each_entry(dp, &dst->ports, list) {
1412 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1417 if (bridge_num + dst->last_switch != dev)
1425 /* Prevent frames from unknown switch or virtual bridge */
1429 /* Frames from DSA links and CPU ports can egress any local port */
1430 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1431 return mv88e6xxx_port_mask(chip);
1435 /* Frames from standalone user ports can only egress on the
1438 if (!dsa_port_bridge_dev_get(dp))
1439 return BIT(dsa_switch_upstream_port(ds));
1441 /* Frames from bridged user ports can egress any local DSA
1442 * links and CPU ports, as well as any local member of their
1445 dsa_switch_for_each_port(other_dp, ds)
1446 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1447 other_dp->type == DSA_PORT_TYPE_DSA ||
1448 dsa_port_bridge_same(dp, other_dp))
1449 pvlan |= BIT(other_dp->index);
1454 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1456 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1458 /* prevent frames from going back out of the port they came in on */
1459 output_ports &= ~BIT(port);
1461 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1464 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1467 struct mv88e6xxx_chip *chip = ds->priv;
1470 mv88e6xxx_reg_lock(chip);
1471 err = mv88e6xxx_port_set_state(chip, port, state);
1472 mv88e6xxx_reg_unlock(chip);
1475 dev_err(ds->dev, "p%d: failed to update state\n", port);
1478 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1482 if (chip->info->ops->ieee_pri_map) {
1483 err = chip->info->ops->ieee_pri_map(chip);
1488 if (chip->info->ops->ip_pri_map) {
1489 err = chip->info->ops->ip_pri_map(chip);
1497 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1499 struct dsa_switch *ds = chip->ds;
1503 if (!chip->info->global2_addr)
1506 /* Initialize the routing port to the 32 possible target devices */
1507 for (target = 0; target < 32; target++) {
1508 port = dsa_routing_port(ds, target);
1509 if (port == ds->num_ports)
1512 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1517 if (chip->info->ops->set_cascade_port) {
1518 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1519 err = chip->info->ops->set_cascade_port(chip, port);
1524 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1531 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1533 /* Clear all trunk masks and mapping */
1534 if (chip->info->global2_addr)
1535 return mv88e6xxx_g2_trunk_clear(chip);
1540 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1542 if (chip->info->ops->rmu_disable)
1543 return chip->info->ops->rmu_disable(chip);
1548 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1550 if (chip->info->ops->pot_clear)
1551 return chip->info->ops->pot_clear(chip);
1556 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1558 if (chip->info->ops->mgmt_rsvd2cpu)
1559 return chip->info->ops->mgmt_rsvd2cpu(chip);
1564 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1568 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1572 /* The chips that have a "learn2all" bit in Global1, ATU
1573 * Control are precisely those whose port registers have a
1574 * Message Port bit in Port Control 1 and hence implement
1575 * ->port_setup_message_port.
1577 if (chip->info->ops->port_setup_message_port) {
1578 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1583 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1586 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1591 if (!chip->info->ops->irl_init_all)
1594 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1595 /* Disable ingress rate limiting by resetting all per port
1596 * ingress rate limit resources to their initial state.
1598 err = chip->info->ops->irl_init_all(chip, port);
1606 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1608 if (chip->info->ops->set_switch_mac) {
1611 eth_random_addr(addr);
1613 return chip->info->ops->set_switch_mac(chip, addr);
1619 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1621 struct dsa_switch_tree *dst = chip->ds->dst;
1622 struct dsa_switch *ds;
1623 struct dsa_port *dp;
1626 if (!mv88e6xxx_has_pvt(chip))
1629 /* Skip the local source device, which uses in-chip port VLAN */
1630 if (dev != chip->ds->index) {
1631 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1633 ds = dsa_switch_find(dst->index, dev);
1634 dp = ds ? dsa_to_port(ds, port) : NULL;
1635 if (dp && dp->lag) {
1636 /* As the PVT is used to limit flooding of
1637 * FORWARD frames, which use the LAG ID as the
1638 * source port, we must translate dev/port to
1639 * the special "LAG device" in the PVT, using
1640 * the LAG ID (one-based) as the port number
1643 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1644 port = dsa_port_lag_id_get(dp) - 1;
1648 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1651 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1656 if (!mv88e6xxx_has_pvt(chip))
1659 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1660 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1662 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1666 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1667 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1668 err = mv88e6xxx_pvt_map(chip, dev, port);
1677 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1680 if (dsa_to_port(chip->ds, port)->lag)
1681 /* Hardware is incapable of fast-aging a LAG through a
1682 * regular ATU move operation. Until we have something
1683 * more fancy in place this is a no-op.
1687 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1690 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1692 struct mv88e6xxx_chip *chip = ds->priv;
1695 mv88e6xxx_reg_lock(chip);
1696 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1697 mv88e6xxx_reg_unlock(chip);
1700 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1704 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1706 if (!mv88e6xxx_max_vid(chip))
1709 return mv88e6xxx_g1_vtu_flush(chip);
1712 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1713 struct mv88e6xxx_vtu_entry *entry)
1717 if (!chip->info->ops->vtu_getnext)
1720 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1721 entry->valid = false;
1723 err = chip->info->ops->vtu_getnext(chip, entry);
1725 if (entry->vid != vid)
1726 entry->valid = false;
1731 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1732 int (*cb)(struct mv88e6xxx_chip *chip,
1733 const struct mv88e6xxx_vtu_entry *entry,
1737 struct mv88e6xxx_vtu_entry entry = {
1738 .vid = mv88e6xxx_max_vid(chip),
1743 if (!chip->info->ops->vtu_getnext)
1747 err = chip->info->ops->vtu_getnext(chip, &entry);
1754 err = cb(chip, &entry, priv);
1757 } while (entry.vid < mv88e6xxx_max_vid(chip));
1762 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1763 struct mv88e6xxx_vtu_entry *entry)
1765 if (!chip->info->ops->vtu_loadpurge)
1768 return chip->info->ops->vtu_loadpurge(chip, entry);
1771 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1772 const struct mv88e6xxx_vtu_entry *entry,
1775 unsigned long *fid_bitmap = _fid_bitmap;
1777 set_bit(entry->fid, fid_bitmap);
1781 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1783 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1785 /* Every FID has an associated VID, so walking the VTU
1786 * will discover the full set of FIDs in use.
1788 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1791 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1793 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1796 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1800 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1801 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1804 /* Clear the database */
1805 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1808 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1809 struct mv88e6xxx_stu_entry *entry)
1811 if (!chip->info->ops->stu_loadpurge)
1814 return chip->info->ops->stu_loadpurge(chip, entry);
1817 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1819 struct mv88e6xxx_stu_entry stu = {
1824 if (!mv88e6xxx_has_stu(chip))
1827 /* Make sure that SID 0 is always valid. This is used by VTU
1828 * entries that do not make use of the STU, e.g. when creating
1829 * a VLAN upper on a port that is also part of a VLAN
1832 return mv88e6xxx_stu_loadpurge(chip, &stu);
1835 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1837 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1838 struct mv88e6xxx_mst *mst;
1842 list_for_each_entry(mst, &chip->msts, node)
1843 __set_bit(mst->stu.sid, busy);
1845 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1847 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1850 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1852 struct mv88e6xxx_mst *mst, *tmp;
1858 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1859 if (mst->stu.sid != sid)
1862 if (!refcount_dec_and_test(&mst->refcnt))
1865 mst->stu.valid = false;
1866 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1868 refcount_set(&mst->refcnt, 1);
1872 list_del(&mst->node);
1880 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1883 struct mv88e6xxx_mst *mst;
1886 if (!mv88e6xxx_has_stu(chip)) {
1896 list_for_each_entry(mst, &chip->msts, node) {
1897 if (mst->br == br && mst->msti == msti) {
1898 refcount_inc(&mst->refcnt);
1899 *sid = mst->stu.sid;
1904 err = mv88e6xxx_sid_get(chip, sid);
1908 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1914 INIT_LIST_HEAD(&mst->node);
1915 refcount_set(&mst->refcnt, 1);
1918 mst->stu.valid = true;
1919 mst->stu.sid = *sid;
1921 /* The bridge starts out all ports in the disabled state. But
1922 * a STU state of disabled means to go by the port-global
1923 * state. So we set all user port's initial state to blocking,
1924 * to match the bridge's behavior.
1926 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1927 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1928 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1929 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1931 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1935 list_add_tail(&mst->node, &chip->msts);
1944 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1945 const struct switchdev_mst_state *st)
1947 struct dsa_port *dp = dsa_to_port(ds, port);
1948 struct mv88e6xxx_chip *chip = ds->priv;
1949 struct mv88e6xxx_mst *mst;
1953 if (!mv88e6xxx_has_stu(chip))
1956 switch (st->state) {
1957 case BR_STATE_DISABLED:
1958 case BR_STATE_BLOCKING:
1959 case BR_STATE_LISTENING:
1960 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1962 case BR_STATE_LEARNING:
1963 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1965 case BR_STATE_FORWARDING:
1966 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1972 list_for_each_entry(mst, &chip->msts, node) {
1973 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1974 mst->msti == st->msti) {
1975 if (mst->stu.state[port] == state)
1978 mst->stu.state[port] = state;
1979 mv88e6xxx_reg_lock(chip);
1980 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1981 mv88e6xxx_reg_unlock(chip);
1989 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1992 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1993 struct mv88e6xxx_chip *chip = ds->priv;
1994 struct mv88e6xxx_vtu_entry vlan;
1997 /* DSA and CPU ports have to be members of multiple vlans */
1998 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2001 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2008 dsa_switch_for_each_user_port(other_dp, ds) {
2009 struct net_device *other_br;
2011 if (vlan.member[other_dp->index] ==
2012 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2015 if (dsa_port_bridge_same(dp, other_dp))
2016 break; /* same bridge, check next VLAN */
2018 other_br = dsa_port_bridge_dev_get(other_dp);
2022 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2023 port, vlan.vid, other_dp->index, netdev_name(other_br));
2030 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2032 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2033 struct net_device *br = dsa_port_bridge_dev_get(dp);
2034 struct mv88e6xxx_port *p = &chip->ports[port];
2035 u16 pvid = MV88E6XXX_VID_STANDALONE;
2036 bool drop_untagged = false;
2040 if (br_vlan_enabled(br)) {
2041 pvid = p->bridge_pvid.vid;
2042 drop_untagged = !p->bridge_pvid.valid;
2044 pvid = MV88E6XXX_VID_BRIDGED;
2048 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2052 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2055 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2056 bool vlan_filtering,
2057 struct netlink_ext_ack *extack)
2059 struct mv88e6xxx_chip *chip = ds->priv;
2060 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2061 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2064 if (!mv88e6xxx_max_vid(chip))
2067 mv88e6xxx_reg_lock(chip);
2069 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2073 err = mv88e6xxx_port_commit_pvid(chip, port);
2078 mv88e6xxx_reg_unlock(chip);
2084 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2085 const struct switchdev_obj_port_vlan *vlan)
2087 struct mv88e6xxx_chip *chip = ds->priv;
2090 if (!mv88e6xxx_max_vid(chip))
2093 /* If the requested port doesn't belong to the same bridge as the VLAN
2094 * members, do not support it (yet) and fallback to software VLAN.
2096 mv88e6xxx_reg_lock(chip);
2097 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2098 mv88e6xxx_reg_unlock(chip);
2103 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2104 const unsigned char *addr, u16 vid,
2107 struct mv88e6xxx_atu_entry entry;
2108 struct mv88e6xxx_vtu_entry vlan;
2112 /* Ports have two private address databases: one for when the port is
2113 * standalone and one for when the port is under a bridge and the
2114 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2115 * address database to remain 100% empty, so we never load an ATU entry
2116 * into a standalone port's database. Therefore, translate the null
2117 * VLAN ID into the port's database used for VLAN-unaware bridging.
2120 fid = MV88E6XXX_FID_BRIDGED;
2122 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2126 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2134 ether_addr_copy(entry.mac, addr);
2135 eth_addr_dec(entry.mac);
2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2141 /* Initialize a fresh ATU entry if it isn't found */
2142 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2143 memset(&entry, 0, sizeof(entry));
2144 ether_addr_copy(entry.mac, addr);
2147 /* Purge the ATU entry only if no port is using it anymore */
2149 entry.portvec &= ~BIT(port);
2153 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2154 entry.portvec = BIT(port);
2156 entry.portvec |= BIT(port);
2158 entry.state = state;
2161 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2164 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2165 const struct mv88e6xxx_policy *policy)
2167 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2168 enum mv88e6xxx_policy_action action = policy->action;
2169 const u8 *addr = policy->addr;
2170 u16 vid = policy->vid;
2175 if (!chip->info->ops->port_set_policy)
2179 case MV88E6XXX_POLICY_MAPPING_DA:
2180 case MV88E6XXX_POLICY_MAPPING_SA:
2181 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2182 state = 0; /* Dissociate the port and address */
2183 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2184 is_multicast_ether_addr(addr))
2185 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2186 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2187 is_unicast_ether_addr(addr))
2188 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2192 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2201 /* Skip the port's policy clearing if the mapping is still in use */
2202 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2203 idr_for_each_entry(&chip->policies, policy, id)
2204 if (policy->port == port &&
2205 policy->mapping == mapping &&
2206 policy->action != action)
2209 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2212 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2213 struct ethtool_rx_flow_spec *fs)
2215 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2216 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2217 enum mv88e6xxx_policy_mapping mapping;
2218 enum mv88e6xxx_policy_action action;
2219 struct mv88e6xxx_policy *policy;
2225 if (fs->location != RX_CLS_LOC_ANY)
2228 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2229 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2233 switch (fs->flow_type & ~FLOW_EXT) {
2235 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2236 is_zero_ether_addr(mac_mask->h_source)) {
2237 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2238 addr = mac_entry->h_dest;
2239 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2240 !is_zero_ether_addr(mac_mask->h_source)) {
2241 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2242 addr = mac_entry->h_source;
2244 /* Cannot support DA and SA mapping in the same rule */
2252 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2253 if (fs->m_ext.vlan_tci != htons(0xffff))
2255 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2258 idr_for_each_entry(&chip->policies, policy, id) {
2259 if (policy->port == port && policy->mapping == mapping &&
2260 policy->action == action && policy->vid == vid &&
2261 ether_addr_equal(policy->addr, addr))
2265 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2270 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2273 devm_kfree(chip->dev, policy);
2277 memcpy(&policy->fs, fs, sizeof(*fs));
2278 ether_addr_copy(policy->addr, addr);
2279 policy->mapping = mapping;
2280 policy->action = action;
2281 policy->port = port;
2284 err = mv88e6xxx_policy_apply(chip, port, policy);
2286 idr_remove(&chip->policies, fs->location);
2287 devm_kfree(chip->dev, policy);
2294 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2295 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2297 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2298 struct mv88e6xxx_chip *chip = ds->priv;
2299 struct mv88e6xxx_policy *policy;
2303 mv88e6xxx_reg_lock(chip);
2305 switch (rxnfc->cmd) {
2306 case ETHTOOL_GRXCLSRLCNT:
2308 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2309 rxnfc->rule_cnt = 0;
2310 idr_for_each_entry(&chip->policies, policy, id)
2311 if (policy->port == port)
2315 case ETHTOOL_GRXCLSRULE:
2317 policy = idr_find(&chip->policies, fs->location);
2319 memcpy(fs, &policy->fs, sizeof(*fs));
2323 case ETHTOOL_GRXCLSRLALL:
2325 rxnfc->rule_cnt = 0;
2326 idr_for_each_entry(&chip->policies, policy, id)
2327 if (policy->port == port)
2328 rule_locs[rxnfc->rule_cnt++] = id;
2336 mv88e6xxx_reg_unlock(chip);
2341 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2342 struct ethtool_rxnfc *rxnfc)
2344 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2345 struct mv88e6xxx_chip *chip = ds->priv;
2346 struct mv88e6xxx_policy *policy;
2349 mv88e6xxx_reg_lock(chip);
2351 switch (rxnfc->cmd) {
2352 case ETHTOOL_SRXCLSRLINS:
2353 err = mv88e6xxx_policy_insert(chip, port, fs);
2355 case ETHTOOL_SRXCLSRLDEL:
2357 policy = idr_remove(&chip->policies, fs->location);
2359 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2360 err = mv88e6xxx_policy_apply(chip, port, policy);
2361 devm_kfree(chip->dev, policy);
2369 mv88e6xxx_reg_unlock(chip);
2374 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2377 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2378 u8 broadcast[ETH_ALEN];
2380 eth_broadcast_addr(broadcast);
2382 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2385 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2390 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2391 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2392 struct net_device *brport;
2394 if (dsa_is_unused_port(chip->ds, port))
2397 brport = dsa_port_to_bridge_port(dp);
2398 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2399 /* Skip bridged user ports where broadcast
2400 * flooding is disabled.
2404 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2412 struct mv88e6xxx_port_broadcast_sync_ctx {
2418 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2419 const struct mv88e6xxx_vtu_entry *vlan,
2422 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2423 u8 broadcast[ETH_ALEN];
2427 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2429 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2431 eth_broadcast_addr(broadcast);
2433 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2437 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2440 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2444 struct mv88e6xxx_vtu_entry vid0 = {
2449 /* Update the port's private database... */
2450 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2454 /* ...and the database for all VLANs. */
2455 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2459 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2460 u16 vid, u8 member, bool warn)
2462 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2463 struct mv88e6xxx_vtu_entry vlan;
2466 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2471 memset(&vlan, 0, sizeof(vlan));
2473 if (vid == MV88E6XXX_VID_STANDALONE)
2476 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2480 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2482 vlan.member[i] = member;
2484 vlan.member[i] = non_member;
2489 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2493 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2496 } else if (vlan.member[port] != member) {
2497 vlan.member[port] = member;
2499 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2503 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2510 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2511 const struct switchdev_obj_port_vlan *vlan,
2512 struct netlink_ext_ack *extack)
2514 struct mv88e6xxx_chip *chip = ds->priv;
2515 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2516 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2517 struct mv88e6xxx_port *p = &chip->ports[port];
2525 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2529 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2530 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2532 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2534 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2536 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2537 * and then the CPU port. Do not warn for duplicates for the CPU port.
2539 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2541 mv88e6xxx_reg_lock(chip);
2543 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2545 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2546 vlan->vid, untagged ? 'u' : 't');
2551 p->bridge_pvid.vid = vlan->vid;
2552 p->bridge_pvid.valid = true;
2554 err = mv88e6xxx_port_commit_pvid(chip, port);
2557 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2558 /* The old pvid was reinstalled as a non-pvid VLAN */
2559 p->bridge_pvid.valid = false;
2561 err = mv88e6xxx_port_commit_pvid(chip, port);
2567 mv88e6xxx_reg_unlock(chip);
2572 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2575 struct mv88e6xxx_vtu_entry vlan;
2581 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2585 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2586 * tell switchdev that this VLAN is likely handled in software.
2589 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2592 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2594 /* keep the VLAN unless all ports are excluded */
2596 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2597 if (vlan.member[i] !=
2598 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2604 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2609 err = mv88e6xxx_mst_put(chip, vlan.sid);
2614 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2617 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2618 const struct switchdev_obj_port_vlan *vlan)
2620 struct mv88e6xxx_chip *chip = ds->priv;
2621 struct mv88e6xxx_port *p = &chip->ports[port];
2625 if (!mv88e6xxx_max_vid(chip))
2628 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2629 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2630 * switchdev workqueue to ensure that all FDB entries are deleted
2631 * before we remove the VLAN.
2633 dsa_flush_workqueue();
2635 mv88e6xxx_reg_lock(chip);
2637 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2641 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2645 if (vlan->vid == pvid) {
2646 p->bridge_pvid.valid = false;
2648 err = mv88e6xxx_port_commit_pvid(chip, port);
2654 mv88e6xxx_reg_unlock(chip);
2659 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2661 struct mv88e6xxx_chip *chip = ds->priv;
2662 struct mv88e6xxx_vtu_entry vlan;
2665 mv88e6xxx_reg_lock(chip);
2667 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2671 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2674 mv88e6xxx_reg_unlock(chip);
2679 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2680 struct dsa_bridge bridge,
2681 const struct switchdev_vlan_msti *msti)
2683 struct mv88e6xxx_chip *chip = ds->priv;
2684 struct mv88e6xxx_vtu_entry vlan;
2685 u8 old_sid, new_sid;
2688 if (!mv88e6xxx_has_stu(chip))
2691 mv88e6xxx_reg_lock(chip);
2693 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2704 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2708 if (new_sid != old_sid) {
2711 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2713 mv88e6xxx_mst_put(chip, new_sid);
2718 err = mv88e6xxx_mst_put(chip, old_sid);
2721 mv88e6xxx_reg_unlock(chip);
2725 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2726 const unsigned char *addr, u16 vid,
2729 struct mv88e6xxx_chip *chip = ds->priv;
2732 mv88e6xxx_reg_lock(chip);
2733 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2734 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2735 mv88e6xxx_reg_unlock(chip);
2740 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2741 const unsigned char *addr, u16 vid,
2744 struct mv88e6xxx_chip *chip = ds->priv;
2747 mv88e6xxx_reg_lock(chip);
2748 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2749 mv88e6xxx_reg_unlock(chip);
2754 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2755 u16 fid, u16 vid, int port,
2756 dsa_fdb_dump_cb_t *cb, void *data)
2758 struct mv88e6xxx_atu_entry addr;
2763 eth_broadcast_addr(addr.mac);
2766 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2773 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2776 if (!is_unicast_ether_addr(addr.mac))
2779 is_static = (addr.state ==
2780 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2781 err = cb(addr.mac, vid, is_static, data);
2784 } while (!is_broadcast_ether_addr(addr.mac));
2789 struct mv88e6xxx_port_db_dump_vlan_ctx {
2791 dsa_fdb_dump_cb_t *cb;
2795 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2796 const struct mv88e6xxx_vtu_entry *entry,
2799 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2801 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2802 ctx->port, ctx->cb, ctx->data);
2805 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2806 dsa_fdb_dump_cb_t *cb, void *data)
2808 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2816 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2817 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2821 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2825 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2828 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2829 dsa_fdb_dump_cb_t *cb, void *data)
2831 struct mv88e6xxx_chip *chip = ds->priv;
2834 mv88e6xxx_reg_lock(chip);
2835 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2836 mv88e6xxx_reg_unlock(chip);
2841 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2842 struct dsa_bridge bridge)
2844 struct dsa_switch *ds = chip->ds;
2845 struct dsa_switch_tree *dst = ds->dst;
2846 struct dsa_port *dp;
2849 list_for_each_entry(dp, &dst->ports, list) {
2850 if (dsa_port_offloads_bridge(dp, &bridge)) {
2852 /* This is a local bridge group member,
2853 * remap its Port VLAN Map.
2855 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2859 /* This is an external bridge group member,
2860 * remap its cross-chip Port VLAN Table entry.
2862 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2873 /* Treat the software bridge as a virtual single-port switch behind the
2874 * CPU and map in the PVT. First dst->last_switch elements are taken by
2875 * physical switches, so start from beyond that range.
2877 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2878 unsigned int bridge_num)
2880 u8 dev = bridge_num + ds->dst->last_switch;
2881 struct mv88e6xxx_chip *chip = ds->priv;
2883 return mv88e6xxx_pvt_map(chip, dev, 0);
2886 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2887 struct dsa_bridge bridge,
2888 bool *tx_fwd_offload,
2889 struct netlink_ext_ack *extack)
2891 struct mv88e6xxx_chip *chip = ds->priv;
2894 mv88e6xxx_reg_lock(chip);
2896 err = mv88e6xxx_bridge_map(chip, bridge);
2900 err = mv88e6xxx_port_set_map_da(chip, port, true);
2904 err = mv88e6xxx_port_commit_pvid(chip, port);
2908 if (mv88e6xxx_has_pvt(chip)) {
2909 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2913 *tx_fwd_offload = true;
2917 mv88e6xxx_reg_unlock(chip);
2922 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2923 struct dsa_bridge bridge)
2925 struct mv88e6xxx_chip *chip = ds->priv;
2928 mv88e6xxx_reg_lock(chip);
2930 if (bridge.tx_fwd_offload &&
2931 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2932 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2934 if (mv88e6xxx_bridge_map(chip, bridge) ||
2935 mv88e6xxx_port_vlan_map(chip, port))
2936 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2938 err = mv88e6xxx_port_set_map_da(chip, port, false);
2941 "port %d failed to restore map-DA: %pe\n",
2942 port, ERR_PTR(err));
2944 err = mv88e6xxx_port_commit_pvid(chip, port);
2947 "port %d failed to restore standalone pvid: %pe\n",
2948 port, ERR_PTR(err));
2950 mv88e6xxx_reg_unlock(chip);
2953 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2954 int tree_index, int sw_index,
2955 int port, struct dsa_bridge bridge,
2956 struct netlink_ext_ack *extack)
2958 struct mv88e6xxx_chip *chip = ds->priv;
2961 if (tree_index != ds->dst->index)
2964 mv88e6xxx_reg_lock(chip);
2965 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2966 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2967 mv88e6xxx_reg_unlock(chip);
2972 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2973 int tree_index, int sw_index,
2974 int port, struct dsa_bridge bridge)
2976 struct mv88e6xxx_chip *chip = ds->priv;
2978 if (tree_index != ds->dst->index)
2981 mv88e6xxx_reg_lock(chip);
2982 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2983 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2984 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2985 mv88e6xxx_reg_unlock(chip);
2988 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2990 if (chip->info->ops->reset)
2991 return chip->info->ops->reset(chip);
2996 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2998 struct gpio_desc *gpiod = chip->reset;
3000 /* If there is a GPIO connected to the reset pin, toggle it */
3002 gpiod_set_value_cansleep(gpiod, 1);
3003 usleep_range(10000, 20000);
3004 gpiod_set_value_cansleep(gpiod, 0);
3005 usleep_range(10000, 20000);
3007 mv88e6xxx_g1_wait_eeprom_done(chip);
3011 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3015 /* Set all ports to the Disabled state */
3016 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3017 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3022 /* Wait for transmit queues to drain,
3023 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3025 usleep_range(2000, 4000);
3030 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3034 err = mv88e6xxx_disable_ports(chip);
3038 mv88e6xxx_hardware_reset(chip);
3040 return mv88e6xxx_software_reset(chip);
3043 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3044 enum mv88e6xxx_frame_mode frame,
3045 enum mv88e6xxx_egress_mode egress, u16 etype)
3049 if (!chip->info->ops->port_set_frame_mode)
3052 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3056 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3060 if (chip->info->ops->port_set_ether_type)
3061 return chip->info->ops->port_set_ether_type(chip, port, etype);
3066 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3068 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3069 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3070 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3073 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3075 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3076 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3077 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3080 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3082 return mv88e6xxx_set_port_mode(chip, port,
3083 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3084 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3088 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3090 if (dsa_is_dsa_port(chip->ds, port))
3091 return mv88e6xxx_set_port_mode_dsa(chip, port);
3093 if (dsa_is_user_port(chip->ds, port))
3094 return mv88e6xxx_set_port_mode_normal(chip, port);
3096 /* Setup CPU port mode depending on its supported tag format */
3097 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3098 return mv88e6xxx_set_port_mode_dsa(chip, port);
3100 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3101 return mv88e6xxx_set_port_mode_edsa(chip, port);
3106 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3108 bool message = dsa_is_dsa_port(chip->ds, port);
3110 return mv88e6xxx_port_set_message_port(chip, port, message);
3113 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3117 if (chip->info->ops->port_set_ucast_flood) {
3118 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3122 if (chip->info->ops->port_set_mcast_flood) {
3123 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3131 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
3133 struct mv88e6xxx_port *mvp = dev_id;
3134 struct mv88e6xxx_chip *chip = mvp->chip;
3135 irqreturn_t ret = IRQ_NONE;
3136 int port = mvp->port;
3139 mv88e6xxx_reg_lock(chip);
3140 lane = mv88e6xxx_serdes_get_lane(chip, port);
3142 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
3143 mv88e6xxx_reg_unlock(chip);
3148 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
3151 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3155 /* Nothing to request if this SERDES port has no IRQ */
3156 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
3160 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
3161 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
3163 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
3164 mv88e6xxx_reg_unlock(chip);
3165 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
3166 IRQF_ONESHOT, dev_id->serdes_irq_name,
3168 mv88e6xxx_reg_lock(chip);
3172 dev_id->serdes_irq = irq;
3174 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
3177 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
3180 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3181 unsigned int irq = dev_id->serdes_irq;
3184 /* Nothing to free if no IRQ has been requested */
3188 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
3190 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
3191 mv88e6xxx_reg_unlock(chip);
3192 free_irq(irq, dev_id);
3193 mv88e6xxx_reg_lock(chip);
3195 dev_id->serdes_irq = 0;
3200 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
3206 lane = mv88e6xxx_serdes_get_lane(chip, port);
3211 err = mv88e6xxx_serdes_power_up(chip, port, lane);
3215 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
3217 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
3221 err = mv88e6xxx_serdes_power_down(chip, port, lane);
3227 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3228 enum mv88e6xxx_egress_direction direction,
3233 if (!chip->info->ops->set_egress_port)
3236 err = chip->info->ops->set_egress_port(chip, direction, port);
3240 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3241 chip->ingress_dest_port = port;
3243 chip->egress_dest_port = port;
3248 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3250 struct dsa_switch *ds = chip->ds;
3254 upstream_port = dsa_upstream_port(ds, port);
3255 if (chip->info->ops->port_set_upstream_port) {
3256 err = chip->info->ops->port_set_upstream_port(chip, port,
3262 if (port == upstream_port) {
3263 if (chip->info->ops->set_cpu_port) {
3264 err = chip->info->ops->set_cpu_port(chip,
3270 err = mv88e6xxx_set_egress_port(chip,
3271 MV88E6XXX_EGRESS_DIR_INGRESS,
3273 if (err && err != -EOPNOTSUPP)
3276 err = mv88e6xxx_set_egress_port(chip,
3277 MV88E6XXX_EGRESS_DIR_EGRESS,
3279 if (err && err != -EOPNOTSUPP)
3286 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3288 struct device_node *phy_handle = NULL;
3289 struct dsa_switch *ds = chip->ds;
3290 phy_interface_t mode;
3291 struct dsa_port *dp;
3296 chip->ports[port].chip = chip;
3297 chip->ports[port].port = port;
3299 dp = dsa_to_port(ds, port);
3301 /* MAC Forcing register: don't force link, speed, duplex or flow control
3302 * state to any particular values on physical ports, but force the CPU
3303 * port and all DSA ports to their maximum bandwidth and full duplex.
3305 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
3306 struct phylink_config pl_config = {};
3309 chip->info->ops->phylink_get_caps(chip, port, &pl_config);
3311 caps = pl_config.mac_capabilities;
3313 if (chip->info->ops->port_max_speed_mode)
3314 mode = chip->info->ops->port_max_speed_mode(port);
3316 mode = PHY_INTERFACE_MODE_NA;
3318 if (caps & MAC_10000FD)
3319 speed = SPEED_10000;
3320 else if (caps & MAC_5000FD)
3322 else if (caps & MAC_2500FD)
3324 else if (caps & MAC_1000)
3326 else if (caps & MAC_100)
3331 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
3335 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3336 SPEED_UNFORCED, DUPLEX_UNFORCED,
3338 PHY_INTERFACE_MODE_NA);
3343 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3344 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3345 * tunneling, determine priority by looking at 802.1p and IP
3346 * priority fields (IP prio has precedence), and set STP state
3349 * If this is the CPU link, use DSA or EDSA tagging depending
3350 * on which tagging mode was configured.
3352 * If this is a link to another switch, use DSA tagging mode.
3354 * If this is the upstream port for this switch, enable
3355 * forwarding of unknown unicasts and multicasts.
3357 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3358 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3359 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3360 * by a USER port to the CPU port to allow snooping.
3362 if (dsa_is_user_port(ds, port))
3363 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3365 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3369 err = mv88e6xxx_setup_port_mode(chip, port);
3373 err = mv88e6xxx_setup_egress_floods(chip, port);
3377 /* Port Control 2: don't force a good FCS, set the MTU size to
3378 * 10222 bytes, disable 802.1q tags checking, don't discard
3379 * tagged or untagged frames on this port, skip destination
3380 * address lookup on user ports, disable ARP mirroring and don't
3381 * send a copy of all transmitted/received frames on this port
3384 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3388 err = mv88e6xxx_setup_upstream_port(chip, port);
3392 /* On chips that support it, set all downstream DSA ports'
3393 * VLAN policy to TRAP. In combination with loading
3394 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3395 * provides a better isolation barrier between standalone
3396 * ports, as the ATU is bypassed on any intermediate switches
3397 * between the incoming port and the CPU.
3399 if (dsa_is_downstream_port(ds, port) &&
3400 chip->info->ops->port_set_policy) {
3401 err = chip->info->ops->port_set_policy(chip, port,
3402 MV88E6XXX_POLICY_MAPPING_VTU,
3403 MV88E6XXX_POLICY_ACTION_TRAP);
3408 /* User ports start out in standalone mode and 802.1Q is
3409 * therefore disabled. On DSA ports, all valid VIDs are always
3410 * loaded in the VTU - therefore, enable 802.1Q in order to take
3411 * advantage of VLAN policy on chips that supports it.
3413 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3414 dsa_is_user_port(ds, port) ?
3415 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3416 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3420 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3421 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3422 * the first free FID. This will be used as the private PVID for
3423 * unbridged ports. Shared (DSA and CPU) ports must also be
3424 * members of this VID, in order to trap all frames assigned to
3427 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3428 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3433 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3434 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3435 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3436 * as the private PVID on ports under a VLAN-unaware bridge.
3437 * Shared (DSA and CPU) ports must also be members of it, to translate
3438 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3439 * relying on their port default FID.
3441 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3442 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3447 if (chip->info->ops->port_set_jumbo_size) {
3448 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3453 /* Port Association Vector: disable automatic address learning
3454 * on all user ports since they start out in standalone
3455 * mode. When joining a bridge, learning will be configured to
3456 * match the bridge port settings. Enable learning on all
3457 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3460 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3461 * and RefreshLocked. I.e. setup standard automatic learning.
3463 if (dsa_is_user_port(ds, port))
3468 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3473 /* Egress rate control 2: disable egress rate control. */
3474 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3479 if (chip->info->ops->port_pause_limit) {
3480 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3485 if (chip->info->ops->port_disable_learn_limit) {
3486 err = chip->info->ops->port_disable_learn_limit(chip, port);
3491 if (chip->info->ops->port_disable_pri_override) {
3492 err = chip->info->ops->port_disable_pri_override(chip, port);
3497 if (chip->info->ops->port_tag_remap) {
3498 err = chip->info->ops->port_tag_remap(chip, port);
3503 if (chip->info->ops->port_egress_rate_limiting) {
3504 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3509 if (chip->info->ops->port_setup_message_port) {
3510 err = chip->info->ops->port_setup_message_port(chip, port);
3515 if (chip->info->ops->serdes_set_tx_amplitude) {
3517 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3519 if (phy_handle && !of_property_read_u32(phy_handle,
3522 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3525 of_node_put(phy_handle);
3531 /* Port based VLAN map: give each port the same default address
3532 * database, and allow bidirectional communication between the
3533 * CPU and DSA port(s), and the other ports.
3535 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3539 err = mv88e6xxx_port_vlan_map(chip, port);
3543 /* Default VLAN ID and priority: don't set a default VLAN
3544 * ID, and set the default packet priority to zero.
3546 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3549 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3551 struct mv88e6xxx_chip *chip = ds->priv;
3553 if (chip->info->ops->port_set_jumbo_size)
3554 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3555 else if (chip->info->ops->set_max_frame_size)
3556 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3557 return ETH_DATA_LEN;
3560 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3562 struct mv88e6xxx_chip *chip = ds->priv;
3565 /* For families where we don't know how to alter the MTU,
3566 * just accept any value up to ETH_DATA_LEN
3568 if (!chip->info->ops->port_set_jumbo_size &&
3569 !chip->info->ops->set_max_frame_size) {
3570 if (new_mtu > ETH_DATA_LEN)
3576 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3577 new_mtu += EDSA_HLEN;
3579 mv88e6xxx_reg_lock(chip);
3580 if (chip->info->ops->port_set_jumbo_size)
3581 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3582 else if (chip->info->ops->set_max_frame_size)
3583 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3584 mv88e6xxx_reg_unlock(chip);
3589 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3590 struct phy_device *phydev)
3592 struct mv88e6xxx_chip *chip = ds->priv;
3595 mv88e6xxx_reg_lock(chip);
3596 err = mv88e6xxx_serdes_power(chip, port, true);
3597 mv88e6xxx_reg_unlock(chip);
3602 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3604 struct mv88e6xxx_chip *chip = ds->priv;
3606 mv88e6xxx_reg_lock(chip);
3607 if (mv88e6xxx_serdes_power(chip, port, false))
3608 dev_err(chip->dev, "failed to power off SERDES\n");
3609 mv88e6xxx_reg_unlock(chip);
3612 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3613 unsigned int ageing_time)
3615 struct mv88e6xxx_chip *chip = ds->priv;
3618 mv88e6xxx_reg_lock(chip);
3619 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3620 mv88e6xxx_reg_unlock(chip);
3625 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3629 /* Initialize the statistics unit */
3630 if (chip->info->ops->stats_set_histogram) {
3631 err = chip->info->ops->stats_set_histogram(chip);
3636 return mv88e6xxx_g1_stats_clear(chip);
3639 /* Check if the errata has already been applied. */
3640 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3646 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3647 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3650 "Error reading hidden register: %d\n", err);
3660 /* The 6390 copper ports have an errata which require poking magic
3661 * values into undocumented hidden registers and then performing a
3664 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3669 if (mv88e6390_setup_errata_applied(chip))
3672 /* Set the ports into blocking mode */
3673 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3674 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3679 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3680 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3685 return mv88e6xxx_software_reset(chip);
3688 /* prod_id for switch families which do not have a PHY model number */
3689 static const u16 family_prod_id_table[] = {
3690 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3691 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3692 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3695 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3697 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3698 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3703 if (!chip->info->ops->phy_read)
3706 mv88e6xxx_reg_lock(chip);
3707 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3708 mv88e6xxx_reg_unlock(chip);
3710 /* Some internal PHYs don't have a model number. */
3711 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3712 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3713 prod_id = family_prod_id_table[chip->info->family];
3715 val |= prod_id >> 4;
3718 return err ? err : val;
3721 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3724 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3725 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3729 if (!chip->info->ops->phy_read_c45)
3732 mv88e6xxx_reg_lock(chip);
3733 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3734 mv88e6xxx_reg_unlock(chip);
3736 return err ? err : val;
3739 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3741 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3742 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3745 if (!chip->info->ops->phy_write)
3748 mv88e6xxx_reg_lock(chip);
3749 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3750 mv88e6xxx_reg_unlock(chip);
3755 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3758 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3759 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3762 if (!chip->info->ops->phy_write_c45)
3765 mv88e6xxx_reg_lock(chip);
3766 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3767 mv88e6xxx_reg_unlock(chip);
3772 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3773 struct device_node *np,
3777 struct mv88e6xxx_mdio_bus *mdio_bus;
3778 struct mii_bus *bus;
3782 mv88e6xxx_reg_lock(chip);
3783 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3784 mv88e6xxx_reg_unlock(chip);
3790 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3794 mdio_bus = bus->priv;
3795 mdio_bus->bus = bus;
3796 mdio_bus->chip = chip;
3797 INIT_LIST_HEAD(&mdio_bus->list);
3798 mdio_bus->external = external;
3801 bus->name = np->full_name;
3802 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3804 bus->name = "mv88e6xxx SMI";
3805 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3808 bus->read = mv88e6xxx_mdio_read;
3809 bus->write = mv88e6xxx_mdio_write;
3810 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3811 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3812 bus->parent = chip->dev;
3813 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3814 mv88e6xxx_num_ports(chip) - 1,
3815 chip->info->phy_base_addr);
3818 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3823 err = of_mdiobus_register(bus, np);
3825 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3826 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3831 list_add_tail(&mdio_bus->list, &chip->mdios);
3833 list_add(&mdio_bus->list, &chip->mdios);
3842 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3845 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3846 struct mii_bus *bus;
3848 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3849 bus = mdio_bus->bus;
3851 if (!mdio_bus->external)
3852 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3854 mdiobus_unregister(bus);
3859 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3861 struct device_node *np = chip->dev->of_node;
3862 struct device_node *child;
3865 /* Always register one mdio bus for the internal/default mdio
3866 * bus. This maybe represented in the device tree, but is
3869 child = of_get_child_by_name(np, "mdio");
3870 err = mv88e6xxx_mdio_register(chip, child, false);
3875 /* Walk the device tree, and see if there are any other nodes
3876 * which say they are compatible with the external mdio
3879 for_each_available_child_of_node(np, child) {
3880 if (of_device_is_compatible(
3881 child, "marvell,mv88e6xxx-mdio-external")) {
3882 err = mv88e6xxx_mdio_register(chip, child, true);
3884 mv88e6xxx_mdios_unregister(chip);
3894 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3896 struct mv88e6xxx_chip *chip = ds->priv;
3898 mv88e6xxx_teardown_devlink_params(ds);
3899 dsa_devlink_resources_unregister(ds);
3900 mv88e6xxx_teardown_devlink_regions_global(ds);
3901 mv88e6xxx_mdios_unregister(chip);
3904 static int mv88e6xxx_setup(struct dsa_switch *ds)
3906 struct mv88e6xxx_chip *chip = ds->priv;
3911 err = mv88e6xxx_mdios_register(chip);
3916 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3918 /* Since virtual bridges are mapped in the PVT, the number we support
3919 * depends on the physical switch topology. We need to let DSA figure
3920 * that out and therefore we cannot set this at dsa_register_switch()
3923 if (mv88e6xxx_has_pvt(chip))
3924 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3925 ds->dst->last_switch - 1;
3927 mv88e6xxx_reg_lock(chip);
3929 if (chip->info->ops->setup_errata) {
3930 err = chip->info->ops->setup_errata(chip);
3935 /* Cache the cmode of each port. */
3936 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3937 if (chip->info->ops->port_get_cmode) {
3938 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3942 chip->ports[i].cmode = cmode;
3946 err = mv88e6xxx_vtu_setup(chip);
3950 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3951 * VTU, thereby also flushing the STU).
3953 err = mv88e6xxx_stu_setup(chip);
3957 /* Setup Switch Port Registers */
3958 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3959 if (dsa_is_unused_port(ds, i))
3962 /* Prevent the use of an invalid port. */
3963 if (mv88e6xxx_is_invalid_port(chip, i)) {
3964 dev_err(chip->dev, "port %d is invalid\n", i);
3969 err = mv88e6xxx_setup_port(chip, i);
3974 err = mv88e6xxx_irl_setup(chip);
3978 err = mv88e6xxx_mac_setup(chip);
3982 err = mv88e6xxx_phy_setup(chip);
3986 err = mv88e6xxx_pvt_setup(chip);
3990 err = mv88e6xxx_atu_setup(chip);
3994 err = mv88e6xxx_broadcast_setup(chip, 0);
3998 err = mv88e6xxx_pot_setup(chip);
4002 err = mv88e6xxx_rmu_setup(chip);
4006 err = mv88e6xxx_rsvd2cpu_setup(chip);
4010 err = mv88e6xxx_trunk_setup(chip);
4014 err = mv88e6xxx_devmap_setup(chip);
4018 err = mv88e6xxx_pri_setup(chip);
4022 /* Setup PTP Hardware Clock and timestamping */
4023 if (chip->info->ptp_support) {
4024 err = mv88e6xxx_ptp_setup(chip);
4028 err = mv88e6xxx_hwtstamp_setup(chip);
4033 err = mv88e6xxx_stats_setup(chip);
4038 mv88e6xxx_reg_unlock(chip);
4043 /* Have to be called without holding the register lock, since
4044 * they take the devlink lock, and we later take the locks in
4045 * the reverse order when getting/setting parameters or
4046 * resource occupancy.
4048 err = mv88e6xxx_setup_devlink_resources(ds);
4052 err = mv88e6xxx_setup_devlink_params(ds);
4056 err = mv88e6xxx_setup_devlink_regions_global(ds);
4063 mv88e6xxx_teardown_devlink_params(ds);
4065 dsa_devlink_resources_unregister(ds);
4067 mv88e6xxx_mdios_unregister(chip);
4072 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4074 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4077 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4079 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4082 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4084 struct mv88e6xxx_chip *chip = ds->priv;
4086 return chip->eeprom_len;
4089 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4090 struct ethtool_eeprom *eeprom, u8 *data)
4092 struct mv88e6xxx_chip *chip = ds->priv;
4095 if (!chip->info->ops->get_eeprom)
4098 mv88e6xxx_reg_lock(chip);
4099 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4100 mv88e6xxx_reg_unlock(chip);
4105 eeprom->magic = 0xc3ec4951;
4110 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4111 struct ethtool_eeprom *eeprom, u8 *data)
4113 struct mv88e6xxx_chip *chip = ds->priv;
4116 if (!chip->info->ops->set_eeprom)
4119 if (eeprom->magic != 0xc3ec4951)
4122 mv88e6xxx_reg_lock(chip);
4123 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4124 mv88e6xxx_reg_unlock(chip);
4129 static const struct mv88e6xxx_ops mv88e6085_ops = {
4130 /* MV88E6XXX_FAMILY_6097 */
4131 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4132 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4133 .irl_init_all = mv88e6352_g2_irl_init_all,
4134 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4135 .phy_read = mv88e6185_phy_ppu_read,
4136 .phy_write = mv88e6185_phy_ppu_write,
4137 .port_set_link = mv88e6xxx_port_set_link,
4138 .port_sync_link = mv88e6xxx_port_sync_link,
4139 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4140 .port_tag_remap = mv88e6095_port_tag_remap,
4141 .port_set_policy = mv88e6352_port_set_policy,
4142 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4143 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4144 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4145 .port_set_ether_type = mv88e6351_port_set_ether_type,
4146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4147 .port_pause_limit = mv88e6097_port_pause_limit,
4148 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4149 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4150 .port_get_cmode = mv88e6185_port_get_cmode,
4151 .port_setup_message_port = mv88e6xxx_setup_message_port,
4152 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4153 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4154 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4155 .stats_get_strings = mv88e6095_stats_get_strings,
4156 .stats_get_stats = mv88e6095_stats_get_stats,
4157 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4158 .set_egress_port = mv88e6095_g1_set_egress_port,
4159 .watchdog_ops = &mv88e6097_watchdog_ops,
4160 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4161 .pot_clear = mv88e6xxx_g2_pot_clear,
4162 .ppu_enable = mv88e6185_g1_ppu_enable,
4163 .ppu_disable = mv88e6185_g1_ppu_disable,
4164 .reset = mv88e6185_g1_reset,
4165 .rmu_disable = mv88e6085_g1_rmu_disable,
4166 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4167 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4168 .stu_getnext = mv88e6352_g1_stu_getnext,
4169 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4170 .phylink_get_caps = mv88e6185_phylink_get_caps,
4171 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4174 static const struct mv88e6xxx_ops mv88e6095_ops = {
4175 /* MV88E6XXX_FAMILY_6095 */
4176 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4177 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4178 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4179 .phy_read = mv88e6185_phy_ppu_read,
4180 .phy_write = mv88e6185_phy_ppu_write,
4181 .port_set_link = mv88e6xxx_port_set_link,
4182 .port_sync_link = mv88e6185_port_sync_link,
4183 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4184 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4185 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4186 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4187 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4188 .port_get_cmode = mv88e6185_port_get_cmode,
4189 .port_setup_message_port = mv88e6xxx_setup_message_port,
4190 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4191 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4192 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4193 .stats_get_strings = mv88e6095_stats_get_strings,
4194 .stats_get_stats = mv88e6095_stats_get_stats,
4195 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4196 .serdes_power = mv88e6185_serdes_power,
4197 .serdes_get_lane = mv88e6185_serdes_get_lane,
4198 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4199 .ppu_enable = mv88e6185_g1_ppu_enable,
4200 .ppu_disable = mv88e6185_g1_ppu_disable,
4201 .reset = mv88e6185_g1_reset,
4202 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4203 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4204 .phylink_get_caps = mv88e6095_phylink_get_caps,
4205 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4208 static const struct mv88e6xxx_ops mv88e6097_ops = {
4209 /* MV88E6XXX_FAMILY_6097 */
4210 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4211 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4212 .irl_init_all = mv88e6352_g2_irl_init_all,
4213 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4214 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4215 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4216 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4217 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4218 .port_set_link = mv88e6xxx_port_set_link,
4219 .port_sync_link = mv88e6185_port_sync_link,
4220 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4221 .port_tag_remap = mv88e6095_port_tag_remap,
4222 .port_set_policy = mv88e6352_port_set_policy,
4223 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4224 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4225 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4226 .port_set_ether_type = mv88e6351_port_set_ether_type,
4227 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4228 .port_pause_limit = mv88e6097_port_pause_limit,
4229 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4230 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4231 .port_get_cmode = mv88e6185_port_get_cmode,
4232 .port_setup_message_port = mv88e6xxx_setup_message_port,
4233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4234 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4236 .stats_get_strings = mv88e6095_stats_get_strings,
4237 .stats_get_stats = mv88e6095_stats_get_stats,
4238 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4239 .set_egress_port = mv88e6095_g1_set_egress_port,
4240 .watchdog_ops = &mv88e6097_watchdog_ops,
4241 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4242 .serdes_power = mv88e6185_serdes_power,
4243 .serdes_get_lane = mv88e6185_serdes_get_lane,
4244 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4245 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4246 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
4247 .serdes_irq_status = mv88e6097_serdes_irq_status,
4248 .pot_clear = mv88e6xxx_g2_pot_clear,
4249 .reset = mv88e6352_g1_reset,
4250 .rmu_disable = mv88e6085_g1_rmu_disable,
4251 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4252 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4253 .phylink_get_caps = mv88e6095_phylink_get_caps,
4254 .stu_getnext = mv88e6352_g1_stu_getnext,
4255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4256 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4259 static const struct mv88e6xxx_ops mv88e6123_ops = {
4260 /* MV88E6XXX_FAMILY_6165 */
4261 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4262 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4263 .irl_init_all = mv88e6352_g2_irl_init_all,
4264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4265 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4266 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4267 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4268 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4269 .port_set_link = mv88e6xxx_port_set_link,
4270 .port_sync_link = mv88e6xxx_port_sync_link,
4271 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4272 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4273 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4274 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4275 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4276 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4277 .port_get_cmode = mv88e6185_port_get_cmode,
4278 .port_setup_message_port = mv88e6xxx_setup_message_port,
4279 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4280 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4281 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4282 .stats_get_strings = mv88e6095_stats_get_strings,
4283 .stats_get_stats = mv88e6095_stats_get_stats,
4284 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4285 .set_egress_port = mv88e6095_g1_set_egress_port,
4286 .watchdog_ops = &mv88e6097_watchdog_ops,
4287 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4288 .pot_clear = mv88e6xxx_g2_pot_clear,
4289 .reset = mv88e6352_g1_reset,
4290 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4291 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4292 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4293 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4294 .stu_getnext = mv88e6352_g1_stu_getnext,
4295 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4296 .phylink_get_caps = mv88e6185_phylink_get_caps,
4297 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4300 static const struct mv88e6xxx_ops mv88e6131_ops = {
4301 /* MV88E6XXX_FAMILY_6185 */
4302 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4303 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4304 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4305 .phy_read = mv88e6185_phy_ppu_read,
4306 .phy_write = mv88e6185_phy_ppu_write,
4307 .port_set_link = mv88e6xxx_port_set_link,
4308 .port_sync_link = mv88e6xxx_port_sync_link,
4309 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4310 .port_tag_remap = mv88e6095_port_tag_remap,
4311 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4312 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4313 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4314 .port_set_ether_type = mv88e6351_port_set_ether_type,
4315 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4318 .port_pause_limit = mv88e6097_port_pause_limit,
4319 .port_set_pause = mv88e6185_port_set_pause,
4320 .port_get_cmode = mv88e6185_port_get_cmode,
4321 .port_setup_message_port = mv88e6xxx_setup_message_port,
4322 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4323 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4324 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4325 .stats_get_strings = mv88e6095_stats_get_strings,
4326 .stats_get_stats = mv88e6095_stats_get_stats,
4327 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4328 .set_egress_port = mv88e6095_g1_set_egress_port,
4329 .watchdog_ops = &mv88e6097_watchdog_ops,
4330 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4331 .ppu_enable = mv88e6185_g1_ppu_enable,
4332 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4333 .ppu_disable = mv88e6185_g1_ppu_disable,
4334 .reset = mv88e6185_g1_reset,
4335 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4336 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4337 .phylink_get_caps = mv88e6185_phylink_get_caps,
4340 static const struct mv88e6xxx_ops mv88e6141_ops = {
4341 /* MV88E6XXX_FAMILY_6341 */
4342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4343 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4344 .irl_init_all = mv88e6352_g2_irl_init_all,
4345 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4346 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4348 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4349 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4350 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4351 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4352 .port_set_link = mv88e6xxx_port_set_link,
4353 .port_sync_link = mv88e6xxx_port_sync_link,
4354 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4355 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4356 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4357 .port_tag_remap = mv88e6095_port_tag_remap,
4358 .port_set_policy = mv88e6352_port_set_policy,
4359 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4360 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4361 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4362 .port_set_ether_type = mv88e6351_port_set_ether_type,
4363 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4364 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4365 .port_pause_limit = mv88e6097_port_pause_limit,
4366 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4367 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4368 .port_get_cmode = mv88e6352_port_get_cmode,
4369 .port_set_cmode = mv88e6341_port_set_cmode,
4370 .port_setup_message_port = mv88e6xxx_setup_message_port,
4371 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4372 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4373 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4374 .stats_get_strings = mv88e6320_stats_get_strings,
4375 .stats_get_stats = mv88e6390_stats_get_stats,
4376 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4377 .set_egress_port = mv88e6390_g1_set_egress_port,
4378 .watchdog_ops = &mv88e6390_watchdog_ops,
4379 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4380 .pot_clear = mv88e6xxx_g2_pot_clear,
4381 .reset = mv88e6352_g1_reset,
4382 .rmu_disable = mv88e6390_g1_rmu_disable,
4383 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4384 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4385 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4386 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4387 .stu_getnext = mv88e6352_g1_stu_getnext,
4388 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4389 .serdes_power = mv88e6390_serdes_power,
4390 .serdes_get_lane = mv88e6341_serdes_get_lane,
4391 /* Check status register pause & lpa register */
4392 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4393 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4394 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4395 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4396 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4397 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4398 .serdes_irq_status = mv88e6390_serdes_irq_status,
4399 .gpio_ops = &mv88e6352_gpio_ops,
4400 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4401 .serdes_get_strings = mv88e6390_serdes_get_strings,
4402 .serdes_get_stats = mv88e6390_serdes_get_stats,
4403 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4404 .serdes_get_regs = mv88e6390_serdes_get_regs,
4405 .phylink_get_caps = mv88e6341_phylink_get_caps,
4408 static const struct mv88e6xxx_ops mv88e6161_ops = {
4409 /* MV88E6XXX_FAMILY_6165 */
4410 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4411 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4412 .irl_init_all = mv88e6352_g2_irl_init_all,
4413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4414 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4415 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4416 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4417 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4418 .port_set_link = mv88e6xxx_port_set_link,
4419 .port_sync_link = mv88e6xxx_port_sync_link,
4420 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4421 .port_tag_remap = mv88e6095_port_tag_remap,
4422 .port_set_policy = mv88e6352_port_set_policy,
4423 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4424 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4425 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4426 .port_set_ether_type = mv88e6351_port_set_ether_type,
4427 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4428 .port_pause_limit = mv88e6097_port_pause_limit,
4429 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4431 .port_get_cmode = mv88e6185_port_get_cmode,
4432 .port_setup_message_port = mv88e6xxx_setup_message_port,
4433 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4434 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4435 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4436 .stats_get_strings = mv88e6095_stats_get_strings,
4437 .stats_get_stats = mv88e6095_stats_get_stats,
4438 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4439 .set_egress_port = mv88e6095_g1_set_egress_port,
4440 .watchdog_ops = &mv88e6097_watchdog_ops,
4441 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4442 .pot_clear = mv88e6xxx_g2_pot_clear,
4443 .reset = mv88e6352_g1_reset,
4444 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4445 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4446 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4448 .stu_getnext = mv88e6352_g1_stu_getnext,
4449 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4450 .avb_ops = &mv88e6165_avb_ops,
4451 .ptp_ops = &mv88e6165_ptp_ops,
4452 .phylink_get_caps = mv88e6185_phylink_get_caps,
4453 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4456 static const struct mv88e6xxx_ops mv88e6165_ops = {
4457 /* MV88E6XXX_FAMILY_6165 */
4458 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4459 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4460 .irl_init_all = mv88e6352_g2_irl_init_all,
4461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4462 .phy_read = mv88e6165_phy_read,
4463 .phy_write = mv88e6165_phy_write,
4464 .port_set_link = mv88e6xxx_port_set_link,
4465 .port_sync_link = mv88e6xxx_port_sync_link,
4466 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4467 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4468 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4469 .port_get_cmode = mv88e6185_port_get_cmode,
4470 .port_setup_message_port = mv88e6xxx_setup_message_port,
4471 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4472 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4473 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4474 .stats_get_strings = mv88e6095_stats_get_strings,
4475 .stats_get_stats = mv88e6095_stats_get_stats,
4476 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4477 .set_egress_port = mv88e6095_g1_set_egress_port,
4478 .watchdog_ops = &mv88e6097_watchdog_ops,
4479 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4480 .pot_clear = mv88e6xxx_g2_pot_clear,
4481 .reset = mv88e6352_g1_reset,
4482 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4483 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4484 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4485 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4486 .stu_getnext = mv88e6352_g1_stu_getnext,
4487 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4488 .avb_ops = &mv88e6165_avb_ops,
4489 .ptp_ops = &mv88e6165_ptp_ops,
4490 .phylink_get_caps = mv88e6185_phylink_get_caps,
4493 static const struct mv88e6xxx_ops mv88e6171_ops = {
4494 /* MV88E6XXX_FAMILY_6351 */
4495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4496 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4497 .irl_init_all = mv88e6352_g2_irl_init_all,
4498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4499 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4500 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4501 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4502 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4503 .port_set_link = mv88e6xxx_port_set_link,
4504 .port_sync_link = mv88e6xxx_port_sync_link,
4505 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4506 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4507 .port_tag_remap = mv88e6095_port_tag_remap,
4508 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4509 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4510 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4511 .port_set_ether_type = mv88e6351_port_set_ether_type,
4512 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4513 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4514 .port_pause_limit = mv88e6097_port_pause_limit,
4515 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4516 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4517 .port_get_cmode = mv88e6352_port_get_cmode,
4518 .port_setup_message_port = mv88e6xxx_setup_message_port,
4519 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4520 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4521 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4522 .stats_get_strings = mv88e6095_stats_get_strings,
4523 .stats_get_stats = mv88e6095_stats_get_stats,
4524 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4525 .set_egress_port = mv88e6095_g1_set_egress_port,
4526 .watchdog_ops = &mv88e6097_watchdog_ops,
4527 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4528 .pot_clear = mv88e6xxx_g2_pot_clear,
4529 .reset = mv88e6352_g1_reset,
4530 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4531 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4532 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4533 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4534 .stu_getnext = mv88e6352_g1_stu_getnext,
4535 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4536 .phylink_get_caps = mv88e6185_phylink_get_caps,
4539 static const struct mv88e6xxx_ops mv88e6172_ops = {
4540 /* MV88E6XXX_FAMILY_6352 */
4541 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4542 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4543 .irl_init_all = mv88e6352_g2_irl_init_all,
4544 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4545 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4546 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4547 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4548 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4549 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4550 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4551 .port_set_link = mv88e6xxx_port_set_link,
4552 .port_sync_link = mv88e6xxx_port_sync_link,
4553 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4554 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4555 .port_tag_remap = mv88e6095_port_tag_remap,
4556 .port_set_policy = mv88e6352_port_set_policy,
4557 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4558 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4559 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4560 .port_set_ether_type = mv88e6351_port_set_ether_type,
4561 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4562 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4563 .port_pause_limit = mv88e6097_port_pause_limit,
4564 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4565 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4566 .port_get_cmode = mv88e6352_port_get_cmode,
4567 .port_setup_message_port = mv88e6xxx_setup_message_port,
4568 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4569 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4570 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4571 .stats_get_strings = mv88e6095_stats_get_strings,
4572 .stats_get_stats = mv88e6095_stats_get_stats,
4573 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4574 .set_egress_port = mv88e6095_g1_set_egress_port,
4575 .watchdog_ops = &mv88e6097_watchdog_ops,
4576 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4577 .pot_clear = mv88e6xxx_g2_pot_clear,
4578 .reset = mv88e6352_g1_reset,
4579 .rmu_disable = mv88e6352_g1_rmu_disable,
4580 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4581 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4582 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4583 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4584 .stu_getnext = mv88e6352_g1_stu_getnext,
4585 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4586 .serdes_get_lane = mv88e6352_serdes_get_lane,
4587 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4588 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4589 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4590 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4591 .serdes_power = mv88e6352_serdes_power,
4592 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4593 .serdes_get_regs = mv88e6352_serdes_get_regs,
4594 .gpio_ops = &mv88e6352_gpio_ops,
4595 .phylink_get_caps = mv88e6352_phylink_get_caps,
4598 static const struct mv88e6xxx_ops mv88e6175_ops = {
4599 /* MV88E6XXX_FAMILY_6351 */
4600 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4601 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4602 .irl_init_all = mv88e6352_g2_irl_init_all,
4603 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4604 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4605 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4606 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4607 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4608 .port_set_link = mv88e6xxx_port_set_link,
4609 .port_sync_link = mv88e6xxx_port_sync_link,
4610 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4611 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4612 .port_tag_remap = mv88e6095_port_tag_remap,
4613 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4614 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4615 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4616 .port_set_ether_type = mv88e6351_port_set_ether_type,
4617 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4619 .port_pause_limit = mv88e6097_port_pause_limit,
4620 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4621 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4622 .port_get_cmode = mv88e6352_port_get_cmode,
4623 .port_setup_message_port = mv88e6xxx_setup_message_port,
4624 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4625 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4626 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4627 .stats_get_strings = mv88e6095_stats_get_strings,
4628 .stats_get_stats = mv88e6095_stats_get_stats,
4629 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4630 .set_egress_port = mv88e6095_g1_set_egress_port,
4631 .watchdog_ops = &mv88e6097_watchdog_ops,
4632 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4633 .pot_clear = mv88e6xxx_g2_pot_clear,
4634 .reset = mv88e6352_g1_reset,
4635 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4636 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4637 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4639 .stu_getnext = mv88e6352_g1_stu_getnext,
4640 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4641 .phylink_get_caps = mv88e6185_phylink_get_caps,
4644 static const struct mv88e6xxx_ops mv88e6176_ops = {
4645 /* MV88E6XXX_FAMILY_6352 */
4646 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4647 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4648 .irl_init_all = mv88e6352_g2_irl_init_all,
4649 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4650 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4651 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4652 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4653 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4654 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4655 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4656 .port_set_link = mv88e6xxx_port_set_link,
4657 .port_sync_link = mv88e6xxx_port_sync_link,
4658 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4659 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4660 .port_tag_remap = mv88e6095_port_tag_remap,
4661 .port_set_policy = mv88e6352_port_set_policy,
4662 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4663 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4664 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4665 .port_set_ether_type = mv88e6351_port_set_ether_type,
4666 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4667 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4668 .port_pause_limit = mv88e6097_port_pause_limit,
4669 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4670 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4671 .port_get_cmode = mv88e6352_port_get_cmode,
4672 .port_setup_message_port = mv88e6xxx_setup_message_port,
4673 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4674 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4675 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4676 .stats_get_strings = mv88e6095_stats_get_strings,
4677 .stats_get_stats = mv88e6095_stats_get_stats,
4678 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4679 .set_egress_port = mv88e6095_g1_set_egress_port,
4680 .watchdog_ops = &mv88e6097_watchdog_ops,
4681 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4682 .pot_clear = mv88e6xxx_g2_pot_clear,
4683 .reset = mv88e6352_g1_reset,
4684 .rmu_disable = mv88e6352_g1_rmu_disable,
4685 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4686 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4687 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4688 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4689 .stu_getnext = mv88e6352_g1_stu_getnext,
4690 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4691 .serdes_get_lane = mv88e6352_serdes_get_lane,
4692 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4693 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4694 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4695 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4696 .serdes_power = mv88e6352_serdes_power,
4697 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4698 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4699 .serdes_irq_status = mv88e6352_serdes_irq_status,
4700 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4701 .serdes_get_regs = mv88e6352_serdes_get_regs,
4702 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4703 .gpio_ops = &mv88e6352_gpio_ops,
4704 .phylink_get_caps = mv88e6352_phylink_get_caps,
4707 static const struct mv88e6xxx_ops mv88e6185_ops = {
4708 /* MV88E6XXX_FAMILY_6185 */
4709 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4710 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4711 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4712 .phy_read = mv88e6185_phy_ppu_read,
4713 .phy_write = mv88e6185_phy_ppu_write,
4714 .port_set_link = mv88e6xxx_port_set_link,
4715 .port_sync_link = mv88e6185_port_sync_link,
4716 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4717 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4718 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4719 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4720 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4721 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4722 .port_set_pause = mv88e6185_port_set_pause,
4723 .port_get_cmode = mv88e6185_port_get_cmode,
4724 .port_setup_message_port = mv88e6xxx_setup_message_port,
4725 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4726 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4727 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4728 .stats_get_strings = mv88e6095_stats_get_strings,
4729 .stats_get_stats = mv88e6095_stats_get_stats,
4730 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4731 .set_egress_port = mv88e6095_g1_set_egress_port,
4732 .watchdog_ops = &mv88e6097_watchdog_ops,
4733 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4734 .serdes_power = mv88e6185_serdes_power,
4735 .serdes_get_lane = mv88e6185_serdes_get_lane,
4736 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4737 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4738 .ppu_enable = mv88e6185_g1_ppu_enable,
4739 .ppu_disable = mv88e6185_g1_ppu_disable,
4740 .reset = mv88e6185_g1_reset,
4741 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4742 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4743 .phylink_get_caps = mv88e6185_phylink_get_caps,
4744 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4747 static const struct mv88e6xxx_ops mv88e6190_ops = {
4748 /* MV88E6XXX_FAMILY_6390 */
4749 .setup_errata = mv88e6390_setup_errata,
4750 .irl_init_all = mv88e6390_g2_irl_init_all,
4751 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4752 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4754 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4755 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4756 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4757 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4758 .port_set_link = mv88e6xxx_port_set_link,
4759 .port_sync_link = mv88e6xxx_port_sync_link,
4760 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4761 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4762 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4763 .port_tag_remap = mv88e6390_port_tag_remap,
4764 .port_set_policy = mv88e6352_port_set_policy,
4765 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4766 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4767 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4768 .port_set_ether_type = mv88e6351_port_set_ether_type,
4769 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4770 .port_pause_limit = mv88e6390_port_pause_limit,
4771 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4772 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4773 .port_get_cmode = mv88e6352_port_get_cmode,
4774 .port_set_cmode = mv88e6390_port_set_cmode,
4775 .port_setup_message_port = mv88e6xxx_setup_message_port,
4776 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4778 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4779 .stats_get_strings = mv88e6320_stats_get_strings,
4780 .stats_get_stats = mv88e6390_stats_get_stats,
4781 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4782 .set_egress_port = mv88e6390_g1_set_egress_port,
4783 .watchdog_ops = &mv88e6390_watchdog_ops,
4784 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4785 .pot_clear = mv88e6xxx_g2_pot_clear,
4786 .reset = mv88e6352_g1_reset,
4787 .rmu_disable = mv88e6390_g1_rmu_disable,
4788 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4789 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4790 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4791 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4792 .stu_getnext = mv88e6390_g1_stu_getnext,
4793 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4794 .serdes_power = mv88e6390_serdes_power,
4795 .serdes_get_lane = mv88e6390_serdes_get_lane,
4796 /* Check status register pause & lpa register */
4797 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4798 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4799 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4800 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4801 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4802 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4803 .serdes_irq_status = mv88e6390_serdes_irq_status,
4804 .serdes_get_strings = mv88e6390_serdes_get_strings,
4805 .serdes_get_stats = mv88e6390_serdes_get_stats,
4806 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4807 .serdes_get_regs = mv88e6390_serdes_get_regs,
4808 .gpio_ops = &mv88e6352_gpio_ops,
4809 .phylink_get_caps = mv88e6390_phylink_get_caps,
4812 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4813 /* MV88E6XXX_FAMILY_6390 */
4814 .setup_errata = mv88e6390_setup_errata,
4815 .irl_init_all = mv88e6390_g2_irl_init_all,
4816 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4817 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4818 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4819 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4820 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4821 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4822 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4823 .port_set_link = mv88e6xxx_port_set_link,
4824 .port_sync_link = mv88e6xxx_port_sync_link,
4825 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4826 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4827 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4828 .port_tag_remap = mv88e6390_port_tag_remap,
4829 .port_set_policy = mv88e6352_port_set_policy,
4830 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4831 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4832 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4833 .port_set_ether_type = mv88e6351_port_set_ether_type,
4834 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4835 .port_pause_limit = mv88e6390_port_pause_limit,
4836 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4837 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4838 .port_get_cmode = mv88e6352_port_get_cmode,
4839 .port_set_cmode = mv88e6390x_port_set_cmode,
4840 .port_setup_message_port = mv88e6xxx_setup_message_port,
4841 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4842 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4843 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4844 .stats_get_strings = mv88e6320_stats_get_strings,
4845 .stats_get_stats = mv88e6390_stats_get_stats,
4846 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4847 .set_egress_port = mv88e6390_g1_set_egress_port,
4848 .watchdog_ops = &mv88e6390_watchdog_ops,
4849 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4850 .pot_clear = mv88e6xxx_g2_pot_clear,
4851 .reset = mv88e6352_g1_reset,
4852 .rmu_disable = mv88e6390_g1_rmu_disable,
4853 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4854 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4855 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4856 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4857 .stu_getnext = mv88e6390_g1_stu_getnext,
4858 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4859 .serdes_power = mv88e6390_serdes_power,
4860 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4861 /* Check status register pause & lpa register */
4862 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4863 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4864 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4865 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4866 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4867 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4868 .serdes_irq_status = mv88e6390_serdes_irq_status,
4869 .serdes_get_strings = mv88e6390_serdes_get_strings,
4870 .serdes_get_stats = mv88e6390_serdes_get_stats,
4871 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4872 .serdes_get_regs = mv88e6390_serdes_get_regs,
4873 .gpio_ops = &mv88e6352_gpio_ops,
4874 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4877 static const struct mv88e6xxx_ops mv88e6191_ops = {
4878 /* MV88E6XXX_FAMILY_6390 */
4879 .setup_errata = mv88e6390_setup_errata,
4880 .irl_init_all = mv88e6390_g2_irl_init_all,
4881 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4882 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4883 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4884 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4885 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4886 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4887 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4888 .port_set_link = mv88e6xxx_port_set_link,
4889 .port_sync_link = mv88e6xxx_port_sync_link,
4890 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4891 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4892 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4893 .port_tag_remap = mv88e6390_port_tag_remap,
4894 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4895 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4896 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4897 .port_set_ether_type = mv88e6351_port_set_ether_type,
4898 .port_pause_limit = mv88e6390_port_pause_limit,
4899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4901 .port_get_cmode = mv88e6352_port_get_cmode,
4902 .port_set_cmode = mv88e6390_port_set_cmode,
4903 .port_setup_message_port = mv88e6xxx_setup_message_port,
4904 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4905 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4906 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4907 .stats_get_strings = mv88e6320_stats_get_strings,
4908 .stats_get_stats = mv88e6390_stats_get_stats,
4909 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4910 .set_egress_port = mv88e6390_g1_set_egress_port,
4911 .watchdog_ops = &mv88e6390_watchdog_ops,
4912 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4913 .pot_clear = mv88e6xxx_g2_pot_clear,
4914 .reset = mv88e6352_g1_reset,
4915 .rmu_disable = mv88e6390_g1_rmu_disable,
4916 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4917 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4918 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4919 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4920 .stu_getnext = mv88e6390_g1_stu_getnext,
4921 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4922 .serdes_power = mv88e6390_serdes_power,
4923 .serdes_get_lane = mv88e6390_serdes_get_lane,
4924 /* Check status register pause & lpa register */
4925 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4926 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4927 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4928 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4929 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4930 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4931 .serdes_irq_status = mv88e6390_serdes_irq_status,
4932 .serdes_get_strings = mv88e6390_serdes_get_strings,
4933 .serdes_get_stats = mv88e6390_serdes_get_stats,
4934 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4935 .serdes_get_regs = mv88e6390_serdes_get_regs,
4936 .avb_ops = &mv88e6390_avb_ops,
4937 .ptp_ops = &mv88e6352_ptp_ops,
4938 .phylink_get_caps = mv88e6390_phylink_get_caps,
4941 static const struct mv88e6xxx_ops mv88e6240_ops = {
4942 /* MV88E6XXX_FAMILY_6352 */
4943 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4944 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4945 .irl_init_all = mv88e6352_g2_irl_init_all,
4946 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4947 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4949 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4950 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4951 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4952 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4953 .port_set_link = mv88e6xxx_port_set_link,
4954 .port_sync_link = mv88e6xxx_port_sync_link,
4955 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4956 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4957 .port_tag_remap = mv88e6095_port_tag_remap,
4958 .port_set_policy = mv88e6352_port_set_policy,
4959 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4960 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4961 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4962 .port_set_ether_type = mv88e6351_port_set_ether_type,
4963 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4964 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4965 .port_pause_limit = mv88e6097_port_pause_limit,
4966 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4967 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4968 .port_get_cmode = mv88e6352_port_get_cmode,
4969 .port_setup_message_port = mv88e6xxx_setup_message_port,
4970 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4971 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4972 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4973 .stats_get_strings = mv88e6095_stats_get_strings,
4974 .stats_get_stats = mv88e6095_stats_get_stats,
4975 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4976 .set_egress_port = mv88e6095_g1_set_egress_port,
4977 .watchdog_ops = &mv88e6097_watchdog_ops,
4978 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4979 .pot_clear = mv88e6xxx_g2_pot_clear,
4980 .reset = mv88e6352_g1_reset,
4981 .rmu_disable = mv88e6352_g1_rmu_disable,
4982 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4983 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4984 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4985 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4986 .stu_getnext = mv88e6352_g1_stu_getnext,
4987 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4988 .serdes_get_lane = mv88e6352_serdes_get_lane,
4989 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4990 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4991 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4992 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4993 .serdes_power = mv88e6352_serdes_power,
4994 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4995 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4996 .serdes_irq_status = mv88e6352_serdes_irq_status,
4997 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4998 .serdes_get_regs = mv88e6352_serdes_get_regs,
4999 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5000 .gpio_ops = &mv88e6352_gpio_ops,
5001 .avb_ops = &mv88e6352_avb_ops,
5002 .ptp_ops = &mv88e6352_ptp_ops,
5003 .phylink_get_caps = mv88e6352_phylink_get_caps,
5006 static const struct mv88e6xxx_ops mv88e6250_ops = {
5007 /* MV88E6XXX_FAMILY_6250 */
5008 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5009 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5010 .irl_init_all = mv88e6352_g2_irl_init_all,
5011 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5012 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5013 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5014 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5015 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5016 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5017 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5018 .port_set_link = mv88e6xxx_port_set_link,
5019 .port_sync_link = mv88e6xxx_port_sync_link,
5020 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5021 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5022 .port_tag_remap = mv88e6095_port_tag_remap,
5023 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5024 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5025 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5026 .port_set_ether_type = mv88e6351_port_set_ether_type,
5027 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5028 .port_pause_limit = mv88e6097_port_pause_limit,
5029 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5030 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5031 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5032 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5033 .stats_get_strings = mv88e6250_stats_get_strings,
5034 .stats_get_stats = mv88e6250_stats_get_stats,
5035 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5036 .set_egress_port = mv88e6095_g1_set_egress_port,
5037 .watchdog_ops = &mv88e6250_watchdog_ops,
5038 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5039 .pot_clear = mv88e6xxx_g2_pot_clear,
5040 .reset = mv88e6250_g1_reset,
5041 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5042 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5043 .avb_ops = &mv88e6352_avb_ops,
5044 .ptp_ops = &mv88e6250_ptp_ops,
5045 .phylink_get_caps = mv88e6250_phylink_get_caps,
5048 static const struct mv88e6xxx_ops mv88e6290_ops = {
5049 /* MV88E6XXX_FAMILY_6390 */
5050 .setup_errata = mv88e6390_setup_errata,
5051 .irl_init_all = mv88e6390_g2_irl_init_all,
5052 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5053 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5054 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5055 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5056 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5057 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5058 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5059 .port_set_link = mv88e6xxx_port_set_link,
5060 .port_sync_link = mv88e6xxx_port_sync_link,
5061 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5062 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5063 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5064 .port_tag_remap = mv88e6390_port_tag_remap,
5065 .port_set_policy = mv88e6352_port_set_policy,
5066 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5067 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5068 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5069 .port_set_ether_type = mv88e6351_port_set_ether_type,
5070 .port_pause_limit = mv88e6390_port_pause_limit,
5071 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5072 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5073 .port_get_cmode = mv88e6352_port_get_cmode,
5074 .port_set_cmode = mv88e6390_port_set_cmode,
5075 .port_setup_message_port = mv88e6xxx_setup_message_port,
5076 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5077 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5078 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5079 .stats_get_strings = mv88e6320_stats_get_strings,
5080 .stats_get_stats = mv88e6390_stats_get_stats,
5081 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5082 .set_egress_port = mv88e6390_g1_set_egress_port,
5083 .watchdog_ops = &mv88e6390_watchdog_ops,
5084 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5085 .pot_clear = mv88e6xxx_g2_pot_clear,
5086 .reset = mv88e6352_g1_reset,
5087 .rmu_disable = mv88e6390_g1_rmu_disable,
5088 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5089 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5090 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5091 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5092 .stu_getnext = mv88e6390_g1_stu_getnext,
5093 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5094 .serdes_power = mv88e6390_serdes_power,
5095 .serdes_get_lane = mv88e6390_serdes_get_lane,
5096 /* Check status register pause & lpa register */
5097 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5098 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5099 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5100 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5101 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5102 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5103 .serdes_irq_status = mv88e6390_serdes_irq_status,
5104 .serdes_get_strings = mv88e6390_serdes_get_strings,
5105 .serdes_get_stats = mv88e6390_serdes_get_stats,
5106 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5107 .serdes_get_regs = mv88e6390_serdes_get_regs,
5108 .gpio_ops = &mv88e6352_gpio_ops,
5109 .avb_ops = &mv88e6390_avb_ops,
5110 .ptp_ops = &mv88e6390_ptp_ops,
5111 .phylink_get_caps = mv88e6390_phylink_get_caps,
5114 static const struct mv88e6xxx_ops mv88e6320_ops = {
5115 /* MV88E6XXX_FAMILY_6320 */
5116 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5117 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5118 .irl_init_all = mv88e6352_g2_irl_init_all,
5119 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5120 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5121 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5122 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5123 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5124 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5125 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5126 .port_set_link = mv88e6xxx_port_set_link,
5127 .port_sync_link = mv88e6xxx_port_sync_link,
5128 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5129 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5130 .port_tag_remap = mv88e6095_port_tag_remap,
5131 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5132 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5133 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5134 .port_set_ether_type = mv88e6351_port_set_ether_type,
5135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5136 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5137 .port_pause_limit = mv88e6097_port_pause_limit,
5138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5140 .port_get_cmode = mv88e6352_port_get_cmode,
5141 .port_setup_message_port = mv88e6xxx_setup_message_port,
5142 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5143 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5144 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5145 .stats_get_strings = mv88e6320_stats_get_strings,
5146 .stats_get_stats = mv88e6320_stats_get_stats,
5147 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5148 .set_egress_port = mv88e6095_g1_set_egress_port,
5149 .watchdog_ops = &mv88e6390_watchdog_ops,
5150 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5151 .pot_clear = mv88e6xxx_g2_pot_clear,
5152 .reset = mv88e6352_g1_reset,
5153 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5154 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5155 .gpio_ops = &mv88e6352_gpio_ops,
5156 .avb_ops = &mv88e6352_avb_ops,
5157 .ptp_ops = &mv88e6352_ptp_ops,
5158 .phylink_get_caps = mv88e6185_phylink_get_caps,
5161 static const struct mv88e6xxx_ops mv88e6321_ops = {
5162 /* MV88E6XXX_FAMILY_6320 */
5163 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5164 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5165 .irl_init_all = mv88e6352_g2_irl_init_all,
5166 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5167 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5168 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5169 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5170 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5171 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5172 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5173 .port_set_link = mv88e6xxx_port_set_link,
5174 .port_sync_link = mv88e6xxx_port_sync_link,
5175 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5176 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5177 .port_tag_remap = mv88e6095_port_tag_remap,
5178 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5179 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5180 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5181 .port_set_ether_type = mv88e6351_port_set_ether_type,
5182 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5183 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5184 .port_pause_limit = mv88e6097_port_pause_limit,
5185 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5186 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5187 .port_get_cmode = mv88e6352_port_get_cmode,
5188 .port_setup_message_port = mv88e6xxx_setup_message_port,
5189 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5190 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5191 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5192 .stats_get_strings = mv88e6320_stats_get_strings,
5193 .stats_get_stats = mv88e6320_stats_get_stats,
5194 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5195 .set_egress_port = mv88e6095_g1_set_egress_port,
5196 .watchdog_ops = &mv88e6390_watchdog_ops,
5197 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5198 .reset = mv88e6352_g1_reset,
5199 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5200 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5201 .gpio_ops = &mv88e6352_gpio_ops,
5202 .avb_ops = &mv88e6352_avb_ops,
5203 .ptp_ops = &mv88e6352_ptp_ops,
5204 .phylink_get_caps = mv88e6185_phylink_get_caps,
5207 static const struct mv88e6xxx_ops mv88e6341_ops = {
5208 /* MV88E6XXX_FAMILY_6341 */
5209 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5210 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5211 .irl_init_all = mv88e6352_g2_irl_init_all,
5212 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5213 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5214 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5215 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5216 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5217 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5218 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5219 .port_set_link = mv88e6xxx_port_set_link,
5220 .port_sync_link = mv88e6xxx_port_sync_link,
5221 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5222 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5223 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5224 .port_tag_remap = mv88e6095_port_tag_remap,
5225 .port_set_policy = mv88e6352_port_set_policy,
5226 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5227 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5228 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5229 .port_set_ether_type = mv88e6351_port_set_ether_type,
5230 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5232 .port_pause_limit = mv88e6097_port_pause_limit,
5233 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5235 .port_get_cmode = mv88e6352_port_get_cmode,
5236 .port_set_cmode = mv88e6341_port_set_cmode,
5237 .port_setup_message_port = mv88e6xxx_setup_message_port,
5238 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5239 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5240 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5241 .stats_get_strings = mv88e6320_stats_get_strings,
5242 .stats_get_stats = mv88e6390_stats_get_stats,
5243 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5244 .set_egress_port = mv88e6390_g1_set_egress_port,
5245 .watchdog_ops = &mv88e6390_watchdog_ops,
5246 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5247 .pot_clear = mv88e6xxx_g2_pot_clear,
5248 .reset = mv88e6352_g1_reset,
5249 .rmu_disable = mv88e6390_g1_rmu_disable,
5250 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5251 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5252 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5253 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5254 .stu_getnext = mv88e6352_g1_stu_getnext,
5255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5256 .serdes_power = mv88e6390_serdes_power,
5257 .serdes_get_lane = mv88e6341_serdes_get_lane,
5258 /* Check status register pause & lpa register */
5259 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5260 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5261 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5262 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5263 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5264 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5265 .serdes_irq_status = mv88e6390_serdes_irq_status,
5266 .gpio_ops = &mv88e6352_gpio_ops,
5267 .avb_ops = &mv88e6390_avb_ops,
5268 .ptp_ops = &mv88e6352_ptp_ops,
5269 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5270 .serdes_get_strings = mv88e6390_serdes_get_strings,
5271 .serdes_get_stats = mv88e6390_serdes_get_stats,
5272 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5273 .serdes_get_regs = mv88e6390_serdes_get_regs,
5274 .phylink_get_caps = mv88e6341_phylink_get_caps,
5277 static const struct mv88e6xxx_ops mv88e6350_ops = {
5278 /* MV88E6XXX_FAMILY_6351 */
5279 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5280 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5281 .irl_init_all = mv88e6352_g2_irl_init_all,
5282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5283 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5284 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5285 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5286 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5287 .port_set_link = mv88e6xxx_port_set_link,
5288 .port_sync_link = mv88e6xxx_port_sync_link,
5289 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5291 .port_tag_remap = mv88e6095_port_tag_remap,
5292 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5293 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5294 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5295 .port_set_ether_type = mv88e6351_port_set_ether_type,
5296 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5297 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5298 .port_pause_limit = mv88e6097_port_pause_limit,
5299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5301 .port_get_cmode = mv88e6352_port_get_cmode,
5302 .port_setup_message_port = mv88e6xxx_setup_message_port,
5303 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5304 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5305 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5306 .stats_get_strings = mv88e6095_stats_get_strings,
5307 .stats_get_stats = mv88e6095_stats_get_stats,
5308 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5309 .set_egress_port = mv88e6095_g1_set_egress_port,
5310 .watchdog_ops = &mv88e6097_watchdog_ops,
5311 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5312 .pot_clear = mv88e6xxx_g2_pot_clear,
5313 .reset = mv88e6352_g1_reset,
5314 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5315 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5316 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5317 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5318 .stu_getnext = mv88e6352_g1_stu_getnext,
5319 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5320 .phylink_get_caps = mv88e6185_phylink_get_caps,
5323 static const struct mv88e6xxx_ops mv88e6351_ops = {
5324 /* MV88E6XXX_FAMILY_6351 */
5325 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5326 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5327 .irl_init_all = mv88e6352_g2_irl_init_all,
5328 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5329 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5330 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5331 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5332 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5333 .port_set_link = mv88e6xxx_port_set_link,
5334 .port_sync_link = mv88e6xxx_port_sync_link,
5335 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5336 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5337 .port_tag_remap = mv88e6095_port_tag_remap,
5338 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5339 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5340 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5341 .port_set_ether_type = mv88e6351_port_set_ether_type,
5342 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5343 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5344 .port_pause_limit = mv88e6097_port_pause_limit,
5345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5347 .port_get_cmode = mv88e6352_port_get_cmode,
5348 .port_setup_message_port = mv88e6xxx_setup_message_port,
5349 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5350 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5351 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5352 .stats_get_strings = mv88e6095_stats_get_strings,
5353 .stats_get_stats = mv88e6095_stats_get_stats,
5354 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5355 .set_egress_port = mv88e6095_g1_set_egress_port,
5356 .watchdog_ops = &mv88e6097_watchdog_ops,
5357 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5358 .pot_clear = mv88e6xxx_g2_pot_clear,
5359 .reset = mv88e6352_g1_reset,
5360 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5361 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5362 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5363 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5364 .stu_getnext = mv88e6352_g1_stu_getnext,
5365 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5366 .avb_ops = &mv88e6352_avb_ops,
5367 .ptp_ops = &mv88e6352_ptp_ops,
5368 .phylink_get_caps = mv88e6185_phylink_get_caps,
5371 static const struct mv88e6xxx_ops mv88e6352_ops = {
5372 /* MV88E6XXX_FAMILY_6352 */
5373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5375 .irl_init_all = mv88e6352_g2_irl_init_all,
5376 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5377 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5379 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5380 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5381 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5382 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5383 .port_set_link = mv88e6xxx_port_set_link,
5384 .port_sync_link = mv88e6xxx_port_sync_link,
5385 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5386 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5387 .port_tag_remap = mv88e6095_port_tag_remap,
5388 .port_set_policy = mv88e6352_port_set_policy,
5389 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5390 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5391 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5392 .port_set_ether_type = mv88e6351_port_set_ether_type,
5393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5395 .port_pause_limit = mv88e6097_port_pause_limit,
5396 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5397 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5398 .port_get_cmode = mv88e6352_port_get_cmode,
5399 .port_setup_message_port = mv88e6xxx_setup_message_port,
5400 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5401 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5402 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5403 .stats_get_strings = mv88e6095_stats_get_strings,
5404 .stats_get_stats = mv88e6095_stats_get_stats,
5405 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5406 .set_egress_port = mv88e6095_g1_set_egress_port,
5407 .watchdog_ops = &mv88e6097_watchdog_ops,
5408 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5409 .pot_clear = mv88e6xxx_g2_pot_clear,
5410 .reset = mv88e6352_g1_reset,
5411 .rmu_disable = mv88e6352_g1_rmu_disable,
5412 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5413 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5414 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5415 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5416 .stu_getnext = mv88e6352_g1_stu_getnext,
5417 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5418 .serdes_get_lane = mv88e6352_serdes_get_lane,
5419 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
5420 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
5421 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
5422 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
5423 .serdes_power = mv88e6352_serdes_power,
5424 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5425 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
5426 .serdes_irq_status = mv88e6352_serdes_irq_status,
5427 .gpio_ops = &mv88e6352_gpio_ops,
5428 .avb_ops = &mv88e6352_avb_ops,
5429 .ptp_ops = &mv88e6352_ptp_ops,
5430 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5431 .serdes_get_strings = mv88e6352_serdes_get_strings,
5432 .serdes_get_stats = mv88e6352_serdes_get_stats,
5433 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5434 .serdes_get_regs = mv88e6352_serdes_get_regs,
5435 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5436 .phylink_get_caps = mv88e6352_phylink_get_caps,
5439 static const struct mv88e6xxx_ops mv88e6390_ops = {
5440 /* MV88E6XXX_FAMILY_6390 */
5441 .setup_errata = mv88e6390_setup_errata,
5442 .irl_init_all = mv88e6390_g2_irl_init_all,
5443 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5444 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5446 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5447 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5448 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5449 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5450 .port_set_link = mv88e6xxx_port_set_link,
5451 .port_sync_link = mv88e6xxx_port_sync_link,
5452 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5453 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5454 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5455 .port_tag_remap = mv88e6390_port_tag_remap,
5456 .port_set_policy = mv88e6352_port_set_policy,
5457 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5458 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5459 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5460 .port_set_ether_type = mv88e6351_port_set_ether_type,
5461 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5462 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5463 .port_pause_limit = mv88e6390_port_pause_limit,
5464 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5465 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5466 .port_get_cmode = mv88e6352_port_get_cmode,
5467 .port_set_cmode = mv88e6390_port_set_cmode,
5468 .port_setup_message_port = mv88e6xxx_setup_message_port,
5469 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5470 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5471 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5472 .stats_get_strings = mv88e6320_stats_get_strings,
5473 .stats_get_stats = mv88e6390_stats_get_stats,
5474 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5475 .set_egress_port = mv88e6390_g1_set_egress_port,
5476 .watchdog_ops = &mv88e6390_watchdog_ops,
5477 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5478 .pot_clear = mv88e6xxx_g2_pot_clear,
5479 .reset = mv88e6352_g1_reset,
5480 .rmu_disable = mv88e6390_g1_rmu_disable,
5481 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485 .stu_getnext = mv88e6390_g1_stu_getnext,
5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487 .serdes_power = mv88e6390_serdes_power,
5488 .serdes_get_lane = mv88e6390_serdes_get_lane,
5489 /* Check status register pause & lpa register */
5490 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5491 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5492 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5493 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5494 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5495 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5496 .serdes_irq_status = mv88e6390_serdes_irq_status,
5497 .gpio_ops = &mv88e6352_gpio_ops,
5498 .avb_ops = &mv88e6390_avb_ops,
5499 .ptp_ops = &mv88e6390_ptp_ops,
5500 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5501 .serdes_get_strings = mv88e6390_serdes_get_strings,
5502 .serdes_get_stats = mv88e6390_serdes_get_stats,
5503 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5504 .serdes_get_regs = mv88e6390_serdes_get_regs,
5505 .phylink_get_caps = mv88e6390_phylink_get_caps,
5508 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5509 /* MV88E6XXX_FAMILY_6390 */
5510 .setup_errata = mv88e6390_setup_errata,
5511 .irl_init_all = mv88e6390_g2_irl_init_all,
5512 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5513 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5514 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5515 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5516 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5517 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5518 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5519 .port_set_link = mv88e6xxx_port_set_link,
5520 .port_sync_link = mv88e6xxx_port_sync_link,
5521 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5522 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5523 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5524 .port_tag_remap = mv88e6390_port_tag_remap,
5525 .port_set_policy = mv88e6352_port_set_policy,
5526 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5527 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5528 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5529 .port_set_ether_type = mv88e6351_port_set_ether_type,
5530 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5531 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5532 .port_pause_limit = mv88e6390_port_pause_limit,
5533 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5534 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5535 .port_get_cmode = mv88e6352_port_get_cmode,
5536 .port_set_cmode = mv88e6390x_port_set_cmode,
5537 .port_setup_message_port = mv88e6xxx_setup_message_port,
5538 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5539 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5540 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5541 .stats_get_strings = mv88e6320_stats_get_strings,
5542 .stats_get_stats = mv88e6390_stats_get_stats,
5543 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5544 .set_egress_port = mv88e6390_g1_set_egress_port,
5545 .watchdog_ops = &mv88e6390_watchdog_ops,
5546 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5547 .pot_clear = mv88e6xxx_g2_pot_clear,
5548 .reset = mv88e6352_g1_reset,
5549 .rmu_disable = mv88e6390_g1_rmu_disable,
5550 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5551 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5552 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5553 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5554 .stu_getnext = mv88e6390_g1_stu_getnext,
5555 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5556 .serdes_power = mv88e6390_serdes_power,
5557 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5558 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5559 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5560 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5561 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5562 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5563 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5564 .serdes_irq_status = mv88e6390_serdes_irq_status,
5565 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5566 .serdes_get_strings = mv88e6390_serdes_get_strings,
5567 .serdes_get_stats = mv88e6390_serdes_get_stats,
5568 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5569 .serdes_get_regs = mv88e6390_serdes_get_regs,
5570 .gpio_ops = &mv88e6352_gpio_ops,
5571 .avb_ops = &mv88e6390_avb_ops,
5572 .ptp_ops = &mv88e6390_ptp_ops,
5573 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5576 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5577 /* MV88E6XXX_FAMILY_6393 */
5578 .setup_errata = mv88e6393x_serdes_setup_errata,
5579 .irl_init_all = mv88e6390_g2_irl_init_all,
5580 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5581 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5582 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5583 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5584 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5585 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5586 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5587 .port_set_link = mv88e6xxx_port_set_link,
5588 .port_sync_link = mv88e6xxx_port_sync_link,
5589 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5590 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5591 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5592 .port_tag_remap = mv88e6390_port_tag_remap,
5593 .port_set_policy = mv88e6393x_port_set_policy,
5594 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5595 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5596 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5597 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5598 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5599 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5600 .port_pause_limit = mv88e6390_port_pause_limit,
5601 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5602 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5603 .port_get_cmode = mv88e6352_port_get_cmode,
5604 .port_set_cmode = mv88e6393x_port_set_cmode,
5605 .port_setup_message_port = mv88e6xxx_setup_message_port,
5606 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5607 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5608 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5609 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5610 .stats_get_strings = mv88e6320_stats_get_strings,
5611 .stats_get_stats = mv88e6390_stats_get_stats,
5612 /* .set_cpu_port is missing because this family does not support a global
5613 * CPU port, only per port CPU port which is set via
5614 * .port_set_upstream_port method.
5616 .set_egress_port = mv88e6393x_set_egress_port,
5617 .watchdog_ops = &mv88e6393x_watchdog_ops,
5618 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5619 .pot_clear = mv88e6xxx_g2_pot_clear,
5620 .reset = mv88e6352_g1_reset,
5621 .rmu_disable = mv88e6390_g1_rmu_disable,
5622 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5623 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5624 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5625 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5626 .stu_getnext = mv88e6390_g1_stu_getnext,
5627 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5628 .serdes_power = mv88e6393x_serdes_power,
5629 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5630 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
5631 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5632 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5633 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5634 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5635 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
5636 .serdes_irq_status = mv88e6393x_serdes_irq_status,
5637 /* TODO: serdes stats */
5638 .gpio_ops = &mv88e6352_gpio_ops,
5639 .avb_ops = &mv88e6390_avb_ops,
5640 .ptp_ops = &mv88e6352_ptp_ops,
5641 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5644 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5646 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5647 .family = MV88E6XXX_FAMILY_6097,
5648 .name = "Marvell 88E6085",
5649 .num_databases = 4096,
5652 .num_internal_phys = 5,
5655 .port_base_addr = 0x10,
5656 .phy_base_addr = 0x0,
5657 .global1_addr = 0x1b,
5658 .global2_addr = 0x1c,
5659 .age_time_coeff = 15000,
5662 .atu_move_port_mask = 0xf,
5665 .ops = &mv88e6085_ops,
5669 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5670 .family = MV88E6XXX_FAMILY_6095,
5671 .name = "Marvell 88E6095/88E6095F",
5672 .num_databases = 256,
5675 .num_internal_phys = 0,
5677 .port_base_addr = 0x10,
5678 .phy_base_addr = 0x0,
5679 .global1_addr = 0x1b,
5680 .global2_addr = 0x1c,
5681 .age_time_coeff = 15000,
5683 .atu_move_port_mask = 0xf,
5685 .ops = &mv88e6095_ops,
5689 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5690 .family = MV88E6XXX_FAMILY_6097,
5691 .name = "Marvell 88E6097/88E6097F",
5692 .num_databases = 4096,
5695 .num_internal_phys = 8,
5698 .port_base_addr = 0x10,
5699 .phy_base_addr = 0x0,
5700 .global1_addr = 0x1b,
5701 .global2_addr = 0x1c,
5702 .age_time_coeff = 15000,
5705 .atu_move_port_mask = 0xf,
5708 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5709 .ops = &mv88e6097_ops,
5713 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5714 .family = MV88E6XXX_FAMILY_6165,
5715 .name = "Marvell 88E6123",
5716 .num_databases = 4096,
5719 .num_internal_phys = 5,
5722 .port_base_addr = 0x10,
5723 .phy_base_addr = 0x0,
5724 .global1_addr = 0x1b,
5725 .global2_addr = 0x1c,
5726 .age_time_coeff = 15000,
5729 .atu_move_port_mask = 0xf,
5732 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5733 .ops = &mv88e6123_ops,
5737 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5738 .family = MV88E6XXX_FAMILY_6185,
5739 .name = "Marvell 88E6131",
5740 .num_databases = 256,
5743 .num_internal_phys = 0,
5745 .port_base_addr = 0x10,
5746 .phy_base_addr = 0x0,
5747 .global1_addr = 0x1b,
5748 .global2_addr = 0x1c,
5749 .age_time_coeff = 15000,
5751 .atu_move_port_mask = 0xf,
5753 .ops = &mv88e6131_ops,
5757 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5758 .family = MV88E6XXX_FAMILY_6341,
5759 .name = "Marvell 88E6141",
5760 .num_databases = 4096,
5763 .num_internal_phys = 5,
5767 .port_base_addr = 0x10,
5768 .phy_base_addr = 0x10,
5769 .global1_addr = 0x1b,
5770 .global2_addr = 0x1c,
5771 .age_time_coeff = 3750,
5772 .atu_move_port_mask = 0x1f,
5777 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5778 .ops = &mv88e6141_ops,
5782 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5783 .family = MV88E6XXX_FAMILY_6165,
5784 .name = "Marvell 88E6161",
5785 .num_databases = 4096,
5788 .num_internal_phys = 5,
5791 .port_base_addr = 0x10,
5792 .phy_base_addr = 0x0,
5793 .global1_addr = 0x1b,
5794 .global2_addr = 0x1c,
5795 .age_time_coeff = 15000,
5798 .atu_move_port_mask = 0xf,
5801 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5802 .ptp_support = true,
5803 .ops = &mv88e6161_ops,
5807 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5808 .family = MV88E6XXX_FAMILY_6165,
5809 .name = "Marvell 88E6165",
5810 .num_databases = 4096,
5813 .num_internal_phys = 0,
5816 .port_base_addr = 0x10,
5817 .phy_base_addr = 0x0,
5818 .global1_addr = 0x1b,
5819 .global2_addr = 0x1c,
5820 .age_time_coeff = 15000,
5823 .atu_move_port_mask = 0xf,
5826 .ptp_support = true,
5827 .ops = &mv88e6165_ops,
5831 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5832 .family = MV88E6XXX_FAMILY_6351,
5833 .name = "Marvell 88E6171",
5834 .num_databases = 4096,
5837 .num_internal_phys = 5,
5840 .port_base_addr = 0x10,
5841 .phy_base_addr = 0x0,
5842 .global1_addr = 0x1b,
5843 .global2_addr = 0x1c,
5844 .age_time_coeff = 15000,
5847 .atu_move_port_mask = 0xf,
5850 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5851 .ops = &mv88e6171_ops,
5855 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5856 .family = MV88E6XXX_FAMILY_6352,
5857 .name = "Marvell 88E6172",
5858 .num_databases = 4096,
5861 .num_internal_phys = 5,
5865 .port_base_addr = 0x10,
5866 .phy_base_addr = 0x0,
5867 .global1_addr = 0x1b,
5868 .global2_addr = 0x1c,
5869 .age_time_coeff = 15000,
5872 .atu_move_port_mask = 0xf,
5875 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5876 .ops = &mv88e6172_ops,
5880 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5881 .family = MV88E6XXX_FAMILY_6351,
5882 .name = "Marvell 88E6175",
5883 .num_databases = 4096,
5886 .num_internal_phys = 5,
5889 .port_base_addr = 0x10,
5890 .phy_base_addr = 0x0,
5891 .global1_addr = 0x1b,
5892 .global2_addr = 0x1c,
5893 .age_time_coeff = 15000,
5896 .atu_move_port_mask = 0xf,
5899 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5900 .ops = &mv88e6175_ops,
5904 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5905 .family = MV88E6XXX_FAMILY_6352,
5906 .name = "Marvell 88E6176",
5907 .num_databases = 4096,
5910 .num_internal_phys = 5,
5914 .port_base_addr = 0x10,
5915 .phy_base_addr = 0x0,
5916 .global1_addr = 0x1b,
5917 .global2_addr = 0x1c,
5918 .age_time_coeff = 15000,
5921 .atu_move_port_mask = 0xf,
5924 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5925 .ops = &mv88e6176_ops,
5929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5930 .family = MV88E6XXX_FAMILY_6185,
5931 .name = "Marvell 88E6185",
5932 .num_databases = 256,
5935 .num_internal_phys = 0,
5937 .port_base_addr = 0x10,
5938 .phy_base_addr = 0x0,
5939 .global1_addr = 0x1b,
5940 .global2_addr = 0x1c,
5941 .age_time_coeff = 15000,
5943 .atu_move_port_mask = 0xf,
5945 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5946 .ops = &mv88e6185_ops,
5950 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5951 .family = MV88E6XXX_FAMILY_6390,
5952 .name = "Marvell 88E6190",
5953 .num_databases = 4096,
5955 .num_ports = 11, /* 10 + Z80 */
5956 .num_internal_phys = 9,
5960 .port_base_addr = 0x0,
5961 .phy_base_addr = 0x0,
5962 .global1_addr = 0x1b,
5963 .global2_addr = 0x1c,
5964 .age_time_coeff = 3750,
5969 .atu_move_port_mask = 0x1f,
5970 .ops = &mv88e6190_ops,
5974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5975 .family = MV88E6XXX_FAMILY_6390,
5976 .name = "Marvell 88E6190X",
5977 .num_databases = 4096,
5979 .num_ports = 11, /* 10 + Z80 */
5980 .num_internal_phys = 9,
5984 .port_base_addr = 0x0,
5985 .phy_base_addr = 0x0,
5986 .global1_addr = 0x1b,
5987 .global2_addr = 0x1c,
5988 .age_time_coeff = 3750,
5991 .atu_move_port_mask = 0x1f,
5994 .ops = &mv88e6190x_ops,
5998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5999 .family = MV88E6XXX_FAMILY_6390,
6000 .name = "Marvell 88E6191",
6001 .num_databases = 4096,
6003 .num_ports = 11, /* 10 + Z80 */
6004 .num_internal_phys = 9,
6007 .port_base_addr = 0x0,
6008 .phy_base_addr = 0x0,
6009 .global1_addr = 0x1b,
6010 .global2_addr = 0x1c,
6011 .age_time_coeff = 3750,
6014 .atu_move_port_mask = 0x1f,
6017 .ptp_support = true,
6018 .ops = &mv88e6191_ops,
6022 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6023 .family = MV88E6XXX_FAMILY_6393,
6024 .name = "Marvell 88E6191X",
6025 .num_databases = 4096,
6026 .num_ports = 11, /* 10 + Z80 */
6027 .num_internal_phys = 9,
6030 .port_base_addr = 0x0,
6031 .phy_base_addr = 0x0,
6032 .global1_addr = 0x1b,
6033 .global2_addr = 0x1c,
6034 .age_time_coeff = 3750,
6037 .atu_move_port_mask = 0x1f,
6040 .ptp_support = true,
6041 .ops = &mv88e6393x_ops,
6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6046 .family = MV88E6XXX_FAMILY_6393,
6047 .name = "Marvell 88E6193X",
6048 .num_databases = 4096,
6049 .num_ports = 11, /* 10 + Z80 */
6050 .num_internal_phys = 9,
6053 .port_base_addr = 0x0,
6054 .phy_base_addr = 0x0,
6055 .global1_addr = 0x1b,
6056 .global2_addr = 0x1c,
6057 .age_time_coeff = 3750,
6060 .atu_move_port_mask = 0x1f,
6063 .ptp_support = true,
6064 .ops = &mv88e6393x_ops,
6068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6069 .family = MV88E6XXX_FAMILY_6250,
6070 .name = "Marvell 88E6220",
6071 .num_databases = 64,
6073 /* Ports 2-4 are not routed to pins
6074 * => usable ports 0, 1, 5, 6
6077 .num_internal_phys = 2,
6078 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6080 .port_base_addr = 0x08,
6081 .phy_base_addr = 0x00,
6082 .global1_addr = 0x0f,
6083 .global2_addr = 0x07,
6084 .age_time_coeff = 15000,
6087 .atu_move_port_mask = 0xf,
6089 .ptp_support = true,
6090 .ops = &mv88e6250_ops,
6094 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6095 .family = MV88E6XXX_FAMILY_6352,
6096 .name = "Marvell 88E6240",
6097 .num_databases = 4096,
6100 .num_internal_phys = 5,
6104 .port_base_addr = 0x10,
6105 .phy_base_addr = 0x0,
6106 .global1_addr = 0x1b,
6107 .global2_addr = 0x1c,
6108 .age_time_coeff = 15000,
6111 .atu_move_port_mask = 0xf,
6114 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6115 .ptp_support = true,
6116 .ops = &mv88e6240_ops,
6120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6121 .family = MV88E6XXX_FAMILY_6250,
6122 .name = "Marvell 88E6250",
6123 .num_databases = 64,
6125 .num_internal_phys = 5,
6127 .port_base_addr = 0x08,
6128 .phy_base_addr = 0x00,
6129 .global1_addr = 0x0f,
6130 .global2_addr = 0x07,
6131 .age_time_coeff = 15000,
6134 .atu_move_port_mask = 0xf,
6136 .ptp_support = true,
6137 .ops = &mv88e6250_ops,
6141 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6142 .family = MV88E6XXX_FAMILY_6390,
6143 .name = "Marvell 88E6290",
6144 .num_databases = 4096,
6145 .num_ports = 11, /* 10 + Z80 */
6146 .num_internal_phys = 9,
6150 .port_base_addr = 0x0,
6151 .phy_base_addr = 0x0,
6152 .global1_addr = 0x1b,
6153 .global2_addr = 0x1c,
6154 .age_time_coeff = 3750,
6157 .atu_move_port_mask = 0x1f,
6160 .ptp_support = true,
6161 .ops = &mv88e6290_ops,
6165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6166 .family = MV88E6XXX_FAMILY_6320,
6167 .name = "Marvell 88E6320",
6168 .num_databases = 4096,
6171 .num_internal_phys = 5,
6174 .port_base_addr = 0x10,
6175 .phy_base_addr = 0x0,
6176 .global1_addr = 0x1b,
6177 .global2_addr = 0x1c,
6178 .age_time_coeff = 15000,
6181 .atu_move_port_mask = 0xf,
6184 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6185 .ptp_support = true,
6186 .ops = &mv88e6320_ops,
6190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6191 .family = MV88E6XXX_FAMILY_6320,
6192 .name = "Marvell 88E6321",
6193 .num_databases = 4096,
6196 .num_internal_phys = 5,
6199 .port_base_addr = 0x10,
6200 .phy_base_addr = 0x0,
6201 .global1_addr = 0x1b,
6202 .global2_addr = 0x1c,
6203 .age_time_coeff = 15000,
6206 .atu_move_port_mask = 0xf,
6208 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6209 .ptp_support = true,
6210 .ops = &mv88e6321_ops,
6214 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6215 .family = MV88E6XXX_FAMILY_6341,
6216 .name = "Marvell 88E6341",
6217 .num_databases = 4096,
6219 .num_internal_phys = 5,
6224 .port_base_addr = 0x10,
6225 .phy_base_addr = 0x10,
6226 .global1_addr = 0x1b,
6227 .global2_addr = 0x1c,
6228 .age_time_coeff = 3750,
6229 .atu_move_port_mask = 0x1f,
6234 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6235 .ptp_support = true,
6236 .ops = &mv88e6341_ops,
6240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6241 .family = MV88E6XXX_FAMILY_6351,
6242 .name = "Marvell 88E6350",
6243 .num_databases = 4096,
6246 .num_internal_phys = 5,
6249 .port_base_addr = 0x10,
6250 .phy_base_addr = 0x0,
6251 .global1_addr = 0x1b,
6252 .global2_addr = 0x1c,
6253 .age_time_coeff = 15000,
6256 .atu_move_port_mask = 0xf,
6259 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6260 .ops = &mv88e6350_ops,
6264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6265 .family = MV88E6XXX_FAMILY_6351,
6266 .name = "Marvell 88E6351",
6267 .num_databases = 4096,
6270 .num_internal_phys = 5,
6273 .port_base_addr = 0x10,
6274 .phy_base_addr = 0x0,
6275 .global1_addr = 0x1b,
6276 .global2_addr = 0x1c,
6277 .age_time_coeff = 15000,
6280 .atu_move_port_mask = 0xf,
6283 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6284 .ops = &mv88e6351_ops,
6288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6289 .family = MV88E6XXX_FAMILY_6352,
6290 .name = "Marvell 88E6352",
6291 .num_databases = 4096,
6294 .num_internal_phys = 5,
6298 .port_base_addr = 0x10,
6299 .phy_base_addr = 0x0,
6300 .global1_addr = 0x1b,
6301 .global2_addr = 0x1c,
6302 .age_time_coeff = 15000,
6305 .atu_move_port_mask = 0xf,
6308 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6309 .ptp_support = true,
6310 .ops = &mv88e6352_ops,
6313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6314 .family = MV88E6XXX_FAMILY_6390,
6315 .name = "Marvell 88E6390",
6316 .num_databases = 4096,
6318 .num_ports = 11, /* 10 + Z80 */
6319 .num_internal_phys = 9,
6323 .port_base_addr = 0x0,
6324 .phy_base_addr = 0x0,
6325 .global1_addr = 0x1b,
6326 .global2_addr = 0x1c,
6327 .age_time_coeff = 3750,
6330 .atu_move_port_mask = 0x1f,
6333 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6334 .ptp_support = true,
6335 .ops = &mv88e6390_ops,
6338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6339 .family = MV88E6XXX_FAMILY_6390,
6340 .name = "Marvell 88E6390X",
6341 .num_databases = 4096,
6343 .num_ports = 11, /* 10 + Z80 */
6344 .num_internal_phys = 9,
6348 .port_base_addr = 0x0,
6349 .phy_base_addr = 0x0,
6350 .global1_addr = 0x1b,
6351 .global2_addr = 0x1c,
6352 .age_time_coeff = 3750,
6355 .atu_move_port_mask = 0x1f,
6358 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6359 .ptp_support = true,
6360 .ops = &mv88e6390x_ops,
6364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6365 .family = MV88E6XXX_FAMILY_6393,
6366 .name = "Marvell 88E6393X",
6367 .num_databases = 4096,
6368 .num_ports = 11, /* 10 + Z80 */
6369 .num_internal_phys = 9,
6372 .port_base_addr = 0x0,
6373 .phy_base_addr = 0x0,
6374 .global1_addr = 0x1b,
6375 .global2_addr = 0x1c,
6376 .age_time_coeff = 3750,
6379 .atu_move_port_mask = 0x1f,
6382 .ptp_support = true,
6383 .ops = &mv88e6393x_ops,
6387 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6391 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6392 if (mv88e6xxx_table[i].prod_num == prod_num)
6393 return &mv88e6xxx_table[i];
6398 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6400 const struct mv88e6xxx_info *info;
6401 unsigned int prod_num, rev;
6405 mv88e6xxx_reg_lock(chip);
6406 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6407 mv88e6xxx_reg_unlock(chip);
6411 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6412 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6414 info = mv88e6xxx_lookup_info(prod_num);
6418 /* Update the compatible info with the probed one */
6421 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6422 chip->info->prod_num, chip->info->name, rev);
6427 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6428 struct mdio_device *mdiodev)
6432 /* dual_chip takes precedence over single/multi-chip modes */
6433 if (chip->info->dual_chip)
6436 /* If the mdio addr is 16 indicating the first port address of a switch
6437 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6438 * configured in single chip addressing mode. Setup the smi access as
6439 * single chip addressing mode and attempt to detect the model of the
6440 * switch, if this fails the device is not configured in single chip
6443 if (mdiodev->addr != 16)
6446 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6450 return mv88e6xxx_detect(chip);
6453 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6455 struct mv88e6xxx_chip *chip;
6457 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6463 mutex_init(&chip->reg_lock);
6464 INIT_LIST_HEAD(&chip->mdios);
6465 idr_init(&chip->policies);
6466 INIT_LIST_HEAD(&chip->msts);
6471 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6473 enum dsa_tag_protocol m)
6475 struct mv88e6xxx_chip *chip = ds->priv;
6477 return chip->tag_protocol;
6480 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6481 enum dsa_tag_protocol proto)
6483 struct mv88e6xxx_chip *chip = ds->priv;
6484 enum dsa_tag_protocol old_protocol;
6485 struct dsa_port *cpu_dp;
6489 case DSA_TAG_PROTO_EDSA:
6490 switch (chip->info->edsa_support) {
6491 case MV88E6XXX_EDSA_UNSUPPORTED:
6492 return -EPROTONOSUPPORT;
6493 case MV88E6XXX_EDSA_UNDOCUMENTED:
6494 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6496 case MV88E6XXX_EDSA_SUPPORTED:
6500 case DSA_TAG_PROTO_DSA:
6503 return -EPROTONOSUPPORT;
6506 old_protocol = chip->tag_protocol;
6507 chip->tag_protocol = proto;
6509 mv88e6xxx_reg_lock(chip);
6510 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6511 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6513 mv88e6xxx_reg_unlock(chip);
6517 mv88e6xxx_reg_unlock(chip);
6522 chip->tag_protocol = old_protocol;
6524 mv88e6xxx_reg_lock(chip);
6525 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6526 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6527 mv88e6xxx_reg_unlock(chip);
6532 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6533 const struct switchdev_obj_port_mdb *mdb,
6536 struct mv88e6xxx_chip *chip = ds->priv;
6539 mv88e6xxx_reg_lock(chip);
6540 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6541 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6542 mv88e6xxx_reg_unlock(chip);
6547 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6548 const struct switchdev_obj_port_mdb *mdb,
6551 struct mv88e6xxx_chip *chip = ds->priv;
6554 mv88e6xxx_reg_lock(chip);
6555 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6556 mv88e6xxx_reg_unlock(chip);
6561 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6562 struct dsa_mall_mirror_tc_entry *mirror,
6564 struct netlink_ext_ack *extack)
6566 enum mv88e6xxx_egress_direction direction = ingress ?
6567 MV88E6XXX_EGRESS_DIR_INGRESS :
6568 MV88E6XXX_EGRESS_DIR_EGRESS;
6569 struct mv88e6xxx_chip *chip = ds->priv;
6570 bool other_mirrors = false;
6574 mutex_lock(&chip->reg_lock);
6575 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6576 mirror->to_local_port) {
6577 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6578 other_mirrors |= ingress ?
6579 chip->ports[i].mirror_ingress :
6580 chip->ports[i].mirror_egress;
6582 /* Can't change egress port when other mirror is active */
6583 if (other_mirrors) {
6588 err = mv88e6xxx_set_egress_port(chip, direction,
6589 mirror->to_local_port);
6594 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6596 mutex_unlock(&chip->reg_lock);
6601 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6602 struct dsa_mall_mirror_tc_entry *mirror)
6604 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6605 MV88E6XXX_EGRESS_DIR_INGRESS :
6606 MV88E6XXX_EGRESS_DIR_EGRESS;
6607 struct mv88e6xxx_chip *chip = ds->priv;
6608 bool other_mirrors = false;
6611 mutex_lock(&chip->reg_lock);
6612 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6613 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6615 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6616 other_mirrors |= mirror->ingress ?
6617 chip->ports[i].mirror_ingress :
6618 chip->ports[i].mirror_egress;
6620 /* Reset egress port when no other mirror is active */
6621 if (!other_mirrors) {
6622 if (mv88e6xxx_set_egress_port(chip, direction,
6623 dsa_upstream_port(ds, port)))
6624 dev_err(ds->dev, "failed to set egress port\n");
6627 mutex_unlock(&chip->reg_lock);
6630 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6631 struct switchdev_brport_flags flags,
6632 struct netlink_ext_ack *extack)
6634 struct mv88e6xxx_chip *chip = ds->priv;
6635 const struct mv88e6xxx_ops *ops;
6637 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6638 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6641 ops = chip->info->ops;
6643 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6646 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6652 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6653 struct switchdev_brport_flags flags,
6654 struct netlink_ext_ack *extack)
6656 struct mv88e6xxx_chip *chip = ds->priv;
6659 mv88e6xxx_reg_lock(chip);
6661 if (flags.mask & BR_LEARNING) {
6662 bool learning = !!(flags.val & BR_LEARNING);
6663 u16 pav = learning ? (1 << port) : 0;
6665 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6670 if (flags.mask & BR_FLOOD) {
6671 bool unicast = !!(flags.val & BR_FLOOD);
6673 err = chip->info->ops->port_set_ucast_flood(chip, port,
6679 if (flags.mask & BR_MCAST_FLOOD) {
6680 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6682 err = chip->info->ops->port_set_mcast_flood(chip, port,
6688 if (flags.mask & BR_BCAST_FLOOD) {
6689 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6691 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6696 if (flags.mask & BR_PORT_MAB) {
6697 bool mab = !!(flags.val & BR_PORT_MAB);
6699 mv88e6xxx_port_set_mab(chip, port, mab);
6702 if (flags.mask & BR_PORT_LOCKED) {
6703 bool locked = !!(flags.val & BR_PORT_LOCKED);
6705 err = mv88e6xxx_port_set_lock(chip, port, locked);
6710 mv88e6xxx_reg_unlock(chip);
6715 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6717 struct netdev_lag_upper_info *info,
6718 struct netlink_ext_ack *extack)
6720 struct mv88e6xxx_chip *chip = ds->priv;
6721 struct dsa_port *dp;
6724 if (!mv88e6xxx_has_lag(chip)) {
6725 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6732 dsa_lag_foreach_port(dp, ds->dst, &lag)
6733 /* Includes the port joining the LAG */
6737 NL_SET_ERR_MSG_MOD(extack,
6738 "Cannot offload more than 8 LAG ports");
6742 /* We could potentially relax this to include active
6743 * backup in the future.
6745 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6746 NL_SET_ERR_MSG_MOD(extack,
6747 "Can only offload LAG using hash TX type");
6751 /* Ideally we would also validate that the hash type matches
6752 * the hardware. Alas, this is always set to unknown on team
6758 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6760 struct mv88e6xxx_chip *chip = ds->priv;
6761 struct dsa_port *dp;
6765 /* DSA LAG IDs are one-based, hardware is zero-based */
6768 /* Build the map of all ports to distribute flows destined for
6769 * this LAG. This can be either a local user port, or a DSA
6770 * port if the LAG port is on a remote chip.
6772 dsa_lag_foreach_port(dp, ds->dst, &lag)
6773 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6775 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6778 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6779 /* Row number corresponds to the number of active members in a
6780 * LAG. Each column states which of the eight hash buckets are
6781 * mapped to the column:th port in the LAG.
6783 * Example: In a LAG with three active ports, the second port
6784 * ([2][1]) would be selected for traffic mapped to buckets
6787 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6788 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6789 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6790 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6791 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6792 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6793 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6794 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6797 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6798 int num_tx, int nth)
6803 num_tx = num_tx <= 8 ? num_tx : 8;
6805 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6807 for (i = 0; i < 8; i++) {
6808 if (BIT(i) & active)
6809 mask[i] |= BIT(port);
6813 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6815 struct mv88e6xxx_chip *chip = ds->priv;
6816 unsigned int id, num_tx;
6817 struct dsa_port *dp;
6818 struct dsa_lag *lag;
6823 /* Assume no port is a member of any LAG. */
6824 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6826 /* Disable all masks for ports that _are_ members of a LAG. */
6827 dsa_switch_for_each_port(dp, ds) {
6831 ivec &= ~BIT(dp->index);
6834 for (i = 0; i < 8; i++)
6837 /* Enable the correct subset of masks for all LAG ports that
6838 * are in the Tx set.
6840 dsa_lags_foreach_id(id, ds->dst) {
6841 lag = dsa_lag_by_id(ds->dst, id);
6846 dsa_lag_foreach_port(dp, ds->dst, lag) {
6847 if (dp->lag_tx_enabled)
6855 dsa_lag_foreach_port(dp, ds->dst, lag) {
6856 if (!dp->lag_tx_enabled)
6860 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6867 for (i = 0; i < 8; i++) {
6868 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6876 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6881 err = mv88e6xxx_lag_sync_masks(ds);
6884 err = mv88e6xxx_lag_sync_map(ds, lag);
6889 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6891 struct mv88e6xxx_chip *chip = ds->priv;
6894 mv88e6xxx_reg_lock(chip);
6895 err = mv88e6xxx_lag_sync_masks(ds);
6896 mv88e6xxx_reg_unlock(chip);
6900 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6902 struct netdev_lag_upper_info *info,
6903 struct netlink_ext_ack *extack)
6905 struct mv88e6xxx_chip *chip = ds->priv;
6908 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6911 /* DSA LAG IDs are one-based */
6914 mv88e6xxx_reg_lock(chip);
6916 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6920 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6922 goto err_clear_trunk;
6924 mv88e6xxx_reg_unlock(chip);
6928 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6930 mv88e6xxx_reg_unlock(chip);
6934 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6937 struct mv88e6xxx_chip *chip = ds->priv;
6938 int err_sync, err_trunk;
6940 mv88e6xxx_reg_lock(chip);
6941 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6942 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6943 mv88e6xxx_reg_unlock(chip);
6944 return err_sync ? : err_trunk;
6947 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6950 struct mv88e6xxx_chip *chip = ds->priv;
6953 mv88e6xxx_reg_lock(chip);
6954 err = mv88e6xxx_lag_sync_masks(ds);
6955 mv88e6xxx_reg_unlock(chip);
6959 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6960 int port, struct dsa_lag lag,
6961 struct netdev_lag_upper_info *info,
6962 struct netlink_ext_ack *extack)
6964 struct mv88e6xxx_chip *chip = ds->priv;
6967 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6970 mv88e6xxx_reg_lock(chip);
6972 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6976 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6979 mv88e6xxx_reg_unlock(chip);
6983 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6984 int port, struct dsa_lag lag)
6986 struct mv88e6xxx_chip *chip = ds->priv;
6987 int err_sync, err_pvt;
6989 mv88e6xxx_reg_lock(chip);
6990 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6991 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6992 mv88e6xxx_reg_unlock(chip);
6993 return err_sync ? : err_pvt;
6996 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6997 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6998 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6999 .setup = mv88e6xxx_setup,
7000 .teardown = mv88e6xxx_teardown,
7001 .port_setup = mv88e6xxx_port_setup,
7002 .port_teardown = mv88e6xxx_port_teardown,
7003 .phylink_get_caps = mv88e6xxx_get_caps,
7004 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
7005 .phylink_mac_config = mv88e6xxx_mac_config,
7006 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
7007 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
7008 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
7009 .get_strings = mv88e6xxx_get_strings,
7010 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7011 .get_sset_count = mv88e6xxx_get_sset_count,
7012 .port_enable = mv88e6xxx_port_enable,
7013 .port_disable = mv88e6xxx_port_disable,
7014 .port_max_mtu = mv88e6xxx_get_max_mtu,
7015 .port_change_mtu = mv88e6xxx_change_mtu,
7016 .get_mac_eee = mv88e6xxx_get_mac_eee,
7017 .set_mac_eee = mv88e6xxx_set_mac_eee,
7018 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7019 .get_eeprom = mv88e6xxx_get_eeprom,
7020 .set_eeprom = mv88e6xxx_set_eeprom,
7021 .get_regs_len = mv88e6xxx_get_regs_len,
7022 .get_regs = mv88e6xxx_get_regs,
7023 .get_rxnfc = mv88e6xxx_get_rxnfc,
7024 .set_rxnfc = mv88e6xxx_set_rxnfc,
7025 .set_ageing_time = mv88e6xxx_set_ageing_time,
7026 .port_bridge_join = mv88e6xxx_port_bridge_join,
7027 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7028 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7029 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7030 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7031 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7032 .port_fast_age = mv88e6xxx_port_fast_age,
7033 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7034 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7035 .port_vlan_add = mv88e6xxx_port_vlan_add,
7036 .port_vlan_del = mv88e6xxx_port_vlan_del,
7037 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7038 .port_fdb_add = mv88e6xxx_port_fdb_add,
7039 .port_fdb_del = mv88e6xxx_port_fdb_del,
7040 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7041 .port_mdb_add = mv88e6xxx_port_mdb_add,
7042 .port_mdb_del = mv88e6xxx_port_mdb_del,
7043 .port_mirror_add = mv88e6xxx_port_mirror_add,
7044 .port_mirror_del = mv88e6xxx_port_mirror_del,
7045 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7046 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7047 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7048 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7049 .port_txtstamp = mv88e6xxx_port_txtstamp,
7050 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7051 .get_ts_info = mv88e6xxx_get_ts_info,
7052 .devlink_param_get = mv88e6xxx_devlink_param_get,
7053 .devlink_param_set = mv88e6xxx_devlink_param_set,
7054 .devlink_info_get = mv88e6xxx_devlink_info_get,
7055 .port_lag_change = mv88e6xxx_port_lag_change,
7056 .port_lag_join = mv88e6xxx_port_lag_join,
7057 .port_lag_leave = mv88e6xxx_port_lag_leave,
7058 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7059 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7060 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7063 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7065 struct device *dev = chip->dev;
7066 struct dsa_switch *ds;
7068 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7073 ds->num_ports = mv88e6xxx_num_ports(chip);
7076 ds->ops = &mv88e6xxx_switch_ops;
7077 ds->ageing_time_min = chip->info->age_time_coeff;
7078 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7080 /* Some chips support up to 32, but that requires enabling the
7081 * 5-bit port mode, which we do not support. 640k^W16 ought to
7082 * be enough for anyone.
7084 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7086 dev_set_drvdata(dev, ds);
7088 return dsa_register_switch(ds);
7091 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7093 dsa_unregister_switch(chip->ds);
7096 static const void *pdata_device_get_match_data(struct device *dev)
7098 const struct of_device_id *matches = dev->driver->of_match_table;
7099 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7101 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7103 if (!strcmp(pdata->compatible, matches->compatible))
7104 return matches->data;
7109 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7110 * would be lost after a power cycle so prevent it to be suspended.
7112 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7117 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7122 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7124 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7126 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7127 const struct mv88e6xxx_info *compat_info = NULL;
7128 struct device *dev = &mdiodev->dev;
7129 struct device_node *np = dev->of_node;
7130 struct mv88e6xxx_chip *chip;
7138 compat_info = of_device_get_match_data(dev);
7141 compat_info = pdata_device_get_match_data(dev);
7146 for (port = 0; port < DSA_MAX_PORTS; port++) {
7147 if (!(pdata->enabled_ports & (1 << port)))
7149 if (strcmp(pdata->cd.port_names[port], "cpu"))
7151 pdata->cd.netdev[port] = &pdata->netdev->dev;
7159 chip = mv88e6xxx_alloc_chip(dev);
7165 chip->info = compat_info;
7167 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7168 if (IS_ERR(chip->reset)) {
7169 err = PTR_ERR(chip->reset);
7173 usleep_range(10000, 20000);
7175 /* Detect if the device is configured in single chip addressing mode,
7176 * otherwise continue with address specific smi init/detection.
7178 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7180 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7184 err = mv88e6xxx_detect(chip);
7189 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7190 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7192 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7194 mv88e6xxx_phy_init(chip);
7196 if (chip->info->ops->get_eeprom) {
7198 of_property_read_u32(np, "eeprom-length",
7201 chip->eeprom_len = pdata->eeprom_len;
7204 mv88e6xxx_reg_lock(chip);
7205 err = mv88e6xxx_switch_reset(chip);
7206 mv88e6xxx_reg_unlock(chip);
7211 chip->irq = of_irq_get(np, 0);
7212 if (chip->irq == -EPROBE_DEFER) {
7219 chip->irq = pdata->irq;
7221 /* Has to be performed before the MDIO bus is created, because
7222 * the PHYs will link their interrupts to these interrupt
7225 mv88e6xxx_reg_lock(chip);
7227 err = mv88e6xxx_g1_irq_setup(chip);
7229 err = mv88e6xxx_irq_poll_setup(chip);
7230 mv88e6xxx_reg_unlock(chip);
7235 if (chip->info->g2_irqs > 0) {
7236 err = mv88e6xxx_g2_irq_setup(chip);
7241 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7245 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7247 goto out_g1_atu_prob_irq;
7249 err = mv88e6xxx_register_switch(chip);
7251 goto out_g1_vtu_prob_irq;
7255 out_g1_vtu_prob_irq:
7256 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7257 out_g1_atu_prob_irq:
7258 mv88e6xxx_g1_atu_prob_irq_free(chip);
7260 if (chip->info->g2_irqs > 0)
7261 mv88e6xxx_g2_irq_free(chip);
7264 mv88e6xxx_g1_irq_free(chip);
7266 mv88e6xxx_irq_poll_free(chip);
7269 dev_put(pdata->netdev);
7274 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7276 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7277 struct mv88e6xxx_chip *chip;
7284 if (chip->info->ptp_support) {
7285 mv88e6xxx_hwtstamp_free(chip);
7286 mv88e6xxx_ptp_free(chip);
7289 mv88e6xxx_phy_destroy(chip);
7290 mv88e6xxx_unregister_switch(chip);
7292 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7293 mv88e6xxx_g1_atu_prob_irq_free(chip);
7295 if (chip->info->g2_irqs > 0)
7296 mv88e6xxx_g2_irq_free(chip);
7299 mv88e6xxx_g1_irq_free(chip);
7301 mv88e6xxx_irq_poll_free(chip);
7304 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7306 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7311 dsa_switch_shutdown(ds);
7313 dev_set_drvdata(&mdiodev->dev, NULL);
7316 static const struct of_device_id mv88e6xxx_of_match[] = {
7318 .compatible = "marvell,mv88e6085",
7319 .data = &mv88e6xxx_table[MV88E6085],
7322 .compatible = "marvell,mv88e6190",
7323 .data = &mv88e6xxx_table[MV88E6190],
7326 .compatible = "marvell,mv88e6250",
7327 .data = &mv88e6xxx_table[MV88E6250],
7332 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7334 static struct mdio_driver mv88e6xxx_driver = {
7335 .probe = mv88e6xxx_probe,
7336 .remove = mv88e6xxx_remove,
7337 .shutdown = mv88e6xxx_shutdown,
7339 .name = "mv88e6085",
7340 .of_match_table = mv88e6xxx_of_match,
7341 .pm = &mv88e6xxx_pm_ops,
7345 mdio_module_driver(mv88e6xxx_driver);
7347 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7348 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7349 MODULE_LICENSE("GPL");