1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
16 #include <linux/irq.h>
20 #define KSZ_MAX_NUM_PORTS 8
30 struct mutex cnt_mutex; /* structure access */
33 struct rtnl_link_stats64 stats64;
34 struct ethtool_pause_stats pause_stats;
35 struct spinlock stats64_lock;
38 struct ksz_mib_names {
40 char string[ETH_GSTRING_LEN];
43 struct ksz_chip_data {
53 const struct ksz_dev_ops *ops;
55 bool ksz87xx_eee_link_erratum;
56 const struct ksz_mib_names *mib_names;
65 int broadcast_ctrl_reg;
66 int multicast_ctrl_reg;
68 bool supports_mii[KSZ_MAX_NUM_PORTS];
69 bool supports_rmii[KSZ_MAX_NUM_PORTS];
70 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
71 bool internal_phy[KSZ_MAX_NUM_PORTS];
72 bool gbit_capable[KSZ_MAX_NUM_PORTS];
73 const struct regmap_access_table *wr_table;
74 const struct regmap_access_table *rd_table;
81 struct irq_domain *domain;
85 struct ksz_device *dev;
89 struct ksz_port *port;
97 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
100 struct phy_device phydev;
102 u32 on:1; /* port is not disabled by hardware */
103 u32 fiber:1; /* port is fiber */
105 u32 read:1; /* read MIB counters in background */
106 u32 freeze:1; /* MIB counter freeze is enabled */
108 struct ksz_port_mib mib;
109 phy_interface_t interface;
112 struct ksz_device *ksz_dev;
115 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
116 struct hwtstamp_config tstamp_config;
119 struct ksz_irq ptpirq;
120 struct ksz_ptp_irq ptpmsg_irq[3];
122 struct completion tstamp_msg_comp;
127 struct dsa_switch *ds;
128 struct ksz_platform_data *pdata;
129 const struct ksz_chip_data *info;
131 struct mutex dev_mutex; /* device access */
132 struct mutex regmap_mutex; /* regmap access */
133 struct mutex alu_mutex; /* ALU access */
134 struct mutex vlan_mutex; /* vlan access */
135 const struct ksz_dev_ops *dev_ops;
138 struct regmap *regmap[3];
143 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
145 /* chip specific data */
148 int cpu_port; /* port connected to CPU */
150 phy_interface_t compat_interface;
152 bool synclko_disable;
154 struct vlan_table *vlan_cache;
156 struct ksz_port *ports;
157 struct delayed_work mib_read;
158 unsigned long mib_read_interval;
162 struct mutex lock_irq; /* IRQ Access */
164 struct ksz_ptp_data ptp_data;
167 /* List of supported models */
188 KSZ8563_CHIP_ID = 0x8563,
189 KSZ8795_CHIP_ID = 0x8795,
190 KSZ8794_CHIP_ID = 0x8794,
191 KSZ8765_CHIP_ID = 0x8765,
192 KSZ8830_CHIP_ID = 0x8830,
193 KSZ9477_CHIP_ID = 0x00947700,
194 KSZ9896_CHIP_ID = 0x00989600,
195 KSZ9897_CHIP_ID = 0x00989700,
196 KSZ9893_CHIP_ID = 0x00989300,
197 KSZ9563_CHIP_ID = 0x00956300,
198 KSZ9567_CHIP_ID = 0x00956700,
199 LAN9370_CHIP_ID = 0x00937000,
200 LAN9371_CHIP_ID = 0x00937100,
201 LAN9372_CHIP_ID = 0x00937200,
202 LAN9373_CHIP_ID = 0x00937300,
203 LAN9374_CHIP_ID = 0x00937400,
230 PORT_802_1P_REMAPPING,
232 MIB_COUNTER_OVERFLOW,
235 VLAN_TABLE_MEMBERSHIP,
237 STATIC_MAC_TABLE_VALID,
238 STATIC_MAC_TABLE_USE_FID,
239 STATIC_MAC_TABLE_FID,
240 STATIC_MAC_TABLE_OVERRIDE,
241 STATIC_MAC_TABLE_FWD_PORTS,
242 DYNAMIC_MAC_TABLE_ENTRIES_H,
243 DYNAMIC_MAC_TABLE_MAC_EMPTY,
244 DYNAMIC_MAC_TABLE_NOT_READY,
245 DYNAMIC_MAC_TABLE_ENTRIES,
246 DYNAMIC_MAC_TABLE_FID,
247 DYNAMIC_MAC_TABLE_SRC_PORT,
248 DYNAMIC_MAC_TABLE_TIMESTAMP,
256 VLAN_TABLE_MEMBERSHIP_S,
258 STATIC_MAC_FWD_PORTS,
260 DYNAMIC_MAC_ENTRIES_H,
263 DYNAMIC_MAC_TIMESTAMP,
264 DYNAMIC_MAC_SRC_PORT,
268 enum ksz_xmii_ctrl0 {
275 enum ksz_xmii_ctrl1 {
304 int (*setup)(struct dsa_switch *ds);
305 void (*teardown)(struct dsa_switch *ds);
306 u32 (*get_port_addr)(int port, int offset);
307 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
308 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
309 void (*port_cleanup)(struct ksz_device *dev, int port);
310 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
311 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
312 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
313 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
314 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
316 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
317 u64 *dropped, u64 *cnt);
318 void (*r_mib_stat64)(struct ksz_device *dev, int port);
319 int (*vlan_filtering)(struct ksz_device *dev, int port,
320 bool flag, struct netlink_ext_ack *extack);
321 int (*vlan_add)(struct ksz_device *dev, int port,
322 const struct switchdev_obj_port_vlan *vlan,
323 struct netlink_ext_ack *extack);
324 int (*vlan_del)(struct ksz_device *dev, int port,
325 const struct switchdev_obj_port_vlan *vlan);
326 int (*mirror_add)(struct ksz_device *dev, int port,
327 struct dsa_mall_mirror_tc_entry *mirror,
328 bool ingress, struct netlink_ext_ack *extack);
329 void (*mirror_del)(struct ksz_device *dev, int port,
330 struct dsa_mall_mirror_tc_entry *mirror);
331 int (*fdb_add)(struct ksz_device *dev, int port,
332 const unsigned char *addr, u16 vid, struct dsa_db db);
333 int (*fdb_del)(struct ksz_device *dev, int port,
334 const unsigned char *addr, u16 vid, struct dsa_db db);
335 int (*fdb_dump)(struct ksz_device *dev, int port,
336 dsa_fdb_dump_cb_t *cb, void *data);
337 int (*mdb_add)(struct ksz_device *dev, int port,
338 const struct switchdev_obj_port_mdb *mdb,
340 int (*mdb_del)(struct ksz_device *dev, int port,
341 const struct switchdev_obj_port_mdb *mdb,
343 void (*get_caps)(struct ksz_device *dev, int port,
344 struct phylink_config *config);
345 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
346 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
347 void (*port_init_cnt)(struct ksz_device *dev, int port);
348 void (*phylink_mac_config)(struct ksz_device *dev, int port,
350 const struct phylink_link_state *state);
351 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
353 phy_interface_t interface,
354 struct phy_device *phydev, int speed,
355 int duplex, bool tx_pause, bool rx_pause);
356 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
357 void (*config_cpu_port)(struct dsa_switch *ds);
358 int (*enable_stp_addr)(struct ksz_device *dev);
359 int (*reset)(struct ksz_device *dev);
360 int (*init)(struct ksz_device *dev);
361 void (*exit)(struct ksz_device *dev);
364 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
365 int ksz_switch_register(struct ksz_device *dev);
366 void ksz_switch_remove(struct ksz_device *dev);
368 void ksz_init_mib_timer(struct ksz_device *dev);
369 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
370 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
371 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
372 bool ksz_get_gbit(struct ksz_device *dev, int port);
373 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
374 extern const struct ksz_chip_data ksz_switch_chips[];
376 /* Common register access functions */
378 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
381 int ret = regmap_read(dev->regmap[0], reg, &value);
384 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
391 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
394 int ret = regmap_read(dev->regmap[1], reg, &value);
397 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
404 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
407 int ret = regmap_read(dev->regmap[2], reg, &value);
410 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
417 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
422 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
424 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
427 *val = (u64)value[0] << 32 | value[1];
432 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
436 ret = regmap_write(dev->regmap[0], reg, value);
438 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
444 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
448 ret = regmap_write(dev->regmap[1], reg, value);
450 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
456 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
460 ret = regmap_write(dev->regmap[2], reg, value);
462 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
468 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
473 ret = regmap_update_bits(dev->regmap[1], reg, mask, value);
475 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
481 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
486 ret = regmap_update_bits(dev->regmap[2], reg, mask, value);
488 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
494 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
498 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
499 value = swab64(value);
500 val[0] = swab32(value & 0xffffffffULL);
501 val[1] = swab32(value >> 32ULL);
503 return regmap_bulk_write(dev->regmap[2], reg, val, 2);
506 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
508 return regmap_update_bits(dev->regmap[0], offset, mask, val);
511 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
514 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
517 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
520 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
523 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
526 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
529 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
532 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
535 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
538 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
542 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
545 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
549 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset,
552 regmap_update_bits(dev->regmap[0],
553 dev->dev_ops->get_port_addr(port, offset),
557 static inline void ksz_regmap_lock(void *__mtx)
559 struct mutex *mtx = __mtx;
563 static inline void ksz_regmap_unlock(void *__mtx)
565 struct mutex *mtx = __mtx;
569 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
571 return dev->chip_id == KSZ8830_CHIP_ID;
574 static inline int is_lan937x(struct ksz_device *dev)
576 return dev->chip_id == LAN9370_CHIP_ID ||
577 dev->chip_id == LAN9371_CHIP_ID ||
578 dev->chip_id == LAN9372_CHIP_ID ||
579 dev->chip_id == LAN9373_CHIP_ID ||
580 dev->chip_id == LAN9374_CHIP_ID;
583 /* STP State Defines */
584 #define PORT_TX_ENABLE BIT(2)
585 #define PORT_RX_ENABLE BIT(1)
586 #define PORT_LEARN_DISABLE BIT(0)
588 /* Switch ID Defines */
589 #define REG_CHIP_ID0 0x00
591 #define SW_FAMILY_ID_M GENMASK(15, 8)
592 #define KSZ87_FAMILY_ID 0x87
593 #define KSZ88_FAMILY_ID 0x88
595 #define KSZ8_PORT_STATUS_0 0x08
596 #define KSZ8_PORT_FIBER_MODE BIT(7)
598 #define SW_CHIP_ID_M GENMASK(7, 4)
599 #define KSZ87_CHIP_ID_94 0x6
600 #define KSZ87_CHIP_ID_95 0x9
601 #define KSZ88_CHIP_ID_63 0x3
603 #define SW_REV_ID_M GENMASK(7, 4)
605 /* KSZ9893, KSZ9563, KSZ8563 specific register */
606 #define REG_CHIP_ID4 0x0f
607 #define SKU_ID_KSZ8563 0x3c
608 #define SKU_ID_KSZ9563 0x1c
610 /* Driver set switch broadcast storm protection at 10% rate. */
611 #define BROADCAST_STORM_PROT_RATE 10
613 /* 148,800 frames * 67 ms / 100 */
614 #define BROADCAST_STORM_VALUE 9969
616 #define BROADCAST_STORM_RATE_HI 0x07
617 #define BROADCAST_STORM_RATE_LO 0xFF
618 #define BROADCAST_STORM_RATE 0x07FF
620 #define MULTICAST_STORM_DISABLE BIT(6)
622 #define SW_START 0x01
624 /* xMII configuration */
625 #define P_MII_DUPLEX_M BIT(6)
626 #define P_MII_100MBIT_M BIT(4)
628 #define P_GMII_1GBIT_M BIT(6)
629 #define P_RGMII_ID_IG_ENABLE BIT(4)
630 #define P_RGMII_ID_EG_ENABLE BIT(3)
631 #define P_MII_MAC_MODE BIT(2)
632 #define P_MII_SEL_M 0x3
635 #define REG_SW_PORT_INT_STATUS__1 0x001B
636 #define REG_SW_PORT_INT_MASK__1 0x001F
638 #define REG_PORT_INT_STATUS 0x001B
639 #define REG_PORT_INT_MASK 0x001F
641 #define PORT_SRC_PHY_INT 1
642 #define PORT_SRC_PTP_INT 2
644 #define KSZ8795_HUGE_PACKET_SIZE 2000
645 #define KSZ8863_HUGE_PACKET_SIZE 1916
646 #define KSZ8863_NORMAL_PACKET_SIZE 1536
647 #define KSZ8_LEGAL_PACKET_SIZE 1518
648 #define KSZ9477_MAX_FRAME_SIZE 9000
650 /* Regmap tables generation */
651 #define KSZ_SPI_OP_RD 3
652 #define KSZ_SPI_OP_WR 2
654 #define swabnot_used(x) 0
656 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
657 swab##swp((opcode) << ((regbits) + (regpad)))
659 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
662 .val_bits = (width), \
664 .reg_bits = (regbits) + (regalign), \
665 .pad_bits = (regpad), \
666 .max_register = BIT(regbits) - 1, \
667 .cache_type = REGCACHE_NONE, \
669 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
672 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
674 .lock = ksz_regmap_lock, \
675 .unlock = ksz_regmap_unlock, \
676 .reg_format_endian = REGMAP_ENDIAN_BIG, \
677 .val_format_endian = REGMAP_ENDIAN_BIG \
680 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
681 static const struct regmap_config ksz##_regmap_config[] = { \
682 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
683 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
684 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \