1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip switch driver main logic
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_device.h>
23 #include <linux/of_net.h>
24 #include <linux/micrel_phy.h>
26 #include <net/switchdev.h>
28 #include "ksz_common.h"
34 #define MIB_COUNTER_NUM 0x20
36 struct ksz_stats_raw {
75 struct ksz88xx_stats_raw {
112 static const struct ksz_mib_names ksz88xx_mib_names[] = {
115 { 0x02, "rx_undersize" },
116 { 0x03, "rx_fragments" },
117 { 0x04, "rx_oversize" },
118 { 0x05, "rx_jabbers" },
119 { 0x06, "rx_symbol_err" },
120 { 0x07, "rx_crc_err" },
121 { 0x08, "rx_align_err" },
122 { 0x09, "rx_mac_ctrl" },
123 { 0x0a, "rx_pause" },
124 { 0x0b, "rx_bcast" },
125 { 0x0c, "rx_mcast" },
126 { 0x0d, "rx_ucast" },
127 { 0x0e, "rx_64_or_less" },
128 { 0x0f, "rx_65_127" },
129 { 0x10, "rx_128_255" },
130 { 0x11, "rx_256_511" },
131 { 0x12, "rx_512_1023" },
132 { 0x13, "rx_1024_1522" },
135 { 0x16, "tx_late_col" },
136 { 0x17, "tx_pause" },
137 { 0x18, "tx_bcast" },
138 { 0x19, "tx_mcast" },
139 { 0x1a, "tx_ucast" },
140 { 0x1b, "tx_deferred" },
141 { 0x1c, "tx_total_col" },
142 { 0x1d, "tx_exc_col" },
143 { 0x1e, "tx_single_col" },
144 { 0x1f, "tx_mult_col" },
145 { 0x100, "rx_discards" },
146 { 0x101, "tx_discards" },
149 static const struct ksz_mib_names ksz9477_mib_names[] = {
151 { 0x01, "rx_undersize" },
152 { 0x02, "rx_fragments" },
153 { 0x03, "rx_oversize" },
154 { 0x04, "rx_jabbers" },
155 { 0x05, "rx_symbol_err" },
156 { 0x06, "rx_crc_err" },
157 { 0x07, "rx_align_err" },
158 { 0x08, "rx_mac_ctrl" },
159 { 0x09, "rx_pause" },
160 { 0x0A, "rx_bcast" },
161 { 0x0B, "rx_mcast" },
162 { 0x0C, "rx_ucast" },
163 { 0x0D, "rx_64_or_less" },
164 { 0x0E, "rx_65_127" },
165 { 0x0F, "rx_128_255" },
166 { 0x10, "rx_256_511" },
167 { 0x11, "rx_512_1023" },
168 { 0x12, "rx_1024_1522" },
169 { 0x13, "rx_1523_2000" },
172 { 0x16, "tx_late_col" },
173 { 0x17, "tx_pause" },
174 { 0x18, "tx_bcast" },
175 { 0x19, "tx_mcast" },
176 { 0x1A, "tx_ucast" },
177 { 0x1B, "tx_deferred" },
178 { 0x1C, "tx_total_col" },
179 { 0x1D, "tx_exc_col" },
180 { 0x1E, "tx_single_col" },
181 { 0x1F, "tx_mult_col" },
182 { 0x80, "rx_total" },
183 { 0x81, "tx_total" },
184 { 0x82, "rx_discards" },
185 { 0x83, "tx_discards" },
188 static const struct ksz_dev_ops ksz8_dev_ops = {
190 .get_port_addr = ksz8_get_port_addr,
191 .cfg_port_member = ksz8_cfg_port_member,
192 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
193 .port_setup = ksz8_port_setup,
196 .r_mib_cnt = ksz8_r_mib_cnt,
197 .r_mib_pkt = ksz8_r_mib_pkt,
198 .r_mib_stat64 = ksz88xx_r_mib_stats64,
199 .freeze_mib = ksz8_freeze_mib,
200 .port_init_cnt = ksz8_port_init_cnt,
201 .fdb_dump = ksz8_fdb_dump,
202 .mdb_add = ksz8_mdb_add,
203 .mdb_del = ksz8_mdb_del,
204 .vlan_filtering = ksz8_port_vlan_filtering,
205 .vlan_add = ksz8_port_vlan_add,
206 .vlan_del = ksz8_port_vlan_del,
207 .mirror_add = ksz8_port_mirror_add,
208 .mirror_del = ksz8_port_mirror_del,
209 .get_caps = ksz8_get_caps,
210 .config_cpu_port = ksz8_config_cpu_port,
211 .enable_stp_addr = ksz8_enable_stp_addr,
212 .reset = ksz8_reset_switch,
213 .init = ksz8_switch_init,
214 .exit = ksz8_switch_exit,
215 .change_mtu = ksz8_change_mtu,
218 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
220 phy_interface_t interface,
221 struct phy_device *phydev, int speed,
222 int duplex, bool tx_pause,
225 static const struct ksz_dev_ops ksz9477_dev_ops = {
226 .setup = ksz9477_setup,
227 .get_port_addr = ksz9477_get_port_addr,
228 .cfg_port_member = ksz9477_cfg_port_member,
229 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
230 .port_setup = ksz9477_port_setup,
231 .set_ageing_time = ksz9477_set_ageing_time,
232 .r_phy = ksz9477_r_phy,
233 .w_phy = ksz9477_w_phy,
234 .r_mib_cnt = ksz9477_r_mib_cnt,
235 .r_mib_pkt = ksz9477_r_mib_pkt,
236 .r_mib_stat64 = ksz_r_mib_stats64,
237 .freeze_mib = ksz9477_freeze_mib,
238 .port_init_cnt = ksz9477_port_init_cnt,
239 .vlan_filtering = ksz9477_port_vlan_filtering,
240 .vlan_add = ksz9477_port_vlan_add,
241 .vlan_del = ksz9477_port_vlan_del,
242 .mirror_add = ksz9477_port_mirror_add,
243 .mirror_del = ksz9477_port_mirror_del,
244 .get_caps = ksz9477_get_caps,
245 .fdb_dump = ksz9477_fdb_dump,
246 .fdb_add = ksz9477_fdb_add,
247 .fdb_del = ksz9477_fdb_del,
248 .mdb_add = ksz9477_mdb_add,
249 .mdb_del = ksz9477_mdb_del,
250 .change_mtu = ksz9477_change_mtu,
251 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
252 .config_cpu_port = ksz9477_config_cpu_port,
253 .enable_stp_addr = ksz9477_enable_stp_addr,
254 .reset = ksz9477_reset_switch,
255 .init = ksz9477_switch_init,
256 .exit = ksz9477_switch_exit,
259 static const struct ksz_dev_ops lan937x_dev_ops = {
260 .setup = lan937x_setup,
261 .teardown = lan937x_teardown,
262 .get_port_addr = ksz9477_get_port_addr,
263 .cfg_port_member = ksz9477_cfg_port_member,
264 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
265 .port_setup = lan937x_port_setup,
266 .set_ageing_time = lan937x_set_ageing_time,
267 .r_phy = lan937x_r_phy,
268 .w_phy = lan937x_w_phy,
269 .r_mib_cnt = ksz9477_r_mib_cnt,
270 .r_mib_pkt = ksz9477_r_mib_pkt,
271 .r_mib_stat64 = ksz_r_mib_stats64,
272 .freeze_mib = ksz9477_freeze_mib,
273 .port_init_cnt = ksz9477_port_init_cnt,
274 .vlan_filtering = ksz9477_port_vlan_filtering,
275 .vlan_add = ksz9477_port_vlan_add,
276 .vlan_del = ksz9477_port_vlan_del,
277 .mirror_add = ksz9477_port_mirror_add,
278 .mirror_del = ksz9477_port_mirror_del,
279 .get_caps = lan937x_phylink_get_caps,
280 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
281 .fdb_dump = ksz9477_fdb_dump,
282 .fdb_add = ksz9477_fdb_add,
283 .fdb_del = ksz9477_fdb_del,
284 .mdb_add = ksz9477_mdb_add,
285 .mdb_del = ksz9477_mdb_del,
286 .change_mtu = lan937x_change_mtu,
287 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
288 .config_cpu_port = lan937x_config_cpu_port,
289 .enable_stp_addr = ksz9477_enable_stp_addr,
290 .reset = lan937x_reset_switch,
291 .init = lan937x_switch_init,
292 .exit = lan937x_switch_exit,
295 static const u16 ksz8795_regs[] = {
296 [REG_IND_CTRL_0] = 0x6E,
297 [REG_IND_DATA_8] = 0x70,
298 [REG_IND_DATA_CHECK] = 0x72,
299 [REG_IND_DATA_HI] = 0x71,
300 [REG_IND_DATA_LO] = 0x75,
301 [REG_IND_MIB_CHECK] = 0x74,
302 [REG_IND_BYTE] = 0xA0,
303 [P_FORCE_CTRL] = 0x0C,
304 [P_LINK_STATUS] = 0x0E,
305 [P_LOCAL_CTRL] = 0x07,
306 [P_NEG_RESTART_CTRL] = 0x0D,
307 [P_REMOTE_STATUS] = 0x08,
308 [P_SPEED_STATUS] = 0x09,
309 [S_TAIL_TAG_CTRL] = 0x0C,
311 [S_START_CTRL] = 0x01,
312 [S_BROADCAST_CTRL] = 0x06,
313 [S_MULTICAST_CTRL] = 0x04,
314 [P_XMII_CTRL_0] = 0x06,
315 [P_XMII_CTRL_1] = 0x56,
318 static const u32 ksz8795_masks[] = {
319 [PORT_802_1P_REMAPPING] = BIT(7),
320 [SW_TAIL_TAG_ENABLE] = BIT(1),
321 [MIB_COUNTER_OVERFLOW] = BIT(6),
322 [MIB_COUNTER_VALID] = BIT(5),
323 [VLAN_TABLE_FID] = GENMASK(6, 0),
324 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
325 [VLAN_TABLE_VALID] = BIT(12),
326 [STATIC_MAC_TABLE_VALID] = BIT(21),
327 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
328 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
329 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
330 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
331 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
332 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
333 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
334 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
335 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
336 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
337 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
338 [P_MII_TX_FLOW_CTRL] = BIT(5),
339 [P_MII_RX_FLOW_CTRL] = BIT(5),
342 static const u8 ksz8795_xmii_ctrl0[] = {
345 [P_MII_FULL_DUPLEX] = 0,
346 [P_MII_HALF_DUPLEX] = 1,
349 static const u8 ksz8795_xmii_ctrl1[] = {
355 [P_GMII_NOT_1GBIT] = 0,
358 static const u8 ksz8795_shifts[] = {
359 [VLAN_TABLE_MEMBERSHIP_S] = 7,
361 [STATIC_MAC_FWD_PORTS] = 16,
362 [STATIC_MAC_FID] = 24,
363 [DYNAMIC_MAC_ENTRIES_H] = 3,
364 [DYNAMIC_MAC_ENTRIES] = 29,
365 [DYNAMIC_MAC_FID] = 16,
366 [DYNAMIC_MAC_TIMESTAMP] = 27,
367 [DYNAMIC_MAC_SRC_PORT] = 24,
370 static const u16 ksz8863_regs[] = {
371 [REG_IND_CTRL_0] = 0x79,
372 [REG_IND_DATA_8] = 0x7B,
373 [REG_IND_DATA_CHECK] = 0x7B,
374 [REG_IND_DATA_HI] = 0x7C,
375 [REG_IND_DATA_LO] = 0x80,
376 [REG_IND_MIB_CHECK] = 0x80,
377 [P_FORCE_CTRL] = 0x0C,
378 [P_LINK_STATUS] = 0x0E,
379 [P_LOCAL_CTRL] = 0x0C,
380 [P_NEG_RESTART_CTRL] = 0x0D,
381 [P_REMOTE_STATUS] = 0x0E,
382 [P_SPEED_STATUS] = 0x0F,
383 [S_TAIL_TAG_CTRL] = 0x03,
385 [S_START_CTRL] = 0x01,
386 [S_BROADCAST_CTRL] = 0x06,
387 [S_MULTICAST_CTRL] = 0x04,
390 static const u32 ksz8863_masks[] = {
391 [PORT_802_1P_REMAPPING] = BIT(3),
392 [SW_TAIL_TAG_ENABLE] = BIT(6),
393 [MIB_COUNTER_OVERFLOW] = BIT(7),
394 [MIB_COUNTER_VALID] = BIT(6),
395 [VLAN_TABLE_FID] = GENMASK(15, 12),
396 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
397 [VLAN_TABLE_VALID] = BIT(19),
398 [STATIC_MAC_TABLE_VALID] = BIT(19),
399 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
400 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
401 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
402 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
403 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
404 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
405 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
406 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
407 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
408 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
409 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
412 static u8 ksz8863_shifts[] = {
413 [VLAN_TABLE_MEMBERSHIP_S] = 16,
414 [STATIC_MAC_FWD_PORTS] = 16,
415 [STATIC_MAC_FID] = 22,
416 [DYNAMIC_MAC_ENTRIES_H] = 3,
417 [DYNAMIC_MAC_ENTRIES] = 24,
418 [DYNAMIC_MAC_FID] = 16,
419 [DYNAMIC_MAC_TIMESTAMP] = 24,
420 [DYNAMIC_MAC_SRC_PORT] = 20,
423 static const u16 ksz9477_regs[] = {
424 [P_STP_CTRL] = 0x0B04,
425 [S_START_CTRL] = 0x0300,
426 [S_BROADCAST_CTRL] = 0x0332,
427 [S_MULTICAST_CTRL] = 0x0331,
428 [P_XMII_CTRL_0] = 0x0300,
429 [P_XMII_CTRL_1] = 0x0301,
432 static const u32 ksz9477_masks[] = {
433 [ALU_STAT_WRITE] = 0,
435 [P_MII_TX_FLOW_CTRL] = BIT(5),
436 [P_MII_RX_FLOW_CTRL] = BIT(3),
439 static const u8 ksz9477_shifts[] = {
440 [ALU_STAT_INDEX] = 16,
443 static const u8 ksz9477_xmii_ctrl0[] = {
446 [P_MII_FULL_DUPLEX] = 1,
447 [P_MII_HALF_DUPLEX] = 0,
450 static const u8 ksz9477_xmii_ctrl1[] = {
456 [P_GMII_NOT_1GBIT] = 1,
459 static const u32 lan937x_masks[] = {
460 [ALU_STAT_WRITE] = 1,
462 [P_MII_TX_FLOW_CTRL] = BIT(5),
463 [P_MII_RX_FLOW_CTRL] = BIT(3),
466 static const u8 lan937x_shifts[] = {
467 [ALU_STAT_INDEX] = 8,
470 static const struct regmap_range ksz8563_valid_regs[] = {
471 regmap_reg_range(0x0000, 0x0003),
472 regmap_reg_range(0x0006, 0x0006),
473 regmap_reg_range(0x000f, 0x001f),
474 regmap_reg_range(0x0100, 0x0100),
475 regmap_reg_range(0x0104, 0x0107),
476 regmap_reg_range(0x010d, 0x010d),
477 regmap_reg_range(0x0110, 0x0113),
478 regmap_reg_range(0x0120, 0x012b),
479 regmap_reg_range(0x0201, 0x0201),
480 regmap_reg_range(0x0210, 0x0213),
481 regmap_reg_range(0x0300, 0x0300),
482 regmap_reg_range(0x0302, 0x031b),
483 regmap_reg_range(0x0320, 0x032b),
484 regmap_reg_range(0x0330, 0x0336),
485 regmap_reg_range(0x0338, 0x033e),
486 regmap_reg_range(0x0340, 0x035f),
487 regmap_reg_range(0x0370, 0x0370),
488 regmap_reg_range(0x0378, 0x0378),
489 regmap_reg_range(0x037c, 0x037d),
490 regmap_reg_range(0x0390, 0x0393),
491 regmap_reg_range(0x0400, 0x040e),
492 regmap_reg_range(0x0410, 0x042f),
493 regmap_reg_range(0x0500, 0x0519),
494 regmap_reg_range(0x0520, 0x054b),
495 regmap_reg_range(0x0550, 0x05b3),
498 regmap_reg_range(0x1000, 0x1001),
499 regmap_reg_range(0x1004, 0x100b),
500 regmap_reg_range(0x1013, 0x1013),
501 regmap_reg_range(0x1017, 0x1017),
502 regmap_reg_range(0x101b, 0x101b),
503 regmap_reg_range(0x101f, 0x1021),
504 regmap_reg_range(0x1030, 0x1030),
505 regmap_reg_range(0x1100, 0x1111),
506 regmap_reg_range(0x111a, 0x111d),
507 regmap_reg_range(0x1122, 0x1127),
508 regmap_reg_range(0x112a, 0x112b),
509 regmap_reg_range(0x1136, 0x1139),
510 regmap_reg_range(0x113e, 0x113f),
511 regmap_reg_range(0x1400, 0x1401),
512 regmap_reg_range(0x1403, 0x1403),
513 regmap_reg_range(0x1410, 0x1417),
514 regmap_reg_range(0x1420, 0x1423),
515 regmap_reg_range(0x1500, 0x1507),
516 regmap_reg_range(0x1600, 0x1612),
517 regmap_reg_range(0x1800, 0x180f),
518 regmap_reg_range(0x1900, 0x1907),
519 regmap_reg_range(0x1914, 0x191b),
520 regmap_reg_range(0x1a00, 0x1a03),
521 regmap_reg_range(0x1a04, 0x1a08),
522 regmap_reg_range(0x1b00, 0x1b01),
523 regmap_reg_range(0x1b04, 0x1b04),
524 regmap_reg_range(0x1c00, 0x1c05),
525 regmap_reg_range(0x1c08, 0x1c1b),
528 regmap_reg_range(0x2000, 0x2001),
529 regmap_reg_range(0x2004, 0x200b),
530 regmap_reg_range(0x2013, 0x2013),
531 regmap_reg_range(0x2017, 0x2017),
532 regmap_reg_range(0x201b, 0x201b),
533 regmap_reg_range(0x201f, 0x2021),
534 regmap_reg_range(0x2030, 0x2030),
535 regmap_reg_range(0x2100, 0x2111),
536 regmap_reg_range(0x211a, 0x211d),
537 regmap_reg_range(0x2122, 0x2127),
538 regmap_reg_range(0x212a, 0x212b),
539 regmap_reg_range(0x2136, 0x2139),
540 regmap_reg_range(0x213e, 0x213f),
541 regmap_reg_range(0x2400, 0x2401),
542 regmap_reg_range(0x2403, 0x2403),
543 regmap_reg_range(0x2410, 0x2417),
544 regmap_reg_range(0x2420, 0x2423),
545 regmap_reg_range(0x2500, 0x2507),
546 regmap_reg_range(0x2600, 0x2612),
547 regmap_reg_range(0x2800, 0x280f),
548 regmap_reg_range(0x2900, 0x2907),
549 regmap_reg_range(0x2914, 0x291b),
550 regmap_reg_range(0x2a00, 0x2a03),
551 regmap_reg_range(0x2a04, 0x2a08),
552 regmap_reg_range(0x2b00, 0x2b01),
553 regmap_reg_range(0x2b04, 0x2b04),
554 regmap_reg_range(0x2c00, 0x2c05),
555 regmap_reg_range(0x2c08, 0x2c1b),
558 regmap_reg_range(0x3000, 0x3001),
559 regmap_reg_range(0x3004, 0x300b),
560 regmap_reg_range(0x3013, 0x3013),
561 regmap_reg_range(0x3017, 0x3017),
562 regmap_reg_range(0x301b, 0x301b),
563 regmap_reg_range(0x301f, 0x3021),
564 regmap_reg_range(0x3030, 0x3030),
565 regmap_reg_range(0x3300, 0x3301),
566 regmap_reg_range(0x3303, 0x3303),
567 regmap_reg_range(0x3400, 0x3401),
568 regmap_reg_range(0x3403, 0x3403),
569 regmap_reg_range(0x3410, 0x3417),
570 regmap_reg_range(0x3420, 0x3423),
571 regmap_reg_range(0x3500, 0x3507),
572 regmap_reg_range(0x3600, 0x3612),
573 regmap_reg_range(0x3800, 0x380f),
574 regmap_reg_range(0x3900, 0x3907),
575 regmap_reg_range(0x3914, 0x391b),
576 regmap_reg_range(0x3a00, 0x3a03),
577 regmap_reg_range(0x3a04, 0x3a08),
578 regmap_reg_range(0x3b00, 0x3b01),
579 regmap_reg_range(0x3b04, 0x3b04),
580 regmap_reg_range(0x3c00, 0x3c05),
581 regmap_reg_range(0x3c08, 0x3c1b),
584 static const struct regmap_access_table ksz8563_register_set = {
585 .yes_ranges = ksz8563_valid_regs,
586 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
589 static const struct regmap_range ksz9477_valid_regs[] = {
590 regmap_reg_range(0x0000, 0x0003),
591 regmap_reg_range(0x0006, 0x0006),
592 regmap_reg_range(0x0010, 0x001f),
593 regmap_reg_range(0x0100, 0x0100),
594 regmap_reg_range(0x0103, 0x0107),
595 regmap_reg_range(0x010d, 0x010d),
596 regmap_reg_range(0x0110, 0x0113),
597 regmap_reg_range(0x0120, 0x012b),
598 regmap_reg_range(0x0201, 0x0201),
599 regmap_reg_range(0x0210, 0x0213),
600 regmap_reg_range(0x0300, 0x0300),
601 regmap_reg_range(0x0302, 0x031b),
602 regmap_reg_range(0x0320, 0x032b),
603 regmap_reg_range(0x0330, 0x0336),
604 regmap_reg_range(0x0338, 0x033b),
605 regmap_reg_range(0x033e, 0x033e),
606 regmap_reg_range(0x0340, 0x035f),
607 regmap_reg_range(0x0370, 0x0370),
608 regmap_reg_range(0x0378, 0x0378),
609 regmap_reg_range(0x037c, 0x037d),
610 regmap_reg_range(0x0390, 0x0393),
611 regmap_reg_range(0x0400, 0x040e),
612 regmap_reg_range(0x0410, 0x042f),
613 regmap_reg_range(0x0444, 0x044b),
614 regmap_reg_range(0x0450, 0x046f),
615 regmap_reg_range(0x0500, 0x0519),
616 regmap_reg_range(0x0520, 0x054b),
617 regmap_reg_range(0x0550, 0x05b3),
618 regmap_reg_range(0x0604, 0x060b),
619 regmap_reg_range(0x0610, 0x0612),
620 regmap_reg_range(0x0614, 0x062c),
621 regmap_reg_range(0x0640, 0x0645),
622 regmap_reg_range(0x0648, 0x064d),
625 regmap_reg_range(0x1000, 0x1001),
626 regmap_reg_range(0x1013, 0x1013),
627 regmap_reg_range(0x1017, 0x1017),
628 regmap_reg_range(0x101b, 0x101b),
629 regmap_reg_range(0x101f, 0x1020),
630 regmap_reg_range(0x1030, 0x1030),
631 regmap_reg_range(0x1100, 0x1115),
632 regmap_reg_range(0x111a, 0x111f),
633 regmap_reg_range(0x1122, 0x1127),
634 regmap_reg_range(0x112a, 0x112b),
635 regmap_reg_range(0x1136, 0x1139),
636 regmap_reg_range(0x113e, 0x113f),
637 regmap_reg_range(0x1400, 0x1401),
638 regmap_reg_range(0x1403, 0x1403),
639 regmap_reg_range(0x1410, 0x1417),
640 regmap_reg_range(0x1420, 0x1423),
641 regmap_reg_range(0x1500, 0x1507),
642 regmap_reg_range(0x1600, 0x1613),
643 regmap_reg_range(0x1800, 0x180f),
644 regmap_reg_range(0x1820, 0x1827),
645 regmap_reg_range(0x1830, 0x1837),
646 regmap_reg_range(0x1840, 0x184b),
647 regmap_reg_range(0x1900, 0x1907),
648 regmap_reg_range(0x1914, 0x191b),
649 regmap_reg_range(0x1920, 0x1920),
650 regmap_reg_range(0x1923, 0x1927),
651 regmap_reg_range(0x1a00, 0x1a03),
652 regmap_reg_range(0x1a04, 0x1a07),
653 regmap_reg_range(0x1b00, 0x1b01),
654 regmap_reg_range(0x1b04, 0x1b04),
655 regmap_reg_range(0x1c00, 0x1c05),
656 regmap_reg_range(0x1c08, 0x1c1b),
659 regmap_reg_range(0x2000, 0x2001),
660 regmap_reg_range(0x2013, 0x2013),
661 regmap_reg_range(0x2017, 0x2017),
662 regmap_reg_range(0x201b, 0x201b),
663 regmap_reg_range(0x201f, 0x2020),
664 regmap_reg_range(0x2030, 0x2030),
665 regmap_reg_range(0x2100, 0x2115),
666 regmap_reg_range(0x211a, 0x211f),
667 regmap_reg_range(0x2122, 0x2127),
668 regmap_reg_range(0x212a, 0x212b),
669 regmap_reg_range(0x2136, 0x2139),
670 regmap_reg_range(0x213e, 0x213f),
671 regmap_reg_range(0x2400, 0x2401),
672 regmap_reg_range(0x2403, 0x2403),
673 regmap_reg_range(0x2410, 0x2417),
674 regmap_reg_range(0x2420, 0x2423),
675 regmap_reg_range(0x2500, 0x2507),
676 regmap_reg_range(0x2600, 0x2613),
677 regmap_reg_range(0x2800, 0x280f),
678 regmap_reg_range(0x2820, 0x2827),
679 regmap_reg_range(0x2830, 0x2837),
680 regmap_reg_range(0x2840, 0x284b),
681 regmap_reg_range(0x2900, 0x2907),
682 regmap_reg_range(0x2914, 0x291b),
683 regmap_reg_range(0x2920, 0x2920),
684 regmap_reg_range(0x2923, 0x2927),
685 regmap_reg_range(0x2a00, 0x2a03),
686 regmap_reg_range(0x2a04, 0x2a07),
687 regmap_reg_range(0x2b00, 0x2b01),
688 regmap_reg_range(0x2b04, 0x2b04),
689 regmap_reg_range(0x2c00, 0x2c05),
690 regmap_reg_range(0x2c08, 0x2c1b),
693 regmap_reg_range(0x3000, 0x3001),
694 regmap_reg_range(0x3013, 0x3013),
695 regmap_reg_range(0x3017, 0x3017),
696 regmap_reg_range(0x301b, 0x301b),
697 regmap_reg_range(0x301f, 0x3020),
698 regmap_reg_range(0x3030, 0x3030),
699 regmap_reg_range(0x3100, 0x3115),
700 regmap_reg_range(0x311a, 0x311f),
701 regmap_reg_range(0x3122, 0x3127),
702 regmap_reg_range(0x312a, 0x312b),
703 regmap_reg_range(0x3136, 0x3139),
704 regmap_reg_range(0x313e, 0x313f),
705 regmap_reg_range(0x3400, 0x3401),
706 regmap_reg_range(0x3403, 0x3403),
707 regmap_reg_range(0x3410, 0x3417),
708 regmap_reg_range(0x3420, 0x3423),
709 regmap_reg_range(0x3500, 0x3507),
710 regmap_reg_range(0x3600, 0x3613),
711 regmap_reg_range(0x3800, 0x380f),
712 regmap_reg_range(0x3820, 0x3827),
713 regmap_reg_range(0x3830, 0x3837),
714 regmap_reg_range(0x3840, 0x384b),
715 regmap_reg_range(0x3900, 0x3907),
716 regmap_reg_range(0x3914, 0x391b),
717 regmap_reg_range(0x3920, 0x3920),
718 regmap_reg_range(0x3923, 0x3927),
719 regmap_reg_range(0x3a00, 0x3a03),
720 regmap_reg_range(0x3a04, 0x3a07),
721 regmap_reg_range(0x3b00, 0x3b01),
722 regmap_reg_range(0x3b04, 0x3b04),
723 regmap_reg_range(0x3c00, 0x3c05),
724 regmap_reg_range(0x3c08, 0x3c1b),
727 regmap_reg_range(0x4000, 0x4001),
728 regmap_reg_range(0x4013, 0x4013),
729 regmap_reg_range(0x4017, 0x4017),
730 regmap_reg_range(0x401b, 0x401b),
731 regmap_reg_range(0x401f, 0x4020),
732 regmap_reg_range(0x4030, 0x4030),
733 regmap_reg_range(0x4100, 0x4115),
734 regmap_reg_range(0x411a, 0x411f),
735 regmap_reg_range(0x4122, 0x4127),
736 regmap_reg_range(0x412a, 0x412b),
737 regmap_reg_range(0x4136, 0x4139),
738 regmap_reg_range(0x413e, 0x413f),
739 regmap_reg_range(0x4400, 0x4401),
740 regmap_reg_range(0x4403, 0x4403),
741 regmap_reg_range(0x4410, 0x4417),
742 regmap_reg_range(0x4420, 0x4423),
743 regmap_reg_range(0x4500, 0x4507),
744 regmap_reg_range(0x4600, 0x4613),
745 regmap_reg_range(0x4800, 0x480f),
746 regmap_reg_range(0x4820, 0x4827),
747 regmap_reg_range(0x4830, 0x4837),
748 regmap_reg_range(0x4840, 0x484b),
749 regmap_reg_range(0x4900, 0x4907),
750 regmap_reg_range(0x4914, 0x491b),
751 regmap_reg_range(0x4920, 0x4920),
752 regmap_reg_range(0x4923, 0x4927),
753 regmap_reg_range(0x4a00, 0x4a03),
754 regmap_reg_range(0x4a04, 0x4a07),
755 regmap_reg_range(0x4b00, 0x4b01),
756 regmap_reg_range(0x4b04, 0x4b04),
757 regmap_reg_range(0x4c00, 0x4c05),
758 regmap_reg_range(0x4c08, 0x4c1b),
761 regmap_reg_range(0x5000, 0x5001),
762 regmap_reg_range(0x5013, 0x5013),
763 regmap_reg_range(0x5017, 0x5017),
764 regmap_reg_range(0x501b, 0x501b),
765 regmap_reg_range(0x501f, 0x5020),
766 regmap_reg_range(0x5030, 0x5030),
767 regmap_reg_range(0x5100, 0x5115),
768 regmap_reg_range(0x511a, 0x511f),
769 regmap_reg_range(0x5122, 0x5127),
770 regmap_reg_range(0x512a, 0x512b),
771 regmap_reg_range(0x5136, 0x5139),
772 regmap_reg_range(0x513e, 0x513f),
773 regmap_reg_range(0x5400, 0x5401),
774 regmap_reg_range(0x5403, 0x5403),
775 regmap_reg_range(0x5410, 0x5417),
776 regmap_reg_range(0x5420, 0x5423),
777 regmap_reg_range(0x5500, 0x5507),
778 regmap_reg_range(0x5600, 0x5613),
779 regmap_reg_range(0x5800, 0x580f),
780 regmap_reg_range(0x5820, 0x5827),
781 regmap_reg_range(0x5830, 0x5837),
782 regmap_reg_range(0x5840, 0x584b),
783 regmap_reg_range(0x5900, 0x5907),
784 regmap_reg_range(0x5914, 0x591b),
785 regmap_reg_range(0x5920, 0x5920),
786 regmap_reg_range(0x5923, 0x5927),
787 regmap_reg_range(0x5a00, 0x5a03),
788 regmap_reg_range(0x5a04, 0x5a07),
789 regmap_reg_range(0x5b00, 0x5b01),
790 regmap_reg_range(0x5b04, 0x5b04),
791 regmap_reg_range(0x5c00, 0x5c05),
792 regmap_reg_range(0x5c08, 0x5c1b),
795 regmap_reg_range(0x6000, 0x6001),
796 regmap_reg_range(0x6013, 0x6013),
797 regmap_reg_range(0x6017, 0x6017),
798 regmap_reg_range(0x601b, 0x601b),
799 regmap_reg_range(0x601f, 0x6020),
800 regmap_reg_range(0x6030, 0x6030),
801 regmap_reg_range(0x6300, 0x6301),
802 regmap_reg_range(0x6400, 0x6401),
803 regmap_reg_range(0x6403, 0x6403),
804 regmap_reg_range(0x6410, 0x6417),
805 regmap_reg_range(0x6420, 0x6423),
806 regmap_reg_range(0x6500, 0x6507),
807 regmap_reg_range(0x6600, 0x6613),
808 regmap_reg_range(0x6800, 0x680f),
809 regmap_reg_range(0x6820, 0x6827),
810 regmap_reg_range(0x6830, 0x6837),
811 regmap_reg_range(0x6840, 0x684b),
812 regmap_reg_range(0x6900, 0x6907),
813 regmap_reg_range(0x6914, 0x691b),
814 regmap_reg_range(0x6920, 0x6920),
815 regmap_reg_range(0x6923, 0x6927),
816 regmap_reg_range(0x6a00, 0x6a03),
817 regmap_reg_range(0x6a04, 0x6a07),
818 regmap_reg_range(0x6b00, 0x6b01),
819 regmap_reg_range(0x6b04, 0x6b04),
820 regmap_reg_range(0x6c00, 0x6c05),
821 regmap_reg_range(0x6c08, 0x6c1b),
824 regmap_reg_range(0x7000, 0x7001),
825 regmap_reg_range(0x7013, 0x7013),
826 regmap_reg_range(0x7017, 0x7017),
827 regmap_reg_range(0x701b, 0x701b),
828 regmap_reg_range(0x701f, 0x7020),
829 regmap_reg_range(0x7030, 0x7030),
830 regmap_reg_range(0x7200, 0x7203),
831 regmap_reg_range(0x7206, 0x7207),
832 regmap_reg_range(0x7300, 0x7301),
833 regmap_reg_range(0x7400, 0x7401),
834 regmap_reg_range(0x7403, 0x7403),
835 regmap_reg_range(0x7410, 0x7417),
836 regmap_reg_range(0x7420, 0x7423),
837 regmap_reg_range(0x7500, 0x7507),
838 regmap_reg_range(0x7600, 0x7613),
839 regmap_reg_range(0x7800, 0x780f),
840 regmap_reg_range(0x7820, 0x7827),
841 regmap_reg_range(0x7830, 0x7837),
842 regmap_reg_range(0x7840, 0x784b),
843 regmap_reg_range(0x7900, 0x7907),
844 regmap_reg_range(0x7914, 0x791b),
845 regmap_reg_range(0x7920, 0x7920),
846 regmap_reg_range(0x7923, 0x7927),
847 regmap_reg_range(0x7a00, 0x7a03),
848 regmap_reg_range(0x7a04, 0x7a07),
849 regmap_reg_range(0x7b00, 0x7b01),
850 regmap_reg_range(0x7b04, 0x7b04),
851 regmap_reg_range(0x7c00, 0x7c05),
852 regmap_reg_range(0x7c08, 0x7c1b),
855 static const struct regmap_access_table ksz9477_register_set = {
856 .yes_ranges = ksz9477_valid_regs,
857 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
860 static const struct regmap_range ksz9896_valid_regs[] = {
861 regmap_reg_range(0x0000, 0x0003),
862 regmap_reg_range(0x0006, 0x0006),
863 regmap_reg_range(0x0010, 0x001f),
864 regmap_reg_range(0x0100, 0x0100),
865 regmap_reg_range(0x0103, 0x0107),
866 regmap_reg_range(0x010d, 0x010d),
867 regmap_reg_range(0x0110, 0x0113),
868 regmap_reg_range(0x0120, 0x0127),
869 regmap_reg_range(0x0201, 0x0201),
870 regmap_reg_range(0x0210, 0x0213),
871 regmap_reg_range(0x0300, 0x0300),
872 regmap_reg_range(0x0302, 0x030b),
873 regmap_reg_range(0x0310, 0x031b),
874 regmap_reg_range(0x0320, 0x032b),
875 regmap_reg_range(0x0330, 0x0336),
876 regmap_reg_range(0x0338, 0x033b),
877 regmap_reg_range(0x033e, 0x033e),
878 regmap_reg_range(0x0340, 0x035f),
879 regmap_reg_range(0x0370, 0x0370),
880 regmap_reg_range(0x0378, 0x0378),
881 regmap_reg_range(0x037c, 0x037d),
882 regmap_reg_range(0x0390, 0x0393),
883 regmap_reg_range(0x0400, 0x040e),
884 regmap_reg_range(0x0410, 0x042f),
887 regmap_reg_range(0x1000, 0x1001),
888 regmap_reg_range(0x1013, 0x1013),
889 regmap_reg_range(0x1017, 0x1017),
890 regmap_reg_range(0x101b, 0x101b),
891 regmap_reg_range(0x101f, 0x1020),
892 regmap_reg_range(0x1030, 0x1030),
893 regmap_reg_range(0x1100, 0x1115),
894 regmap_reg_range(0x111a, 0x111f),
895 regmap_reg_range(0x1122, 0x1127),
896 regmap_reg_range(0x112a, 0x112b),
897 regmap_reg_range(0x1136, 0x1139),
898 regmap_reg_range(0x113e, 0x113f),
899 regmap_reg_range(0x1400, 0x1401),
900 regmap_reg_range(0x1403, 0x1403),
901 regmap_reg_range(0x1410, 0x1417),
902 regmap_reg_range(0x1420, 0x1423),
903 regmap_reg_range(0x1500, 0x1507),
904 regmap_reg_range(0x1600, 0x1612),
905 regmap_reg_range(0x1800, 0x180f),
906 regmap_reg_range(0x1820, 0x1827),
907 regmap_reg_range(0x1830, 0x1837),
908 regmap_reg_range(0x1840, 0x184b),
909 regmap_reg_range(0x1900, 0x1907),
910 regmap_reg_range(0x1914, 0x1915),
911 regmap_reg_range(0x1a00, 0x1a03),
912 regmap_reg_range(0x1a04, 0x1a07),
913 regmap_reg_range(0x1b00, 0x1b01),
914 regmap_reg_range(0x1b04, 0x1b04),
917 regmap_reg_range(0x2000, 0x2001),
918 regmap_reg_range(0x2013, 0x2013),
919 regmap_reg_range(0x2017, 0x2017),
920 regmap_reg_range(0x201b, 0x201b),
921 regmap_reg_range(0x201f, 0x2020),
922 regmap_reg_range(0x2030, 0x2030),
923 regmap_reg_range(0x2100, 0x2115),
924 regmap_reg_range(0x211a, 0x211f),
925 regmap_reg_range(0x2122, 0x2127),
926 regmap_reg_range(0x212a, 0x212b),
927 regmap_reg_range(0x2136, 0x2139),
928 regmap_reg_range(0x213e, 0x213f),
929 regmap_reg_range(0x2400, 0x2401),
930 regmap_reg_range(0x2403, 0x2403),
931 regmap_reg_range(0x2410, 0x2417),
932 regmap_reg_range(0x2420, 0x2423),
933 regmap_reg_range(0x2500, 0x2507),
934 regmap_reg_range(0x2600, 0x2612),
935 regmap_reg_range(0x2800, 0x280f),
936 regmap_reg_range(0x2820, 0x2827),
937 regmap_reg_range(0x2830, 0x2837),
938 regmap_reg_range(0x2840, 0x284b),
939 regmap_reg_range(0x2900, 0x2907),
940 regmap_reg_range(0x2914, 0x2915),
941 regmap_reg_range(0x2a00, 0x2a03),
942 regmap_reg_range(0x2a04, 0x2a07),
943 regmap_reg_range(0x2b00, 0x2b01),
944 regmap_reg_range(0x2b04, 0x2b04),
947 regmap_reg_range(0x3000, 0x3001),
948 regmap_reg_range(0x3013, 0x3013),
949 regmap_reg_range(0x3017, 0x3017),
950 regmap_reg_range(0x301b, 0x301b),
951 regmap_reg_range(0x301f, 0x3020),
952 regmap_reg_range(0x3030, 0x3030),
953 regmap_reg_range(0x3100, 0x3115),
954 regmap_reg_range(0x311a, 0x311f),
955 regmap_reg_range(0x3122, 0x3127),
956 regmap_reg_range(0x312a, 0x312b),
957 regmap_reg_range(0x3136, 0x3139),
958 regmap_reg_range(0x313e, 0x313f),
959 regmap_reg_range(0x3400, 0x3401),
960 regmap_reg_range(0x3403, 0x3403),
961 regmap_reg_range(0x3410, 0x3417),
962 regmap_reg_range(0x3420, 0x3423),
963 regmap_reg_range(0x3500, 0x3507),
964 regmap_reg_range(0x3600, 0x3612),
965 regmap_reg_range(0x3800, 0x380f),
966 regmap_reg_range(0x3820, 0x3827),
967 regmap_reg_range(0x3830, 0x3837),
968 regmap_reg_range(0x3840, 0x384b),
969 regmap_reg_range(0x3900, 0x3907),
970 regmap_reg_range(0x3914, 0x3915),
971 regmap_reg_range(0x3a00, 0x3a03),
972 regmap_reg_range(0x3a04, 0x3a07),
973 regmap_reg_range(0x3b00, 0x3b01),
974 regmap_reg_range(0x3b04, 0x3b04),
977 regmap_reg_range(0x4000, 0x4001),
978 regmap_reg_range(0x4013, 0x4013),
979 regmap_reg_range(0x4017, 0x4017),
980 regmap_reg_range(0x401b, 0x401b),
981 regmap_reg_range(0x401f, 0x4020),
982 regmap_reg_range(0x4030, 0x4030),
983 regmap_reg_range(0x4100, 0x4115),
984 regmap_reg_range(0x411a, 0x411f),
985 regmap_reg_range(0x4122, 0x4127),
986 regmap_reg_range(0x412a, 0x412b),
987 regmap_reg_range(0x4136, 0x4139),
988 regmap_reg_range(0x413e, 0x413f),
989 regmap_reg_range(0x4400, 0x4401),
990 regmap_reg_range(0x4403, 0x4403),
991 regmap_reg_range(0x4410, 0x4417),
992 regmap_reg_range(0x4420, 0x4423),
993 regmap_reg_range(0x4500, 0x4507),
994 regmap_reg_range(0x4600, 0x4612),
995 regmap_reg_range(0x4800, 0x480f),
996 regmap_reg_range(0x4820, 0x4827),
997 regmap_reg_range(0x4830, 0x4837),
998 regmap_reg_range(0x4840, 0x484b),
999 regmap_reg_range(0x4900, 0x4907),
1000 regmap_reg_range(0x4914, 0x4915),
1001 regmap_reg_range(0x4a00, 0x4a03),
1002 regmap_reg_range(0x4a04, 0x4a07),
1003 regmap_reg_range(0x4b00, 0x4b01),
1004 regmap_reg_range(0x4b04, 0x4b04),
1007 regmap_reg_range(0x5000, 0x5001),
1008 regmap_reg_range(0x5013, 0x5013),
1009 regmap_reg_range(0x5017, 0x5017),
1010 regmap_reg_range(0x501b, 0x501b),
1011 regmap_reg_range(0x501f, 0x5020),
1012 regmap_reg_range(0x5030, 0x5030),
1013 regmap_reg_range(0x5100, 0x5115),
1014 regmap_reg_range(0x511a, 0x511f),
1015 regmap_reg_range(0x5122, 0x5127),
1016 regmap_reg_range(0x512a, 0x512b),
1017 regmap_reg_range(0x5136, 0x5139),
1018 regmap_reg_range(0x513e, 0x513f),
1019 regmap_reg_range(0x5400, 0x5401),
1020 regmap_reg_range(0x5403, 0x5403),
1021 regmap_reg_range(0x5410, 0x5417),
1022 regmap_reg_range(0x5420, 0x5423),
1023 regmap_reg_range(0x5500, 0x5507),
1024 regmap_reg_range(0x5600, 0x5612),
1025 regmap_reg_range(0x5800, 0x580f),
1026 regmap_reg_range(0x5820, 0x5827),
1027 regmap_reg_range(0x5830, 0x5837),
1028 regmap_reg_range(0x5840, 0x584b),
1029 regmap_reg_range(0x5900, 0x5907),
1030 regmap_reg_range(0x5914, 0x5915),
1031 regmap_reg_range(0x5a00, 0x5a03),
1032 regmap_reg_range(0x5a04, 0x5a07),
1033 regmap_reg_range(0x5b00, 0x5b01),
1034 regmap_reg_range(0x5b04, 0x5b04),
1037 regmap_reg_range(0x6000, 0x6001),
1038 regmap_reg_range(0x6013, 0x6013),
1039 regmap_reg_range(0x6017, 0x6017),
1040 regmap_reg_range(0x601b, 0x601b),
1041 regmap_reg_range(0x601f, 0x6020),
1042 regmap_reg_range(0x6030, 0x6030),
1043 regmap_reg_range(0x6100, 0x6115),
1044 regmap_reg_range(0x611a, 0x611f),
1045 regmap_reg_range(0x6122, 0x6127),
1046 regmap_reg_range(0x612a, 0x612b),
1047 regmap_reg_range(0x6136, 0x6139),
1048 regmap_reg_range(0x613e, 0x613f),
1049 regmap_reg_range(0x6300, 0x6301),
1050 regmap_reg_range(0x6400, 0x6401),
1051 regmap_reg_range(0x6403, 0x6403),
1052 regmap_reg_range(0x6410, 0x6417),
1053 regmap_reg_range(0x6420, 0x6423),
1054 regmap_reg_range(0x6500, 0x6507),
1055 regmap_reg_range(0x6600, 0x6612),
1056 regmap_reg_range(0x6800, 0x680f),
1057 regmap_reg_range(0x6820, 0x6827),
1058 regmap_reg_range(0x6830, 0x6837),
1059 regmap_reg_range(0x6840, 0x684b),
1060 regmap_reg_range(0x6900, 0x6907),
1061 regmap_reg_range(0x6914, 0x6915),
1062 regmap_reg_range(0x6a00, 0x6a03),
1063 regmap_reg_range(0x6a04, 0x6a07),
1064 regmap_reg_range(0x6b00, 0x6b01),
1065 regmap_reg_range(0x6b04, 0x6b04),
1068 static const struct regmap_access_table ksz9896_register_set = {
1069 .yes_ranges = ksz9896_valid_regs,
1070 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1073 const struct ksz_chip_data ksz_switch_chips[] = {
1075 .chip_id = KSZ8563_CHIP_ID,
1076 .dev_name = "KSZ8563",
1080 .cpu_ports = 0x07, /* can be configured as cpu port */
1081 .port_cnt = 3, /* total port count */
1084 .ops = &ksz9477_dev_ops,
1085 .mib_names = ksz9477_mib_names,
1086 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1087 .reg_mib_cnt = MIB_COUNTER_NUM,
1088 .regs = ksz9477_regs,
1089 .masks = ksz9477_masks,
1090 .shifts = ksz9477_shifts,
1091 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1092 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1093 .supports_mii = {false, false, true},
1094 .supports_rmii = {false, false, true},
1095 .supports_rgmii = {false, false, true},
1096 .internal_phy = {true, true, false},
1097 .gbit_capable = {false, false, true},
1098 .wr_table = &ksz8563_register_set,
1099 .rd_table = &ksz8563_register_set,
1103 .chip_id = KSZ8795_CHIP_ID,
1104 .dev_name = "KSZ8795",
1108 .cpu_ports = 0x10, /* can be configured as cpu port */
1109 .port_cnt = 5, /* total cpu and user ports */
1111 .ops = &ksz8_dev_ops,
1112 .ksz87xx_eee_link_erratum = true,
1113 .mib_names = ksz9477_mib_names,
1114 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1115 .reg_mib_cnt = MIB_COUNTER_NUM,
1116 .regs = ksz8795_regs,
1117 .masks = ksz8795_masks,
1118 .shifts = ksz8795_shifts,
1119 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1120 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1121 .supports_mii = {false, false, false, false, true},
1122 .supports_rmii = {false, false, false, false, true},
1123 .supports_rgmii = {false, false, false, false, true},
1124 .internal_phy = {true, true, true, true, false},
1130 * KSZ8794 is similar to KSZ8795, except the port map
1131 * contains a gap between external and CPU ports, the
1132 * port map is NOT continuous. The per-port register
1133 * map is shifted accordingly too, i.e. registers at
1134 * offset 0x40 are NOT used on KSZ8794 and they ARE
1135 * used on KSZ8795 for external port 3.
1140 * port_cnt is configured as 5, even though it is 4
1142 .chip_id = KSZ8794_CHIP_ID,
1143 .dev_name = "KSZ8794",
1147 .cpu_ports = 0x10, /* can be configured as cpu port */
1148 .port_cnt = 5, /* total cpu and user ports */
1150 .ops = &ksz8_dev_ops,
1151 .ksz87xx_eee_link_erratum = true,
1152 .mib_names = ksz9477_mib_names,
1153 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1154 .reg_mib_cnt = MIB_COUNTER_NUM,
1155 .regs = ksz8795_regs,
1156 .masks = ksz8795_masks,
1157 .shifts = ksz8795_shifts,
1158 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1159 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1160 .supports_mii = {false, false, false, false, true},
1161 .supports_rmii = {false, false, false, false, true},
1162 .supports_rgmii = {false, false, false, false, true},
1163 .internal_phy = {true, true, true, false, false},
1167 .chip_id = KSZ8765_CHIP_ID,
1168 .dev_name = "KSZ8765",
1172 .cpu_ports = 0x10, /* can be configured as cpu port */
1173 .port_cnt = 5, /* total cpu and user ports */
1175 .ops = &ksz8_dev_ops,
1176 .ksz87xx_eee_link_erratum = true,
1177 .mib_names = ksz9477_mib_names,
1178 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1179 .reg_mib_cnt = MIB_COUNTER_NUM,
1180 .regs = ksz8795_regs,
1181 .masks = ksz8795_masks,
1182 .shifts = ksz8795_shifts,
1183 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1184 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1185 .supports_mii = {false, false, false, false, true},
1186 .supports_rmii = {false, false, false, false, true},
1187 .supports_rgmii = {false, false, false, false, true},
1188 .internal_phy = {true, true, true, true, false},
1192 .chip_id = KSZ8830_CHIP_ID,
1193 .dev_name = "KSZ8863/KSZ8873",
1197 .cpu_ports = 0x4, /* can be configured as cpu port */
1200 .ops = &ksz8_dev_ops,
1201 .mib_names = ksz88xx_mib_names,
1202 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1203 .reg_mib_cnt = MIB_COUNTER_NUM,
1204 .regs = ksz8863_regs,
1205 .masks = ksz8863_masks,
1206 .shifts = ksz8863_shifts,
1207 .supports_mii = {false, false, true},
1208 .supports_rmii = {false, false, true},
1209 .internal_phy = {true, true, false},
1213 .chip_id = KSZ9477_CHIP_ID,
1214 .dev_name = "KSZ9477",
1218 .cpu_ports = 0x7F, /* can be configured as cpu port */
1219 .port_cnt = 7, /* total physical port count */
1222 .ops = &ksz9477_dev_ops,
1223 .phy_errata_9477 = true,
1224 .mib_names = ksz9477_mib_names,
1225 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1226 .reg_mib_cnt = MIB_COUNTER_NUM,
1227 .regs = ksz9477_regs,
1228 .masks = ksz9477_masks,
1229 .shifts = ksz9477_shifts,
1230 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1231 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1232 .supports_mii = {false, false, false, false,
1233 false, true, false},
1234 .supports_rmii = {false, false, false, false,
1235 false, true, false},
1236 .supports_rgmii = {false, false, false, false,
1237 false, true, false},
1238 .internal_phy = {true, true, true, true,
1239 true, false, false},
1240 .gbit_capable = {true, true, true, true, true, true, true},
1241 .wr_table = &ksz9477_register_set,
1242 .rd_table = &ksz9477_register_set,
1246 .chip_id = KSZ9896_CHIP_ID,
1247 .dev_name = "KSZ9896",
1251 .cpu_ports = 0x3F, /* can be configured as cpu port */
1252 .port_cnt = 6, /* total physical port count */
1255 .ops = &ksz9477_dev_ops,
1256 .phy_errata_9477 = true,
1257 .mib_names = ksz9477_mib_names,
1258 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1259 .reg_mib_cnt = MIB_COUNTER_NUM,
1260 .regs = ksz9477_regs,
1261 .masks = ksz9477_masks,
1262 .shifts = ksz9477_shifts,
1263 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1264 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1265 .supports_mii = {false, false, false, false,
1267 .supports_rmii = {false, false, false, false,
1269 .supports_rgmii = {false, false, false, false,
1271 .internal_phy = {true, true, true, true,
1273 .gbit_capable = {true, true, true, true, true, true},
1274 .wr_table = &ksz9896_register_set,
1275 .rd_table = &ksz9896_register_set,
1279 .chip_id = KSZ9897_CHIP_ID,
1280 .dev_name = "KSZ9897",
1284 .cpu_ports = 0x7F, /* can be configured as cpu port */
1285 .port_cnt = 7, /* total physical port count */
1288 .ops = &ksz9477_dev_ops,
1289 .phy_errata_9477 = true,
1290 .mib_names = ksz9477_mib_names,
1291 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1292 .reg_mib_cnt = MIB_COUNTER_NUM,
1293 .regs = ksz9477_regs,
1294 .masks = ksz9477_masks,
1295 .shifts = ksz9477_shifts,
1296 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1297 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1298 .supports_mii = {false, false, false, false,
1300 .supports_rmii = {false, false, false, false,
1302 .supports_rgmii = {false, false, false, false,
1304 .internal_phy = {true, true, true, true,
1305 true, false, false},
1306 .gbit_capable = {true, true, true, true, true, true, true},
1310 .chip_id = KSZ9893_CHIP_ID,
1311 .dev_name = "KSZ9893",
1315 .cpu_ports = 0x07, /* can be configured as cpu port */
1316 .port_cnt = 3, /* total port count */
1319 .ops = &ksz9477_dev_ops,
1320 .mib_names = ksz9477_mib_names,
1321 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1322 .reg_mib_cnt = MIB_COUNTER_NUM,
1323 .regs = ksz9477_regs,
1324 .masks = ksz9477_masks,
1325 .shifts = ksz9477_shifts,
1326 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1327 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1328 .supports_mii = {false, false, true},
1329 .supports_rmii = {false, false, true},
1330 .supports_rgmii = {false, false, true},
1331 .internal_phy = {true, true, false},
1332 .gbit_capable = {true, true, true},
1336 .chip_id = KSZ9563_CHIP_ID,
1337 .dev_name = "KSZ9563",
1341 .cpu_ports = 0x07, /* can be configured as cpu port */
1342 .port_cnt = 3, /* total port count */
1345 .ops = &ksz9477_dev_ops,
1346 .mib_names = ksz9477_mib_names,
1347 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1348 .reg_mib_cnt = MIB_COUNTER_NUM,
1349 .regs = ksz9477_regs,
1350 .masks = ksz9477_masks,
1351 .shifts = ksz9477_shifts,
1352 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1353 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1354 .supports_mii = {false, false, true},
1355 .supports_rmii = {false, false, true},
1356 .supports_rgmii = {false, false, true},
1357 .internal_phy = {true, true, false},
1358 .gbit_capable = {true, true, true},
1362 .chip_id = KSZ9567_CHIP_ID,
1363 .dev_name = "KSZ9567",
1367 .cpu_ports = 0x7F, /* can be configured as cpu port */
1368 .port_cnt = 7, /* total physical port count */
1371 .ops = &ksz9477_dev_ops,
1372 .phy_errata_9477 = true,
1373 .mib_names = ksz9477_mib_names,
1374 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1375 .reg_mib_cnt = MIB_COUNTER_NUM,
1376 .regs = ksz9477_regs,
1377 .masks = ksz9477_masks,
1378 .shifts = ksz9477_shifts,
1379 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1380 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1381 .supports_mii = {false, false, false, false,
1383 .supports_rmii = {false, false, false, false,
1385 .supports_rgmii = {false, false, false, false,
1387 .internal_phy = {true, true, true, true,
1388 true, false, false},
1389 .gbit_capable = {true, true, true, true, true, true, true},
1393 .chip_id = LAN9370_CHIP_ID,
1394 .dev_name = "LAN9370",
1398 .cpu_ports = 0x10, /* can be configured as cpu port */
1399 .port_cnt = 5, /* total physical port count */
1402 .ops = &lan937x_dev_ops,
1403 .mib_names = ksz9477_mib_names,
1404 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1405 .reg_mib_cnt = MIB_COUNTER_NUM,
1406 .regs = ksz9477_regs,
1407 .masks = lan937x_masks,
1408 .shifts = lan937x_shifts,
1409 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1410 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1411 .supports_mii = {false, false, false, false, true},
1412 .supports_rmii = {false, false, false, false, true},
1413 .supports_rgmii = {false, false, false, false, true},
1414 .internal_phy = {true, true, true, true, false},
1418 .chip_id = LAN9371_CHIP_ID,
1419 .dev_name = "LAN9371",
1423 .cpu_ports = 0x30, /* can be configured as cpu port */
1424 .port_cnt = 6, /* total physical port count */
1427 .ops = &lan937x_dev_ops,
1428 .mib_names = ksz9477_mib_names,
1429 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1430 .reg_mib_cnt = MIB_COUNTER_NUM,
1431 .regs = ksz9477_regs,
1432 .masks = lan937x_masks,
1433 .shifts = lan937x_shifts,
1434 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1435 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1436 .supports_mii = {false, false, false, false, true, true},
1437 .supports_rmii = {false, false, false, false, true, true},
1438 .supports_rgmii = {false, false, false, false, true, true},
1439 .internal_phy = {true, true, true, true, false, false},
1443 .chip_id = LAN9372_CHIP_ID,
1444 .dev_name = "LAN9372",
1448 .cpu_ports = 0x30, /* can be configured as cpu port */
1449 .port_cnt = 8, /* total physical port count */
1452 .ops = &lan937x_dev_ops,
1453 .mib_names = ksz9477_mib_names,
1454 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1455 .reg_mib_cnt = MIB_COUNTER_NUM,
1456 .regs = ksz9477_regs,
1457 .masks = lan937x_masks,
1458 .shifts = lan937x_shifts,
1459 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1460 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1461 .supports_mii = {false, false, false, false,
1462 true, true, false, false},
1463 .supports_rmii = {false, false, false, false,
1464 true, true, false, false},
1465 .supports_rgmii = {false, false, false, false,
1466 true, true, false, false},
1467 .internal_phy = {true, true, true, true,
1468 false, false, true, true},
1472 .chip_id = LAN9373_CHIP_ID,
1473 .dev_name = "LAN9373",
1477 .cpu_ports = 0x38, /* can be configured as cpu port */
1478 .port_cnt = 5, /* total physical port count */
1481 .ops = &lan937x_dev_ops,
1482 .mib_names = ksz9477_mib_names,
1483 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1484 .reg_mib_cnt = MIB_COUNTER_NUM,
1485 .regs = ksz9477_regs,
1486 .masks = lan937x_masks,
1487 .shifts = lan937x_shifts,
1488 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1489 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1490 .supports_mii = {false, false, false, false,
1491 true, true, false, false},
1492 .supports_rmii = {false, false, false, false,
1493 true, true, false, false},
1494 .supports_rgmii = {false, false, false, false,
1495 true, true, false, false},
1496 .internal_phy = {true, true, true, false,
1497 false, false, true, true},
1501 .chip_id = LAN9374_CHIP_ID,
1502 .dev_name = "LAN9374",
1506 .cpu_ports = 0x30, /* can be configured as cpu port */
1507 .port_cnt = 8, /* total physical port count */
1510 .ops = &lan937x_dev_ops,
1511 .mib_names = ksz9477_mib_names,
1512 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1513 .reg_mib_cnt = MIB_COUNTER_NUM,
1514 .regs = ksz9477_regs,
1515 .masks = lan937x_masks,
1516 .shifts = lan937x_shifts,
1517 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1518 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1519 .supports_mii = {false, false, false, false,
1520 true, true, false, false},
1521 .supports_rmii = {false, false, false, false,
1522 true, true, false, false},
1523 .supports_rgmii = {false, false, false, false,
1524 true, true, false, false},
1525 .internal_phy = {true, true, true, true,
1526 false, false, true, true},
1529 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1531 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1535 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1536 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1538 if (chip->chip_id == prod_num)
1545 static int ksz_check_device_id(struct ksz_device *dev)
1547 const struct ksz_chip_data *dt_chip_data;
1549 dt_chip_data = of_device_get_match_data(dev->dev);
1551 /* Check for Device Tree and Chip ID */
1552 if (dt_chip_data->chip_id != dev->chip_id) {
1554 "Device tree specifies chip %s but found %s, please fix it!\n",
1555 dt_chip_data->dev_name, dev->info->dev_name);
1562 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1563 struct phylink_config *config)
1565 struct ksz_device *dev = ds->priv;
1567 config->legacy_pre_march2020 = false;
1569 if (dev->info->supports_mii[port])
1570 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1572 if (dev->info->supports_rmii[port])
1573 __set_bit(PHY_INTERFACE_MODE_RMII,
1574 config->supported_interfaces);
1576 if (dev->info->supports_rgmii[port])
1577 phy_interface_set_rgmii(config->supported_interfaces);
1579 if (dev->info->internal_phy[port]) {
1580 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1581 config->supported_interfaces);
1582 /* Compatibility for phylib's default interface type when the
1583 * phy-mode property is absent
1585 __set_bit(PHY_INTERFACE_MODE_GMII,
1586 config->supported_interfaces);
1589 if (dev->dev_ops->get_caps)
1590 dev->dev_ops->get_caps(dev, port, config);
1593 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1595 struct ethtool_pause_stats *pstats;
1596 struct rtnl_link_stats64 *stats;
1597 struct ksz_stats_raw *raw;
1598 struct ksz_port_mib *mib;
1600 mib = &dev->ports[port].mib;
1601 stats = &mib->stats64;
1602 pstats = &mib->pause_stats;
1603 raw = (struct ksz_stats_raw *)mib->counters;
1605 spin_lock(&mib->stats64_lock);
1607 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1609 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1612 /* HW counters are counting bytes + FCS which is not acceptable
1613 * for rtnl_link_stats64 interface
1615 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1616 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1618 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1621 stats->rx_crc_errors = raw->rx_crc_err;
1622 stats->rx_frame_errors = raw->rx_align_err;
1623 stats->rx_dropped = raw->rx_discards;
1624 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1625 stats->rx_frame_errors + stats->rx_dropped;
1627 stats->tx_window_errors = raw->tx_late_col;
1628 stats->tx_fifo_errors = raw->tx_discards;
1629 stats->tx_aborted_errors = raw->tx_exc_col;
1630 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1631 stats->tx_aborted_errors;
1633 stats->multicast = raw->rx_mcast;
1634 stats->collisions = raw->tx_total_col;
1636 pstats->tx_pause_frames = raw->tx_pause;
1637 pstats->rx_pause_frames = raw->rx_pause;
1639 spin_unlock(&mib->stats64_lock);
1642 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1644 struct ethtool_pause_stats *pstats;
1645 struct rtnl_link_stats64 *stats;
1646 struct ksz88xx_stats_raw *raw;
1647 struct ksz_port_mib *mib;
1649 mib = &dev->ports[port].mib;
1650 stats = &mib->stats64;
1651 pstats = &mib->pause_stats;
1652 raw = (struct ksz88xx_stats_raw *)mib->counters;
1654 spin_lock(&mib->stats64_lock);
1656 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1658 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1661 /* HW counters are counting bytes + FCS which is not acceptable
1662 * for rtnl_link_stats64 interface
1664 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1665 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1667 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1670 stats->rx_crc_errors = raw->rx_crc_err;
1671 stats->rx_frame_errors = raw->rx_align_err;
1672 stats->rx_dropped = raw->rx_discards;
1673 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1674 stats->rx_frame_errors + stats->rx_dropped;
1676 stats->tx_window_errors = raw->tx_late_col;
1677 stats->tx_fifo_errors = raw->tx_discards;
1678 stats->tx_aborted_errors = raw->tx_exc_col;
1679 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1680 stats->tx_aborted_errors;
1682 stats->multicast = raw->rx_mcast;
1683 stats->collisions = raw->tx_total_col;
1685 pstats->tx_pause_frames = raw->tx_pause;
1686 pstats->rx_pause_frames = raw->rx_pause;
1688 spin_unlock(&mib->stats64_lock);
1691 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1692 struct rtnl_link_stats64 *s)
1694 struct ksz_device *dev = ds->priv;
1695 struct ksz_port_mib *mib;
1697 mib = &dev->ports[port].mib;
1699 spin_lock(&mib->stats64_lock);
1700 memcpy(s, &mib->stats64, sizeof(*s));
1701 spin_unlock(&mib->stats64_lock);
1704 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1705 struct ethtool_pause_stats *pause_stats)
1707 struct ksz_device *dev = ds->priv;
1708 struct ksz_port_mib *mib;
1710 mib = &dev->ports[port].mib;
1712 spin_lock(&mib->stats64_lock);
1713 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1714 spin_unlock(&mib->stats64_lock);
1717 static void ksz_get_strings(struct dsa_switch *ds, int port,
1718 u32 stringset, uint8_t *buf)
1720 struct ksz_device *dev = ds->priv;
1723 if (stringset != ETH_SS_STATS)
1726 for (i = 0; i < dev->info->mib_cnt; i++) {
1727 memcpy(buf + i * ETH_GSTRING_LEN,
1728 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1732 static void ksz_update_port_member(struct ksz_device *dev, int port)
1734 struct ksz_port *p = &dev->ports[port];
1735 struct dsa_switch *ds = dev->ds;
1736 u8 port_member = 0, cpu_port;
1737 const struct dsa_port *dp;
1740 if (!dsa_is_user_port(ds, port))
1743 dp = dsa_to_port(ds, port);
1744 cpu_port = BIT(dsa_upstream_port(ds, port));
1746 for (i = 0; i < ds->num_ports; i++) {
1747 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1748 struct ksz_port *other_p = &dev->ports[i];
1751 if (!dsa_is_user_port(ds, i))
1755 if (!dsa_port_bridge_same(dp, other_dp))
1757 if (other_p->stp_state != BR_STATE_FORWARDING)
1760 if (p->stp_state == BR_STATE_FORWARDING) {
1762 port_member |= BIT(i);
1765 /* Retain port [i]'s relationship to other ports than [port] */
1766 for (j = 0; j < ds->num_ports; j++) {
1767 const struct dsa_port *third_dp;
1768 struct ksz_port *third_p;
1774 if (!dsa_is_user_port(ds, j))
1776 third_p = &dev->ports[j];
1777 if (third_p->stp_state != BR_STATE_FORWARDING)
1779 third_dp = dsa_to_port(ds, j);
1780 if (dsa_port_bridge_same(other_dp, third_dp))
1784 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1787 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1790 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1792 struct ksz_device *dev = bus->priv;
1796 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1803 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1806 struct ksz_device *dev = bus->priv;
1808 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1811 static int ksz_irq_phy_setup(struct ksz_device *dev)
1813 struct dsa_switch *ds = dev->ds;
1818 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1819 if (BIT(phy) & ds->phys_mii_mask) {
1820 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1826 ds->slave_mii_bus->irq[phy] = irq;
1832 if (BIT(phy) & ds->phys_mii_mask)
1833 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1838 static void ksz_irq_phy_free(struct ksz_device *dev)
1840 struct dsa_switch *ds = dev->ds;
1843 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1844 if (BIT(phy) & ds->phys_mii_mask)
1845 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1848 static int ksz_mdio_register(struct ksz_device *dev)
1850 struct dsa_switch *ds = dev->ds;
1851 struct device_node *mdio_np;
1852 struct mii_bus *bus;
1855 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1859 bus = devm_mdiobus_alloc(ds->dev);
1861 of_node_put(mdio_np);
1866 bus->read = ksz_sw_mdio_read;
1867 bus->write = ksz_sw_mdio_write;
1868 bus->name = "ksz slave smi";
1869 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1870 bus->parent = ds->dev;
1871 bus->phy_mask = ~ds->phys_mii_mask;
1873 ds->slave_mii_bus = bus;
1876 ret = ksz_irq_phy_setup(dev);
1878 of_node_put(mdio_np);
1883 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1885 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1888 ksz_irq_phy_free(dev);
1891 of_node_put(mdio_np);
1896 static void ksz_irq_mask(struct irq_data *d)
1898 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1900 kirq->masked |= BIT(d->hwirq);
1903 static void ksz_irq_unmask(struct irq_data *d)
1905 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1907 kirq->masked &= ~BIT(d->hwirq);
1910 static void ksz_irq_bus_lock(struct irq_data *d)
1912 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1914 mutex_lock(&kirq->dev->lock_irq);
1917 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1919 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1920 struct ksz_device *dev = kirq->dev;
1923 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1925 dev_err(dev->dev, "failed to change IRQ mask\n");
1927 mutex_unlock(&dev->lock_irq);
1930 static const struct irq_chip ksz_irq_chip = {
1932 .irq_mask = ksz_irq_mask,
1933 .irq_unmask = ksz_irq_unmask,
1934 .irq_bus_lock = ksz_irq_bus_lock,
1935 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1938 static int ksz_irq_domain_map(struct irq_domain *d,
1939 unsigned int irq, irq_hw_number_t hwirq)
1941 irq_set_chip_data(irq, d->host_data);
1942 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1943 irq_set_noprobe(irq);
1948 static const struct irq_domain_ops ksz_irq_domain_ops = {
1949 .map = ksz_irq_domain_map,
1950 .xlate = irq_domain_xlate_twocell,
1953 static void ksz_irq_free(struct ksz_irq *kirq)
1957 free_irq(kirq->irq_num, kirq);
1959 for (irq = 0; irq < kirq->nirqs; irq++) {
1960 virq = irq_find_mapping(kirq->domain, irq);
1961 irq_dispose_mapping(virq);
1964 irq_domain_remove(kirq->domain);
1967 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
1969 struct ksz_irq *kirq = dev_id;
1970 unsigned int nhandled = 0;
1971 struct ksz_device *dev;
1972 unsigned int sub_irq;
1979 /* Read interrupt status register */
1980 ret = ksz_read8(dev, kirq->reg_status, &data);
1984 for (n = 0; n < kirq->nirqs; ++n) {
1985 if (data & BIT(n)) {
1986 sub_irq = irq_find_mapping(kirq->domain, n);
1987 handle_nested_irq(sub_irq);
1992 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1995 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2002 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2003 &ksz_irq_domain_ops, kirq);
2007 for (n = 0; n < kirq->nirqs; n++)
2008 irq_create_mapping(kirq->domain, n);
2010 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2011 IRQF_ONESHOT, kirq->name, kirq);
2023 static int ksz_girq_setup(struct ksz_device *dev)
2025 struct ksz_irq *girq = &dev->girq;
2027 girq->nirqs = dev->info->port_cnt;
2028 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2029 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2030 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2032 girq->irq_num = dev->irq;
2034 return ksz_irq_common_setup(dev, girq);
2037 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2039 struct ksz_irq *pirq = &dev->ports[p].pirq;
2041 pirq->nirqs = dev->info->port_nirqs;
2042 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2043 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2044 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2046 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2047 if (pirq->irq_num < 0)
2048 return pirq->irq_num;
2050 return ksz_irq_common_setup(dev, pirq);
2053 static int ksz_setup(struct dsa_switch *ds)
2055 struct ksz_device *dev = ds->priv;
2056 struct dsa_port *dp;
2061 regs = dev->info->regs;
2063 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2064 dev->info->num_vlans, GFP_KERNEL);
2065 if (!dev->vlan_cache)
2068 ret = dev->dev_ops->reset(dev);
2070 dev_err(ds->dev, "failed to reset switch\n");
2074 /* set broadcast storm protection 10% rate */
2075 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
2076 BROADCAST_STORM_RATE,
2077 (BROADCAST_STORM_VALUE *
2078 BROADCAST_STORM_PROT_RATE) / 100);
2080 dev->dev_ops->config_cpu_port(ds);
2082 dev->dev_ops->enable_stp_addr(dev);
2084 ds->num_tx_queues = dev->info->num_tx_queues;
2086 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
2087 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2089 ksz_init_mib_timer(dev);
2091 ds->configure_vlan_while_not_filtering = false;
2093 if (dev->dev_ops->setup) {
2094 ret = dev->dev_ops->setup(ds);
2099 /* Start with learning disabled on standalone user ports, and enabled
2100 * on the CPU port. In lack of other finer mechanisms, learning on the
2101 * CPU port will avoid flooding bridge local addresses on the network
2104 p = &dev->ports[dev->cpu_port];
2108 ret = ksz_girq_setup(dev);
2112 dsa_switch_for_each_user_port(dp, dev->ds) {
2113 ret = ksz_pirq_setup(dev, dp->index);
2117 ret = ksz_ptp_irq_setup(ds, dp->index);
2123 ret = ksz_ptp_clock_register(ds);
2125 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2129 ret = ksz_mdio_register(dev);
2131 dev_err(dev->dev, "failed to register the mdio");
2132 goto out_ptp_clock_unregister;
2136 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
2137 SW_START, SW_START);
2141 out_ptp_clock_unregister:
2142 ksz_ptp_clock_unregister(ds);
2145 dsa_switch_for_each_user_port(dp, dev->ds)
2146 ksz_ptp_irq_free(ds, dp->index);
2149 dsa_switch_for_each_user_port(dp, dev->ds)
2150 ksz_irq_free(&dev->ports[dp->index].pirq);
2153 ksz_irq_free(&dev->girq);
2158 static void ksz_teardown(struct dsa_switch *ds)
2160 struct ksz_device *dev = ds->priv;
2161 struct dsa_port *dp;
2163 ksz_ptp_clock_unregister(ds);
2166 dsa_switch_for_each_user_port(dp, dev->ds) {
2167 ksz_ptp_irq_free(ds, dp->index);
2169 ksz_irq_free(&dev->ports[dp->index].pirq);
2172 ksz_irq_free(&dev->girq);
2175 if (dev->dev_ops->teardown)
2176 dev->dev_ops->teardown(ds);
2179 static void port_r_cnt(struct ksz_device *dev, int port)
2181 struct ksz_port_mib *mib = &dev->ports[port].mib;
2184 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2185 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2186 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2187 &mib->counters[mib->cnt_ptr]);
2191 /* last one in storage */
2192 dropped = &mib->counters[dev->info->mib_cnt];
2194 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2195 while (mib->cnt_ptr < dev->info->mib_cnt) {
2196 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2197 dropped, &mib->counters[mib->cnt_ptr]);
2203 static void ksz_mib_read_work(struct work_struct *work)
2205 struct ksz_device *dev = container_of(work, struct ksz_device,
2207 struct ksz_port_mib *mib;
2211 for (i = 0; i < dev->info->port_cnt; i++) {
2212 if (dsa_is_unused_port(dev->ds, i))
2217 mutex_lock(&mib->cnt_mutex);
2219 /* Only read MIB counters when the port is told to do.
2220 * If not, read only dropped counters when link is not up.
2223 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2225 if (!netif_carrier_ok(dp->slave))
2226 mib->cnt_ptr = dev->info->reg_mib_cnt;
2231 if (dev->dev_ops->r_mib_stat64)
2232 dev->dev_ops->r_mib_stat64(dev, i);
2234 mutex_unlock(&mib->cnt_mutex);
2237 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2240 void ksz_init_mib_timer(struct ksz_device *dev)
2244 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2246 for (i = 0; i < dev->info->port_cnt; i++) {
2247 struct ksz_port_mib *mib = &dev->ports[i].mib;
2249 dev->dev_ops->port_init_cnt(dev, i);
2252 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2256 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2258 struct ksz_device *dev = ds->priv;
2262 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2269 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2271 struct ksz_device *dev = ds->priv;
2274 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2281 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2283 struct ksz_device *dev = ds->priv;
2285 if (dev->chip_id == KSZ8830_CHIP_ID) {
2286 /* Silicon Errata Sheet (DS80000830A):
2287 * Port 1 does not work with LinkMD Cable-Testing.
2288 * Port 1 does not respond to received PAUSE control frames.
2291 return MICREL_KSZ8_P1_ERRATA;
2297 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2298 unsigned int mode, phy_interface_t interface)
2300 struct ksz_device *dev = ds->priv;
2301 struct ksz_port *p = &dev->ports[port];
2303 /* Read all MIB counters when the link is going down. */
2306 if (dev->mib_read_interval)
2307 schedule_delayed_work(&dev->mib_read, 0);
2310 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2312 struct ksz_device *dev = ds->priv;
2314 if (sset != ETH_SS_STATS)
2317 return dev->info->mib_cnt;
2320 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2323 const struct dsa_port *dp = dsa_to_port(ds, port);
2324 struct ksz_device *dev = ds->priv;
2325 struct ksz_port_mib *mib;
2327 mib = &dev->ports[port].mib;
2328 mutex_lock(&mib->cnt_mutex);
2330 /* Only read dropped counters if no link. */
2331 if (!netif_carrier_ok(dp->slave))
2332 mib->cnt_ptr = dev->info->reg_mib_cnt;
2333 port_r_cnt(dev, port);
2334 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2335 mutex_unlock(&mib->cnt_mutex);
2338 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2339 struct dsa_bridge bridge,
2340 bool *tx_fwd_offload,
2341 struct netlink_ext_ack *extack)
2343 /* port_stp_state_set() will be called after to put the port in
2344 * appropriate state so there is no need to do anything.
2350 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2351 struct dsa_bridge bridge)
2353 /* port_stp_state_set() will be called after to put the port in
2354 * forwarding state so there is no need to do anything.
2358 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2360 struct ksz_device *dev = ds->priv;
2362 dev->dev_ops->flush_dyn_mac_table(dev, port);
2365 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2367 struct ksz_device *dev = ds->priv;
2369 if (!dev->dev_ops->set_ageing_time)
2372 return dev->dev_ops->set_ageing_time(dev, msecs);
2375 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2376 const unsigned char *addr, u16 vid,
2379 struct ksz_device *dev = ds->priv;
2381 if (!dev->dev_ops->fdb_add)
2384 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2387 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2388 const unsigned char *addr,
2389 u16 vid, struct dsa_db db)
2391 struct ksz_device *dev = ds->priv;
2393 if (!dev->dev_ops->fdb_del)
2396 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2399 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2400 dsa_fdb_dump_cb_t *cb, void *data)
2402 struct ksz_device *dev = ds->priv;
2404 if (!dev->dev_ops->fdb_dump)
2407 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2410 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2411 const struct switchdev_obj_port_mdb *mdb,
2414 struct ksz_device *dev = ds->priv;
2416 if (!dev->dev_ops->mdb_add)
2419 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2422 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2423 const struct switchdev_obj_port_mdb *mdb,
2426 struct ksz_device *dev = ds->priv;
2428 if (!dev->dev_ops->mdb_del)
2431 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2434 static int ksz_enable_port(struct dsa_switch *ds, int port,
2435 struct phy_device *phy)
2437 struct ksz_device *dev = ds->priv;
2439 if (!dsa_is_user_port(ds, port))
2442 /* setup slave port */
2443 dev->dev_ops->port_setup(dev, port, false);
2445 /* port_stp_state_set() will be called after to enable the port so
2446 * there is no need to do anything.
2452 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2454 struct ksz_device *dev = ds->priv;
2459 regs = dev->info->regs;
2461 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2462 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2464 p = &dev->ports[port];
2467 case BR_STATE_DISABLED:
2468 data |= PORT_LEARN_DISABLE;
2470 case BR_STATE_LISTENING:
2471 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2473 case BR_STATE_LEARNING:
2474 data |= PORT_RX_ENABLE;
2476 data |= PORT_LEARN_DISABLE;
2478 case BR_STATE_FORWARDING:
2479 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2481 data |= PORT_LEARN_DISABLE;
2483 case BR_STATE_BLOCKING:
2484 data |= PORT_LEARN_DISABLE;
2487 dev_err(ds->dev, "invalid STP state: %d\n", state);
2491 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2493 p->stp_state = state;
2495 ksz_update_port_member(dev, port);
2498 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2499 struct switchdev_brport_flags flags,
2500 struct netlink_ext_ack *extack)
2502 if (flags.mask & ~BR_LEARNING)
2508 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2509 struct switchdev_brport_flags flags,
2510 struct netlink_ext_ack *extack)
2512 struct ksz_device *dev = ds->priv;
2513 struct ksz_port *p = &dev->ports[port];
2515 if (flags.mask & BR_LEARNING) {
2516 p->learning = !!(flags.val & BR_LEARNING);
2518 /* Make the change take effect immediately */
2519 ksz_port_stp_state_set(ds, port, p->stp_state);
2525 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2527 enum dsa_tag_protocol mp)
2529 struct ksz_device *dev = ds->priv;
2530 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2532 if (dev->chip_id == KSZ8795_CHIP_ID ||
2533 dev->chip_id == KSZ8794_CHIP_ID ||
2534 dev->chip_id == KSZ8765_CHIP_ID)
2535 proto = DSA_TAG_PROTO_KSZ8795;
2537 if (dev->chip_id == KSZ8830_CHIP_ID ||
2538 dev->chip_id == KSZ8563_CHIP_ID ||
2539 dev->chip_id == KSZ9893_CHIP_ID ||
2540 dev->chip_id == KSZ9563_CHIP_ID)
2541 proto = DSA_TAG_PROTO_KSZ9893;
2543 if (dev->chip_id == KSZ9477_CHIP_ID ||
2544 dev->chip_id == KSZ9896_CHIP_ID ||
2545 dev->chip_id == KSZ9897_CHIP_ID ||
2546 dev->chip_id == KSZ9567_CHIP_ID)
2547 proto = DSA_TAG_PROTO_KSZ9477;
2549 if (is_lan937x(dev))
2550 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2555 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2556 enum dsa_tag_protocol proto)
2558 struct ksz_tagger_data *tagger_data;
2560 tagger_data = ksz_tagger_data(ds);
2561 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2566 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2567 bool flag, struct netlink_ext_ack *extack)
2569 struct ksz_device *dev = ds->priv;
2571 if (!dev->dev_ops->vlan_filtering)
2574 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2577 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2578 const struct switchdev_obj_port_vlan *vlan,
2579 struct netlink_ext_ack *extack)
2581 struct ksz_device *dev = ds->priv;
2583 if (!dev->dev_ops->vlan_add)
2586 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2589 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2590 const struct switchdev_obj_port_vlan *vlan)
2592 struct ksz_device *dev = ds->priv;
2594 if (!dev->dev_ops->vlan_del)
2597 return dev->dev_ops->vlan_del(dev, port, vlan);
2600 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2601 struct dsa_mall_mirror_tc_entry *mirror,
2602 bool ingress, struct netlink_ext_ack *extack)
2604 struct ksz_device *dev = ds->priv;
2606 if (!dev->dev_ops->mirror_add)
2609 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2612 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2613 struct dsa_mall_mirror_tc_entry *mirror)
2615 struct ksz_device *dev = ds->priv;
2617 if (dev->dev_ops->mirror_del)
2618 dev->dev_ops->mirror_del(dev, port, mirror);
2621 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2623 struct ksz_device *dev = ds->priv;
2625 if (!dev->dev_ops->change_mtu)
2628 return dev->dev_ops->change_mtu(dev, port, mtu);
2631 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2633 struct ksz_device *dev = ds->priv;
2635 switch (dev->chip_id) {
2636 case KSZ8795_CHIP_ID:
2637 case KSZ8794_CHIP_ID:
2638 case KSZ8765_CHIP_ID:
2639 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2640 case KSZ8830_CHIP_ID:
2641 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2642 case KSZ8563_CHIP_ID:
2643 case KSZ9477_CHIP_ID:
2644 case KSZ9563_CHIP_ID:
2645 case KSZ9567_CHIP_ID:
2646 case KSZ9893_CHIP_ID:
2647 case KSZ9896_CHIP_ID:
2648 case KSZ9897_CHIP_ID:
2649 case LAN9370_CHIP_ID:
2650 case LAN9371_CHIP_ID:
2651 case LAN9372_CHIP_ID:
2652 case LAN9373_CHIP_ID:
2653 case LAN9374_CHIP_ID:
2654 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2660 static void ksz_set_xmii(struct ksz_device *dev, int port,
2661 phy_interface_t interface)
2663 const u8 *bitval = dev->info->xmii_ctrl1;
2664 struct ksz_port *p = &dev->ports[port];
2665 const u16 *regs = dev->info->regs;
2668 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2670 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2671 P_RGMII_ID_EG_ENABLE);
2673 switch (interface) {
2674 case PHY_INTERFACE_MODE_MII:
2675 data8 |= bitval[P_MII_SEL];
2677 case PHY_INTERFACE_MODE_RMII:
2678 data8 |= bitval[P_RMII_SEL];
2680 case PHY_INTERFACE_MODE_GMII:
2681 data8 |= bitval[P_GMII_SEL];
2683 case PHY_INTERFACE_MODE_RGMII:
2684 case PHY_INTERFACE_MODE_RGMII_ID:
2685 case PHY_INTERFACE_MODE_RGMII_TXID:
2686 case PHY_INTERFACE_MODE_RGMII_RXID:
2687 data8 |= bitval[P_RGMII_SEL];
2688 /* On KSZ9893, disable RGMII in-band status support */
2689 if (dev->chip_id == KSZ9893_CHIP_ID ||
2690 dev->chip_id == KSZ8563_CHIP_ID ||
2691 dev->chip_id == KSZ9563_CHIP_ID)
2692 data8 &= ~P_MII_MAC_MODE;
2695 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2696 phy_modes(interface), port);
2700 if (p->rgmii_tx_val)
2701 data8 |= P_RGMII_ID_EG_ENABLE;
2703 if (p->rgmii_rx_val)
2704 data8 |= P_RGMII_ID_IG_ENABLE;
2706 /* Write the updated value */
2707 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2710 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2712 const u8 *bitval = dev->info->xmii_ctrl1;
2713 const u16 *regs = dev->info->regs;
2714 phy_interface_t interface;
2718 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2720 val = FIELD_GET(P_MII_SEL_M, data8);
2722 if (val == bitval[P_MII_SEL]) {
2724 interface = PHY_INTERFACE_MODE_GMII;
2726 interface = PHY_INTERFACE_MODE_MII;
2727 } else if (val == bitval[P_RMII_SEL]) {
2728 interface = PHY_INTERFACE_MODE_RGMII;
2730 interface = PHY_INTERFACE_MODE_RGMII;
2731 if (data8 & P_RGMII_ID_EG_ENABLE)
2732 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2733 if (data8 & P_RGMII_ID_IG_ENABLE) {
2734 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2735 if (data8 & P_RGMII_ID_EG_ENABLE)
2736 interface = PHY_INTERFACE_MODE_RGMII_ID;
2743 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2745 const struct phylink_link_state *state)
2747 struct ksz_device *dev = ds->priv;
2749 if (ksz_is_ksz88x3(dev))
2753 if (dev->info->internal_phy[port])
2756 if (phylink_autoneg_inband(mode)) {
2757 dev_err(dev->dev, "In-band AN not supported!\n");
2761 ksz_set_xmii(dev, port, state->interface);
2763 if (dev->dev_ops->phylink_mac_config)
2764 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2766 if (dev->dev_ops->setup_rgmii_delay)
2767 dev->dev_ops->setup_rgmii_delay(dev, port);
2770 bool ksz_get_gbit(struct ksz_device *dev, int port)
2772 const u8 *bitval = dev->info->xmii_ctrl1;
2773 const u16 *regs = dev->info->regs;
2778 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2780 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2782 if (val == bitval[P_GMII_1GBIT])
2788 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2790 const u8 *bitval = dev->info->xmii_ctrl1;
2791 const u16 *regs = dev->info->regs;
2794 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2796 data8 &= ~P_GMII_1GBIT_M;
2799 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2801 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2803 /* Write the updated value */
2804 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2807 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2809 const u8 *bitval = dev->info->xmii_ctrl0;
2810 const u16 *regs = dev->info->regs;
2813 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2815 data8 &= ~P_MII_100MBIT_M;
2817 if (speed == SPEED_100)
2818 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2820 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2822 /* Write the updated value */
2823 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2826 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2828 if (speed == SPEED_1000)
2829 ksz_set_gbit(dev, port, true);
2831 ksz_set_gbit(dev, port, false);
2833 if (speed == SPEED_100 || speed == SPEED_10)
2834 ksz_set_100_10mbit(dev, port, speed);
2837 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2838 bool tx_pause, bool rx_pause)
2840 const u8 *bitval = dev->info->xmii_ctrl0;
2841 const u32 *masks = dev->info->masks;
2842 const u16 *regs = dev->info->regs;
2846 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2847 masks[P_MII_RX_FLOW_CTRL];
2849 if (duplex == DUPLEX_FULL)
2850 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2852 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2855 val |= masks[P_MII_TX_FLOW_CTRL];
2858 val |= masks[P_MII_RX_FLOW_CTRL];
2860 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2863 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2865 phy_interface_t interface,
2866 struct phy_device *phydev, int speed,
2867 int duplex, bool tx_pause,
2872 p = &dev->ports[port];
2875 if (dev->info->internal_phy[port])
2878 p->phydev.speed = speed;
2880 ksz_port_set_xmii_speed(dev, port, speed);
2882 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
2885 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
2887 phy_interface_t interface,
2888 struct phy_device *phydev, int speed,
2889 int duplex, bool tx_pause, bool rx_pause)
2891 struct ksz_device *dev = ds->priv;
2893 if (dev->dev_ops->phylink_mac_link_up)
2894 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
2895 phydev, speed, duplex,
2896 tx_pause, rx_pause);
2899 static int ksz_switch_detect(struct ksz_device *dev)
2907 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2911 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2912 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2915 case KSZ87_FAMILY_ID:
2916 if (id2 == KSZ87_CHIP_ID_95) {
2919 dev->chip_id = KSZ8795_CHIP_ID;
2921 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
2922 if (val & KSZ8_PORT_FIBER_MODE)
2923 dev->chip_id = KSZ8765_CHIP_ID;
2924 } else if (id2 == KSZ87_CHIP_ID_94) {
2925 dev->chip_id = KSZ8794_CHIP_ID;
2930 case KSZ88_FAMILY_ID:
2931 if (id2 == KSZ88_CHIP_ID_63)
2932 dev->chip_id = KSZ8830_CHIP_ID;
2937 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
2941 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
2945 case KSZ9477_CHIP_ID:
2946 case KSZ9896_CHIP_ID:
2947 case KSZ9897_CHIP_ID:
2948 case KSZ9567_CHIP_ID:
2949 case LAN9370_CHIP_ID:
2950 case LAN9371_CHIP_ID:
2951 case LAN9372_CHIP_ID:
2952 case LAN9373_CHIP_ID:
2953 case LAN9374_CHIP_ID:
2954 dev->chip_id = id32;
2956 case KSZ9893_CHIP_ID:
2957 ret = ksz_read8(dev, REG_CHIP_ID4,
2962 if (id4 == SKU_ID_KSZ8563)
2963 dev->chip_id = KSZ8563_CHIP_ID;
2964 else if (id4 == SKU_ID_KSZ9563)
2965 dev->chip_id = KSZ9563_CHIP_ID;
2967 dev->chip_id = KSZ9893_CHIP_ID;
2972 "unsupported switch detected %x)\n", id32);
2979 static const struct dsa_switch_ops ksz_switch_ops = {
2980 .get_tag_protocol = ksz_get_tag_protocol,
2981 .connect_tag_protocol = ksz_connect_tag_protocol,
2982 .get_phy_flags = ksz_get_phy_flags,
2984 .teardown = ksz_teardown,
2985 .phy_read = ksz_phy_read16,
2986 .phy_write = ksz_phy_write16,
2987 .phylink_get_caps = ksz_phylink_get_caps,
2988 .phylink_mac_config = ksz_phylink_mac_config,
2989 .phylink_mac_link_up = ksz_phylink_mac_link_up,
2990 .phylink_mac_link_down = ksz_mac_link_down,
2991 .port_enable = ksz_enable_port,
2992 .set_ageing_time = ksz_set_ageing_time,
2993 .get_strings = ksz_get_strings,
2994 .get_ethtool_stats = ksz_get_ethtool_stats,
2995 .get_sset_count = ksz_sset_count,
2996 .port_bridge_join = ksz_port_bridge_join,
2997 .port_bridge_leave = ksz_port_bridge_leave,
2998 .port_stp_state_set = ksz_port_stp_state_set,
2999 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3000 .port_bridge_flags = ksz_port_bridge_flags,
3001 .port_fast_age = ksz_port_fast_age,
3002 .port_vlan_filtering = ksz_port_vlan_filtering,
3003 .port_vlan_add = ksz_port_vlan_add,
3004 .port_vlan_del = ksz_port_vlan_del,
3005 .port_fdb_dump = ksz_port_fdb_dump,
3006 .port_fdb_add = ksz_port_fdb_add,
3007 .port_fdb_del = ksz_port_fdb_del,
3008 .port_mdb_add = ksz_port_mdb_add,
3009 .port_mdb_del = ksz_port_mdb_del,
3010 .port_mirror_add = ksz_port_mirror_add,
3011 .port_mirror_del = ksz_port_mirror_del,
3012 .get_stats64 = ksz_get_stats64,
3013 .get_pause_stats = ksz_get_pause_stats,
3014 .port_change_mtu = ksz_change_mtu,
3015 .port_max_mtu = ksz_max_mtu,
3016 .get_ts_info = ksz_get_ts_info,
3017 .port_hwtstamp_get = ksz_hwtstamp_get,
3018 .port_hwtstamp_set = ksz_hwtstamp_set,
3019 .port_txtstamp = ksz_port_txtstamp,
3020 .port_rxtstamp = ksz_port_rxtstamp,
3023 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3025 struct dsa_switch *ds;
3026 struct ksz_device *swdev;
3028 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3033 ds->num_ports = DSA_MAX_PORTS;
3034 ds->ops = &ksz_switch_ops;
3036 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3048 EXPORT_SYMBOL(ksz_switch_alloc);
3050 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3051 struct device_node *port_dn)
3053 phy_interface_t phy_mode = dev->ports[port_num].interface;
3054 int rx_delay = -1, tx_delay = -1;
3056 if (!phy_interface_mode_is_rgmii(phy_mode))
3059 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3060 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3062 if (rx_delay == -1 && tx_delay == -1) {
3064 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3065 "please update device tree to specify \"rx-internal-delay-ps\" and "
3066 "\"tx-internal-delay-ps\"",
3069 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3070 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3073 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3074 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3083 dev->ports[port_num].rgmii_rx_val = rx_delay;
3084 dev->ports[port_num].rgmii_tx_val = tx_delay;
3087 int ksz_switch_register(struct ksz_device *dev)
3089 const struct ksz_chip_data *info;
3090 struct device_node *port, *ports;
3091 phy_interface_t interface;
3092 unsigned int port_num;
3097 dev->chip_id = dev->pdata->chip_id;
3099 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3101 if (IS_ERR(dev->reset_gpio))
3102 return PTR_ERR(dev->reset_gpio);
3104 if (dev->reset_gpio) {
3105 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3106 usleep_range(10000, 12000);
3107 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3111 mutex_init(&dev->dev_mutex);
3112 mutex_init(&dev->regmap_mutex);
3113 mutex_init(&dev->alu_mutex);
3114 mutex_init(&dev->vlan_mutex);
3116 ret = ksz_switch_detect(dev);
3120 info = ksz_lookup_info(dev->chip_id);
3124 /* Update the compatible info with the probed one */
3127 dev_info(dev->dev, "found switch: %s, rev %i\n",
3128 dev->info->dev_name, dev->chip_rev);
3130 ret = ksz_check_device_id(dev);
3134 dev->dev_ops = dev->info->ops;
3136 ret = dev->dev_ops->init(dev);
3140 dev->ports = devm_kzalloc(dev->dev,
3141 dev->info->port_cnt * sizeof(struct ksz_port),
3146 for (i = 0; i < dev->info->port_cnt; i++) {
3147 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3148 mutex_init(&dev->ports[i].mib.cnt_mutex);
3149 dev->ports[i].mib.counters =
3150 devm_kzalloc(dev->dev,
3151 sizeof(u64) * (dev->info->mib_cnt + 1),
3153 if (!dev->ports[i].mib.counters)
3156 dev->ports[i].ksz_dev = dev;
3157 dev->ports[i].num = i;
3160 /* set the real number of ports */
3161 dev->ds->num_ports = dev->info->port_cnt;
3163 /* Host port interface will be self detected, or specifically set in
3166 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3167 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3168 if (dev->dev->of_node) {
3169 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3171 dev->compat_interface = interface;
3172 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3174 ports = of_get_child_by_name(dev->dev->of_node, "ports");
3176 for_each_available_child_of_node(ports, port) {
3177 if (of_property_read_u32(port, "reg",
3180 if (!(dev->port_mask & BIT(port_num))) {
3185 of_get_phy_mode(port,
3186 &dev->ports[port_num].interface);
3188 ksz_parse_rgmii_delay(dev, port_num, port);
3192 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3193 "microchip,synclko-125");
3194 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3195 "microchip,synclko-disable");
3196 if (dev->synclko_125 && dev->synclko_disable) {
3197 dev_err(dev->dev, "inconsistent synclko settings\n");
3202 ret = dsa_register_switch(dev->ds);
3204 dev->dev_ops->exit(dev);
3208 /* Read MIB counters every 30 seconds to avoid overflow. */
3209 dev->mib_read_interval = msecs_to_jiffies(5000);
3211 /* Start the MIB timer. */
3212 schedule_delayed_work(&dev->mib_read, 0);
3216 EXPORT_SYMBOL(ksz_switch_register);
3218 void ksz_switch_remove(struct ksz_device *dev)
3221 if (dev->mib_read_interval) {
3222 dev->mib_read_interval = 0;
3223 cancel_delayed_work_sync(&dev->mib_read);
3226 dev->dev_ops->exit(dev);
3227 dsa_unregister_switch(dev->ds);
3229 if (dev->reset_gpio)
3230 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3233 EXPORT_SYMBOL(ksz_switch_remove);
3235 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3236 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3237 MODULE_LICENSE("GPL");
projects / platform / kernel / linux-starfive.git / blob