1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip switch driver main logic
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_device.h>
23 #include <linux/of_net.h>
24 #include <linux/micrel_phy.h>
26 #include <net/pkt_cls.h>
27 #include <net/switchdev.h>
29 #include "ksz_common.h"
35 #define MIB_COUNTER_NUM 0x20
37 struct ksz_stats_raw {
76 struct ksz88xx_stats_raw {
113 static const struct ksz_mib_names ksz88xx_mib_names[] = {
116 { 0x02, "rx_undersize" },
117 { 0x03, "rx_fragments" },
118 { 0x04, "rx_oversize" },
119 { 0x05, "rx_jabbers" },
120 { 0x06, "rx_symbol_err" },
121 { 0x07, "rx_crc_err" },
122 { 0x08, "rx_align_err" },
123 { 0x09, "rx_mac_ctrl" },
124 { 0x0a, "rx_pause" },
125 { 0x0b, "rx_bcast" },
126 { 0x0c, "rx_mcast" },
127 { 0x0d, "rx_ucast" },
128 { 0x0e, "rx_64_or_less" },
129 { 0x0f, "rx_65_127" },
130 { 0x10, "rx_128_255" },
131 { 0x11, "rx_256_511" },
132 { 0x12, "rx_512_1023" },
133 { 0x13, "rx_1024_1522" },
136 { 0x16, "tx_late_col" },
137 { 0x17, "tx_pause" },
138 { 0x18, "tx_bcast" },
139 { 0x19, "tx_mcast" },
140 { 0x1a, "tx_ucast" },
141 { 0x1b, "tx_deferred" },
142 { 0x1c, "tx_total_col" },
143 { 0x1d, "tx_exc_col" },
144 { 0x1e, "tx_single_col" },
145 { 0x1f, "tx_mult_col" },
146 { 0x100, "rx_discards" },
147 { 0x101, "tx_discards" },
150 static const struct ksz_mib_names ksz9477_mib_names[] = {
152 { 0x01, "rx_undersize" },
153 { 0x02, "rx_fragments" },
154 { 0x03, "rx_oversize" },
155 { 0x04, "rx_jabbers" },
156 { 0x05, "rx_symbol_err" },
157 { 0x06, "rx_crc_err" },
158 { 0x07, "rx_align_err" },
159 { 0x08, "rx_mac_ctrl" },
160 { 0x09, "rx_pause" },
161 { 0x0A, "rx_bcast" },
162 { 0x0B, "rx_mcast" },
163 { 0x0C, "rx_ucast" },
164 { 0x0D, "rx_64_or_less" },
165 { 0x0E, "rx_65_127" },
166 { 0x0F, "rx_128_255" },
167 { 0x10, "rx_256_511" },
168 { 0x11, "rx_512_1023" },
169 { 0x12, "rx_1024_1522" },
170 { 0x13, "rx_1523_2000" },
173 { 0x16, "tx_late_col" },
174 { 0x17, "tx_pause" },
175 { 0x18, "tx_bcast" },
176 { 0x19, "tx_mcast" },
177 { 0x1A, "tx_ucast" },
178 { 0x1B, "tx_deferred" },
179 { 0x1C, "tx_total_col" },
180 { 0x1D, "tx_exc_col" },
181 { 0x1E, "tx_single_col" },
182 { 0x1F, "tx_mult_col" },
183 { 0x80, "rx_total" },
184 { 0x81, "tx_total" },
185 { 0x82, "rx_discards" },
186 { 0x83, "tx_discards" },
189 static const struct ksz_dev_ops ksz8_dev_ops = {
191 .get_port_addr = ksz8_get_port_addr,
192 .cfg_port_member = ksz8_cfg_port_member,
193 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
194 .port_setup = ksz8_port_setup,
197 .r_mib_cnt = ksz8_r_mib_cnt,
198 .r_mib_pkt = ksz8_r_mib_pkt,
199 .r_mib_stat64 = ksz88xx_r_mib_stats64,
200 .freeze_mib = ksz8_freeze_mib,
201 .port_init_cnt = ksz8_port_init_cnt,
202 .fdb_dump = ksz8_fdb_dump,
203 .fdb_add = ksz8_fdb_add,
204 .fdb_del = ksz8_fdb_del,
205 .mdb_add = ksz8_mdb_add,
206 .mdb_del = ksz8_mdb_del,
207 .vlan_filtering = ksz8_port_vlan_filtering,
208 .vlan_add = ksz8_port_vlan_add,
209 .vlan_del = ksz8_port_vlan_del,
210 .mirror_add = ksz8_port_mirror_add,
211 .mirror_del = ksz8_port_mirror_del,
212 .get_caps = ksz8_get_caps,
213 .config_cpu_port = ksz8_config_cpu_port,
214 .enable_stp_addr = ksz8_enable_stp_addr,
215 .reset = ksz8_reset_switch,
216 .init = ksz8_switch_init,
217 .exit = ksz8_switch_exit,
218 .change_mtu = ksz8_change_mtu,
221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
223 phy_interface_t interface,
224 struct phy_device *phydev, int speed,
225 int duplex, bool tx_pause,
228 static const struct ksz_dev_ops ksz9477_dev_ops = {
229 .setup = ksz9477_setup,
230 .get_port_addr = ksz9477_get_port_addr,
231 .cfg_port_member = ksz9477_cfg_port_member,
232 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
233 .port_setup = ksz9477_port_setup,
234 .set_ageing_time = ksz9477_set_ageing_time,
235 .r_phy = ksz9477_r_phy,
236 .w_phy = ksz9477_w_phy,
237 .r_mib_cnt = ksz9477_r_mib_cnt,
238 .r_mib_pkt = ksz9477_r_mib_pkt,
239 .r_mib_stat64 = ksz_r_mib_stats64,
240 .freeze_mib = ksz9477_freeze_mib,
241 .port_init_cnt = ksz9477_port_init_cnt,
242 .vlan_filtering = ksz9477_port_vlan_filtering,
243 .vlan_add = ksz9477_port_vlan_add,
244 .vlan_del = ksz9477_port_vlan_del,
245 .mirror_add = ksz9477_port_mirror_add,
246 .mirror_del = ksz9477_port_mirror_del,
247 .get_caps = ksz9477_get_caps,
248 .fdb_dump = ksz9477_fdb_dump,
249 .fdb_add = ksz9477_fdb_add,
250 .fdb_del = ksz9477_fdb_del,
251 .mdb_add = ksz9477_mdb_add,
252 .mdb_del = ksz9477_mdb_del,
253 .change_mtu = ksz9477_change_mtu,
254 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
255 .config_cpu_port = ksz9477_config_cpu_port,
256 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
257 .enable_stp_addr = ksz9477_enable_stp_addr,
258 .reset = ksz9477_reset_switch,
259 .init = ksz9477_switch_init,
260 .exit = ksz9477_switch_exit,
263 static const struct ksz_dev_ops lan937x_dev_ops = {
264 .setup = lan937x_setup,
265 .teardown = lan937x_teardown,
266 .get_port_addr = ksz9477_get_port_addr,
267 .cfg_port_member = ksz9477_cfg_port_member,
268 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
269 .port_setup = lan937x_port_setup,
270 .set_ageing_time = lan937x_set_ageing_time,
271 .r_phy = lan937x_r_phy,
272 .w_phy = lan937x_w_phy,
273 .r_mib_cnt = ksz9477_r_mib_cnt,
274 .r_mib_pkt = ksz9477_r_mib_pkt,
275 .r_mib_stat64 = ksz_r_mib_stats64,
276 .freeze_mib = ksz9477_freeze_mib,
277 .port_init_cnt = ksz9477_port_init_cnt,
278 .vlan_filtering = ksz9477_port_vlan_filtering,
279 .vlan_add = ksz9477_port_vlan_add,
280 .vlan_del = ksz9477_port_vlan_del,
281 .mirror_add = ksz9477_port_mirror_add,
282 .mirror_del = ksz9477_port_mirror_del,
283 .get_caps = lan937x_phylink_get_caps,
284 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
285 .fdb_dump = ksz9477_fdb_dump,
286 .fdb_add = ksz9477_fdb_add,
287 .fdb_del = ksz9477_fdb_del,
288 .mdb_add = ksz9477_mdb_add,
289 .mdb_del = ksz9477_mdb_del,
290 .change_mtu = lan937x_change_mtu,
291 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
292 .config_cpu_port = lan937x_config_cpu_port,
293 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
294 .enable_stp_addr = ksz9477_enable_stp_addr,
295 .reset = lan937x_reset_switch,
296 .init = lan937x_switch_init,
297 .exit = lan937x_switch_exit,
300 static const u16 ksz8795_regs[] = {
301 [REG_IND_CTRL_0] = 0x6E,
302 [REG_IND_DATA_8] = 0x70,
303 [REG_IND_DATA_CHECK] = 0x72,
304 [REG_IND_DATA_HI] = 0x71,
305 [REG_IND_DATA_LO] = 0x75,
306 [REG_IND_MIB_CHECK] = 0x74,
307 [REG_IND_BYTE] = 0xA0,
308 [P_FORCE_CTRL] = 0x0C,
309 [P_LINK_STATUS] = 0x0E,
310 [P_LOCAL_CTRL] = 0x07,
311 [P_NEG_RESTART_CTRL] = 0x0D,
312 [P_REMOTE_STATUS] = 0x08,
313 [P_SPEED_STATUS] = 0x09,
314 [S_TAIL_TAG_CTRL] = 0x0C,
316 [S_START_CTRL] = 0x01,
317 [S_BROADCAST_CTRL] = 0x06,
318 [S_MULTICAST_CTRL] = 0x04,
319 [P_XMII_CTRL_0] = 0x06,
320 [P_XMII_CTRL_1] = 0x06,
323 static const u32 ksz8795_masks[] = {
324 [PORT_802_1P_REMAPPING] = BIT(7),
325 [SW_TAIL_TAG_ENABLE] = BIT(1),
326 [MIB_COUNTER_OVERFLOW] = BIT(6),
327 [MIB_COUNTER_VALID] = BIT(5),
328 [VLAN_TABLE_FID] = GENMASK(6, 0),
329 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
330 [VLAN_TABLE_VALID] = BIT(12),
331 [STATIC_MAC_TABLE_VALID] = BIT(21),
332 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
334 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
335 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
336 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
337 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
338 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
339 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
340 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
342 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
343 [P_MII_TX_FLOW_CTRL] = BIT(5),
344 [P_MII_RX_FLOW_CTRL] = BIT(5),
347 static const u8 ksz8795_xmii_ctrl0[] = {
350 [P_MII_FULL_DUPLEX] = 0,
351 [P_MII_HALF_DUPLEX] = 1,
354 static const u8 ksz8795_xmii_ctrl1[] = {
360 [P_GMII_NOT_1GBIT] = 0,
363 static const u8 ksz8795_shifts[] = {
364 [VLAN_TABLE_MEMBERSHIP_S] = 7,
366 [STATIC_MAC_FWD_PORTS] = 16,
367 [STATIC_MAC_FID] = 24,
368 [DYNAMIC_MAC_ENTRIES_H] = 3,
369 [DYNAMIC_MAC_ENTRIES] = 29,
370 [DYNAMIC_MAC_FID] = 16,
371 [DYNAMIC_MAC_TIMESTAMP] = 27,
372 [DYNAMIC_MAC_SRC_PORT] = 24,
375 static const u16 ksz8863_regs[] = {
376 [REG_IND_CTRL_0] = 0x79,
377 [REG_IND_DATA_8] = 0x7B,
378 [REG_IND_DATA_CHECK] = 0x7B,
379 [REG_IND_DATA_HI] = 0x7C,
380 [REG_IND_DATA_LO] = 0x80,
381 [REG_IND_MIB_CHECK] = 0x80,
382 [P_FORCE_CTRL] = 0x0C,
383 [P_LINK_STATUS] = 0x0E,
384 [P_LOCAL_CTRL] = 0x0C,
385 [P_NEG_RESTART_CTRL] = 0x0D,
386 [P_REMOTE_STATUS] = 0x0E,
387 [P_SPEED_STATUS] = 0x0F,
388 [S_TAIL_TAG_CTRL] = 0x03,
390 [S_START_CTRL] = 0x01,
391 [S_BROADCAST_CTRL] = 0x06,
392 [S_MULTICAST_CTRL] = 0x04,
395 static const u32 ksz8863_masks[] = {
396 [PORT_802_1P_REMAPPING] = BIT(3),
397 [SW_TAIL_TAG_ENABLE] = BIT(6),
398 [MIB_COUNTER_OVERFLOW] = BIT(7),
399 [MIB_COUNTER_VALID] = BIT(6),
400 [VLAN_TABLE_FID] = GENMASK(15, 12),
401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
402 [VLAN_TABLE_VALID] = BIT(19),
403 [STATIC_MAC_TABLE_VALID] = BIT(19),
404 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
405 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
417 static u8 ksz8863_shifts[] = {
418 [VLAN_TABLE_MEMBERSHIP_S] = 16,
419 [STATIC_MAC_FWD_PORTS] = 16,
420 [STATIC_MAC_FID] = 22,
421 [DYNAMIC_MAC_ENTRIES_H] = 8,
422 [DYNAMIC_MAC_ENTRIES] = 24,
423 [DYNAMIC_MAC_FID] = 16,
424 [DYNAMIC_MAC_TIMESTAMP] = 22,
425 [DYNAMIC_MAC_SRC_PORT] = 20,
428 static const u16 ksz9477_regs[] = {
429 [P_STP_CTRL] = 0x0B04,
430 [S_START_CTRL] = 0x0300,
431 [S_BROADCAST_CTRL] = 0x0332,
432 [S_MULTICAST_CTRL] = 0x0331,
433 [P_XMII_CTRL_0] = 0x0300,
434 [P_XMII_CTRL_1] = 0x0301,
437 static const u32 ksz9477_masks[] = {
438 [ALU_STAT_WRITE] = 0,
440 [P_MII_TX_FLOW_CTRL] = BIT(5),
441 [P_MII_RX_FLOW_CTRL] = BIT(3),
444 static const u8 ksz9477_shifts[] = {
445 [ALU_STAT_INDEX] = 16,
448 static const u8 ksz9477_xmii_ctrl0[] = {
451 [P_MII_FULL_DUPLEX] = 1,
452 [P_MII_HALF_DUPLEX] = 0,
455 static const u8 ksz9477_xmii_ctrl1[] = {
461 [P_GMII_NOT_1GBIT] = 1,
464 static const u32 lan937x_masks[] = {
465 [ALU_STAT_WRITE] = 1,
467 [P_MII_TX_FLOW_CTRL] = BIT(5),
468 [P_MII_RX_FLOW_CTRL] = BIT(3),
471 static const u8 lan937x_shifts[] = {
472 [ALU_STAT_INDEX] = 8,
475 static const struct regmap_range ksz8563_valid_regs[] = {
476 regmap_reg_range(0x0000, 0x0003),
477 regmap_reg_range(0x0006, 0x0006),
478 regmap_reg_range(0x000f, 0x001f),
479 regmap_reg_range(0x0100, 0x0100),
480 regmap_reg_range(0x0104, 0x0107),
481 regmap_reg_range(0x010d, 0x010d),
482 regmap_reg_range(0x0110, 0x0113),
483 regmap_reg_range(0x0120, 0x012b),
484 regmap_reg_range(0x0201, 0x0201),
485 regmap_reg_range(0x0210, 0x0213),
486 regmap_reg_range(0x0300, 0x0300),
487 regmap_reg_range(0x0302, 0x031b),
488 regmap_reg_range(0x0320, 0x032b),
489 regmap_reg_range(0x0330, 0x0336),
490 regmap_reg_range(0x0338, 0x033e),
491 regmap_reg_range(0x0340, 0x035f),
492 regmap_reg_range(0x0370, 0x0370),
493 regmap_reg_range(0x0378, 0x0378),
494 regmap_reg_range(0x037c, 0x037d),
495 regmap_reg_range(0x0390, 0x0393),
496 regmap_reg_range(0x0400, 0x040e),
497 regmap_reg_range(0x0410, 0x042f),
498 regmap_reg_range(0x0500, 0x0519),
499 regmap_reg_range(0x0520, 0x054b),
500 regmap_reg_range(0x0550, 0x05b3),
503 regmap_reg_range(0x1000, 0x1001),
504 regmap_reg_range(0x1004, 0x100b),
505 regmap_reg_range(0x1013, 0x1013),
506 regmap_reg_range(0x1017, 0x1017),
507 regmap_reg_range(0x101b, 0x101b),
508 regmap_reg_range(0x101f, 0x1021),
509 regmap_reg_range(0x1030, 0x1030),
510 regmap_reg_range(0x1100, 0x1111),
511 regmap_reg_range(0x111a, 0x111d),
512 regmap_reg_range(0x1122, 0x1127),
513 regmap_reg_range(0x112a, 0x112b),
514 regmap_reg_range(0x1136, 0x1139),
515 regmap_reg_range(0x113e, 0x113f),
516 regmap_reg_range(0x1400, 0x1401),
517 regmap_reg_range(0x1403, 0x1403),
518 regmap_reg_range(0x1410, 0x1417),
519 regmap_reg_range(0x1420, 0x1423),
520 regmap_reg_range(0x1500, 0x1507),
521 regmap_reg_range(0x1600, 0x1612),
522 regmap_reg_range(0x1800, 0x180f),
523 regmap_reg_range(0x1900, 0x1907),
524 regmap_reg_range(0x1914, 0x191b),
525 regmap_reg_range(0x1a00, 0x1a03),
526 regmap_reg_range(0x1a04, 0x1a08),
527 regmap_reg_range(0x1b00, 0x1b01),
528 regmap_reg_range(0x1b04, 0x1b04),
529 regmap_reg_range(0x1c00, 0x1c05),
530 regmap_reg_range(0x1c08, 0x1c1b),
533 regmap_reg_range(0x2000, 0x2001),
534 regmap_reg_range(0x2004, 0x200b),
535 regmap_reg_range(0x2013, 0x2013),
536 regmap_reg_range(0x2017, 0x2017),
537 regmap_reg_range(0x201b, 0x201b),
538 regmap_reg_range(0x201f, 0x2021),
539 regmap_reg_range(0x2030, 0x2030),
540 regmap_reg_range(0x2100, 0x2111),
541 regmap_reg_range(0x211a, 0x211d),
542 regmap_reg_range(0x2122, 0x2127),
543 regmap_reg_range(0x212a, 0x212b),
544 regmap_reg_range(0x2136, 0x2139),
545 regmap_reg_range(0x213e, 0x213f),
546 regmap_reg_range(0x2400, 0x2401),
547 regmap_reg_range(0x2403, 0x2403),
548 regmap_reg_range(0x2410, 0x2417),
549 regmap_reg_range(0x2420, 0x2423),
550 regmap_reg_range(0x2500, 0x2507),
551 regmap_reg_range(0x2600, 0x2612),
552 regmap_reg_range(0x2800, 0x280f),
553 regmap_reg_range(0x2900, 0x2907),
554 regmap_reg_range(0x2914, 0x291b),
555 regmap_reg_range(0x2a00, 0x2a03),
556 regmap_reg_range(0x2a04, 0x2a08),
557 regmap_reg_range(0x2b00, 0x2b01),
558 regmap_reg_range(0x2b04, 0x2b04),
559 regmap_reg_range(0x2c00, 0x2c05),
560 regmap_reg_range(0x2c08, 0x2c1b),
563 regmap_reg_range(0x3000, 0x3001),
564 regmap_reg_range(0x3004, 0x300b),
565 regmap_reg_range(0x3013, 0x3013),
566 regmap_reg_range(0x3017, 0x3017),
567 regmap_reg_range(0x301b, 0x301b),
568 regmap_reg_range(0x301f, 0x3021),
569 regmap_reg_range(0x3030, 0x3030),
570 regmap_reg_range(0x3300, 0x3301),
571 regmap_reg_range(0x3303, 0x3303),
572 regmap_reg_range(0x3400, 0x3401),
573 regmap_reg_range(0x3403, 0x3403),
574 regmap_reg_range(0x3410, 0x3417),
575 regmap_reg_range(0x3420, 0x3423),
576 regmap_reg_range(0x3500, 0x3507),
577 regmap_reg_range(0x3600, 0x3612),
578 regmap_reg_range(0x3800, 0x380f),
579 regmap_reg_range(0x3900, 0x3907),
580 regmap_reg_range(0x3914, 0x391b),
581 regmap_reg_range(0x3a00, 0x3a03),
582 regmap_reg_range(0x3a04, 0x3a08),
583 regmap_reg_range(0x3b00, 0x3b01),
584 regmap_reg_range(0x3b04, 0x3b04),
585 regmap_reg_range(0x3c00, 0x3c05),
586 regmap_reg_range(0x3c08, 0x3c1b),
589 static const struct regmap_access_table ksz8563_register_set = {
590 .yes_ranges = ksz8563_valid_regs,
591 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
594 static const struct regmap_range ksz9477_valid_regs[] = {
595 regmap_reg_range(0x0000, 0x0003),
596 regmap_reg_range(0x0006, 0x0006),
597 regmap_reg_range(0x0010, 0x001f),
598 regmap_reg_range(0x0100, 0x0100),
599 regmap_reg_range(0x0103, 0x0107),
600 regmap_reg_range(0x010d, 0x010d),
601 regmap_reg_range(0x0110, 0x0113),
602 regmap_reg_range(0x0120, 0x012b),
603 regmap_reg_range(0x0201, 0x0201),
604 regmap_reg_range(0x0210, 0x0213),
605 regmap_reg_range(0x0300, 0x0300),
606 regmap_reg_range(0x0302, 0x031b),
607 regmap_reg_range(0x0320, 0x032b),
608 regmap_reg_range(0x0330, 0x0336),
609 regmap_reg_range(0x0338, 0x033b),
610 regmap_reg_range(0x033e, 0x033e),
611 regmap_reg_range(0x0340, 0x035f),
612 regmap_reg_range(0x0370, 0x0370),
613 regmap_reg_range(0x0378, 0x0378),
614 regmap_reg_range(0x037c, 0x037d),
615 regmap_reg_range(0x0390, 0x0393),
616 regmap_reg_range(0x0400, 0x040e),
617 regmap_reg_range(0x0410, 0x042f),
618 regmap_reg_range(0x0444, 0x044b),
619 regmap_reg_range(0x0450, 0x046f),
620 regmap_reg_range(0x0500, 0x0519),
621 regmap_reg_range(0x0520, 0x054b),
622 regmap_reg_range(0x0550, 0x05b3),
623 regmap_reg_range(0x0604, 0x060b),
624 regmap_reg_range(0x0610, 0x0612),
625 regmap_reg_range(0x0614, 0x062c),
626 regmap_reg_range(0x0640, 0x0645),
627 regmap_reg_range(0x0648, 0x064d),
630 regmap_reg_range(0x1000, 0x1001),
631 regmap_reg_range(0x1013, 0x1013),
632 regmap_reg_range(0x1017, 0x1017),
633 regmap_reg_range(0x101b, 0x101b),
634 regmap_reg_range(0x101f, 0x1020),
635 regmap_reg_range(0x1030, 0x1030),
636 regmap_reg_range(0x1100, 0x1115),
637 regmap_reg_range(0x111a, 0x111f),
638 regmap_reg_range(0x1122, 0x1127),
639 regmap_reg_range(0x112a, 0x112b),
640 regmap_reg_range(0x1136, 0x1139),
641 regmap_reg_range(0x113e, 0x113f),
642 regmap_reg_range(0x1400, 0x1401),
643 regmap_reg_range(0x1403, 0x1403),
644 regmap_reg_range(0x1410, 0x1417),
645 regmap_reg_range(0x1420, 0x1423),
646 regmap_reg_range(0x1500, 0x1507),
647 regmap_reg_range(0x1600, 0x1613),
648 regmap_reg_range(0x1800, 0x180f),
649 regmap_reg_range(0x1820, 0x1827),
650 regmap_reg_range(0x1830, 0x1837),
651 regmap_reg_range(0x1840, 0x184b),
652 regmap_reg_range(0x1900, 0x1907),
653 regmap_reg_range(0x1914, 0x191b),
654 regmap_reg_range(0x1920, 0x1920),
655 regmap_reg_range(0x1923, 0x1927),
656 regmap_reg_range(0x1a00, 0x1a03),
657 regmap_reg_range(0x1a04, 0x1a07),
658 regmap_reg_range(0x1b00, 0x1b01),
659 regmap_reg_range(0x1b04, 0x1b04),
660 regmap_reg_range(0x1c00, 0x1c05),
661 regmap_reg_range(0x1c08, 0x1c1b),
664 regmap_reg_range(0x2000, 0x2001),
665 regmap_reg_range(0x2013, 0x2013),
666 regmap_reg_range(0x2017, 0x2017),
667 regmap_reg_range(0x201b, 0x201b),
668 regmap_reg_range(0x201f, 0x2020),
669 regmap_reg_range(0x2030, 0x2030),
670 regmap_reg_range(0x2100, 0x2115),
671 regmap_reg_range(0x211a, 0x211f),
672 regmap_reg_range(0x2122, 0x2127),
673 regmap_reg_range(0x212a, 0x212b),
674 regmap_reg_range(0x2136, 0x2139),
675 regmap_reg_range(0x213e, 0x213f),
676 regmap_reg_range(0x2400, 0x2401),
677 regmap_reg_range(0x2403, 0x2403),
678 regmap_reg_range(0x2410, 0x2417),
679 regmap_reg_range(0x2420, 0x2423),
680 regmap_reg_range(0x2500, 0x2507),
681 regmap_reg_range(0x2600, 0x2613),
682 regmap_reg_range(0x2800, 0x280f),
683 regmap_reg_range(0x2820, 0x2827),
684 regmap_reg_range(0x2830, 0x2837),
685 regmap_reg_range(0x2840, 0x284b),
686 regmap_reg_range(0x2900, 0x2907),
687 regmap_reg_range(0x2914, 0x291b),
688 regmap_reg_range(0x2920, 0x2920),
689 regmap_reg_range(0x2923, 0x2927),
690 regmap_reg_range(0x2a00, 0x2a03),
691 regmap_reg_range(0x2a04, 0x2a07),
692 regmap_reg_range(0x2b00, 0x2b01),
693 regmap_reg_range(0x2b04, 0x2b04),
694 regmap_reg_range(0x2c00, 0x2c05),
695 regmap_reg_range(0x2c08, 0x2c1b),
698 regmap_reg_range(0x3000, 0x3001),
699 regmap_reg_range(0x3013, 0x3013),
700 regmap_reg_range(0x3017, 0x3017),
701 regmap_reg_range(0x301b, 0x301b),
702 regmap_reg_range(0x301f, 0x3020),
703 regmap_reg_range(0x3030, 0x3030),
704 regmap_reg_range(0x3100, 0x3115),
705 regmap_reg_range(0x311a, 0x311f),
706 regmap_reg_range(0x3122, 0x3127),
707 regmap_reg_range(0x312a, 0x312b),
708 regmap_reg_range(0x3136, 0x3139),
709 regmap_reg_range(0x313e, 0x313f),
710 regmap_reg_range(0x3400, 0x3401),
711 regmap_reg_range(0x3403, 0x3403),
712 regmap_reg_range(0x3410, 0x3417),
713 regmap_reg_range(0x3420, 0x3423),
714 regmap_reg_range(0x3500, 0x3507),
715 regmap_reg_range(0x3600, 0x3613),
716 regmap_reg_range(0x3800, 0x380f),
717 regmap_reg_range(0x3820, 0x3827),
718 regmap_reg_range(0x3830, 0x3837),
719 regmap_reg_range(0x3840, 0x384b),
720 regmap_reg_range(0x3900, 0x3907),
721 regmap_reg_range(0x3914, 0x391b),
722 regmap_reg_range(0x3920, 0x3920),
723 regmap_reg_range(0x3923, 0x3927),
724 regmap_reg_range(0x3a00, 0x3a03),
725 regmap_reg_range(0x3a04, 0x3a07),
726 regmap_reg_range(0x3b00, 0x3b01),
727 regmap_reg_range(0x3b04, 0x3b04),
728 regmap_reg_range(0x3c00, 0x3c05),
729 regmap_reg_range(0x3c08, 0x3c1b),
732 regmap_reg_range(0x4000, 0x4001),
733 regmap_reg_range(0x4013, 0x4013),
734 regmap_reg_range(0x4017, 0x4017),
735 regmap_reg_range(0x401b, 0x401b),
736 regmap_reg_range(0x401f, 0x4020),
737 regmap_reg_range(0x4030, 0x4030),
738 regmap_reg_range(0x4100, 0x4115),
739 regmap_reg_range(0x411a, 0x411f),
740 regmap_reg_range(0x4122, 0x4127),
741 regmap_reg_range(0x412a, 0x412b),
742 regmap_reg_range(0x4136, 0x4139),
743 regmap_reg_range(0x413e, 0x413f),
744 regmap_reg_range(0x4400, 0x4401),
745 regmap_reg_range(0x4403, 0x4403),
746 regmap_reg_range(0x4410, 0x4417),
747 regmap_reg_range(0x4420, 0x4423),
748 regmap_reg_range(0x4500, 0x4507),
749 regmap_reg_range(0x4600, 0x4613),
750 regmap_reg_range(0x4800, 0x480f),
751 regmap_reg_range(0x4820, 0x4827),
752 regmap_reg_range(0x4830, 0x4837),
753 regmap_reg_range(0x4840, 0x484b),
754 regmap_reg_range(0x4900, 0x4907),
755 regmap_reg_range(0x4914, 0x491b),
756 regmap_reg_range(0x4920, 0x4920),
757 regmap_reg_range(0x4923, 0x4927),
758 regmap_reg_range(0x4a00, 0x4a03),
759 regmap_reg_range(0x4a04, 0x4a07),
760 regmap_reg_range(0x4b00, 0x4b01),
761 regmap_reg_range(0x4b04, 0x4b04),
762 regmap_reg_range(0x4c00, 0x4c05),
763 regmap_reg_range(0x4c08, 0x4c1b),
766 regmap_reg_range(0x5000, 0x5001),
767 regmap_reg_range(0x5013, 0x5013),
768 regmap_reg_range(0x5017, 0x5017),
769 regmap_reg_range(0x501b, 0x501b),
770 regmap_reg_range(0x501f, 0x5020),
771 regmap_reg_range(0x5030, 0x5030),
772 regmap_reg_range(0x5100, 0x5115),
773 regmap_reg_range(0x511a, 0x511f),
774 regmap_reg_range(0x5122, 0x5127),
775 regmap_reg_range(0x512a, 0x512b),
776 regmap_reg_range(0x5136, 0x5139),
777 regmap_reg_range(0x513e, 0x513f),
778 regmap_reg_range(0x5400, 0x5401),
779 regmap_reg_range(0x5403, 0x5403),
780 regmap_reg_range(0x5410, 0x5417),
781 regmap_reg_range(0x5420, 0x5423),
782 regmap_reg_range(0x5500, 0x5507),
783 regmap_reg_range(0x5600, 0x5613),
784 regmap_reg_range(0x5800, 0x580f),
785 regmap_reg_range(0x5820, 0x5827),
786 regmap_reg_range(0x5830, 0x5837),
787 regmap_reg_range(0x5840, 0x584b),
788 regmap_reg_range(0x5900, 0x5907),
789 regmap_reg_range(0x5914, 0x591b),
790 regmap_reg_range(0x5920, 0x5920),
791 regmap_reg_range(0x5923, 0x5927),
792 regmap_reg_range(0x5a00, 0x5a03),
793 regmap_reg_range(0x5a04, 0x5a07),
794 regmap_reg_range(0x5b00, 0x5b01),
795 regmap_reg_range(0x5b04, 0x5b04),
796 regmap_reg_range(0x5c00, 0x5c05),
797 regmap_reg_range(0x5c08, 0x5c1b),
800 regmap_reg_range(0x6000, 0x6001),
801 regmap_reg_range(0x6013, 0x6013),
802 regmap_reg_range(0x6017, 0x6017),
803 regmap_reg_range(0x601b, 0x601b),
804 regmap_reg_range(0x601f, 0x6020),
805 regmap_reg_range(0x6030, 0x6030),
806 regmap_reg_range(0x6300, 0x6301),
807 regmap_reg_range(0x6400, 0x6401),
808 regmap_reg_range(0x6403, 0x6403),
809 regmap_reg_range(0x6410, 0x6417),
810 regmap_reg_range(0x6420, 0x6423),
811 regmap_reg_range(0x6500, 0x6507),
812 regmap_reg_range(0x6600, 0x6613),
813 regmap_reg_range(0x6800, 0x680f),
814 regmap_reg_range(0x6820, 0x6827),
815 regmap_reg_range(0x6830, 0x6837),
816 regmap_reg_range(0x6840, 0x684b),
817 regmap_reg_range(0x6900, 0x6907),
818 regmap_reg_range(0x6914, 0x691b),
819 regmap_reg_range(0x6920, 0x6920),
820 regmap_reg_range(0x6923, 0x6927),
821 regmap_reg_range(0x6a00, 0x6a03),
822 regmap_reg_range(0x6a04, 0x6a07),
823 regmap_reg_range(0x6b00, 0x6b01),
824 regmap_reg_range(0x6b04, 0x6b04),
825 regmap_reg_range(0x6c00, 0x6c05),
826 regmap_reg_range(0x6c08, 0x6c1b),
829 regmap_reg_range(0x7000, 0x7001),
830 regmap_reg_range(0x7013, 0x7013),
831 regmap_reg_range(0x7017, 0x7017),
832 regmap_reg_range(0x701b, 0x701b),
833 regmap_reg_range(0x701f, 0x7020),
834 regmap_reg_range(0x7030, 0x7030),
835 regmap_reg_range(0x7200, 0x7203),
836 regmap_reg_range(0x7206, 0x7207),
837 regmap_reg_range(0x7300, 0x7301),
838 regmap_reg_range(0x7400, 0x7401),
839 regmap_reg_range(0x7403, 0x7403),
840 regmap_reg_range(0x7410, 0x7417),
841 regmap_reg_range(0x7420, 0x7423),
842 regmap_reg_range(0x7500, 0x7507),
843 regmap_reg_range(0x7600, 0x7613),
844 regmap_reg_range(0x7800, 0x780f),
845 regmap_reg_range(0x7820, 0x7827),
846 regmap_reg_range(0x7830, 0x7837),
847 regmap_reg_range(0x7840, 0x784b),
848 regmap_reg_range(0x7900, 0x7907),
849 regmap_reg_range(0x7914, 0x791b),
850 regmap_reg_range(0x7920, 0x7920),
851 regmap_reg_range(0x7923, 0x7927),
852 regmap_reg_range(0x7a00, 0x7a03),
853 regmap_reg_range(0x7a04, 0x7a07),
854 regmap_reg_range(0x7b00, 0x7b01),
855 regmap_reg_range(0x7b04, 0x7b04),
856 regmap_reg_range(0x7c00, 0x7c05),
857 regmap_reg_range(0x7c08, 0x7c1b),
860 static const struct regmap_access_table ksz9477_register_set = {
861 .yes_ranges = ksz9477_valid_regs,
862 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
865 static const struct regmap_range ksz9896_valid_regs[] = {
866 regmap_reg_range(0x0000, 0x0003),
867 regmap_reg_range(0x0006, 0x0006),
868 regmap_reg_range(0x0010, 0x001f),
869 regmap_reg_range(0x0100, 0x0100),
870 regmap_reg_range(0x0103, 0x0107),
871 regmap_reg_range(0x010d, 0x010d),
872 regmap_reg_range(0x0110, 0x0113),
873 regmap_reg_range(0x0120, 0x0127),
874 regmap_reg_range(0x0201, 0x0201),
875 regmap_reg_range(0x0210, 0x0213),
876 regmap_reg_range(0x0300, 0x0300),
877 regmap_reg_range(0x0302, 0x030b),
878 regmap_reg_range(0x0310, 0x031b),
879 regmap_reg_range(0x0320, 0x032b),
880 regmap_reg_range(0x0330, 0x0336),
881 regmap_reg_range(0x0338, 0x033b),
882 regmap_reg_range(0x033e, 0x033e),
883 regmap_reg_range(0x0340, 0x035f),
884 regmap_reg_range(0x0370, 0x0370),
885 regmap_reg_range(0x0378, 0x0378),
886 regmap_reg_range(0x037c, 0x037d),
887 regmap_reg_range(0x0390, 0x0393),
888 regmap_reg_range(0x0400, 0x040e),
889 regmap_reg_range(0x0410, 0x042f),
892 regmap_reg_range(0x1000, 0x1001),
893 regmap_reg_range(0x1013, 0x1013),
894 regmap_reg_range(0x1017, 0x1017),
895 regmap_reg_range(0x101b, 0x101b),
896 regmap_reg_range(0x101f, 0x1020),
897 regmap_reg_range(0x1030, 0x1030),
898 regmap_reg_range(0x1100, 0x1115),
899 regmap_reg_range(0x111a, 0x111f),
900 regmap_reg_range(0x1122, 0x1127),
901 regmap_reg_range(0x112a, 0x112b),
902 regmap_reg_range(0x1136, 0x1139),
903 regmap_reg_range(0x113e, 0x113f),
904 regmap_reg_range(0x1400, 0x1401),
905 regmap_reg_range(0x1403, 0x1403),
906 regmap_reg_range(0x1410, 0x1417),
907 regmap_reg_range(0x1420, 0x1423),
908 regmap_reg_range(0x1500, 0x1507),
909 regmap_reg_range(0x1600, 0x1612),
910 regmap_reg_range(0x1800, 0x180f),
911 regmap_reg_range(0x1820, 0x1827),
912 regmap_reg_range(0x1830, 0x1837),
913 regmap_reg_range(0x1840, 0x184b),
914 regmap_reg_range(0x1900, 0x1907),
915 regmap_reg_range(0x1914, 0x1915),
916 regmap_reg_range(0x1a00, 0x1a03),
917 regmap_reg_range(0x1a04, 0x1a07),
918 regmap_reg_range(0x1b00, 0x1b01),
919 regmap_reg_range(0x1b04, 0x1b04),
922 regmap_reg_range(0x2000, 0x2001),
923 regmap_reg_range(0x2013, 0x2013),
924 regmap_reg_range(0x2017, 0x2017),
925 regmap_reg_range(0x201b, 0x201b),
926 regmap_reg_range(0x201f, 0x2020),
927 regmap_reg_range(0x2030, 0x2030),
928 regmap_reg_range(0x2100, 0x2115),
929 regmap_reg_range(0x211a, 0x211f),
930 regmap_reg_range(0x2122, 0x2127),
931 regmap_reg_range(0x212a, 0x212b),
932 regmap_reg_range(0x2136, 0x2139),
933 regmap_reg_range(0x213e, 0x213f),
934 regmap_reg_range(0x2400, 0x2401),
935 regmap_reg_range(0x2403, 0x2403),
936 regmap_reg_range(0x2410, 0x2417),
937 regmap_reg_range(0x2420, 0x2423),
938 regmap_reg_range(0x2500, 0x2507),
939 regmap_reg_range(0x2600, 0x2612),
940 regmap_reg_range(0x2800, 0x280f),
941 regmap_reg_range(0x2820, 0x2827),
942 regmap_reg_range(0x2830, 0x2837),
943 regmap_reg_range(0x2840, 0x284b),
944 regmap_reg_range(0x2900, 0x2907),
945 regmap_reg_range(0x2914, 0x2915),
946 regmap_reg_range(0x2a00, 0x2a03),
947 regmap_reg_range(0x2a04, 0x2a07),
948 regmap_reg_range(0x2b00, 0x2b01),
949 regmap_reg_range(0x2b04, 0x2b04),
952 regmap_reg_range(0x3000, 0x3001),
953 regmap_reg_range(0x3013, 0x3013),
954 regmap_reg_range(0x3017, 0x3017),
955 regmap_reg_range(0x301b, 0x301b),
956 regmap_reg_range(0x301f, 0x3020),
957 regmap_reg_range(0x3030, 0x3030),
958 regmap_reg_range(0x3100, 0x3115),
959 regmap_reg_range(0x311a, 0x311f),
960 regmap_reg_range(0x3122, 0x3127),
961 regmap_reg_range(0x312a, 0x312b),
962 regmap_reg_range(0x3136, 0x3139),
963 regmap_reg_range(0x313e, 0x313f),
964 regmap_reg_range(0x3400, 0x3401),
965 regmap_reg_range(0x3403, 0x3403),
966 regmap_reg_range(0x3410, 0x3417),
967 regmap_reg_range(0x3420, 0x3423),
968 regmap_reg_range(0x3500, 0x3507),
969 regmap_reg_range(0x3600, 0x3612),
970 regmap_reg_range(0x3800, 0x380f),
971 regmap_reg_range(0x3820, 0x3827),
972 regmap_reg_range(0x3830, 0x3837),
973 regmap_reg_range(0x3840, 0x384b),
974 regmap_reg_range(0x3900, 0x3907),
975 regmap_reg_range(0x3914, 0x3915),
976 regmap_reg_range(0x3a00, 0x3a03),
977 regmap_reg_range(0x3a04, 0x3a07),
978 regmap_reg_range(0x3b00, 0x3b01),
979 regmap_reg_range(0x3b04, 0x3b04),
982 regmap_reg_range(0x4000, 0x4001),
983 regmap_reg_range(0x4013, 0x4013),
984 regmap_reg_range(0x4017, 0x4017),
985 regmap_reg_range(0x401b, 0x401b),
986 regmap_reg_range(0x401f, 0x4020),
987 regmap_reg_range(0x4030, 0x4030),
988 regmap_reg_range(0x4100, 0x4115),
989 regmap_reg_range(0x411a, 0x411f),
990 regmap_reg_range(0x4122, 0x4127),
991 regmap_reg_range(0x412a, 0x412b),
992 regmap_reg_range(0x4136, 0x4139),
993 regmap_reg_range(0x413e, 0x413f),
994 regmap_reg_range(0x4400, 0x4401),
995 regmap_reg_range(0x4403, 0x4403),
996 regmap_reg_range(0x4410, 0x4417),
997 regmap_reg_range(0x4420, 0x4423),
998 regmap_reg_range(0x4500, 0x4507),
999 regmap_reg_range(0x4600, 0x4612),
1000 regmap_reg_range(0x4800, 0x480f),
1001 regmap_reg_range(0x4820, 0x4827),
1002 regmap_reg_range(0x4830, 0x4837),
1003 regmap_reg_range(0x4840, 0x484b),
1004 regmap_reg_range(0x4900, 0x4907),
1005 regmap_reg_range(0x4914, 0x4915),
1006 regmap_reg_range(0x4a00, 0x4a03),
1007 regmap_reg_range(0x4a04, 0x4a07),
1008 regmap_reg_range(0x4b00, 0x4b01),
1009 regmap_reg_range(0x4b04, 0x4b04),
1012 regmap_reg_range(0x5000, 0x5001),
1013 regmap_reg_range(0x5013, 0x5013),
1014 regmap_reg_range(0x5017, 0x5017),
1015 regmap_reg_range(0x501b, 0x501b),
1016 regmap_reg_range(0x501f, 0x5020),
1017 regmap_reg_range(0x5030, 0x5030),
1018 regmap_reg_range(0x5100, 0x5115),
1019 regmap_reg_range(0x511a, 0x511f),
1020 regmap_reg_range(0x5122, 0x5127),
1021 regmap_reg_range(0x512a, 0x512b),
1022 regmap_reg_range(0x5136, 0x5139),
1023 regmap_reg_range(0x513e, 0x513f),
1024 regmap_reg_range(0x5400, 0x5401),
1025 regmap_reg_range(0x5403, 0x5403),
1026 regmap_reg_range(0x5410, 0x5417),
1027 regmap_reg_range(0x5420, 0x5423),
1028 regmap_reg_range(0x5500, 0x5507),
1029 regmap_reg_range(0x5600, 0x5612),
1030 regmap_reg_range(0x5800, 0x580f),
1031 regmap_reg_range(0x5820, 0x5827),
1032 regmap_reg_range(0x5830, 0x5837),
1033 regmap_reg_range(0x5840, 0x584b),
1034 regmap_reg_range(0x5900, 0x5907),
1035 regmap_reg_range(0x5914, 0x5915),
1036 regmap_reg_range(0x5a00, 0x5a03),
1037 regmap_reg_range(0x5a04, 0x5a07),
1038 regmap_reg_range(0x5b00, 0x5b01),
1039 regmap_reg_range(0x5b04, 0x5b04),
1042 regmap_reg_range(0x6000, 0x6001),
1043 regmap_reg_range(0x6013, 0x6013),
1044 regmap_reg_range(0x6017, 0x6017),
1045 regmap_reg_range(0x601b, 0x601b),
1046 regmap_reg_range(0x601f, 0x6020),
1047 regmap_reg_range(0x6030, 0x6030),
1048 regmap_reg_range(0x6100, 0x6115),
1049 regmap_reg_range(0x611a, 0x611f),
1050 regmap_reg_range(0x6122, 0x6127),
1051 regmap_reg_range(0x612a, 0x612b),
1052 regmap_reg_range(0x6136, 0x6139),
1053 regmap_reg_range(0x613e, 0x613f),
1054 regmap_reg_range(0x6300, 0x6301),
1055 regmap_reg_range(0x6400, 0x6401),
1056 regmap_reg_range(0x6403, 0x6403),
1057 regmap_reg_range(0x6410, 0x6417),
1058 regmap_reg_range(0x6420, 0x6423),
1059 regmap_reg_range(0x6500, 0x6507),
1060 regmap_reg_range(0x6600, 0x6612),
1061 regmap_reg_range(0x6800, 0x680f),
1062 regmap_reg_range(0x6820, 0x6827),
1063 regmap_reg_range(0x6830, 0x6837),
1064 regmap_reg_range(0x6840, 0x684b),
1065 regmap_reg_range(0x6900, 0x6907),
1066 regmap_reg_range(0x6914, 0x6915),
1067 regmap_reg_range(0x6a00, 0x6a03),
1068 regmap_reg_range(0x6a04, 0x6a07),
1069 regmap_reg_range(0x6b00, 0x6b01),
1070 regmap_reg_range(0x6b04, 0x6b04),
1073 static const struct regmap_access_table ksz9896_register_set = {
1074 .yes_ranges = ksz9896_valid_regs,
1075 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1078 static const struct regmap_range ksz8873_valid_regs[] = {
1079 regmap_reg_range(0x00, 0x01),
1080 /* global control register */
1081 regmap_reg_range(0x02, 0x0f),
1083 /* port registers */
1084 regmap_reg_range(0x10, 0x1d),
1085 regmap_reg_range(0x1e, 0x1f),
1086 regmap_reg_range(0x20, 0x2d),
1087 regmap_reg_range(0x2e, 0x2f),
1088 regmap_reg_range(0x30, 0x39),
1089 regmap_reg_range(0x3f, 0x3f),
1091 /* advanced control registers */
1092 regmap_reg_range(0x60, 0x6f),
1093 regmap_reg_range(0x70, 0x75),
1094 regmap_reg_range(0x76, 0x78),
1095 regmap_reg_range(0x79, 0x7a),
1096 regmap_reg_range(0x7b, 0x83),
1097 regmap_reg_range(0x8e, 0x99),
1098 regmap_reg_range(0x9a, 0xa5),
1099 regmap_reg_range(0xa6, 0xa6),
1100 regmap_reg_range(0xa7, 0xaa),
1101 regmap_reg_range(0xab, 0xae),
1102 regmap_reg_range(0xaf, 0xba),
1103 regmap_reg_range(0xbb, 0xbc),
1104 regmap_reg_range(0xbd, 0xbd),
1105 regmap_reg_range(0xc0, 0xc0),
1106 regmap_reg_range(0xc2, 0xc2),
1107 regmap_reg_range(0xc3, 0xc3),
1108 regmap_reg_range(0xc4, 0xc4),
1109 regmap_reg_range(0xc6, 0xc6),
1112 static const struct regmap_access_table ksz8873_register_set = {
1113 .yes_ranges = ksz8873_valid_regs,
1114 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1117 const struct ksz_chip_data ksz_switch_chips[] = {
1119 .chip_id = KSZ8563_CHIP_ID,
1120 .dev_name = "KSZ8563",
1124 .cpu_ports = 0x07, /* can be configured as cpu port */
1125 .port_cnt = 3, /* total port count */
1128 .tc_cbs_supported = true,
1129 .tc_ets_supported = true,
1130 .ops = &ksz9477_dev_ops,
1131 .mib_names = ksz9477_mib_names,
1132 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1133 .reg_mib_cnt = MIB_COUNTER_NUM,
1134 .regs = ksz9477_regs,
1135 .masks = ksz9477_masks,
1136 .shifts = ksz9477_shifts,
1137 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1138 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1139 .supports_mii = {false, false, true},
1140 .supports_rmii = {false, false, true},
1141 .supports_rgmii = {false, false, true},
1142 .internal_phy = {true, true, false},
1143 .gbit_capable = {false, false, true},
1144 .wr_table = &ksz8563_register_set,
1145 .rd_table = &ksz8563_register_set,
1149 .chip_id = KSZ8795_CHIP_ID,
1150 .dev_name = "KSZ8795",
1154 .cpu_ports = 0x10, /* can be configured as cpu port */
1155 .port_cnt = 5, /* total cpu and user ports */
1157 .ops = &ksz8_dev_ops,
1158 .ksz87xx_eee_link_erratum = true,
1159 .mib_names = ksz9477_mib_names,
1160 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1161 .reg_mib_cnt = MIB_COUNTER_NUM,
1162 .regs = ksz8795_regs,
1163 .masks = ksz8795_masks,
1164 .shifts = ksz8795_shifts,
1165 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1166 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1167 .supports_mii = {false, false, false, false, true},
1168 .supports_rmii = {false, false, false, false, true},
1169 .supports_rgmii = {false, false, false, false, true},
1170 .internal_phy = {true, true, true, true, false},
1176 * KSZ8794 is similar to KSZ8795, except the port map
1177 * contains a gap between external and CPU ports, the
1178 * port map is NOT continuous. The per-port register
1179 * map is shifted accordingly too, i.e. registers at
1180 * offset 0x40 are NOT used on KSZ8794 and they ARE
1181 * used on KSZ8795 for external port 3.
1186 * port_cnt is configured as 5, even though it is 4
1188 .chip_id = KSZ8794_CHIP_ID,
1189 .dev_name = "KSZ8794",
1193 .cpu_ports = 0x10, /* can be configured as cpu port */
1194 .port_cnt = 5, /* total cpu and user ports */
1196 .ops = &ksz8_dev_ops,
1197 .ksz87xx_eee_link_erratum = true,
1198 .mib_names = ksz9477_mib_names,
1199 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1200 .reg_mib_cnt = MIB_COUNTER_NUM,
1201 .regs = ksz8795_regs,
1202 .masks = ksz8795_masks,
1203 .shifts = ksz8795_shifts,
1204 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1205 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1206 .supports_mii = {false, false, false, false, true},
1207 .supports_rmii = {false, false, false, false, true},
1208 .supports_rgmii = {false, false, false, false, true},
1209 .internal_phy = {true, true, true, false, false},
1213 .chip_id = KSZ8765_CHIP_ID,
1214 .dev_name = "KSZ8765",
1218 .cpu_ports = 0x10, /* can be configured as cpu port */
1219 .port_cnt = 5, /* total cpu and user ports */
1221 .ops = &ksz8_dev_ops,
1222 .ksz87xx_eee_link_erratum = true,
1223 .mib_names = ksz9477_mib_names,
1224 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1225 .reg_mib_cnt = MIB_COUNTER_NUM,
1226 .regs = ksz8795_regs,
1227 .masks = ksz8795_masks,
1228 .shifts = ksz8795_shifts,
1229 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1230 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1231 .supports_mii = {false, false, false, false, true},
1232 .supports_rmii = {false, false, false, false, true},
1233 .supports_rgmii = {false, false, false, false, true},
1234 .internal_phy = {true, true, true, true, false},
1238 .chip_id = KSZ8830_CHIP_ID,
1239 .dev_name = "KSZ8863/KSZ8873",
1243 .cpu_ports = 0x4, /* can be configured as cpu port */
1246 .ops = &ksz8_dev_ops,
1247 .mib_names = ksz88xx_mib_names,
1248 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1249 .reg_mib_cnt = MIB_COUNTER_NUM,
1250 .regs = ksz8863_regs,
1251 .masks = ksz8863_masks,
1252 .shifts = ksz8863_shifts,
1253 .supports_mii = {false, false, true},
1254 .supports_rmii = {false, false, true},
1255 .internal_phy = {true, true, false},
1256 .wr_table = &ksz8873_register_set,
1257 .rd_table = &ksz8873_register_set,
1261 .chip_id = KSZ9477_CHIP_ID,
1262 .dev_name = "KSZ9477",
1266 .cpu_ports = 0x7F, /* can be configured as cpu port */
1267 .port_cnt = 7, /* total physical port count */
1270 .tc_cbs_supported = true,
1271 .tc_ets_supported = true,
1272 .ops = &ksz9477_dev_ops,
1273 .mib_names = ksz9477_mib_names,
1274 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1275 .reg_mib_cnt = MIB_COUNTER_NUM,
1276 .regs = ksz9477_regs,
1277 .masks = ksz9477_masks,
1278 .shifts = ksz9477_shifts,
1279 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1280 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1281 .supports_mii = {false, false, false, false,
1282 false, true, false},
1283 .supports_rmii = {false, false, false, false,
1284 false, true, false},
1285 .supports_rgmii = {false, false, false, false,
1286 false, true, false},
1287 .internal_phy = {true, true, true, true,
1288 true, false, false},
1289 .gbit_capable = {true, true, true, true, true, true, true},
1290 .wr_table = &ksz9477_register_set,
1291 .rd_table = &ksz9477_register_set,
1295 .chip_id = KSZ9896_CHIP_ID,
1296 .dev_name = "KSZ9896",
1300 .cpu_ports = 0x3F, /* can be configured as cpu port */
1301 .port_cnt = 6, /* total physical port count */
1304 .ops = &ksz9477_dev_ops,
1305 .mib_names = ksz9477_mib_names,
1306 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1307 .reg_mib_cnt = MIB_COUNTER_NUM,
1308 .regs = ksz9477_regs,
1309 .masks = ksz9477_masks,
1310 .shifts = ksz9477_shifts,
1311 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1312 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1313 .supports_mii = {false, false, false, false,
1315 .supports_rmii = {false, false, false, false,
1317 .supports_rgmii = {false, false, false, false,
1319 .internal_phy = {true, true, true, true,
1321 .gbit_capable = {true, true, true, true, true, true},
1322 .wr_table = &ksz9896_register_set,
1323 .rd_table = &ksz9896_register_set,
1327 .chip_id = KSZ9897_CHIP_ID,
1328 .dev_name = "KSZ9897",
1332 .cpu_ports = 0x7F, /* can be configured as cpu port */
1333 .port_cnt = 7, /* total physical port count */
1336 .ops = &ksz9477_dev_ops,
1337 .mib_names = ksz9477_mib_names,
1338 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1339 .reg_mib_cnt = MIB_COUNTER_NUM,
1340 .regs = ksz9477_regs,
1341 .masks = ksz9477_masks,
1342 .shifts = ksz9477_shifts,
1343 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1344 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1345 .supports_mii = {false, false, false, false,
1347 .supports_rmii = {false, false, false, false,
1349 .supports_rgmii = {false, false, false, false,
1351 .internal_phy = {true, true, true, true,
1352 true, false, false},
1353 .gbit_capable = {true, true, true, true, true, true, true},
1357 .chip_id = KSZ9893_CHIP_ID,
1358 .dev_name = "KSZ9893",
1362 .cpu_ports = 0x07, /* can be configured as cpu port */
1363 .port_cnt = 3, /* total port count */
1366 .ops = &ksz9477_dev_ops,
1367 .mib_names = ksz9477_mib_names,
1368 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1369 .reg_mib_cnt = MIB_COUNTER_NUM,
1370 .regs = ksz9477_regs,
1371 .masks = ksz9477_masks,
1372 .shifts = ksz9477_shifts,
1373 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1374 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1375 .supports_mii = {false, false, true},
1376 .supports_rmii = {false, false, true},
1377 .supports_rgmii = {false, false, true},
1378 .internal_phy = {true, true, false},
1379 .gbit_capable = {true, true, true},
1383 .chip_id = KSZ9563_CHIP_ID,
1384 .dev_name = "KSZ9563",
1388 .cpu_ports = 0x07, /* can be configured as cpu port */
1389 .port_cnt = 3, /* total port count */
1392 .tc_cbs_supported = true,
1393 .tc_ets_supported = true,
1394 .ops = &ksz9477_dev_ops,
1395 .mib_names = ksz9477_mib_names,
1396 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1397 .reg_mib_cnt = MIB_COUNTER_NUM,
1398 .regs = ksz9477_regs,
1399 .masks = ksz9477_masks,
1400 .shifts = ksz9477_shifts,
1401 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1402 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1403 .supports_mii = {false, false, true},
1404 .supports_rmii = {false, false, true},
1405 .supports_rgmii = {false, false, true},
1406 .internal_phy = {true, true, false},
1407 .gbit_capable = {true, true, true},
1411 .chip_id = KSZ9567_CHIP_ID,
1412 .dev_name = "KSZ9567",
1416 .cpu_ports = 0x7F, /* can be configured as cpu port */
1417 .port_cnt = 7, /* total physical port count */
1420 .tc_cbs_supported = true,
1421 .tc_ets_supported = true,
1422 .ops = &ksz9477_dev_ops,
1423 .mib_names = ksz9477_mib_names,
1424 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1425 .reg_mib_cnt = MIB_COUNTER_NUM,
1426 .regs = ksz9477_regs,
1427 .masks = ksz9477_masks,
1428 .shifts = ksz9477_shifts,
1429 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1430 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1431 .supports_mii = {false, false, false, false,
1433 .supports_rmii = {false, false, false, false,
1435 .supports_rgmii = {false, false, false, false,
1437 .internal_phy = {true, true, true, true,
1438 true, false, false},
1439 .gbit_capable = {true, true, true, true, true, true, true},
1443 .chip_id = LAN9370_CHIP_ID,
1444 .dev_name = "LAN9370",
1448 .cpu_ports = 0x10, /* can be configured as cpu port */
1449 .port_cnt = 5, /* total physical port count */
1452 .tc_cbs_supported = true,
1453 .tc_ets_supported = true,
1454 .ops = &lan937x_dev_ops,
1455 .mib_names = ksz9477_mib_names,
1456 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1457 .reg_mib_cnt = MIB_COUNTER_NUM,
1458 .regs = ksz9477_regs,
1459 .masks = lan937x_masks,
1460 .shifts = lan937x_shifts,
1461 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1462 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1463 .supports_mii = {false, false, false, false, true},
1464 .supports_rmii = {false, false, false, false, true},
1465 .supports_rgmii = {false, false, false, false, true},
1466 .internal_phy = {true, true, true, true, false},
1470 .chip_id = LAN9371_CHIP_ID,
1471 .dev_name = "LAN9371",
1475 .cpu_ports = 0x30, /* can be configured as cpu port */
1476 .port_cnt = 6, /* total physical port count */
1479 .tc_cbs_supported = true,
1480 .tc_ets_supported = true,
1481 .ops = &lan937x_dev_ops,
1482 .mib_names = ksz9477_mib_names,
1483 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1484 .reg_mib_cnt = MIB_COUNTER_NUM,
1485 .regs = ksz9477_regs,
1486 .masks = lan937x_masks,
1487 .shifts = lan937x_shifts,
1488 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1489 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1490 .supports_mii = {false, false, false, false, true, true},
1491 .supports_rmii = {false, false, false, false, true, true},
1492 .supports_rgmii = {false, false, false, false, true, true},
1493 .internal_phy = {true, true, true, true, false, false},
1497 .chip_id = LAN9372_CHIP_ID,
1498 .dev_name = "LAN9372",
1502 .cpu_ports = 0x30, /* can be configured as cpu port */
1503 .port_cnt = 8, /* total physical port count */
1506 .tc_cbs_supported = true,
1507 .tc_ets_supported = true,
1508 .ops = &lan937x_dev_ops,
1509 .mib_names = ksz9477_mib_names,
1510 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1511 .reg_mib_cnt = MIB_COUNTER_NUM,
1512 .regs = ksz9477_regs,
1513 .masks = lan937x_masks,
1514 .shifts = lan937x_shifts,
1515 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1516 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1517 .supports_mii = {false, false, false, false,
1518 true, true, false, false},
1519 .supports_rmii = {false, false, false, false,
1520 true, true, false, false},
1521 .supports_rgmii = {false, false, false, false,
1522 true, true, false, false},
1523 .internal_phy = {true, true, true, true,
1524 false, false, true, true},
1528 .chip_id = LAN9373_CHIP_ID,
1529 .dev_name = "LAN9373",
1533 .cpu_ports = 0x38, /* can be configured as cpu port */
1534 .port_cnt = 5, /* total physical port count */
1537 .tc_cbs_supported = true,
1538 .tc_ets_supported = true,
1539 .ops = &lan937x_dev_ops,
1540 .mib_names = ksz9477_mib_names,
1541 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1542 .reg_mib_cnt = MIB_COUNTER_NUM,
1543 .regs = ksz9477_regs,
1544 .masks = lan937x_masks,
1545 .shifts = lan937x_shifts,
1546 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1547 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1548 .supports_mii = {false, false, false, false,
1549 true, true, false, false},
1550 .supports_rmii = {false, false, false, false,
1551 true, true, false, false},
1552 .supports_rgmii = {false, false, false, false,
1553 true, true, false, false},
1554 .internal_phy = {true, true, true, false,
1555 false, false, true, true},
1559 .chip_id = LAN9374_CHIP_ID,
1560 .dev_name = "LAN9374",
1564 .cpu_ports = 0x30, /* can be configured as cpu port */
1565 .port_cnt = 8, /* total physical port count */
1568 .tc_cbs_supported = true,
1569 .tc_ets_supported = true,
1570 .ops = &lan937x_dev_ops,
1571 .mib_names = ksz9477_mib_names,
1572 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1573 .reg_mib_cnt = MIB_COUNTER_NUM,
1574 .regs = ksz9477_regs,
1575 .masks = lan937x_masks,
1576 .shifts = lan937x_shifts,
1577 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1578 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1579 .supports_mii = {false, false, false, false,
1580 true, true, false, false},
1581 .supports_rmii = {false, false, false, false,
1582 true, true, false, false},
1583 .supports_rgmii = {false, false, false, false,
1584 true, true, false, false},
1585 .internal_phy = {true, true, true, true,
1586 false, false, true, true},
1589 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1591 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1595 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1596 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1598 if (chip->chip_id == prod_num)
1605 static int ksz_check_device_id(struct ksz_device *dev)
1607 const struct ksz_chip_data *dt_chip_data;
1609 dt_chip_data = of_device_get_match_data(dev->dev);
1611 /* Check for Device Tree and Chip ID */
1612 if (dt_chip_data->chip_id != dev->chip_id) {
1614 "Device tree specifies chip %s but found %s, please fix it!\n",
1615 dt_chip_data->dev_name, dev->info->dev_name);
1622 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1623 struct phylink_config *config)
1625 struct ksz_device *dev = ds->priv;
1627 config->legacy_pre_march2020 = false;
1629 if (dev->info->supports_mii[port])
1630 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1632 if (dev->info->supports_rmii[port])
1633 __set_bit(PHY_INTERFACE_MODE_RMII,
1634 config->supported_interfaces);
1636 if (dev->info->supports_rgmii[port])
1637 phy_interface_set_rgmii(config->supported_interfaces);
1639 if (dev->info->internal_phy[port]) {
1640 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1641 config->supported_interfaces);
1642 /* Compatibility for phylib's default interface type when the
1643 * phy-mode property is absent
1645 __set_bit(PHY_INTERFACE_MODE_GMII,
1646 config->supported_interfaces);
1649 if (dev->dev_ops->get_caps)
1650 dev->dev_ops->get_caps(dev, port, config);
1653 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1655 struct ethtool_pause_stats *pstats;
1656 struct rtnl_link_stats64 *stats;
1657 struct ksz_stats_raw *raw;
1658 struct ksz_port_mib *mib;
1660 mib = &dev->ports[port].mib;
1661 stats = &mib->stats64;
1662 pstats = &mib->pause_stats;
1663 raw = (struct ksz_stats_raw *)mib->counters;
1665 spin_lock(&mib->stats64_lock);
1667 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1669 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1672 /* HW counters are counting bytes + FCS which is not acceptable
1673 * for rtnl_link_stats64 interface
1675 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1676 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1678 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1681 stats->rx_crc_errors = raw->rx_crc_err;
1682 stats->rx_frame_errors = raw->rx_align_err;
1683 stats->rx_dropped = raw->rx_discards;
1684 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1685 stats->rx_frame_errors + stats->rx_dropped;
1687 stats->tx_window_errors = raw->tx_late_col;
1688 stats->tx_fifo_errors = raw->tx_discards;
1689 stats->tx_aborted_errors = raw->tx_exc_col;
1690 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1691 stats->tx_aborted_errors;
1693 stats->multicast = raw->rx_mcast;
1694 stats->collisions = raw->tx_total_col;
1696 pstats->tx_pause_frames = raw->tx_pause;
1697 pstats->rx_pause_frames = raw->rx_pause;
1699 spin_unlock(&mib->stats64_lock);
1702 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1704 struct ethtool_pause_stats *pstats;
1705 struct rtnl_link_stats64 *stats;
1706 struct ksz88xx_stats_raw *raw;
1707 struct ksz_port_mib *mib;
1709 mib = &dev->ports[port].mib;
1710 stats = &mib->stats64;
1711 pstats = &mib->pause_stats;
1712 raw = (struct ksz88xx_stats_raw *)mib->counters;
1714 spin_lock(&mib->stats64_lock);
1716 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1718 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1721 /* HW counters are counting bytes + FCS which is not acceptable
1722 * for rtnl_link_stats64 interface
1724 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1725 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1727 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1730 stats->rx_crc_errors = raw->rx_crc_err;
1731 stats->rx_frame_errors = raw->rx_align_err;
1732 stats->rx_dropped = raw->rx_discards;
1733 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1734 stats->rx_frame_errors + stats->rx_dropped;
1736 stats->tx_window_errors = raw->tx_late_col;
1737 stats->tx_fifo_errors = raw->tx_discards;
1738 stats->tx_aborted_errors = raw->tx_exc_col;
1739 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1740 stats->tx_aborted_errors;
1742 stats->multicast = raw->rx_mcast;
1743 stats->collisions = raw->tx_total_col;
1745 pstats->tx_pause_frames = raw->tx_pause;
1746 pstats->rx_pause_frames = raw->rx_pause;
1748 spin_unlock(&mib->stats64_lock);
1751 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1752 struct rtnl_link_stats64 *s)
1754 struct ksz_device *dev = ds->priv;
1755 struct ksz_port_mib *mib;
1757 mib = &dev->ports[port].mib;
1759 spin_lock(&mib->stats64_lock);
1760 memcpy(s, &mib->stats64, sizeof(*s));
1761 spin_unlock(&mib->stats64_lock);
1764 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1765 struct ethtool_pause_stats *pause_stats)
1767 struct ksz_device *dev = ds->priv;
1768 struct ksz_port_mib *mib;
1770 mib = &dev->ports[port].mib;
1772 spin_lock(&mib->stats64_lock);
1773 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1774 spin_unlock(&mib->stats64_lock);
1777 static void ksz_get_strings(struct dsa_switch *ds, int port,
1778 u32 stringset, uint8_t *buf)
1780 struct ksz_device *dev = ds->priv;
1783 if (stringset != ETH_SS_STATS)
1786 for (i = 0; i < dev->info->mib_cnt; i++) {
1787 memcpy(buf + i * ETH_GSTRING_LEN,
1788 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1792 static void ksz_update_port_member(struct ksz_device *dev, int port)
1794 struct ksz_port *p = &dev->ports[port];
1795 struct dsa_switch *ds = dev->ds;
1796 u8 port_member = 0, cpu_port;
1797 const struct dsa_port *dp;
1800 if (!dsa_is_user_port(ds, port))
1803 dp = dsa_to_port(ds, port);
1804 cpu_port = BIT(dsa_upstream_port(ds, port));
1806 for (i = 0; i < ds->num_ports; i++) {
1807 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1808 struct ksz_port *other_p = &dev->ports[i];
1811 if (!dsa_is_user_port(ds, i))
1815 if (!dsa_port_bridge_same(dp, other_dp))
1817 if (other_p->stp_state != BR_STATE_FORWARDING)
1820 if (p->stp_state == BR_STATE_FORWARDING) {
1822 port_member |= BIT(i);
1825 /* Retain port [i]'s relationship to other ports than [port] */
1826 for (j = 0; j < ds->num_ports; j++) {
1827 const struct dsa_port *third_dp;
1828 struct ksz_port *third_p;
1834 if (!dsa_is_user_port(ds, j))
1836 third_p = &dev->ports[j];
1837 if (third_p->stp_state != BR_STATE_FORWARDING)
1839 third_dp = dsa_to_port(ds, j);
1840 if (dsa_port_bridge_same(other_dp, third_dp))
1844 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1847 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1850 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1852 struct ksz_device *dev = bus->priv;
1856 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1863 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1866 struct ksz_device *dev = bus->priv;
1868 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1871 static int ksz_irq_phy_setup(struct ksz_device *dev)
1873 struct dsa_switch *ds = dev->ds;
1878 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1879 if (BIT(phy) & ds->phys_mii_mask) {
1880 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1886 ds->slave_mii_bus->irq[phy] = irq;
1892 if (BIT(phy) & ds->phys_mii_mask)
1893 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1898 static void ksz_irq_phy_free(struct ksz_device *dev)
1900 struct dsa_switch *ds = dev->ds;
1903 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1904 if (BIT(phy) & ds->phys_mii_mask)
1905 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1908 static int ksz_mdio_register(struct ksz_device *dev)
1910 struct dsa_switch *ds = dev->ds;
1911 struct device_node *mdio_np;
1912 struct mii_bus *bus;
1915 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1919 bus = devm_mdiobus_alloc(ds->dev);
1921 of_node_put(mdio_np);
1926 bus->read = ksz_sw_mdio_read;
1927 bus->write = ksz_sw_mdio_write;
1928 bus->name = "ksz slave smi";
1929 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1930 bus->parent = ds->dev;
1931 bus->phy_mask = ~ds->phys_mii_mask;
1933 ds->slave_mii_bus = bus;
1936 ret = ksz_irq_phy_setup(dev);
1938 of_node_put(mdio_np);
1943 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1945 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1948 ksz_irq_phy_free(dev);
1951 of_node_put(mdio_np);
1956 static void ksz_irq_mask(struct irq_data *d)
1958 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1960 kirq->masked |= BIT(d->hwirq);
1963 static void ksz_irq_unmask(struct irq_data *d)
1965 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1967 kirq->masked &= ~BIT(d->hwirq);
1970 static void ksz_irq_bus_lock(struct irq_data *d)
1972 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1974 mutex_lock(&kirq->dev->lock_irq);
1977 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1979 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1980 struct ksz_device *dev = kirq->dev;
1983 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1985 dev_err(dev->dev, "failed to change IRQ mask\n");
1987 mutex_unlock(&dev->lock_irq);
1990 static const struct irq_chip ksz_irq_chip = {
1992 .irq_mask = ksz_irq_mask,
1993 .irq_unmask = ksz_irq_unmask,
1994 .irq_bus_lock = ksz_irq_bus_lock,
1995 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1998 static int ksz_irq_domain_map(struct irq_domain *d,
1999 unsigned int irq, irq_hw_number_t hwirq)
2001 irq_set_chip_data(irq, d->host_data);
2002 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2003 irq_set_noprobe(irq);
2008 static const struct irq_domain_ops ksz_irq_domain_ops = {
2009 .map = ksz_irq_domain_map,
2010 .xlate = irq_domain_xlate_twocell,
2013 static void ksz_irq_free(struct ksz_irq *kirq)
2017 free_irq(kirq->irq_num, kirq);
2019 for (irq = 0; irq < kirq->nirqs; irq++) {
2020 virq = irq_find_mapping(kirq->domain, irq);
2021 irq_dispose_mapping(virq);
2024 irq_domain_remove(kirq->domain);
2027 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2029 struct ksz_irq *kirq = dev_id;
2030 unsigned int nhandled = 0;
2031 struct ksz_device *dev;
2032 unsigned int sub_irq;
2039 /* Read interrupt status register */
2040 ret = ksz_read8(dev, kirq->reg_status, &data);
2044 for (n = 0; n < kirq->nirqs; ++n) {
2045 if (data & BIT(n)) {
2046 sub_irq = irq_find_mapping(kirq->domain, n);
2047 handle_nested_irq(sub_irq);
2052 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2055 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2062 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2063 &ksz_irq_domain_ops, kirq);
2067 for (n = 0; n < kirq->nirqs; n++)
2068 irq_create_mapping(kirq->domain, n);
2070 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2071 IRQF_ONESHOT, kirq->name, kirq);
2083 static int ksz_girq_setup(struct ksz_device *dev)
2085 struct ksz_irq *girq = &dev->girq;
2087 girq->nirqs = dev->info->port_cnt;
2088 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2089 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2090 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2092 girq->irq_num = dev->irq;
2094 return ksz_irq_common_setup(dev, girq);
2097 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2099 struct ksz_irq *pirq = &dev->ports[p].pirq;
2101 pirq->nirqs = dev->info->port_nirqs;
2102 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2103 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2104 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2106 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2107 if (pirq->irq_num < 0)
2108 return pirq->irq_num;
2110 return ksz_irq_common_setup(dev, pirq);
2113 static int ksz_setup(struct dsa_switch *ds)
2115 struct ksz_device *dev = ds->priv;
2116 struct dsa_port *dp;
2121 regs = dev->info->regs;
2123 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2124 dev->info->num_vlans, GFP_KERNEL);
2125 if (!dev->vlan_cache)
2128 ret = dev->dev_ops->reset(dev);
2130 dev_err(ds->dev, "failed to reset switch\n");
2134 /* set broadcast storm protection 10% rate */
2135 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2136 BROADCAST_STORM_RATE,
2137 (BROADCAST_STORM_VALUE *
2138 BROADCAST_STORM_PROT_RATE) / 100);
2140 dev->dev_ops->config_cpu_port(ds);
2142 dev->dev_ops->enable_stp_addr(dev);
2144 ds->num_tx_queues = dev->info->num_tx_queues;
2146 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2147 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2149 ksz_init_mib_timer(dev);
2151 ds->configure_vlan_while_not_filtering = false;
2153 if (dev->dev_ops->setup) {
2154 ret = dev->dev_ops->setup(ds);
2159 /* Start with learning disabled on standalone user ports, and enabled
2160 * on the CPU port. In lack of other finer mechanisms, learning on the
2161 * CPU port will avoid flooding bridge local addresses on the network
2164 p = &dev->ports[dev->cpu_port];
2168 ret = ksz_girq_setup(dev);
2172 dsa_switch_for_each_user_port(dp, dev->ds) {
2173 ret = ksz_pirq_setup(dev, dp->index);
2177 ret = ksz_ptp_irq_setup(ds, dp->index);
2183 ret = ksz_ptp_clock_register(ds);
2185 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2189 ret = ksz_mdio_register(dev);
2191 dev_err(dev->dev, "failed to register the mdio");
2192 goto out_ptp_clock_unregister;
2196 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2197 SW_START, SW_START);
2201 out_ptp_clock_unregister:
2202 ksz_ptp_clock_unregister(ds);
2205 dsa_switch_for_each_user_port(dp, dev->ds)
2206 ksz_ptp_irq_free(ds, dp->index);
2209 dsa_switch_for_each_user_port(dp, dev->ds)
2210 ksz_irq_free(&dev->ports[dp->index].pirq);
2213 ksz_irq_free(&dev->girq);
2218 static void ksz_teardown(struct dsa_switch *ds)
2220 struct ksz_device *dev = ds->priv;
2221 struct dsa_port *dp;
2223 ksz_ptp_clock_unregister(ds);
2226 dsa_switch_for_each_user_port(dp, dev->ds) {
2227 ksz_ptp_irq_free(ds, dp->index);
2229 ksz_irq_free(&dev->ports[dp->index].pirq);
2232 ksz_irq_free(&dev->girq);
2235 if (dev->dev_ops->teardown)
2236 dev->dev_ops->teardown(ds);
2239 static void port_r_cnt(struct ksz_device *dev, int port)
2241 struct ksz_port_mib *mib = &dev->ports[port].mib;
2244 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2245 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2246 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2247 &mib->counters[mib->cnt_ptr]);
2251 /* last one in storage */
2252 dropped = &mib->counters[dev->info->mib_cnt];
2254 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2255 while (mib->cnt_ptr < dev->info->mib_cnt) {
2256 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2257 dropped, &mib->counters[mib->cnt_ptr]);
2263 static void ksz_mib_read_work(struct work_struct *work)
2265 struct ksz_device *dev = container_of(work, struct ksz_device,
2267 struct ksz_port_mib *mib;
2271 for (i = 0; i < dev->info->port_cnt; i++) {
2272 if (dsa_is_unused_port(dev->ds, i))
2277 mutex_lock(&mib->cnt_mutex);
2279 /* Only read MIB counters when the port is told to do.
2280 * If not, read only dropped counters when link is not up.
2283 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2285 if (!netif_carrier_ok(dp->slave))
2286 mib->cnt_ptr = dev->info->reg_mib_cnt;
2291 if (dev->dev_ops->r_mib_stat64)
2292 dev->dev_ops->r_mib_stat64(dev, i);
2294 mutex_unlock(&mib->cnt_mutex);
2297 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2300 void ksz_init_mib_timer(struct ksz_device *dev)
2304 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2306 for (i = 0; i < dev->info->port_cnt; i++) {
2307 struct ksz_port_mib *mib = &dev->ports[i].mib;
2309 dev->dev_ops->port_init_cnt(dev, i);
2312 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2316 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2318 struct ksz_device *dev = ds->priv;
2322 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2329 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2331 struct ksz_device *dev = ds->priv;
2334 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2341 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2343 struct ksz_device *dev = ds->priv;
2345 if (dev->chip_id == KSZ8830_CHIP_ID) {
2346 /* Silicon Errata Sheet (DS80000830A):
2347 * Port 1 does not work with LinkMD Cable-Testing.
2348 * Port 1 does not respond to received PAUSE control frames.
2351 return MICREL_KSZ8_P1_ERRATA;
2357 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2358 unsigned int mode, phy_interface_t interface)
2360 struct ksz_device *dev = ds->priv;
2361 struct ksz_port *p = &dev->ports[port];
2363 /* Read all MIB counters when the link is going down. */
2366 if (dev->mib_read_interval)
2367 schedule_delayed_work(&dev->mib_read, 0);
2370 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2372 struct ksz_device *dev = ds->priv;
2374 if (sset != ETH_SS_STATS)
2377 return dev->info->mib_cnt;
2380 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2383 const struct dsa_port *dp = dsa_to_port(ds, port);
2384 struct ksz_device *dev = ds->priv;
2385 struct ksz_port_mib *mib;
2387 mib = &dev->ports[port].mib;
2388 mutex_lock(&mib->cnt_mutex);
2390 /* Only read dropped counters if no link. */
2391 if (!netif_carrier_ok(dp->slave))
2392 mib->cnt_ptr = dev->info->reg_mib_cnt;
2393 port_r_cnt(dev, port);
2394 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2395 mutex_unlock(&mib->cnt_mutex);
2398 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2399 struct dsa_bridge bridge,
2400 bool *tx_fwd_offload,
2401 struct netlink_ext_ack *extack)
2403 /* port_stp_state_set() will be called after to put the port in
2404 * appropriate state so there is no need to do anything.
2410 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2411 struct dsa_bridge bridge)
2413 /* port_stp_state_set() will be called after to put the port in
2414 * forwarding state so there is no need to do anything.
2418 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2420 struct ksz_device *dev = ds->priv;
2422 dev->dev_ops->flush_dyn_mac_table(dev, port);
2425 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2427 struct ksz_device *dev = ds->priv;
2429 if (!dev->dev_ops->set_ageing_time)
2432 return dev->dev_ops->set_ageing_time(dev, msecs);
2435 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2436 const unsigned char *addr, u16 vid,
2439 struct ksz_device *dev = ds->priv;
2441 if (!dev->dev_ops->fdb_add)
2444 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2447 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2448 const unsigned char *addr,
2449 u16 vid, struct dsa_db db)
2451 struct ksz_device *dev = ds->priv;
2453 if (!dev->dev_ops->fdb_del)
2456 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2459 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2460 dsa_fdb_dump_cb_t *cb, void *data)
2462 struct ksz_device *dev = ds->priv;
2464 if (!dev->dev_ops->fdb_dump)
2467 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2470 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2471 const struct switchdev_obj_port_mdb *mdb,
2474 struct ksz_device *dev = ds->priv;
2476 if (!dev->dev_ops->mdb_add)
2479 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2482 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2483 const struct switchdev_obj_port_mdb *mdb,
2486 struct ksz_device *dev = ds->priv;
2488 if (!dev->dev_ops->mdb_del)
2491 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2494 static int ksz_enable_port(struct dsa_switch *ds, int port,
2495 struct phy_device *phy)
2497 struct ksz_device *dev = ds->priv;
2499 if (!dsa_is_user_port(ds, port))
2502 /* setup slave port */
2503 dev->dev_ops->port_setup(dev, port, false);
2505 /* port_stp_state_set() will be called after to enable the port so
2506 * there is no need to do anything.
2512 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2514 struct ksz_device *dev = ds->priv;
2519 regs = dev->info->regs;
2521 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2522 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2524 p = &dev->ports[port];
2527 case BR_STATE_DISABLED:
2528 data |= PORT_LEARN_DISABLE;
2530 case BR_STATE_LISTENING:
2531 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2533 case BR_STATE_LEARNING:
2534 data |= PORT_RX_ENABLE;
2536 data |= PORT_LEARN_DISABLE;
2538 case BR_STATE_FORWARDING:
2539 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2541 data |= PORT_LEARN_DISABLE;
2543 case BR_STATE_BLOCKING:
2544 data |= PORT_LEARN_DISABLE;
2547 dev_err(ds->dev, "invalid STP state: %d\n", state);
2551 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2553 p->stp_state = state;
2555 ksz_update_port_member(dev, port);
2558 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2559 struct switchdev_brport_flags flags,
2560 struct netlink_ext_ack *extack)
2562 if (flags.mask & ~BR_LEARNING)
2568 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2569 struct switchdev_brport_flags flags,
2570 struct netlink_ext_ack *extack)
2572 struct ksz_device *dev = ds->priv;
2573 struct ksz_port *p = &dev->ports[port];
2575 if (flags.mask & BR_LEARNING) {
2576 p->learning = !!(flags.val & BR_LEARNING);
2578 /* Make the change take effect immediately */
2579 ksz_port_stp_state_set(ds, port, p->stp_state);
2585 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2587 enum dsa_tag_protocol mp)
2589 struct ksz_device *dev = ds->priv;
2590 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2592 if (dev->chip_id == KSZ8795_CHIP_ID ||
2593 dev->chip_id == KSZ8794_CHIP_ID ||
2594 dev->chip_id == KSZ8765_CHIP_ID)
2595 proto = DSA_TAG_PROTO_KSZ8795;
2597 if (dev->chip_id == KSZ8830_CHIP_ID ||
2598 dev->chip_id == KSZ8563_CHIP_ID ||
2599 dev->chip_id == KSZ9893_CHIP_ID ||
2600 dev->chip_id == KSZ9563_CHIP_ID)
2601 proto = DSA_TAG_PROTO_KSZ9893;
2603 if (dev->chip_id == KSZ9477_CHIP_ID ||
2604 dev->chip_id == KSZ9896_CHIP_ID ||
2605 dev->chip_id == KSZ9897_CHIP_ID ||
2606 dev->chip_id == KSZ9567_CHIP_ID)
2607 proto = DSA_TAG_PROTO_KSZ9477;
2609 if (is_lan937x(dev))
2610 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2615 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2616 enum dsa_tag_protocol proto)
2618 struct ksz_tagger_data *tagger_data;
2620 tagger_data = ksz_tagger_data(ds);
2621 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2626 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2627 bool flag, struct netlink_ext_ack *extack)
2629 struct ksz_device *dev = ds->priv;
2631 if (!dev->dev_ops->vlan_filtering)
2634 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2637 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2638 const struct switchdev_obj_port_vlan *vlan,
2639 struct netlink_ext_ack *extack)
2641 struct ksz_device *dev = ds->priv;
2643 if (!dev->dev_ops->vlan_add)
2646 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2649 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2650 const struct switchdev_obj_port_vlan *vlan)
2652 struct ksz_device *dev = ds->priv;
2654 if (!dev->dev_ops->vlan_del)
2657 return dev->dev_ops->vlan_del(dev, port, vlan);
2660 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2661 struct dsa_mall_mirror_tc_entry *mirror,
2662 bool ingress, struct netlink_ext_ack *extack)
2664 struct ksz_device *dev = ds->priv;
2666 if (!dev->dev_ops->mirror_add)
2669 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2672 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2673 struct dsa_mall_mirror_tc_entry *mirror)
2675 struct ksz_device *dev = ds->priv;
2677 if (dev->dev_ops->mirror_del)
2678 dev->dev_ops->mirror_del(dev, port, mirror);
2681 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2683 struct ksz_device *dev = ds->priv;
2685 if (!dev->dev_ops->change_mtu)
2688 return dev->dev_ops->change_mtu(dev, port, mtu);
2691 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2693 struct ksz_device *dev = ds->priv;
2695 switch (dev->chip_id) {
2696 case KSZ8795_CHIP_ID:
2697 case KSZ8794_CHIP_ID:
2698 case KSZ8765_CHIP_ID:
2699 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2700 case KSZ8830_CHIP_ID:
2701 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2702 case KSZ8563_CHIP_ID:
2703 case KSZ9477_CHIP_ID:
2704 case KSZ9563_CHIP_ID:
2705 case KSZ9567_CHIP_ID:
2706 case KSZ9893_CHIP_ID:
2707 case KSZ9896_CHIP_ID:
2708 case KSZ9897_CHIP_ID:
2709 case LAN9370_CHIP_ID:
2710 case LAN9371_CHIP_ID:
2711 case LAN9372_CHIP_ID:
2712 case LAN9373_CHIP_ID:
2713 case LAN9374_CHIP_ID:
2714 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2720 static int ksz_validate_eee(struct dsa_switch *ds, int port)
2722 struct ksz_device *dev = ds->priv;
2724 if (!dev->info->internal_phy[port])
2727 switch (dev->chip_id) {
2728 case KSZ8563_CHIP_ID:
2729 case KSZ9477_CHIP_ID:
2730 case KSZ9563_CHIP_ID:
2731 case KSZ9567_CHIP_ID:
2732 case KSZ9893_CHIP_ID:
2733 case KSZ9896_CHIP_ID:
2734 case KSZ9897_CHIP_ID:
2741 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2742 struct ethtool_eee *e)
2746 ret = ksz_validate_eee(ds, port);
2750 /* There is no documented control of Tx LPI configuration. */
2751 e->tx_lpi_enabled = true;
2753 /* There is no documented control of Tx LPI timer. According to tests
2754 * Tx LPI timer seems to be set by default to minimal value.
2756 e->tx_lpi_timer = 0;
2761 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2762 struct ethtool_eee *e)
2764 struct ksz_device *dev = ds->priv;
2767 ret = ksz_validate_eee(ds, port);
2771 if (!e->tx_lpi_enabled) {
2772 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2776 if (e->tx_lpi_timer) {
2777 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2784 static void ksz_set_xmii(struct ksz_device *dev, int port,
2785 phy_interface_t interface)
2787 const u8 *bitval = dev->info->xmii_ctrl1;
2788 struct ksz_port *p = &dev->ports[port];
2789 const u16 *regs = dev->info->regs;
2792 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2794 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2795 P_RGMII_ID_EG_ENABLE);
2797 switch (interface) {
2798 case PHY_INTERFACE_MODE_MII:
2799 data8 |= bitval[P_MII_SEL];
2801 case PHY_INTERFACE_MODE_RMII:
2802 data8 |= bitval[P_RMII_SEL];
2804 case PHY_INTERFACE_MODE_GMII:
2805 data8 |= bitval[P_GMII_SEL];
2807 case PHY_INTERFACE_MODE_RGMII:
2808 case PHY_INTERFACE_MODE_RGMII_ID:
2809 case PHY_INTERFACE_MODE_RGMII_TXID:
2810 case PHY_INTERFACE_MODE_RGMII_RXID:
2811 data8 |= bitval[P_RGMII_SEL];
2812 /* On KSZ9893, disable RGMII in-band status support */
2813 if (dev->chip_id == KSZ9893_CHIP_ID ||
2814 dev->chip_id == KSZ8563_CHIP_ID ||
2815 dev->chip_id == KSZ9563_CHIP_ID)
2816 data8 &= ~P_MII_MAC_MODE;
2819 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2820 phy_modes(interface), port);
2824 if (p->rgmii_tx_val)
2825 data8 |= P_RGMII_ID_EG_ENABLE;
2827 if (p->rgmii_rx_val)
2828 data8 |= P_RGMII_ID_IG_ENABLE;
2830 /* Write the updated value */
2831 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2834 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2836 const u8 *bitval = dev->info->xmii_ctrl1;
2837 const u16 *regs = dev->info->regs;
2838 phy_interface_t interface;
2842 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2844 val = FIELD_GET(P_MII_SEL_M, data8);
2846 if (val == bitval[P_MII_SEL]) {
2848 interface = PHY_INTERFACE_MODE_GMII;
2850 interface = PHY_INTERFACE_MODE_MII;
2851 } else if (val == bitval[P_RMII_SEL]) {
2852 interface = PHY_INTERFACE_MODE_RGMII;
2854 interface = PHY_INTERFACE_MODE_RGMII;
2855 if (data8 & P_RGMII_ID_EG_ENABLE)
2856 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2857 if (data8 & P_RGMII_ID_IG_ENABLE) {
2858 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2859 if (data8 & P_RGMII_ID_EG_ENABLE)
2860 interface = PHY_INTERFACE_MODE_RGMII_ID;
2867 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2869 const struct phylink_link_state *state)
2871 struct ksz_device *dev = ds->priv;
2873 if (ksz_is_ksz88x3(dev))
2877 if (dev->info->internal_phy[port])
2880 if (phylink_autoneg_inband(mode)) {
2881 dev_err(dev->dev, "In-band AN not supported!\n");
2885 ksz_set_xmii(dev, port, state->interface);
2887 if (dev->dev_ops->phylink_mac_config)
2888 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2890 if (dev->dev_ops->setup_rgmii_delay)
2891 dev->dev_ops->setup_rgmii_delay(dev, port);
2894 bool ksz_get_gbit(struct ksz_device *dev, int port)
2896 const u8 *bitval = dev->info->xmii_ctrl1;
2897 const u16 *regs = dev->info->regs;
2902 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2904 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2906 if (val == bitval[P_GMII_1GBIT])
2912 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2914 const u8 *bitval = dev->info->xmii_ctrl1;
2915 const u16 *regs = dev->info->regs;
2918 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2920 data8 &= ~P_GMII_1GBIT_M;
2923 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2925 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2927 /* Write the updated value */
2928 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2931 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2933 const u8 *bitval = dev->info->xmii_ctrl0;
2934 const u16 *regs = dev->info->regs;
2937 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2939 data8 &= ~P_MII_100MBIT_M;
2941 if (speed == SPEED_100)
2942 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2944 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2946 /* Write the updated value */
2947 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2950 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2952 if (speed == SPEED_1000)
2953 ksz_set_gbit(dev, port, true);
2955 ksz_set_gbit(dev, port, false);
2957 if (speed == SPEED_100 || speed == SPEED_10)
2958 ksz_set_100_10mbit(dev, port, speed);
2961 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2962 bool tx_pause, bool rx_pause)
2964 const u8 *bitval = dev->info->xmii_ctrl0;
2965 const u32 *masks = dev->info->masks;
2966 const u16 *regs = dev->info->regs;
2970 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2971 masks[P_MII_RX_FLOW_CTRL];
2973 if (duplex == DUPLEX_FULL)
2974 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2976 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2979 val |= masks[P_MII_TX_FLOW_CTRL];
2982 val |= masks[P_MII_RX_FLOW_CTRL];
2984 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2987 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2989 phy_interface_t interface,
2990 struct phy_device *phydev, int speed,
2991 int duplex, bool tx_pause,
2996 p = &dev->ports[port];
2999 if (dev->info->internal_phy[port])
3002 p->phydev.speed = speed;
3004 ksz_port_set_xmii_speed(dev, port, speed);
3006 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3009 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
3011 phy_interface_t interface,
3012 struct phy_device *phydev, int speed,
3013 int duplex, bool tx_pause, bool rx_pause)
3015 struct ksz_device *dev = ds->priv;
3017 if (dev->dev_ops->phylink_mac_link_up)
3018 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
3019 phydev, speed, duplex,
3020 tx_pause, rx_pause);
3023 static int ksz_switch_detect(struct ksz_device *dev)
3031 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3035 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3036 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3039 case KSZ87_FAMILY_ID:
3040 if (id2 == KSZ87_CHIP_ID_95) {
3043 dev->chip_id = KSZ8795_CHIP_ID;
3045 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3046 if (val & KSZ8_PORT_FIBER_MODE)
3047 dev->chip_id = KSZ8765_CHIP_ID;
3048 } else if (id2 == KSZ87_CHIP_ID_94) {
3049 dev->chip_id = KSZ8794_CHIP_ID;
3054 case KSZ88_FAMILY_ID:
3055 if (id2 == KSZ88_CHIP_ID_63)
3056 dev->chip_id = KSZ8830_CHIP_ID;
3061 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3065 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3069 case KSZ9477_CHIP_ID:
3070 case KSZ9896_CHIP_ID:
3071 case KSZ9897_CHIP_ID:
3072 case KSZ9567_CHIP_ID:
3073 case LAN9370_CHIP_ID:
3074 case LAN9371_CHIP_ID:
3075 case LAN9372_CHIP_ID:
3076 case LAN9373_CHIP_ID:
3077 case LAN9374_CHIP_ID:
3078 dev->chip_id = id32;
3080 case KSZ9893_CHIP_ID:
3081 ret = ksz_read8(dev, REG_CHIP_ID4,
3086 if (id4 == SKU_ID_KSZ8563)
3087 dev->chip_id = KSZ8563_CHIP_ID;
3088 else if (id4 == SKU_ID_KSZ9563)
3089 dev->chip_id = KSZ9563_CHIP_ID;
3091 dev->chip_id = KSZ9893_CHIP_ID;
3096 "unsupported switch detected %x)\n", id32);
3103 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3104 * is converted to Hex-decimal using the successive multiplication method. On
3105 * every step, integer part is taken and decimal part is carry forwarded.
3107 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3115 txrate = idle_slope - send_slope;
3122 /* 24 bit register */
3123 for (i = 0; i < 6; i++) {
3126 temp = rate / txrate;
3130 cinc = ((cinc << 4) | temp);
3138 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3141 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3142 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3143 FIELD_PREP(MTI_SHAPING_M, shaper));
3146 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3147 struct tc_cbs_qopt_offload *qopt)
3149 struct ksz_device *dev = ds->priv;
3153 if (!dev->info->tc_cbs_supported)
3156 if (qopt->queue > dev->info->num_tx_queues)
3159 /* Queue Selection */
3160 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3165 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3169 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3175 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3180 /* Credit Increment Register */
3181 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3185 if (dev->dev_ops->tc_cbs_set_cinc) {
3186 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3191 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3195 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3199 /* Configuration will not take effect until the last Port Queue X
3200 * Egress Limit Control Register is written.
3202 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3203 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3204 KSZ9477_OUT_RATE_NO_LIMIT);
3212 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3215 /* Compared to queues, bands prioritize packets differently. In strict
3216 * priority mode, the lowest priority is assigned to Queue 0 while the
3217 * highest priority is given to Band 0.
3219 return p->bands - 1 - band;
3222 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3226 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3230 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3234 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3239 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3243 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3248 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3251 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3252 struct tc_ets_qopt_offload_replace_params *p)
3254 int ret, band, tc_prio;
3257 /* In order to ensure proper prioritization, it is necessary to set the
3258 * rate limit for the related queue to zero. Otherwise strict priority
3259 * or WRR mode will not work. This is a hardware limitation.
3261 ret = ksz_disable_egress_rate_limit(dev, port);
3265 /* Configure queue scheduling mode for all bands. Currently only strict
3266 * prio mode is supported.
3268 for (band = 0; band < p->bands; band++) {
3269 int queue = ksz_ets_band_to_queue(p, band);
3271 ret = ksz_queue_set_strict(dev, port, queue);
3276 /* Configure the mapping between traffic classes and queues. Note:
3277 * priomap variable support 16 traffic classes, but the chip can handle
3280 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3283 if (tc_prio > KSZ9477_MAX_TC_PRIO)
3286 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3287 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3290 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3293 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3295 int ret, queue, tc_prio, s;
3298 /* To restore the default chip configuration, set all queues to use the
3299 * WRR scheduler with a weight of 1.
3301 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3302 ret = ksz_queue_set_wrr(dev, port, queue,
3303 KSZ9477_DEFAULT_WRR_WEIGHT);
3308 switch (dev->info->num_tx_queues) {
3322 /* Revert the queue mapping for TC-priority to its default setting on
3325 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3328 queue = tc_prio >> s;
3329 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3332 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3335 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3336 struct tc_ets_qopt_offload_replace_params *p)
3340 /* Since it is not feasible to share one port among multiple qdisc,
3341 * the user must configure all available queues appropriately.
3343 if (p->bands != dev->info->num_tx_queues) {
3344 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3345 dev->info->num_tx_queues);
3349 for (band = 0; band < p->bands; ++band) {
3350 /* The KSZ switches utilize a weighted round robin configuration
3351 * where a certain number of packets can be transmitted from a
3352 * queue before the next queue is serviced. For more information
3353 * on this, refer to section 5.2.8.4 of the KSZ8565R
3354 * documentation on the Port Transmit Queue Control 1 Register.
3355 * However, the current ETS Qdisc implementation (as of February
3356 * 2023) assigns a weight to each queue based on the number of
3357 * bytes or extrapolated bandwidth in percentages. Since this
3358 * differs from the KSZ switches' method and we don't want to
3359 * fake support by converting bytes to packets, it is better to
3360 * return an error instead.
3362 if (p->quanta[band]) {
3363 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3371 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3372 struct tc_ets_qopt_offload *qopt)
3374 struct ksz_device *dev = ds->priv;
3377 if (!dev->info->tc_ets_supported)
3380 if (qopt->parent != TC_H_ROOT) {
3381 dev_err(dev->dev, "Parent should be \"root\"\n");
3385 switch (qopt->command) {
3386 case TC_ETS_REPLACE:
3387 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3391 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3392 case TC_ETS_DESTROY:
3393 return ksz_tc_ets_del(dev, port);
3402 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3403 enum tc_setup_type type, void *type_data)
3406 case TC_SETUP_QDISC_CBS:
3407 return ksz_setup_tc_cbs(ds, port, type_data);
3408 case TC_SETUP_QDISC_ETS:
3409 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3415 static const struct dsa_switch_ops ksz_switch_ops = {
3416 .get_tag_protocol = ksz_get_tag_protocol,
3417 .connect_tag_protocol = ksz_connect_tag_protocol,
3418 .get_phy_flags = ksz_get_phy_flags,
3420 .teardown = ksz_teardown,
3421 .phy_read = ksz_phy_read16,
3422 .phy_write = ksz_phy_write16,
3423 .phylink_get_caps = ksz_phylink_get_caps,
3424 .phylink_mac_config = ksz_phylink_mac_config,
3425 .phylink_mac_link_up = ksz_phylink_mac_link_up,
3426 .phylink_mac_link_down = ksz_mac_link_down,
3427 .port_enable = ksz_enable_port,
3428 .set_ageing_time = ksz_set_ageing_time,
3429 .get_strings = ksz_get_strings,
3430 .get_ethtool_stats = ksz_get_ethtool_stats,
3431 .get_sset_count = ksz_sset_count,
3432 .port_bridge_join = ksz_port_bridge_join,
3433 .port_bridge_leave = ksz_port_bridge_leave,
3434 .port_stp_state_set = ksz_port_stp_state_set,
3435 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3436 .port_bridge_flags = ksz_port_bridge_flags,
3437 .port_fast_age = ksz_port_fast_age,
3438 .port_vlan_filtering = ksz_port_vlan_filtering,
3439 .port_vlan_add = ksz_port_vlan_add,
3440 .port_vlan_del = ksz_port_vlan_del,
3441 .port_fdb_dump = ksz_port_fdb_dump,
3442 .port_fdb_add = ksz_port_fdb_add,
3443 .port_fdb_del = ksz_port_fdb_del,
3444 .port_mdb_add = ksz_port_mdb_add,
3445 .port_mdb_del = ksz_port_mdb_del,
3446 .port_mirror_add = ksz_port_mirror_add,
3447 .port_mirror_del = ksz_port_mirror_del,
3448 .get_stats64 = ksz_get_stats64,
3449 .get_pause_stats = ksz_get_pause_stats,
3450 .port_change_mtu = ksz_change_mtu,
3451 .port_max_mtu = ksz_max_mtu,
3452 .get_ts_info = ksz_get_ts_info,
3453 .port_hwtstamp_get = ksz_hwtstamp_get,
3454 .port_hwtstamp_set = ksz_hwtstamp_set,
3455 .port_txtstamp = ksz_port_txtstamp,
3456 .port_rxtstamp = ksz_port_rxtstamp,
3457 .port_setup_tc = ksz_setup_tc,
3458 .get_mac_eee = ksz_get_mac_eee,
3459 .set_mac_eee = ksz_set_mac_eee,
3462 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3464 struct dsa_switch *ds;
3465 struct ksz_device *swdev;
3467 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3472 ds->num_ports = DSA_MAX_PORTS;
3473 ds->ops = &ksz_switch_ops;
3475 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3487 EXPORT_SYMBOL(ksz_switch_alloc);
3489 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3490 struct device_node *port_dn)
3492 phy_interface_t phy_mode = dev->ports[port_num].interface;
3493 int rx_delay = -1, tx_delay = -1;
3495 if (!phy_interface_mode_is_rgmii(phy_mode))
3498 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3499 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3501 if (rx_delay == -1 && tx_delay == -1) {
3503 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3504 "please update device tree to specify \"rx-internal-delay-ps\" and "
3505 "\"tx-internal-delay-ps\"",
3508 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3509 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3512 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3513 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3522 dev->ports[port_num].rgmii_rx_val = rx_delay;
3523 dev->ports[port_num].rgmii_tx_val = tx_delay;
3526 int ksz_switch_register(struct ksz_device *dev)
3528 const struct ksz_chip_data *info;
3529 struct device_node *port, *ports;
3530 phy_interface_t interface;
3531 unsigned int port_num;
3536 dev->chip_id = dev->pdata->chip_id;
3538 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3540 if (IS_ERR(dev->reset_gpio))
3541 return PTR_ERR(dev->reset_gpio);
3543 if (dev->reset_gpio) {
3544 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3545 usleep_range(10000, 12000);
3546 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3550 mutex_init(&dev->dev_mutex);
3551 mutex_init(&dev->regmap_mutex);
3552 mutex_init(&dev->alu_mutex);
3553 mutex_init(&dev->vlan_mutex);
3555 ret = ksz_switch_detect(dev);
3559 info = ksz_lookup_info(dev->chip_id);
3563 /* Update the compatible info with the probed one */
3566 dev_info(dev->dev, "found switch: %s, rev %i\n",
3567 dev->info->dev_name, dev->chip_rev);
3569 ret = ksz_check_device_id(dev);
3573 dev->dev_ops = dev->info->ops;
3575 ret = dev->dev_ops->init(dev);
3579 dev->ports = devm_kzalloc(dev->dev,
3580 dev->info->port_cnt * sizeof(struct ksz_port),
3585 for (i = 0; i < dev->info->port_cnt; i++) {
3586 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3587 mutex_init(&dev->ports[i].mib.cnt_mutex);
3588 dev->ports[i].mib.counters =
3589 devm_kzalloc(dev->dev,
3590 sizeof(u64) * (dev->info->mib_cnt + 1),
3592 if (!dev->ports[i].mib.counters)
3595 dev->ports[i].ksz_dev = dev;
3596 dev->ports[i].num = i;
3599 /* set the real number of ports */
3600 dev->ds->num_ports = dev->info->port_cnt;
3602 /* Host port interface will be self detected, or specifically set in
3605 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3606 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3607 if (dev->dev->of_node) {
3608 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3610 dev->compat_interface = interface;
3611 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3613 ports = of_get_child_by_name(dev->dev->of_node, "ports");
3615 for_each_available_child_of_node(ports, port) {
3616 if (of_property_read_u32(port, "reg",
3619 if (!(dev->port_mask & BIT(port_num))) {
3624 of_get_phy_mode(port,
3625 &dev->ports[port_num].interface);
3627 ksz_parse_rgmii_delay(dev, port_num, port);
3631 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3632 "microchip,synclko-125");
3633 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3634 "microchip,synclko-disable");
3635 if (dev->synclko_125 && dev->synclko_disable) {
3636 dev_err(dev->dev, "inconsistent synclko settings\n");
3641 ret = dsa_register_switch(dev->ds);
3643 dev->dev_ops->exit(dev);
3647 /* Read MIB counters every 30 seconds to avoid overflow. */
3648 dev->mib_read_interval = msecs_to_jiffies(5000);
3650 /* Start the MIB timer. */
3651 schedule_delayed_work(&dev->mib_read, 0);
3655 EXPORT_SYMBOL(ksz_switch_register);
3657 void ksz_switch_remove(struct ksz_device *dev)
3660 if (dev->mib_read_interval) {
3661 dev->mib_read_interval = 0;
3662 cancel_delayed_work_sync(&dev->mib_read);
3665 dev->dev_ops->exit(dev);
3666 dsa_unregister_switch(dev->ds);
3668 if (dev->reset_gpio)
3669 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3672 EXPORT_SYMBOL(ksz_switch_remove);
3674 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3675 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3676 MODULE_LICENSE("GPL");