drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/if_bridge.h>
  32 #include <net/dsa.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         u8 mgmt;
 330
 331         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 332
 333         if (enable)
 334                 mgmt |= SM_SW_FWD_EN;
 335         else
 336                 mgmt &= ~SM_SW_FWD_EN;
 337
 338         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 339
 340         /* Include IMP port in dumb forwarding mode
 341          */
 342         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 343         mgmt |= B53_MII_DUMB_FWDG_EN;
 344         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 345
 346         /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
 347          * frames should be flooded or not.
 348          */
 349         b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
 350         mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
 351         b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
 352 }
 353
 354 static void b53_enable_vlan(struct b53_device *dev, bool enable,
 355                             bool enable_filtering)
 356 {
 357         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 358
 359         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 360         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 361         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 362
 363         if (is5325(dev) || is5365(dev)) {
 364                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 365                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 366         } else if (is63xx(dev)) {
 367                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 368                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 369         } else {
 370                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 371                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 372         }
 373
 374         mgmt &= ~SM_SW_FWD_MODE;
 375
 376         if (enable) {
 377                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 378                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 379                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 380                 if (enable_filtering) {
 381                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 382                         vc5 |= VC5_DROP_VTABLE_MISS;
 383                 } else {
 384                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 385                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 386                 }
 387
 388                 if (is5325(dev))
 389                         vc0 &= ~VC0_RESERVED_1;
 390
 391                 if (is5325(dev) || is5365(dev))
 392                         vc1 |= VC1_RX_MCST_TAG_EN;
 393
 394         } else {
 395                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 396                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 397                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 398                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 399
 400                 if (is5325(dev) || is5365(dev))
 401                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 402                 else
 403                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 404
 405                 if (is5325(dev) || is5365(dev))
 406                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 407         }
 408
 409         if (!is5325(dev) && !is5365(dev))
 410                 vc5 &= ~VC5_VID_FFF_EN;
 411
 412         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 413         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 414
 415         if (is5325(dev) || is5365(dev)) {
 416                 /* enable the high 8 bit vid check on 5325 */
 417                 if (is5325(dev) && enable)
 418                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 419                                    VC3_HIGH_8BIT_EN);
 420                 else
 421                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 422
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 425         } else if (is63xx(dev)) {
 426                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 427                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 428                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 429         } else {
 430                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 431                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 432                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 433         }
 434
 435         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 436
 437         dev->vlan_enabled = enable;
 438 }
 439
 440 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 441 {
 442         u32 port_mask = 0;
 443         u16 max_size = JMS_MIN_SIZE;
 444
 445         if (is5325(dev) || is5365(dev))
 446                 return -EINVAL;
 447
 448         if (enable) {
 449                 port_mask = dev->enabled_ports;
 450                 max_size = JMS_MAX_SIZE;
 451                 if (allow_10_100)
 452                         port_mask |= JPM_10_100_JUMBO_EN;
 453         }
 454
 455         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 456         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 457 }
 458
 459 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 460 {
 461         unsigned int i;
 462
 463         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 464                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 465
 466         for (i = 0; i < 10; i++) {
 467                 u8 fast_age_ctrl;
 468
 469                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 470                           &fast_age_ctrl);
 471
 472                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 473                         goto out;
 474
 475                 msleep(1);
 476         }
 477
 478         return -ETIMEDOUT;
 479 out:
 480         /* Only age dynamic entries (default behavior) */
 481         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 482         return 0;
 483 }
 484
 485 static int b53_fast_age_port(struct b53_device *dev, int port)
 486 {
 487         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 488
 489         return b53_flush_arl(dev, FAST_AGE_PORT);
 490 }
 491
 492 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 493 {
 494         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 495
 496         return b53_flush_arl(dev, FAST_AGE_VLAN);
 497 }
 498
 499 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 500 {
 501         struct b53_device *dev = ds->priv;
 502         unsigned int i;
 503         u16 pvlan;
 504
 505         /* Enable the IMP port to be in the same VLAN as the other ports
 506          * on a per-port basis such that we only have Port i and IMP in
 507          * the same VLAN.
 508          */
 509         b53_for_each_port(dev, i) {
 510                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 511                 pvlan |= BIT(cpu_port);
 512                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 513         }
 514 }
 515 EXPORT_SYMBOL(b53_imp_vlan_setup);
 516
 517 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 518 {
 519         struct b53_device *dev = ds->priv;
 520         unsigned int cpu_port;
 521         int ret = 0;
 522         u16 pvlan;
 523
 524         if (!dsa_is_user_port(ds, port))
 525                 return 0;
 526
 527         cpu_port = ds->ports[port].cpu_dp->index;
 528
 529         b53_br_egress_floods(ds, port, true, true);
 530
 531         if (dev->ops->irq_enable)
 532                 ret = dev->ops->irq_enable(dev, port);
 533         if (ret)
 534                 return ret;
 535
 536         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 537         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 538
 539         /* Set this port, and only this one to be in the default VLAN,
 540          * if member of a bridge, restore its membership prior to
 541          * bringing down this port.
 542          */
 543         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 544         pvlan &= ~0x1ff;
 545         pvlan |= BIT(port);
 546         pvlan |= dev->ports[port].vlan_ctl_mask;
 547         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 548
 549         b53_imp_vlan_setup(ds, cpu_port);
 550
 551         /* If EEE was enabled, restore it */
 552         if (dev->ports[port].eee.eee_enabled)
 553                 b53_eee_enable_set(ds, port, true);
 554
 555         return 0;
 556 }
 557 EXPORT_SYMBOL(b53_enable_port);
 558
 559 void b53_disable_port(struct dsa_switch *ds, int port)
 560 {
 561         struct b53_device *dev = ds->priv;
 562         u8 reg;
 563
 564         /* Disable Tx/Rx for the port */
 565         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 566         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 567         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 568
 569         if (dev->ops->irq_disable)
 570                 dev->ops->irq_disable(dev, port);
 571 }
 572 EXPORT_SYMBOL(b53_disable_port);
 573
 574 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 575 {
 576         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 577                          DSA_TAG_PROTO_NONE);
 578         struct b53_device *dev = ds->priv;
 579         u8 hdr_ctl, val;
 580         u16 reg;
 581
 582         /* Resolve which bit controls the Broadcom tag */
 583         switch (port) {
 584         case 8:
 585                 val = BRCM_HDR_P8_EN;
 586                 break;
 587         case 7:
 588                 val = BRCM_HDR_P7_EN;
 589                 break;
 590         case 5:
 591                 val = BRCM_HDR_P5_EN;
 592                 break;
 593         default:
 594                 val = 0;
 595                 break;
 596         }
 597
 598         /* Enable Broadcom tags for IMP port */
 599         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 600         if (tag_en)
 601                 hdr_ctl |= val;
 602         else
 603                 hdr_ctl &= ~val;
 604         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 605
 606         /* Registers below are only accessible on newer devices */
 607         if (!is58xx(dev))
 608                 return;
 609
 610         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 611          * allow us to tag outgoing frames
 612          */
 613         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 614         if (tag_en)
 615                 reg &= ~BIT(port);
 616         else
 617                 reg |= BIT(port);
 618         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 619
 620         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 621          * allow delivering frames to the per-port net_devices
 622          */
 623         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 624         if (tag_en)
 625                 reg &= ~BIT(port);
 626         else
 627                 reg |= BIT(port);
 628         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 629 }
 630 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 631
 632 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 633 {
 634         u8 port_ctrl;
 635
 636         /* BCM5325 CPU port is at 8 */
 637         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 638                 port = B53_CPU_PORT;
 639
 640         port_ctrl = PORT_CTRL_RX_BCST_EN |
 641                     PORT_CTRL_RX_MCST_EN |
 642                     PORT_CTRL_RX_UCST_EN;
 643         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 644
 645         b53_brcm_hdr_setup(dev->ds, port);
 646
 647         b53_br_egress_floods(dev->ds, port, true, true);
 648 }
 649
 650 static void b53_enable_mib(struct b53_device *dev)
 651 {
 652         u8 gc;
 653
 654         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 655         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 656         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 657 }
 658
 659 static u16 b53_default_pvid(struct b53_device *dev)
 660 {
 661         if (is5325(dev) || is5365(dev))
 662                 return 1;
 663         else
 664                 return 0;
 665 }
 666
 667 int b53_configure_vlan(struct dsa_switch *ds)
 668 {
 669         struct b53_device *dev = ds->priv;
 670         struct b53_vlan vl = { 0 };
 671         int i, def_vid;
 672
 673         def_vid = b53_default_pvid(dev);
 674
 675         /* clear all vlan entries */
 676         if (is5325(dev) || is5365(dev)) {
 677                 for (i = def_vid; i < dev->num_vlans; i++)
 678                         b53_set_vlan_entry(dev, i, &vl);
 679         } else {
 680                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 681         }
 682
 683         b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);
 684
 685         b53_for_each_port(dev, i)
 686                 b53_write16(dev, B53_VLAN_PAGE,
 687                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 688
 689         if (!is5325(dev) && !is5365(dev))
 690                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 691
 692         return 0;
 693 }
 694 EXPORT_SYMBOL(b53_configure_vlan);
 695
 696 static void b53_switch_reset_gpio(struct b53_device *dev)
 697 {
 698         int gpio = dev->reset_gpio;
 699
 700         if (gpio < 0)
 701                 return;
 702
 703         /* Reset sequence: RESET low(50ms)->high(20ms)
 704          */
 705         gpio_set_value(gpio, 0);
 706         mdelay(50);
 707
 708         gpio_set_value(gpio, 1);
 709         mdelay(20);
 710
 711         dev->current_page = 0xff;
 712 }
 713
 714 static int b53_switch_reset(struct b53_device *dev)
 715 {
 716         unsigned int timeout = 1000;
 717         u8 mgmt, reg;
 718
 719         b53_switch_reset_gpio(dev);
 720
 721         if (is539x(dev)) {
 722                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 723                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 724         }
 725
 726         /* This is specific to 58xx devices here, do not use is58xx() which
 727          * covers the larger Starfigther 2 family, including 7445/7278 which
 728          * still use this driver as a library and need to perform the reset
 729          * earlier.
 730          */
 731         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 732             dev->chip_id == BCM583XX_DEVICE_ID) {
 733                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 734                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 735                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 736
 737                 do {
 738                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 739                         if (!(reg & SW_RST))
 740                                 break;
 741
 742                         usleep_range(1000, 2000);
 743                 } while (timeout-- > 0);
 744
 745                 if (timeout == 0)
 746                         return -ETIMEDOUT;
 747         }
 748
 749         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 750
 751         if (!(mgmt & SM_SW_FWD_EN)) {
 752                 mgmt &= ~SM_SW_FWD_MODE;
 753                 mgmt |= SM_SW_FWD_EN;
 754
 755                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 756                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 757
 758                 if (!(mgmt & SM_SW_FWD_EN)) {
 759                         dev_err(dev->dev, "Failed to enable switch!\n");
 760                         return -EINVAL;
 761                 }
 762         }
 763
 764         b53_enable_mib(dev);
 765
 766         return b53_flush_arl(dev, FAST_AGE_STATIC);
 767 }
 768
 769 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 770 {
 771         struct b53_device *priv = ds->priv;
 772         u16 value = 0;
 773         int ret;
 774
 775         if (priv->ops->phy_read16)
 776                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 777         else
 778                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 779                                  reg * 2, &value);
 780
 781         return ret ? ret : value;
 782 }
 783
 784 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 785 {
 786         struct b53_device *priv = ds->priv;
 787
 788         if (priv->ops->phy_write16)
 789                 return priv->ops->phy_write16(priv, addr, reg, val);
 790
 791         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 792 }
 793
 794 static int b53_reset_switch(struct b53_device *priv)
 795 {
 796         /* reset vlans */
 797         priv->enable_jumbo = false;
 798
 799         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 800         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 801
 802         priv->serdes_lane = B53_INVALID_LANE;
 803
 804         return b53_switch_reset(priv);
 805 }
 806
 807 static int b53_apply_config(struct b53_device *priv)
 808 {
 809         /* disable switching */
 810         b53_set_forwarding(priv, 0);
 811
 812         b53_configure_vlan(priv->ds);
 813
 814         /* enable switching */
 815         b53_set_forwarding(priv, 1);
 816
 817         return 0;
 818 }
 819
 820 static void b53_reset_mib(struct b53_device *priv)
 821 {
 822         u8 gc;
 823
 824         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 825
 826         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 827         msleep(1);
 828         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 829         msleep(1);
 830 }
 831
 832 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 833 {
 834         if (is5365(dev))
 835                 return b53_mibs_65;
 836         else if (is63xx(dev))
 837                 return b53_mibs_63xx;
 838         else if (is58xx(dev))
 839                 return b53_mibs_58xx;
 840         else
 841                 return b53_mibs;
 842 }
 843
 844 static unsigned int b53_get_mib_size(struct b53_device *dev)
 845 {
 846         if (is5365(dev))
 847                 return B53_MIBS_65_SIZE;
 848         else if (is63xx(dev))
 849                 return B53_MIBS_63XX_SIZE;
 850         else if (is58xx(dev))
 851                 return B53_MIBS_58XX_SIZE;
 852         else
 853                 return B53_MIBS_SIZE;
 854 }
 855
 856 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 857 {
 858         /* These ports typically do not have built-in PHYs */
 859         switch (port) {
 860         case B53_CPU_PORT_25:
 861         case 7:
 862         case B53_CPU_PORT:
 863                 return NULL;
 864         }
 865
 866         return mdiobus_get_phy(ds->slave_mii_bus, port);
 867 }
 868
 869 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 870                      uint8_t *data)
 871 {
 872         struct b53_device *dev = ds->priv;
 873         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 874         unsigned int mib_size = b53_get_mib_size(dev);
 875         struct phy_device *phydev;
 876         unsigned int i;
 877
 878         if (stringset == ETH_SS_STATS) {
 879                 for (i = 0; i < mib_size; i++)
 880                         strlcpy(data + i * ETH_GSTRING_LEN,
 881                                 mibs[i].name, ETH_GSTRING_LEN);
 882         } else if (stringset == ETH_SS_PHY_STATS) {
 883                 phydev = b53_get_phy_device(ds, port);
 884                 if (!phydev)
 885                         return;
 886
 887                 phy_ethtool_get_strings(phydev, data);
 888         }
 889 }
 890 EXPORT_SYMBOL(b53_get_strings);
 891
 892 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 893 {
 894         struct b53_device *dev = ds->priv;
 895         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 896         unsigned int mib_size = b53_get_mib_size(dev);
 897         const struct b53_mib_desc *s;
 898         unsigned int i;
 899         u64 val = 0;
 900
 901         if (is5365(dev) && port == 5)
 902                 port = 8;
 903
 904         mutex_lock(&dev->stats_mutex);
 905
 906         for (i = 0; i < mib_size; i++) {
 907                 s = &mibs[i];
 908
 909                 if (s->size == 8) {
 910                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 911                 } else {
 912                         u32 val32;
 913
 914                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 915                                    &val32);
 916                         val = val32;
 917                 }
 918                 data[i] = (u64)val;
 919         }
 920
 921         mutex_unlock(&dev->stats_mutex);
 922 }
 923 EXPORT_SYMBOL(b53_get_ethtool_stats);
 924
 925 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 926 {
 927         struct phy_device *phydev;
 928
 929         phydev = b53_get_phy_device(ds, port);
 930         if (!phydev)
 931                 return;
 932
 933         phy_ethtool_get_stats(phydev, NULL, data);
 934 }
 935 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 936
 937 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 938 {
 939         struct b53_device *dev = ds->priv;
 940         struct phy_device *phydev;
 941
 942         if (sset == ETH_SS_STATS) {
 943                 return b53_get_mib_size(dev);
 944         } else if (sset == ETH_SS_PHY_STATS) {
 945                 phydev = b53_get_phy_device(ds, port);
 946                 if (!phydev)
 947                         return 0;
 948
 949                 return phy_ethtool_get_sset_count(phydev);
 950         }
 951
 952         return 0;
 953 }
 954 EXPORT_SYMBOL(b53_get_sset_count);
 955
 956 static int b53_setup(struct dsa_switch *ds)
 957 {
 958         struct b53_device *dev = ds->priv;
 959         unsigned int port;
 960         int ret;
 961
 962         ret = b53_reset_switch(dev);
 963         if (ret) {
 964                 dev_err(ds->dev, "failed to reset switch\n");
 965                 return ret;
 966         }
 967
 968         b53_reset_mib(dev);
 969
 970         ret = b53_apply_config(dev);
 971         if (ret)
 972                 dev_err(ds->dev, "failed to apply configuration\n");
 973
 974         /* Configure IMP/CPU port, disable all other ports. Enabled
 975          * ports will be configured with .port_enable
 976          */
 977         for (port = 0; port < dev->num_ports; port++) {
 978                 if (dsa_is_cpu_port(ds, port))
 979                         b53_enable_cpu_port(dev, port);
 980                 else
 981                         b53_disable_port(ds, port);
 982         }
 983
 984         /* Let DSA handle the case were multiple bridges span the same switch
 985          * device and different VLAN awareness settings are requested, which
 986          * would be breaking filtering semantics for any of the other bridge
 987          * devices. (not hardware supported)
 988          */
 989         ds->vlan_filtering_is_global = true;
 990
 991         return ret;
 992 }
 993
 994 static void b53_force_link(struct b53_device *dev, int port, int link)
 995 {
 996         u8 reg, val, off;
 997
 998         /* Override the port settings */
 999         if (port == dev->cpu_port) {
1000                 off = B53_PORT_OVERRIDE_CTRL;
1001                 val = PORT_OVERRIDE_EN;
1002         } else {
1003                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1004                 val = GMII_PO_EN;
1005         }
1006
1007         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1008         reg |= val;
1009         if (link)
1010                 reg |= PORT_OVERRIDE_LINK;
1011         else
1012                 reg &= ~PORT_OVERRIDE_LINK;
1013         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1014 }
1015
1016 static void b53_force_port_config(struct b53_device *dev, int port,
1017                                   int speed, int duplex, int pause)
1018 {
1019         u8 reg, val, off;
1020
1021         /* Override the port settings */
1022         if (port == dev->cpu_port) {
1023                 off = B53_PORT_OVERRIDE_CTRL;
1024                 val = PORT_OVERRIDE_EN;
1025         } else {
1026                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1027                 val = GMII_PO_EN;
1028         }
1029
1030         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1031         reg |= val;
1032         if (duplex == DUPLEX_FULL)
1033                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1034         else
1035                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1036
1037         switch (speed) {
1038         case 2000:
1039                 reg |= PORT_OVERRIDE_SPEED_2000M;
1040                 /* fallthrough */
1041         case SPEED_1000:
1042                 reg |= PORT_OVERRIDE_SPEED_1000M;
1043                 break;
1044         case SPEED_100:
1045                 reg |= PORT_OVERRIDE_SPEED_100M;
1046                 break;
1047         case SPEED_10:
1048                 reg |= PORT_OVERRIDE_SPEED_10M;
1049                 break;
1050         default:
1051                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1052                 return;
1053         }
1054
1055         if (pause & MLO_PAUSE_RX)
1056                 reg |= PORT_OVERRIDE_RX_FLOW;
1057         if (pause & MLO_PAUSE_TX)
1058                 reg |= PORT_OVERRIDE_TX_FLOW;
1059
1060         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1061 }
1062
1063 static void b53_adjust_link(struct dsa_switch *ds, int port,
1064                             struct phy_device *phydev)
1065 {
1066         struct b53_device *dev = ds->priv;
1067         struct ethtool_eee *p = &dev->ports[port].eee;
1068         u8 rgmii_ctrl = 0, reg = 0, off;
1069         int pause = 0;
1070
1071         if (!phy_is_pseudo_fixed_link(phydev))
1072                 return;
1073
1074         /* Enable flow control on BCM5301x's CPU port */
1075         if (is5301x(dev) && port == dev->cpu_port)
1076                 pause = MLO_PAUSE_TXRX_MASK;
1077
1078         if (phydev->pause) {
1079                 if (phydev->asym_pause)
1080                         pause |= MLO_PAUSE_TX;
1081                 pause |= MLO_PAUSE_RX;
1082         }
1083
1084         b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause);
1085         b53_force_link(dev, port, phydev->link);
1086
1087         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1088                 if (port == 8)
1089                         off = B53_RGMII_CTRL_IMP;
1090                 else
1091                         off = B53_RGMII_CTRL_P(port);
1092
1093                 /* Configure the port RGMII clock delay by DLL disabled and
1094                  * tx_clk aligned timing (restoring to reset defaults)
1095                  */
1096                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1097                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1098                                 RGMII_CTRL_TIMING_SEL);
1099
1100                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1101                  * sure that we enable the port TX clock internal delay to
1102                  * account for this internal delay that is inserted, otherwise
1103                  * the switch won't be able to receive correctly.
1104                  *
1105                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1106                  * any delay neither on transmission nor reception, so the
1107                  * BCM53125 must also be configured accordingly to account for
1108                  * the lack of delay and introduce
1109                  *
1110                  * The BCM53125 switch has its RX clock and TX clock control
1111                  * swapped, hence the reason why we modify the TX clock path in
1112                  * the "RGMII" case
1113                  */
1114                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1115                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1116                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1117                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1118                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1119                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1120
1121                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1122                          phy_modes(phydev->interface));
1123         }
1124
1125         /* configure MII port if necessary */
1126         if (is5325(dev)) {
1127                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1128                           &reg);
1129
1130                 /* reverse mii needs to be enabled */
1131                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1132                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1133                                    reg | PORT_OVERRIDE_RV_MII_25);
1134                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1135                                   &reg);
1136
1137                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1138                                 dev_err(ds->dev,
1139                                         "Failed to enable reverse MII mode\n");
1140                                 return;
1141                         }
1142                 }
1143         } else if (is5301x(dev)) {
1144                 if (port != dev->cpu_port) {
1145                         b53_force_port_config(dev, dev->cpu_port, 2000,
1146                                               DUPLEX_FULL, MLO_PAUSE_TXRX_MASK);
1147                         b53_force_link(dev, dev->cpu_port, 1);
1148                 }
1149         }
1150
1151         /* Re-negotiate EEE if it was enabled already */
1152         p->eee_enabled = b53_eee_init(ds, port, phydev);
1153 }
1154
1155 void b53_port_event(struct dsa_switch *ds, int port)
1156 {
1157         struct b53_device *dev = ds->priv;
1158         bool link;
1159         u16 sts;
1160
1161         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1162         link = !!(sts & BIT(port));
1163         dsa_port_phylink_mac_change(ds, port, link);
1164 }
1165 EXPORT_SYMBOL(b53_port_event);
1166
1167 void b53_phylink_validate(struct dsa_switch *ds, int port,
1168                           unsigned long *supported,
1169                           struct phylink_link_state *state)
1170 {
1171         struct b53_device *dev = ds->priv;
1172         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1173
1174         if (dev->ops->serdes_phylink_validate)
1175                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1176
1177         /* Allow all the expected bits */
1178         phylink_set(mask, Autoneg);
1179         phylink_set_port_modes(mask);
1180         phylink_set(mask, Pause);
1181         phylink_set(mask, Asym_Pause);
1182
1183         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1184          * support Gigabit, including Half duplex.
1185          */
1186         if (state->interface != PHY_INTERFACE_MODE_MII &&
1187             state->interface != PHY_INTERFACE_MODE_REVMII &&
1188             !phy_interface_mode_is_8023z(state->interface) &&
1189             !(is5325(dev) || is5365(dev))) {
1190                 phylink_set(mask, 1000baseT_Full);
1191                 phylink_set(mask, 1000baseT_Half);
1192         }
1193
1194         if (!phy_interface_mode_is_8023z(state->interface)) {
1195                 phylink_set(mask, 10baseT_Half);
1196                 phylink_set(mask, 10baseT_Full);
1197                 phylink_set(mask, 100baseT_Half);
1198                 phylink_set(mask, 100baseT_Full);
1199         }
1200
1201         bitmap_and(supported, supported, mask,
1202                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1203         bitmap_and(state->advertising, state->advertising, mask,
1204                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1205
1206         phylink_helper_basex_speed(state);
1207 }
1208 EXPORT_SYMBOL(b53_phylink_validate);
1209
1210 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1211                                struct phylink_link_state *state)
1212 {
1213         struct b53_device *dev = ds->priv;
1214         int ret = -EOPNOTSUPP;
1215
1216         if ((phy_interface_mode_is_8023z(state->interface) ||
1217              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1218              dev->ops->serdes_link_state)
1219                 ret = dev->ops->serdes_link_state(dev, port, state);
1220
1221         return ret;
1222 }
1223 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1224
1225 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1226                             unsigned int mode,
1227                             const struct phylink_link_state *state)
1228 {
1229         struct b53_device *dev = ds->priv;
1230
1231         if (mode == MLO_AN_PHY)
1232                 return;
1233
1234         if (mode == MLO_AN_FIXED) {
1235                 b53_force_port_config(dev, port, state->speed,
1236                                       state->duplex, state->pause);
1237                 return;
1238         }
1239
1240         if ((phy_interface_mode_is_8023z(state->interface) ||
1241              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1242              dev->ops->serdes_config)
1243                 dev->ops->serdes_config(dev, port, mode, state);
1244 }
1245 EXPORT_SYMBOL(b53_phylink_mac_config);
1246
1247 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1248 {
1249         struct b53_device *dev = ds->priv;
1250
1251         if (dev->ops->serdes_an_restart)
1252                 dev->ops->serdes_an_restart(dev, port);
1253 }
1254 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1255
1256 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1257                                unsigned int mode,
1258                                phy_interface_t interface)
1259 {
1260         struct b53_device *dev = ds->priv;
1261
1262         if (mode == MLO_AN_PHY)
1263                 return;
1264
1265         if (mode == MLO_AN_FIXED) {
1266                 b53_force_link(dev, port, false);
1267                 return;
1268         }
1269
1270         if (phy_interface_mode_is_8023z(interface) &&
1271             dev->ops->serdes_link_set)
1272                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1273 }
1274 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1275
1276 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1277                              unsigned int mode,
1278                              phy_interface_t interface,
1279                              struct phy_device *phydev)
1280 {
1281         struct b53_device *dev = ds->priv;
1282
1283         if (mode == MLO_AN_PHY)
1284                 return;
1285
1286         if (mode == MLO_AN_FIXED) {
1287                 b53_force_link(dev, port, true);
1288                 return;
1289         }
1290
1291         if (phy_interface_mode_is_8023z(interface) &&
1292             dev->ops->serdes_link_set)
1293                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1294 }
1295 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1296
1297 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1298 {
1299         struct b53_device *dev = ds->priv;
1300         u16 pvid, new_pvid;
1301
1302         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1303         new_pvid = pvid;
1304         if (!vlan_filtering) {
1305                 /* Filtering is currently enabled, use the default PVID since
1306                  * the bridge does not expect tagging anymore
1307                  */
1308                 dev->ports[port].pvid = pvid;
1309                 new_pvid = b53_default_pvid(dev);
1310         } else {
1311                 /* Filtering is currently disabled, restore the previous PVID */
1312                 new_pvid = dev->ports[port].pvid;
1313         }
1314
1315         if (pvid != new_pvid)
1316                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1317                             new_pvid);
1318
1319         b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1320
1321         return 0;
1322 }
1323 EXPORT_SYMBOL(b53_vlan_filtering);
1324
1325 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1326                      const struct switchdev_obj_port_vlan *vlan)
1327 {
1328         struct b53_device *dev = ds->priv;
1329
1330         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1331                 return -EOPNOTSUPP;
1332
1333         if (vlan->vid_end > dev->num_vlans)
1334                 return -ERANGE;
1335
1336         b53_enable_vlan(dev, true, ds->vlan_filtering);
1337
1338         return 0;
1339 }
1340 EXPORT_SYMBOL(b53_vlan_prepare);
1341
1342 void b53_vlan_add(struct dsa_switch *ds, int port,
1343                   const struct switchdev_obj_port_vlan *vlan)
1344 {
1345         struct b53_device *dev = ds->priv;
1346         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1347         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1348         struct b53_vlan *vl;
1349         u16 vid;
1350
1351         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1352                 vl = &dev->vlans[vid];
1353
1354                 b53_get_vlan_entry(dev, vid, vl);
1355
1356                 if (vid == 0 && vid == b53_default_pvid(dev))
1357                         untagged = true;
1358
1359                 vl->members |= BIT(port);
1360                 if (untagged && !dsa_is_cpu_port(ds, port))
1361                         vl->untag |= BIT(port);
1362                 else
1363                         vl->untag &= ~BIT(port);
1364
1365                 b53_set_vlan_entry(dev, vid, vl);
1366                 b53_fast_age_vlan(dev, vid);
1367         }
1368
1369         if (pvid && !dsa_is_cpu_port(ds, port)) {
1370                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1371                             vlan->vid_end);
1372                 b53_fast_age_vlan(dev, vid);
1373         }
1374 }
1375 EXPORT_SYMBOL(b53_vlan_add);
1376
1377 int b53_vlan_del(struct dsa_switch *ds, int port,
1378                  const struct switchdev_obj_port_vlan *vlan)
1379 {
1380         struct b53_device *dev = ds->priv;
1381         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1382         struct b53_vlan *vl;
1383         u16 vid;
1384         u16 pvid;
1385
1386         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1387
1388         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1389                 vl = &dev->vlans[vid];
1390
1391                 b53_get_vlan_entry(dev, vid, vl);
1392
1393                 vl->members &= ~BIT(port);
1394
1395                 if (pvid == vid)
1396                         pvid = b53_default_pvid(dev);
1397
1398                 if (untagged && !dsa_is_cpu_port(ds, port))
1399                         vl->untag &= ~(BIT(port));
1400
1401                 b53_set_vlan_entry(dev, vid, vl);
1402                 b53_fast_age_vlan(dev, vid);
1403         }
1404
1405         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1406         b53_fast_age_vlan(dev, pvid);
1407
1408         return 0;
1409 }
1410 EXPORT_SYMBOL(b53_vlan_del);
1411
1412 /* Address Resolution Logic routines */
1413 static int b53_arl_op_wait(struct b53_device *dev)
1414 {
1415         unsigned int timeout = 10;
1416         u8 reg;
1417
1418         do {
1419                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1420                 if (!(reg & ARLTBL_START_DONE))
1421                         return 0;
1422
1423                 usleep_range(1000, 2000);
1424         } while (timeout--);
1425
1426         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1427
1428         return -ETIMEDOUT;
1429 }
1430
1431 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1432 {
1433         u8 reg;
1434
1435         if (op > ARLTBL_RW)
1436                 return -EINVAL;
1437
1438         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1439         reg |= ARLTBL_START_DONE;
1440         if (op)
1441                 reg |= ARLTBL_RW;
1442         else
1443                 reg &= ~ARLTBL_RW;
1444         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1445
1446         return b53_arl_op_wait(dev);
1447 }
1448
1449 static int b53_arl_read(struct b53_device *dev, u64 mac,
1450                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1451                         bool is_valid)
1452 {
1453         DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1454         unsigned int i;
1455         int ret;
1456
1457         ret = b53_arl_op_wait(dev);
1458         if (ret)
1459                 return ret;
1460
1461         bitmap_zero(free_bins, dev->num_arl_entries);
1462
1463         /* Read the bins */
1464         for (i = 0; i < dev->num_arl_entries; i++) {
1465                 u64 mac_vid;
1466                 u32 fwd_entry;
1467
1468                 b53_read64(dev, B53_ARLIO_PAGE,
1469                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1470                 b53_read32(dev, B53_ARLIO_PAGE,
1471                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1472                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1473
1474                 if (!(fwd_entry & ARLTBL_VALID)) {
1475                         set_bit(i, free_bins);
1476                         continue;
1477                 }
1478                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1479                         continue;
1480                 if (dev->vlan_enabled &&
1481                     ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1482                         continue;
1483                 *idx = i;
1484                 return 0;
1485         }
1486
1487         if (bitmap_weight(free_bins, dev->num_arl_entries) == 0)
1488                 return -ENOSPC;
1489
1490         *idx = find_first_bit(free_bins, dev->num_arl_entries);
1491
1492         return -ENOENT;
1493 }
1494
1495 static int b53_arl_op(struct b53_device *dev, int op, int port,
1496                       const unsigned char *addr, u16 vid, bool is_valid)
1497 {
1498         struct b53_arl_entry ent;
1499         u32 fwd_entry;
1500         u64 mac, mac_vid = 0;
1501         u8 idx = 0;
1502         int ret;
1503
1504         /* Convert the array into a 64-bit MAC */
1505         mac = ether_addr_to_u64(addr);
1506
1507         /* Perform a read for the given MAC and VID */
1508         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1509         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1510
1511         /* Issue a read operation for this MAC */
1512         ret = b53_arl_rw_op(dev, 1);
1513         if (ret)
1514                 return ret;
1515
1516         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1517         /* If this is a read, just finish now */
1518         if (op)
1519                 return ret;
1520
1521         switch (ret) {
1522         case -ENOSPC:
1523                 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1524                         addr, vid);
1525                 return is_valid ? ret : 0;
1526         case -ENOENT:
1527                 /* We could not find a matching MAC, so reset to a new entry */
1528                 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1529                         addr, vid, idx);
1530                 fwd_entry = 0;
1531                 break;
1532         default:
1533                 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1534                         addr, vid, idx);
1535                 break;
1536         }
1537
1538         memset(&ent, 0, sizeof(ent));
1539         ent.port = port;
1540         ent.vid = vid;
1541         ent.is_static = true;
1542         memcpy(ent.mac, addr, ETH_ALEN);
1543         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1544
1545         b53_write64(dev, B53_ARLIO_PAGE,
1546                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1547         b53_write32(dev, B53_ARLIO_PAGE,
1548                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1549
1550         return b53_arl_rw_op(dev, 0);
1551 }
1552
1553 int b53_fdb_add(struct dsa_switch *ds, int port,
1554                 const unsigned char *addr, u16 vid)
1555 {
1556         struct b53_device *priv = ds->priv;
1557
1558         /* 5325 and 5365 require some more massaging, but could
1559          * be supported eventually
1560          */
1561         if (is5325(priv) || is5365(priv))
1562                 return -EOPNOTSUPP;
1563
1564         return b53_arl_op(priv, 0, port, addr, vid, true);
1565 }
1566 EXPORT_SYMBOL(b53_fdb_add);
1567
1568 int b53_fdb_del(struct dsa_switch *ds, int port,
1569                 const unsigned char *addr, u16 vid)
1570 {
1571         struct b53_device *priv = ds->priv;
1572
1573         return b53_arl_op(priv, 0, port, addr, vid, false);
1574 }
1575 EXPORT_SYMBOL(b53_fdb_del);
1576
1577 static int b53_arl_search_wait(struct b53_device *dev)
1578 {
1579         unsigned int timeout = 1000;
1580         u8 reg;
1581
1582         do {
1583                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1584                 if (!(reg & ARL_SRCH_STDN))
1585                         return 0;
1586
1587                 if (reg & ARL_SRCH_VLID)
1588                         return 0;
1589
1590                 usleep_range(1000, 2000);
1591         } while (timeout--);
1592
1593         return -ETIMEDOUT;
1594 }
1595
1596 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1597                               struct b53_arl_entry *ent)
1598 {
1599         u64 mac_vid;
1600         u32 fwd_entry;
1601
1602         b53_read64(dev, B53_ARLIO_PAGE,
1603                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1604         b53_read32(dev, B53_ARLIO_PAGE,
1605                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1606         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1607 }
1608
1609 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1610                         dsa_fdb_dump_cb_t *cb, void *data)
1611 {
1612         if (!ent->is_valid)
1613                 return 0;
1614
1615         if (port != ent->port)
1616                 return 0;
1617
1618         return cb(ent->mac, ent->vid, ent->is_static, data);
1619 }
1620
1621 int b53_fdb_dump(struct dsa_switch *ds, int port,
1622                  dsa_fdb_dump_cb_t *cb, void *data)
1623 {
1624         struct b53_device *priv = ds->priv;
1625         struct b53_arl_entry results[2];
1626         unsigned int count = 0;
1627         int ret;
1628         u8 reg;
1629
1630         /* Start search operation */
1631         reg = ARL_SRCH_STDN;
1632         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1633
1634         do {
1635                 ret = b53_arl_search_wait(priv);
1636                 if (ret)
1637                         return ret;
1638
1639                 b53_arl_search_rd(priv, 0, &results[0]);
1640                 ret = b53_fdb_copy(port, &results[0], cb, data);
1641                 if (ret)
1642                         return ret;
1643
1644                 if (priv->num_arl_entries > 2) {
1645                         b53_arl_search_rd(priv, 1, &results[1]);
1646                         ret = b53_fdb_copy(port, &results[1], cb, data);
1647                         if (ret)
1648                                 return ret;
1649
1650                         if (!results[0].is_valid && !results[1].is_valid)
1651                                 break;
1652                 }
1653
1654         } while (count++ < 1024);
1655
1656         return 0;
1657 }
1658 EXPORT_SYMBOL(b53_fdb_dump);
1659
1660 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1661 {
1662         struct b53_device *dev = ds->priv;
1663         s8 cpu_port = ds->ports[port].cpu_dp->index;
1664         u16 pvlan, reg;
1665         unsigned int i;
1666
1667         /* Make this port leave the all VLANs join since we will have proper
1668          * VLAN entries from now on
1669          */
1670         if (is58xx(dev)) {
1671                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1672                 reg &= ~BIT(port);
1673                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1674                         reg &= ~BIT(cpu_port);
1675                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1676         }
1677
1678         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1679
1680         b53_for_each_port(dev, i) {
1681                 if (dsa_to_port(ds, i)->bridge_dev != br)
1682                         continue;
1683
1684                 /* Add this local port to the remote port VLAN control
1685                  * membership and update the remote port bitmask
1686                  */
1687                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1688                 reg |= BIT(port);
1689                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1690                 dev->ports[i].vlan_ctl_mask = reg;
1691
1692                 pvlan |= BIT(i);
1693         }
1694
1695         /* Configure the local port VLAN control membership to include
1696          * remote ports and update the local port bitmask
1697          */
1698         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1699         dev->ports[port].vlan_ctl_mask = pvlan;
1700
1701         return 0;
1702 }
1703 EXPORT_SYMBOL(b53_br_join);
1704
1705 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1706 {
1707         struct b53_device *dev = ds->priv;
1708         struct b53_vlan *vl = &dev->vlans[0];
1709         s8 cpu_port = ds->ports[port].cpu_dp->index;
1710         unsigned int i;
1711         u16 pvlan, reg, pvid;
1712
1713         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1714
1715         b53_for_each_port(dev, i) {
1716                 /* Don't touch the remaining ports */
1717                 if (dsa_to_port(ds, i)->bridge_dev != br)
1718                         continue;
1719
1720                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1721                 reg &= ~BIT(port);
1722                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1723                 dev->ports[port].vlan_ctl_mask = reg;
1724
1725                 /* Prevent self removal to preserve isolation */
1726                 if (port != i)
1727                         pvlan &= ~BIT(i);
1728         }
1729
1730         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1731         dev->ports[port].vlan_ctl_mask = pvlan;
1732
1733         pvid = b53_default_pvid(dev);
1734
1735         /* Make this port join all VLANs without VLAN entries */
1736         if (is58xx(dev)) {
1737                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1738                 reg |= BIT(port);
1739                 if (!(reg & BIT(cpu_port)))
1740                         reg |= BIT(cpu_port);
1741                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1742         } else {
1743                 b53_get_vlan_entry(dev, pvid, vl);
1744                 vl->members |= BIT(port) | BIT(cpu_port);
1745                 vl->untag |= BIT(port) | BIT(cpu_port);
1746                 b53_set_vlan_entry(dev, pvid, vl);
1747         }
1748 }
1749 EXPORT_SYMBOL(b53_br_leave);
1750
1751 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1752 {
1753         struct b53_device *dev = ds->priv;
1754         u8 hw_state;
1755         u8 reg;
1756
1757         switch (state) {
1758         case BR_STATE_DISABLED:
1759                 hw_state = PORT_CTRL_DIS_STATE;
1760                 break;
1761         case BR_STATE_LISTENING:
1762                 hw_state = PORT_CTRL_LISTEN_STATE;
1763                 break;
1764         case BR_STATE_LEARNING:
1765                 hw_state = PORT_CTRL_LEARN_STATE;
1766                 break;
1767         case BR_STATE_FORWARDING:
1768                 hw_state = PORT_CTRL_FWD_STATE;
1769                 break;
1770         case BR_STATE_BLOCKING:
1771                 hw_state = PORT_CTRL_BLOCK_STATE;
1772                 break;
1773         default:
1774                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1775                 return;
1776         }
1777
1778         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1779         reg &= ~PORT_CTRL_STP_STATE_MASK;
1780         reg |= hw_state;
1781         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1782 }
1783 EXPORT_SYMBOL(b53_br_set_stp_state);
1784
1785 void b53_br_fast_age(struct dsa_switch *ds, int port)
1786 {
1787         struct b53_device *dev = ds->priv;
1788
1789         if (b53_fast_age_port(dev, port))
1790                 dev_err(ds->dev, "fast ageing failed\n");
1791 }
1792 EXPORT_SYMBOL(b53_br_fast_age);
1793
1794 int b53_br_egress_floods(struct dsa_switch *ds, int port,
1795                          bool unicast, bool multicast)
1796 {
1797         struct b53_device *dev = ds->priv;
1798         u16 uc, mc;
1799
1800         b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
1801         if (unicast)
1802                 uc |= BIT(port);
1803         else
1804                 uc &= ~BIT(port);
1805         b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
1806
1807         b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
1808         if (multicast)
1809                 mc |= BIT(port);
1810         else
1811                 mc &= ~BIT(port);
1812         b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
1813
1814         b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
1815         if (multicast)
1816                 mc |= BIT(port);
1817         else
1818                 mc &= ~BIT(port);
1819         b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
1820
1821         return 0;
1822
1823 }
1824 EXPORT_SYMBOL(b53_br_egress_floods);
1825
1826 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1827 {
1828         /* Broadcom switches will accept enabling Broadcom tags on the
1829          * following ports: 5, 7 and 8, any other port is not supported
1830          */
1831         switch (port) {
1832         case B53_CPU_PORT_25:
1833         case 7:
1834         case B53_CPU_PORT:
1835                 return true;
1836         }
1837
1838         return false;
1839 }
1840
1841 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1842 {
1843         bool ret = b53_possible_cpu_port(ds, port);
1844
1845         if (!ret)
1846                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1847                          port);
1848         return ret;
1849 }
1850
1851 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1852 {
1853         struct b53_device *dev = ds->priv;
1854
1855         /* Older models (5325, 5365) support a different tag format that we do
1856          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1857          * mode to be turned on which means we need to specifically manage ARL
1858          * misses on multicast addresses (TBD).
1859          */
1860         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1861             !b53_can_enable_brcm_tags(ds, port))
1862                 return DSA_TAG_PROTO_NONE;
1863
1864         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1865          * which requires us to use the prepended Broadcom tag type
1866          */
1867         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1868                 return DSA_TAG_PROTO_BRCM_PREPEND;
1869
1870         return DSA_TAG_PROTO_BRCM;
1871 }
1872 EXPORT_SYMBOL(b53_get_tag_protocol);
1873
1874 int b53_mirror_add(struct dsa_switch *ds, int port,
1875                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1876 {
1877         struct b53_device *dev = ds->priv;
1878         u16 reg, loc;
1879
1880         if (ingress)
1881                 loc = B53_IG_MIR_CTL;
1882         else
1883                 loc = B53_EG_MIR_CTL;
1884
1885         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1886         reg |= BIT(port);
1887         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1888
1889         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1890         reg &= ~CAP_PORT_MASK;
1891         reg |= mirror->to_local_port;
1892         reg |= MIRROR_EN;
1893         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1894
1895         return 0;
1896 }
1897 EXPORT_SYMBOL(b53_mirror_add);
1898
1899 void b53_mirror_del(struct dsa_switch *ds, int port,
1900                     struct dsa_mall_mirror_tc_entry *mirror)
1901 {
1902         struct b53_device *dev = ds->priv;
1903         bool loc_disable = false, other_loc_disable = false;
1904         u16 reg, loc;
1905
1906         if (mirror->ingress)
1907                 loc = B53_IG_MIR_CTL;
1908         else
1909                 loc = B53_EG_MIR_CTL;
1910
1911         /* Update the desired ingress/egress register */
1912         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1913         reg &= ~BIT(port);
1914         if (!(reg & MIRROR_MASK))
1915                 loc_disable = true;
1916         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1917
1918         /* Now look at the other one to know if we can disable mirroring
1919          * entirely
1920          */
1921         if (mirror->ingress)
1922                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1923         else
1924                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1925         if (!(reg & MIRROR_MASK))
1926                 other_loc_disable = true;
1927
1928         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1929         /* Both no longer have ports, let's disable mirroring */
1930         if (loc_disable && other_loc_disable) {
1931                 reg &= ~MIRROR_EN;
1932                 reg &= ~mirror->to_local_port;
1933         }
1934         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1935 }
1936 EXPORT_SYMBOL(b53_mirror_del);
1937
1938 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1939 {
1940         struct b53_device *dev = ds->priv;
1941         u16 reg;
1942
1943         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1944         if (enable)
1945                 reg |= BIT(port);
1946         else
1947                 reg &= ~BIT(port);
1948         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1949 }
1950 EXPORT_SYMBOL(b53_eee_enable_set);
1951
1952
1953 /* Returns 0 if EEE was not enabled, or 1 otherwise
1954  */
1955 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1956 {
1957         int ret;
1958
1959         ret = phy_init_eee(phy, 0);
1960         if (ret)
1961                 return 0;
1962
1963         b53_eee_enable_set(ds, port, true);
1964
1965         return 1;
1966 }
1967 EXPORT_SYMBOL(b53_eee_init);
1968
1969 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1970 {
1971         struct b53_device *dev = ds->priv;
1972         struct ethtool_eee *p = &dev->ports[port].eee;
1973         u16 reg;
1974
1975         if (is5325(dev) || is5365(dev))
1976                 return -EOPNOTSUPP;
1977
1978         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1979         e->eee_enabled = p->eee_enabled;
1980         e->eee_active = !!(reg & BIT(port));
1981
1982         return 0;
1983 }
1984 EXPORT_SYMBOL(b53_get_mac_eee);
1985
1986 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1987 {
1988         struct b53_device *dev = ds->priv;
1989         struct ethtool_eee *p = &dev->ports[port].eee;
1990
1991         if (is5325(dev) || is5365(dev))
1992                 return -EOPNOTSUPP;
1993
1994         p->eee_enabled = e->eee_enabled;
1995         b53_eee_enable_set(ds, port, e->eee_enabled);
1996
1997         return 0;
1998 }
1999 EXPORT_SYMBOL(b53_set_mac_eee);
2000
2001 static const struct dsa_switch_ops b53_switch_ops = {
2002         .get_tag_protocol       = b53_get_tag_protocol,
2003         .setup                  = b53_setup,
2004         .get_strings            = b53_get_strings,
2005         .get_ethtool_stats      = b53_get_ethtool_stats,
2006         .get_sset_count         = b53_get_sset_count,
2007         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
2008         .phy_read               = b53_phy_read16,
2009         .phy_write              = b53_phy_write16,
2010         .adjust_link            = b53_adjust_link,
2011         .phylink_validate       = b53_phylink_validate,
2012         .phylink_mac_link_state = b53_phylink_mac_link_state,
2013         .phylink_mac_config     = b53_phylink_mac_config,
2014         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2015         .phylink_mac_link_down  = b53_phylink_mac_link_down,
2016         .phylink_mac_link_up    = b53_phylink_mac_link_up,
2017         .port_enable            = b53_enable_port,
2018         .port_disable           = b53_disable_port,
2019         .get_mac_eee            = b53_get_mac_eee,
2020         .set_mac_eee            = b53_set_mac_eee,
2021         .port_bridge_join       = b53_br_join,
2022         .port_bridge_leave      = b53_br_leave,
2023         .port_stp_state_set     = b53_br_set_stp_state,
2024         .port_fast_age          = b53_br_fast_age,
2025         .port_egress_floods     = b53_br_egress_floods,
2026         .port_vlan_filtering    = b53_vlan_filtering,
2027         .port_vlan_prepare      = b53_vlan_prepare,
2028         .port_vlan_add          = b53_vlan_add,
2029         .port_vlan_del          = b53_vlan_del,
2030         .port_fdb_dump          = b53_fdb_dump,
2031         .port_fdb_add           = b53_fdb_add,
2032         .port_fdb_del           = b53_fdb_del,
2033         .port_mirror_add        = b53_mirror_add,
2034         .port_mirror_del        = b53_mirror_del,
2035 };
2036
2037 struct b53_chip_data {
2038         u32 chip_id;
2039         const char *dev_name;
2040         u16 vlans;
2041         u16 enabled_ports;
2042         u8 cpu_port;
2043         u8 vta_regs[3];
2044         u8 arl_entries;
2045         u8 duplex_reg;
2046         u8 jumbo_pm_reg;
2047         u8 jumbo_size_reg;
2048 };
2049
2050 #define B53_VTA_REGS    \
2051         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2052 #define B53_VTA_REGS_9798 \
2053         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2054 #define B53_VTA_REGS_63XX \
2055         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2056
2057 static const struct b53_chip_data b53_switch_chips[] = {
2058         {
2059                 .chip_id = BCM5325_DEVICE_ID,
2060                 .dev_name = "BCM5325",
2061                 .vlans = 16,
2062                 .enabled_ports = 0x1f,
2063                 .arl_entries = 2,
2064                 .cpu_port = B53_CPU_PORT_25,
2065                 .duplex_reg = B53_DUPLEX_STAT_FE,
2066         },
2067         {
2068                 .chip_id = BCM5365_DEVICE_ID,
2069                 .dev_name = "BCM5365",
2070                 .vlans = 256,
2071                 .enabled_ports = 0x1f,
2072                 .arl_entries = 2,
2073                 .cpu_port = B53_CPU_PORT_25,
2074                 .duplex_reg = B53_DUPLEX_STAT_FE,
2075         },
2076         {
2077                 .chip_id = BCM5389_DEVICE_ID,
2078                 .dev_name = "BCM5389",
2079                 .vlans = 4096,
2080                 .enabled_ports = 0x1f,
2081                 .arl_entries = 4,
2082                 .cpu_port = B53_CPU_PORT,
2083                 .vta_regs = B53_VTA_REGS,
2084                 .duplex_reg = B53_DUPLEX_STAT_GE,
2085                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2086                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2087         },
2088         {
2089                 .chip_id = BCM5395_DEVICE_ID,
2090                 .dev_name = "BCM5395",
2091                 .vlans = 4096,
2092                 .enabled_ports = 0x1f,
2093                 .arl_entries = 4,
2094                 .cpu_port = B53_CPU_PORT,
2095                 .vta_regs = B53_VTA_REGS,
2096                 .duplex_reg = B53_DUPLEX_STAT_GE,
2097                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2098                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2099         },
2100         {
2101                 .chip_id = BCM5397_DEVICE_ID,
2102                 .dev_name = "BCM5397",
2103                 .vlans = 4096,
2104                 .enabled_ports = 0x1f,
2105                 .arl_entries = 4,
2106                 .cpu_port = B53_CPU_PORT,
2107                 .vta_regs = B53_VTA_REGS_9798,
2108                 .duplex_reg = B53_DUPLEX_STAT_GE,
2109                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2110                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2111         },
2112         {
2113                 .chip_id = BCM5398_DEVICE_ID,
2114                 .dev_name = "BCM5398",
2115                 .vlans = 4096,
2116                 .enabled_ports = 0x7f,
2117                 .arl_entries = 4,
2118                 .cpu_port = B53_CPU_PORT,
2119                 .vta_regs = B53_VTA_REGS_9798,
2120                 .duplex_reg = B53_DUPLEX_STAT_GE,
2121                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2122                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2123         },
2124         {
2125                 .chip_id = BCM53115_DEVICE_ID,
2126                 .dev_name = "BCM53115",
2127                 .vlans = 4096,
2128                 .enabled_ports = 0x1f,
2129                 .arl_entries = 4,
2130                 .vta_regs = B53_VTA_REGS,
2131                 .cpu_port = B53_CPU_PORT,
2132                 .duplex_reg = B53_DUPLEX_STAT_GE,
2133                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2134                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2135         },
2136         {
2137                 .chip_id = BCM53125_DEVICE_ID,
2138                 .dev_name = "BCM53125",
2139                 .vlans = 4096,
2140                 .enabled_ports = 0xff,
2141                 .arl_entries = 4,
2142                 .cpu_port = B53_CPU_PORT,
2143                 .vta_regs = B53_VTA_REGS,
2144                 .duplex_reg = B53_DUPLEX_STAT_GE,
2145                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2146                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2147         },
2148         {
2149                 .chip_id = BCM53128_DEVICE_ID,
2150                 .dev_name = "BCM53128",
2151                 .vlans = 4096,
2152                 .enabled_ports = 0x1ff,
2153                 .arl_entries = 4,
2154                 .cpu_port = B53_CPU_PORT,
2155                 .vta_regs = B53_VTA_REGS,
2156                 .duplex_reg = B53_DUPLEX_STAT_GE,
2157                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2158                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2159         },
2160         {
2161                 .chip_id = BCM63XX_DEVICE_ID,
2162                 .dev_name = "BCM63xx",
2163                 .vlans = 4096,
2164                 .enabled_ports = 0, /* pdata must provide them */
2165                 .arl_entries = 4,
2166                 .cpu_port = B53_CPU_PORT,
2167                 .vta_regs = B53_VTA_REGS_63XX,
2168                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2169                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2170                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2171         },
2172         {
2173                 .chip_id = BCM53010_DEVICE_ID,
2174                 .dev_name = "BCM53010",
2175                 .vlans = 4096,
2176                 .enabled_ports = 0x1f,
2177                 .arl_entries = 4,
2178                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2179                 .vta_regs = B53_VTA_REGS,
2180                 .duplex_reg = B53_DUPLEX_STAT_GE,
2181                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2182                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2183         },
2184         {
2185                 .chip_id = BCM53011_DEVICE_ID,
2186                 .dev_name = "BCM53011",
2187                 .vlans = 4096,
2188                 .enabled_ports = 0x1bf,
2189                 .arl_entries = 4,
2190                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2191                 .vta_regs = B53_VTA_REGS,
2192                 .duplex_reg = B53_DUPLEX_STAT_GE,
2193                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2194                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2195         },
2196         {
2197                 .chip_id = BCM53012_DEVICE_ID,
2198                 .dev_name = "BCM53012",
2199                 .vlans = 4096,
2200                 .enabled_ports = 0x1bf,
2201                 .arl_entries = 4,
2202                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2203                 .vta_regs = B53_VTA_REGS,
2204                 .duplex_reg = B53_DUPLEX_STAT_GE,
2205                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2206                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2207         },
2208         {
2209                 .chip_id = BCM53018_DEVICE_ID,
2210                 .dev_name = "BCM53018",
2211                 .vlans = 4096,
2212                 .enabled_ports = 0x1f,
2213                 .arl_entries = 4,
2214                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2215                 .vta_regs = B53_VTA_REGS,
2216                 .duplex_reg = B53_DUPLEX_STAT_GE,
2217                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2218                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2219         },
2220         {
2221                 .chip_id = BCM53019_DEVICE_ID,
2222                 .dev_name = "BCM53019",
2223                 .vlans = 4096,
2224                 .enabled_ports = 0x1f,
2225                 .arl_entries = 4,
2226                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2227                 .vta_regs = B53_VTA_REGS,
2228                 .duplex_reg = B53_DUPLEX_STAT_GE,
2229                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2230                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2231         },
2232         {
2233                 .chip_id = BCM58XX_DEVICE_ID,
2234                 .dev_name = "BCM585xx/586xx/88312",
2235                 .vlans  = 4096,
2236                 .enabled_ports = 0x1ff,
2237                 .arl_entries = 4,
2238                 .cpu_port = B53_CPU_PORT,
2239                 .vta_regs = B53_VTA_REGS,
2240                 .duplex_reg = B53_DUPLEX_STAT_GE,
2241                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2242                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2243         },
2244         {
2245                 .chip_id = BCM583XX_DEVICE_ID,
2246                 .dev_name = "BCM583xx/11360",
2247                 .vlans = 4096,
2248                 .enabled_ports = 0x103,
2249                 .arl_entries = 4,
2250                 .cpu_port = B53_CPU_PORT,
2251                 .vta_regs = B53_VTA_REGS,
2252                 .duplex_reg = B53_DUPLEX_STAT_GE,
2253                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2254                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2255         },
2256         {
2257                 .chip_id = BCM7445_DEVICE_ID,
2258                 .dev_name = "BCM7445",
2259                 .vlans  = 4096,
2260                 .enabled_ports = 0x1ff,
2261                 .arl_entries = 4,
2262                 .cpu_port = B53_CPU_PORT,
2263                 .vta_regs = B53_VTA_REGS,
2264                 .duplex_reg = B53_DUPLEX_STAT_GE,
2265                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2266                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2267         },
2268         {
2269                 .chip_id = BCM7278_DEVICE_ID,
2270                 .dev_name = "BCM7278",
2271                 .vlans = 4096,
2272                 .enabled_ports = 0x1ff,
2273                 .arl_entries= 4,
2274                 .cpu_port = B53_CPU_PORT,
2275                 .vta_regs = B53_VTA_REGS,
2276                 .duplex_reg = B53_DUPLEX_STAT_GE,
2277                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2278                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2279         },
2280 };
2281
2282 static int b53_switch_init(struct b53_device *dev)
2283 {
2284         unsigned int i;
2285         int ret;
2286
2287         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2288                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2289
2290                 if (chip->chip_id == dev->chip_id) {
2291                         if (!dev->enabled_ports)
2292                                 dev->enabled_ports = chip->enabled_ports;
2293                         dev->name = chip->dev_name;
2294                         dev->duplex_reg = chip->duplex_reg;
2295                         dev->vta_regs[0] = chip->vta_regs[0];
2296                         dev->vta_regs[1] = chip->vta_regs[1];
2297                         dev->vta_regs[2] = chip->vta_regs[2];
2298                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2299                         dev->cpu_port = chip->cpu_port;
2300                         dev->num_vlans = chip->vlans;
2301                         dev->num_arl_entries = chip->arl_entries;
2302                         break;
2303                 }
2304         }
2305
2306         /* check which BCM5325x version we have */
2307         if (is5325(dev)) {
2308                 u8 vc4;
2309
2310                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2311
2312                 /* check reserved bits */
2313                 switch (vc4 & 3) {
2314                 case 1:
2315                         /* BCM5325E */
2316                         break;
2317                 case 3:
2318                         /* BCM5325F - do not use port 4 */
2319                         dev->enabled_ports &= ~BIT(4);
2320                         break;
2321                 default:
2322 /* On the BCM47XX SoCs this is the supported internal switch.*/
2323 #ifndef CONFIG_BCM47XX
2324                         /* BCM5325M */
2325                         return -EINVAL;
2326 #else
2327                         break;
2328 #endif
2329                 }
2330         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2331                 u64 strap_value;
2332
2333                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2334                 /* use second IMP port if GMII is enabled */
2335                 if (strap_value & SV_GMII_CTRL_115)
2336                         dev->cpu_port = 5;
2337         }
2338
2339         /* cpu port is always last */
2340         dev->num_ports = dev->cpu_port + 1;
2341         dev->enabled_ports |= BIT(dev->cpu_port);
2342
2343         /* Include non standard CPU port built-in PHYs to be probed */
2344         if (is539x(dev) || is531x5(dev)) {
2345                 for (i = 0; i < dev->num_ports; i++) {
2346                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2347                             !b53_possible_cpu_port(dev->ds, i))
2348                                 dev->ds->phys_mii_mask |= BIT(i);
2349                 }
2350         }
2351
2352         dev->ports = devm_kcalloc(dev->dev,
2353                                   dev->num_ports, sizeof(struct b53_port),
2354                                   GFP_KERNEL);
2355         if (!dev->ports)
2356                 return -ENOMEM;
2357
2358         dev->vlans = devm_kcalloc(dev->dev,
2359                                   dev->num_vlans, sizeof(struct b53_vlan),
2360                                   GFP_KERNEL);
2361         if (!dev->vlans)
2362                 return -ENOMEM;
2363
2364         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2365         if (dev->reset_gpio >= 0) {
2366                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2367                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2368                 if (ret)
2369                         return ret;
2370         }
2371
2372         return 0;
2373 }
2374
2375 struct b53_device *b53_switch_alloc(struct device *base,
2376                                     const struct b53_io_ops *ops,
2377                                     void *priv)
2378 {
2379         struct dsa_switch *ds;
2380         struct b53_device *dev;
2381
2382         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2383         if (!ds)
2384                 return NULL;
2385
2386         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2387         if (!dev)
2388                 return NULL;
2389
2390         ds->priv = dev;
2391         dev->dev = base;
2392
2393         dev->ds = ds;
2394         dev->priv = priv;
2395         dev->ops = ops;
2396         ds->ops = &b53_switch_ops;
2397         mutex_init(&dev->reg_mutex);
2398         mutex_init(&dev->stats_mutex);
2399
2400         return dev;
2401 }
2402 EXPORT_SYMBOL(b53_switch_alloc);
2403
2404 int b53_switch_detect(struct b53_device *dev)
2405 {
2406         u32 id32;
2407         u16 tmp;
2408         u8 id8;
2409         int ret;
2410
2411         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2412         if (ret)
2413                 return ret;
2414
2415         switch (id8) {
2416         case 0:
2417                 /* BCM5325 and BCM5365 do not have this register so reads
2418                  * return 0. But the read operation did succeed, so assume this
2419                  * is one of them.
2420                  *
2421                  * Next check if we can write to the 5325's VTA register; for
2422                  * 5365 it is read only.
2423                  */
2424                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2425                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2426
2427                 if (tmp == 0xf)
2428                         dev->chip_id = BCM5325_DEVICE_ID;
2429                 else
2430                         dev->chip_id = BCM5365_DEVICE_ID;
2431                 break;
2432         case BCM5389_DEVICE_ID:
2433         case BCM5395_DEVICE_ID:
2434         case BCM5397_DEVICE_ID:
2435         case BCM5398_DEVICE_ID:
2436                 dev->chip_id = id8;
2437                 break;
2438         default:
2439                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2440                 if (ret)
2441                         return ret;
2442
2443                 switch (id32) {
2444                 case BCM53115_DEVICE_ID:
2445                 case BCM53125_DEVICE_ID:
2446                 case BCM53128_DEVICE_ID:
2447                 case BCM53010_DEVICE_ID:
2448                 case BCM53011_DEVICE_ID:
2449                 case BCM53012_DEVICE_ID:
2450                 case BCM53018_DEVICE_ID:
2451                 case BCM53019_DEVICE_ID:
2452                         dev->chip_id = id32;
2453                         break;
2454                 default:
2455                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2456                                id8, id32);
2457                         return -ENODEV;
2458                 }
2459         }
2460
2461         if (dev->chip_id == BCM5325_DEVICE_ID)
2462                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2463                                  &dev->core_rev);
2464         else
2465                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2466                                  &dev->core_rev);
2467 }
2468 EXPORT_SYMBOL(b53_switch_detect);
2469
2470 int b53_switch_register(struct b53_device *dev)
2471 {
2472         int ret;
2473
2474         if (dev->pdata) {
2475                 dev->chip_id = dev->pdata->chip_id;
2476                 dev->enabled_ports = dev->pdata->enabled_ports;
2477         }
2478
2479         if (!dev->chip_id && b53_switch_detect(dev))
2480                 return -EINVAL;
2481
2482         ret = b53_switch_init(dev);
2483         if (ret)
2484                 return ret;
2485
2486         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2487
2488         return dsa_register_switch(dev->ds);
2489 }
2490 EXPORT_SYMBOL(b53_switch_register);
2491
2492 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2493 MODULE_DESCRIPTION("B53 switch library");
2494 MODULE_LICENSE("Dual BSD/GPL");