1 // SPDX-License-Identifier: GPL-2.0+
3 dm9000.c: Version 1.2 12/15/2003
5 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
6 Copyright (C) 1997 Sten Wang
8 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
10 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
11 06/22/2001 Support DM9801 progrmming
12 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
13 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
14 R17 = (R17 & 0xfff0) | NF + 3
15 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
16 R17 = (R17 & 0xfff0) | NF
18 v1.00 modify by simon 2001.9.5
19 change for kernel 2.4.x
21 v1.1 11/09/2001 fix force mode bug
23 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
25 Added tx/rx 32 bit mode.
26 Cleaned up for kernel merge.
28 --------------------------------------
30 12/15/2003 Initial port to u-boot by
31 Sascha Hauer <saschahauer@web.de>
33 06/03/2008 Remy Bohmer <linux@bohmer.net>
34 - Fixed the driver to work with DM9000A.
35 (check on ISR receive status bit before reading the
36 FIFO as described in DM9000 programming guide and
38 - Added autodetect of databus width.
39 - Made debug code compile again.
40 - Adapt eth_send such that it matches the DM9000*
41 application notes. Needed to make it work properly
43 - Adapted reset procedure to match DM9000 application
44 notes (i.e. double reset)
45 - some minor code cleanups
46 These changes are tested with DM9000{A,EP,E} together
47 with a 200MHz Atmel AT91SAM9261 core
49 TODO: external MII is not functional, only internal at the moment.
57 #include <linux/delay.h>
61 /* Structure/enum declaration ------------------------------- */
62 typedef struct board_info {
63 u32 runt_length_counter; /* counter: RX length < 64byte */
64 u32 long_length_counter; /* counter: RX length > 1514byte */
65 u32 reset_counter; /* counter: RESET */
66 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
67 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
72 u8 device_wait_reset; /* device state */
73 unsigned char srom[128];
74 void (*outblk)(void *data_ptr, int count);
75 void (*inblk)(void *data_ptr, int count);
76 void (*rx_status)(u16 *rxstatus, u16 *rxlen);
77 struct eth_device netdev;
79 static board_info_t dm9000_info;
82 /* function declaration ------------------------------------- */
83 static int dm9000_probe(void);
84 static u16 dm9000_phy_read(int);
85 static void dm9000_phy_write(int, u16);
86 static u8 dm9000_ior(int);
87 static void dm9000_iow(int reg, u8 value);
89 /* DM9000 network board routine ---------------------------- */
90 #ifndef CONFIG_DM9000_BYTE_SWAPPED
91 #define dm9000_outb(d,r) writeb((d), (r))
92 #define dm9000_outw(d,r) writew((d), (r))
93 #define dm9000_outl(d,r) writel((d), (r))
94 #define dm9000_inb(r) readb(r)
95 #define dm9000_inw(r) readw(r)
96 #define dm9000_inl(r) readl(r)
98 #define dm9000_outb(d, r) __raw_writeb(d, r)
99 #define dm9000_outw(d, r) __raw_writew(d, r)
100 #define dm9000_outl(d, r) __raw_writel(d, r)
101 #define dm9000_inb(r) __raw_readb(r)
102 #define dm9000_inw(r) __raw_readw(r)
103 #define dm9000_inl(r) __raw_readl(r)
107 static void dm9000_dump_packet(const char *func, u8 *packet, int length)
111 printf("%s: length: %d\n", func, length);
113 for (i = 0; i < length; i++) {
115 printf("\n%s: %02x: ", func, i);
116 printf("%02x ", packet[i]);
122 static void dm9000_dump_packet(const char *func, u8 *packet, int length) {}
125 static void dm9000_outblk_8bit(void *data_ptr, int count)
128 for (i = 0; i < count; i++)
129 dm9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
132 static void dm9000_outblk_16bit(void *data_ptr, int count)
135 u32 tmplen = (count + 1) / 2;
137 for (i = 0; i < tmplen; i++)
138 dm9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
140 static void dm9000_outblk_32bit(void *data_ptr, int count)
143 u32 tmplen = (count + 3) / 4;
145 for (i = 0; i < tmplen; i++)
146 dm9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
149 static void dm9000_inblk_8bit(void *data_ptr, int count)
152 for (i = 0; i < count; i++)
153 ((u8 *) data_ptr)[i] = dm9000_inb(DM9000_DATA);
156 static void dm9000_inblk_16bit(void *data_ptr, int count)
159 u32 tmplen = (count + 1) / 2;
161 for (i = 0; i < tmplen; i++)
162 ((u16 *) data_ptr)[i] = dm9000_inw(DM9000_DATA);
164 static void dm9000_inblk_32bit(void *data_ptr, int count)
167 u32 tmplen = (count + 3) / 4;
169 for (i = 0; i < tmplen; i++)
170 ((u32 *) data_ptr)[i] = dm9000_inl(DM9000_DATA);
173 static void dm9000_rx_status_32bit(u16 *rxstatus, u16 *rxlen)
177 dm9000_outb(DM9000_MRCMD, DM9000_IO);
179 tmpdata = dm9000_inl(DM9000_DATA);
180 *rxstatus = __le16_to_cpu(tmpdata);
181 *rxlen = __le16_to_cpu(tmpdata >> 16);
184 static void dm9000_rx_status_16bit(u16 *rxstatus, u16 *rxlen)
186 dm9000_outb(DM9000_MRCMD, DM9000_IO);
188 *rxstatus = __le16_to_cpu(dm9000_inw(DM9000_DATA));
189 *rxlen = __le16_to_cpu(dm9000_inw(DM9000_DATA));
192 static void dm9000_rx_status_8bit(u16 *rxstatus, u16 *rxlen)
194 dm9000_outb(DM9000_MRCMD, DM9000_IO);
197 __le16_to_cpu(dm9000_inb(DM9000_DATA) +
198 (dm9000_inb(DM9000_DATA) << 8));
200 __le16_to_cpu(dm9000_inb(DM9000_DATA) +
201 (dm9000_inb(DM9000_DATA) << 8));
205 Search DM9000 board, allocate space and register it
211 id_val = dm9000_ior(DM9000_VIDL);
212 id_val |= dm9000_ior(DM9000_VIDH) << 8;
213 id_val |= dm9000_ior(DM9000_PIDL) << 16;
214 id_val |= dm9000_ior(DM9000_PIDH) << 24;
215 if (id_val == DM9000_ID) {
216 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
220 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
221 CONFIG_DM9000_BASE, id_val);
226 /* General Purpose dm9000 reset routine */
230 debug("resetting DM9000\n");
233 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
235 /* DEBUG: Make all GPIO0 outputs, all others inputs */
236 dm9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
237 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
238 dm9000_iow(DM9000_GPR, 0);
239 /* Step 2: Software reset */
240 dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
243 debug("resetting the DM9000, 1st reset\n");
244 udelay(25); /* Wait at least 20 us */
245 } while (dm9000_ior(DM9000_NCR) & 1);
247 dm9000_iow(DM9000_NCR, 0);
248 dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
251 debug("resetting the DM9000, 2nd reset\n");
252 udelay(25); /* Wait at least 20 us */
253 } while (dm9000_ior(DM9000_NCR) & 1);
255 /* Check whether the ethernet controller is present */
256 if ((dm9000_ior(DM9000_PIDL) != 0x0) ||
257 (dm9000_ior(DM9000_PIDH) != 0x90))
258 printf("ERROR: resetting DM9000 -> not responding\n");
261 /* Initialize dm9000 board
263 static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
267 struct board_info *db = &dm9000_info;
269 debug("%s\n", __func__);
274 if (dm9000_probe() < 0)
277 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
278 io_mode = dm9000_ior(DM9000_ISR) >> 6;
281 case 0x0: /* 16-bit mode */
282 printf("DM9000: running in 16 bit mode\n");
283 db->outblk = dm9000_outblk_16bit;
284 db->inblk = dm9000_inblk_16bit;
285 db->rx_status = dm9000_rx_status_16bit;
287 case 0x01: /* 32-bit mode */
288 printf("DM9000: running in 32 bit mode\n");
289 db->outblk = dm9000_outblk_32bit;
290 db->inblk = dm9000_inblk_32bit;
291 db->rx_status = dm9000_rx_status_32bit;
293 case 0x02: /* 8 bit mode */
294 printf("DM9000: running in 8 bit mode\n");
295 db->outblk = dm9000_outblk_8bit;
296 db->inblk = dm9000_inblk_8bit;
297 db->rx_status = dm9000_rx_status_8bit;
300 /* Assume 8 bit mode, will probably not work anyway */
301 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
302 db->outblk = dm9000_outblk_8bit;
303 db->inblk = dm9000_inblk_8bit;
304 db->rx_status = dm9000_rx_status_8bit;
308 /* Program operating register, only internal phy supported */
309 dm9000_iow(DM9000_NCR, 0x0);
310 /* TX Polling clear */
311 dm9000_iow(DM9000_TCR, 0);
312 /* Less 3Kb, 200us */
313 dm9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
314 /* Flow Control : High/Low Water */
315 dm9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
316 /* SH FIXME: This looks strange! Flow Control */
317 dm9000_iow(DM9000_FCR, 0x0);
319 dm9000_iow(DM9000_SMCR, 0);
320 /* clear TX status */
321 dm9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
322 /* Clear interrupt status */
323 dm9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
325 printf("MAC: %pM\n", dev->enetaddr);
326 if (!is_valid_ethaddr(dev->enetaddr)) {
327 printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
330 /* fill device MAC address registers */
331 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
332 dm9000_iow(oft, dev->enetaddr[i]);
333 for (i = 0, oft = 0x16; i < 8; i++, oft++)
334 dm9000_iow(oft, 0xff);
336 /* read back mac, just to be sure */
337 for (i = 0, oft = 0x10; i < 6; i++, oft++)
338 debug("%02x:", dm9000_ior(oft));
341 /* Activate DM9000 */
343 dm9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
344 /* Enable TX/RX interrupt mask */
345 dm9000_iow(DM9000_IMR, IMR_PAR);
348 while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
352 printf("could not establish link\n");
357 /* see what we've got */
358 lnk = dm9000_phy_read(17) >> 12;
359 printf("operating at ");
362 printf("10M half duplex ");
365 printf("10M full duplex ");
368 printf("100M half duplex ");
371 printf("100M full duplex ");
374 printf("unknown: %d ", lnk);
382 Hardware start transmission.
383 Send a packet to media from the upper layer.
385 static int dm9000_send(struct eth_device *netdev, void *packet, int length)
388 struct board_info *db = &dm9000_info;
390 dm9000_dump_packet(__func__ , packet, length);
392 dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
394 /* Move data to DM9000 TX RAM */
395 dm9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
397 /* push the data to the TX-fifo */
398 (db->outblk)(packet, length);
400 /* Set TX length to DM9000 */
401 dm9000_iow(DM9000_TXPLL, length & 0xff);
402 dm9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
404 /* Issue TX polling command */
405 dm9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
407 /* wait for end of transmission */
408 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
409 while ( !(dm9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
410 !(dm9000_ior(DM9000_ISR) & IMR_PTM) ) {
411 if (get_timer(0) >= tmo) {
412 printf("transmission timeout\n");
416 dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
418 debug("transmit done\n\n");
424 The interface is stopped when it is brought.
426 static void dm9000_halt(struct eth_device *netdev)
428 debug("%s\n", __func__);
431 dm9000_phy_write(0, 0x8000); /* PHY RESET */
432 dm9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
433 dm9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
434 dm9000_iow(DM9000_RCR, 0x00); /* Disable RX */
438 Received a packet and pass to upper layer
440 static int dm9000_rx(struct eth_device *netdev)
443 u8 *rdptr = (u8 *)net_rx_packets[0];
444 u16 rxstatus, rxlen = 0;
445 struct board_info *db = &dm9000_info;
447 /* Check packet ready or not, we must check
448 the ISR status first for DM9000A */
449 if (!(dm9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
452 dm9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
454 /* There is _at least_ 1 package in the fifo, read them all */
456 dm9000_ior(DM9000_MRCMDX); /* Dummy read */
458 /* Get most updated data,
459 only look at bits 0:1, See application notes DM9000 */
460 rxbyte = dm9000_inb(DM9000_DATA) & 0x03;
462 /* Status check: this byte must be 0 or 1 */
463 if (rxbyte > DM9000_PKT_RDY) {
464 dm9000_iow(DM9000_RCR, 0x00); /* Stop Device */
465 dm9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
466 printf("DM9000 error: status check fail: 0x%x\n",
471 if (rxbyte != DM9000_PKT_RDY)
472 return 0; /* No packet received, ignore */
474 debug("receiving packet\n");
476 /* A packet ready now & Get status/length */
477 (db->rx_status)(&rxstatus, &rxlen);
479 debug("rx status: 0x%04x rx len: %d\n", rxstatus, rxlen);
481 /* Move data from DM9000 */
482 /* Read received packet from RX SRAM */
483 (db->inblk)(rdptr, rxlen);
485 if ((rxstatus & 0xbf00) || (rxlen < 0x40)
486 || (rxlen > DM9000_PKT_MAX)) {
487 if (rxstatus & 0x100) {
488 printf("rx fifo error\n");
490 if (rxstatus & 0x200) {
491 printf("rx crc error\n");
493 if (rxstatus & 0x8000) {
494 printf("rx length error\n");
496 if (rxlen > DM9000_PKT_MAX) {
497 printf("rx length too big\n");
501 dm9000_dump_packet(__func__ , rdptr, rxlen);
503 debug("passing packet to upper layer\n");
504 net_process_received_packet(net_rx_packets[0], rxlen);
511 Read a word data from SROM
513 #if !defined(CONFIG_DM9000_NO_SROM)
514 void dm9000_read_srom_word(int offset, u8 *to)
516 dm9000_iow(DM9000_EPAR, offset);
517 dm9000_iow(DM9000_EPCR, 0x4);
519 dm9000_iow(DM9000_EPCR, 0x0);
520 to[0] = dm9000_ior(DM9000_EPDRL);
521 to[1] = dm9000_ior(DM9000_EPDRH);
524 void dm9000_write_srom_word(int offset, u16 val)
526 dm9000_iow(DM9000_EPAR, offset);
527 dm9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
528 dm9000_iow(DM9000_EPDRL, (val & 0xff));
529 dm9000_iow(DM9000_EPCR, 0x12);
531 dm9000_iow(DM9000_EPCR, 0);
535 static void dm9000_get_enetaddr(struct eth_device *dev)
537 #if !defined(CONFIG_DM9000_NO_SROM)
539 for (i = 0; i < 3; i++)
540 dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
545 Read a byte from I/O port
550 dm9000_outb(reg, DM9000_IO);
551 return dm9000_inb(DM9000_DATA);
555 Write a byte to I/O port
558 dm9000_iow(int reg, u8 value)
560 dm9000_outb(reg, DM9000_IO);
561 dm9000_outb(value, DM9000_DATA);
565 Read a word from phyxcer
568 dm9000_phy_read(int reg)
572 /* Fill the phyxcer register into REG_0C */
573 dm9000_iow(DM9000_EPAR, DM9000_PHY | reg);
574 dm9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
575 udelay(100); /* Wait read complete */
576 dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
577 val = (dm9000_ior(DM9000_EPDRH) << 8) | dm9000_ior(DM9000_EPDRL);
579 /* The read data keeps on REG_0D & REG_0E */
580 debug("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
585 Write a word to phyxcer
588 dm9000_phy_write(int reg, u16 value)
591 /* Fill the phyxcer register into REG_0C */
592 dm9000_iow(DM9000_EPAR, DM9000_PHY | reg);
594 /* Fill the written data into REG_0D & REG_0E */
595 dm9000_iow(DM9000_EPDRL, (value & 0xff));
596 dm9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
597 dm9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
598 udelay(500); /* Wait write complete */
599 dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
600 debug("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
603 int dm9000_initialize(struct bd_info *bis)
605 struct eth_device *dev = &(dm9000_info.netdev);
607 /* Load MAC address from EEPROM */
608 dm9000_get_enetaddr(dev);
610 dev->init = dm9000_init;
611 dev->halt = dm9000_halt;
612 dev->send = dm9000_send;
613 dev->recv = dm9000_rx;
614 strcpy(dev->name, "dm9000");