1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * Designware ethernet IP driver for U-Boot
22 #include <asm/cache.h>
23 #include <dm/device_compat.h>
24 #include <dm/devres.h>
25 #include <linux/compiler.h>
26 #include <linux/err.h>
27 #include <linux/kernel.h>
29 #include <power/regulator.h>
30 #include "designware.h"
32 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
35 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
36 struct eth_mac_regs *mac_p = priv->mac_regs_p;
38 struct eth_mac_regs *mac_p = bus->priv;
42 int timeout = CONFIG_MDIO_TIMEOUT;
44 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
45 ((reg << MIIREGSHIFT) & MII_REGMSK);
47 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
50 while (get_timer(start) < timeout) {
51 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
52 return readl(&mac_p->miidata);
59 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
63 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
64 struct eth_mac_regs *mac_p = priv->mac_regs_p;
66 struct eth_mac_regs *mac_p = bus->priv;
70 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
72 writel(val, &mac_p->miidata);
73 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
74 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
76 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
79 while (get_timer(start) < timeout) {
80 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
90 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
91 static int dw_mdio_reset(struct mii_dev *bus)
93 struct udevice *dev = bus->priv;
94 struct dw_eth_dev *priv = dev_get_priv(dev);
95 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
98 if (!dm_gpio_is_valid(&priv->reset_gpio))
102 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
106 udelay(pdata->reset_delays[0]);
108 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
112 udelay(pdata->reset_delays[1]);
114 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
118 udelay(pdata->reset_delays[2]);
124 static int dw_mdio_init(const char *name, void *priv)
126 struct mii_dev *bus = mdio_alloc();
129 printf("Failed to allocate MDIO bus\n");
133 bus->read = dw_mdio_read;
134 bus->write = dw_mdio_write;
135 snprintf(bus->name, sizeof(bus->name), "%s", name);
136 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
137 bus->reset = dw_mdio_reset;
142 return mdio_register(bus);
145 static void tx_descs_init(struct dw_eth_dev *priv)
147 struct eth_dma_regs *dma_p = priv->dma_regs_p;
148 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
149 char *txbuffs = &priv->txbuffs[0];
150 struct dmamacdescr *desc_p;
153 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
154 desc_p = &desc_table_p[idx];
155 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
156 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
158 #if defined(CONFIG_DW_ALTDESCRIPTOR)
159 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
160 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
161 DESC_TXSTS_TXCHECKINSCTRL |
162 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
164 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
165 desc_p->dmamac_cntl = 0;
166 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
168 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
169 desc_p->txrx_status = 0;
173 /* Correcting the last pointer of the chain */
174 desc_p->dmamac_next = (ulong)&desc_table_p[0];
176 /* Flush all Tx buffer descriptors at once */
177 flush_dcache_range((ulong)priv->tx_mac_descrtable,
178 (ulong)priv->tx_mac_descrtable +
179 sizeof(priv->tx_mac_descrtable));
181 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
182 priv->tx_currdescnum = 0;
185 static void rx_descs_init(struct dw_eth_dev *priv)
187 struct eth_dma_regs *dma_p = priv->dma_regs_p;
188 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
189 char *rxbuffs = &priv->rxbuffs[0];
190 struct dmamacdescr *desc_p;
193 /* Before passing buffers to GMAC we need to make sure zeros
194 * written there right after "priv" structure allocation were
196 * Otherwise there's a chance to get some of them flushed in RAM when
197 * GMAC is already pushing data to RAM via DMA. This way incoming from
198 * GMAC data will be corrupted. */
199 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
201 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
202 desc_p = &desc_table_p[idx];
203 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
204 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
206 desc_p->dmamac_cntl =
207 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
210 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
213 /* Correcting the last pointer of the chain */
214 desc_p->dmamac_next = (ulong)&desc_table_p[0];
216 /* Flush all Rx buffer descriptors at once */
217 flush_dcache_range((ulong)priv->rx_mac_descrtable,
218 (ulong)priv->rx_mac_descrtable +
219 sizeof(priv->rx_mac_descrtable));
221 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
222 priv->rx_currdescnum = 0;
225 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
227 struct eth_mac_regs *mac_p = priv->mac_regs_p;
228 u32 macid_lo, macid_hi;
230 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
232 macid_hi = mac_id[4] + (mac_id[5] << 8);
234 writel(macid_hi, &mac_p->macaddr0hi);
235 writel(macid_lo, &mac_p->macaddr0lo);
240 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
241 struct phy_device *phydev)
243 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
246 printf("%s: No link.\n", phydev->dev->name);
250 if (phydev->speed != 1000)
251 conf |= MII_PORTSELECT;
253 conf &= ~MII_PORTSELECT;
255 if (phydev->speed == 100)
259 conf |= FULLDPLXMODE;
261 writel(conf, &mac_p->conf);
263 printf("Speed: %d, %s duplex%s\n", phydev->speed,
264 (phydev->duplex) ? "full" : "half",
265 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
270 static void _dw_eth_halt(struct dw_eth_dev *priv)
272 struct eth_mac_regs *mac_p = priv->mac_regs_p;
273 struct eth_dma_regs *dma_p = priv->dma_regs_p;
275 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
276 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
278 phy_shutdown(priv->phydev);
281 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
283 struct eth_mac_regs *mac_p = priv->mac_regs_p;
284 struct eth_dma_regs *dma_p = priv->dma_regs_p;
288 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
291 * When a MII PHY is used, we must set the PS bit for the DMA
294 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
295 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
297 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
299 start = get_timer(0);
300 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
301 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
302 printf("DMA reset timeout\n");
310 * Soft reset above clears HW address registers.
311 * So we have to set it here once again.
313 _dw_write_hwaddr(priv, enetaddr);
318 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
320 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
321 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
324 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
328 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
330 #ifdef CONFIG_DW_AXI_BURST_LEN
331 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
334 /* Start up the PHY */
335 ret = phy_startup(priv->phydev);
337 printf("Could not initialize PHY %s\n",
338 priv->phydev->dev->name);
342 ret = dw_adjust_link(priv, mac_p, priv->phydev);
349 int designware_eth_enable(struct dw_eth_dev *priv)
351 struct eth_mac_regs *mac_p = priv->mac_regs_p;
353 if (!priv->phydev->link)
356 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
363 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
365 struct eth_dma_regs *dma_p = priv->dma_regs_p;
366 u32 desc_num = priv->tx_currdescnum;
367 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
368 ulong desc_start = (ulong)desc_p;
369 ulong desc_end = desc_start +
370 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
371 ulong data_start = desc_p->dmamac_addr;
372 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
374 * Strictly we only need to invalidate the "txrx_status" field
375 * for the following check, but on some platforms we cannot
376 * invalidate only 4 bytes, so we flush the entire descriptor,
377 * which is 16 bytes in total. This is safe because the
378 * individual descriptors in the array are each aligned to
379 * ARCH_DMA_MINALIGN and padded appropriately.
381 invalidate_dcache_range(desc_start, desc_end);
383 /* Check if the descriptor is owned by CPU */
384 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
385 printf("CPU not owner of tx frame\n");
389 memcpy((void *)data_start, packet, length);
390 if (length < ETH_ZLEN) {
391 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
395 /* Flush data to be sent */
396 flush_dcache_range(data_start, data_end);
398 #if defined(CONFIG_DW_ALTDESCRIPTOR)
399 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
400 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
401 ((length << DESC_TXCTRL_SIZE1SHFT) &
402 DESC_TXCTRL_SIZE1MASK);
404 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
405 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
407 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
408 ((length << DESC_TXCTRL_SIZE1SHFT) &
409 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
412 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
415 /* Flush modified buffer descriptor */
416 flush_dcache_range(desc_start, desc_end);
418 /* Test the wrap-around condition. */
419 if (++desc_num >= CONFIG_TX_DESCR_NUM)
422 priv->tx_currdescnum = desc_num;
424 /* Start the transmission */
425 writel(POLL_DATA, &dma_p->txpolldemand);
430 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
432 u32 status, desc_num = priv->rx_currdescnum;
433 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
434 int length = -EAGAIN;
435 ulong desc_start = (ulong)desc_p;
436 ulong desc_end = desc_start +
437 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
438 ulong data_start = desc_p->dmamac_addr;
441 /* Invalidate entire buffer descriptor */
442 invalidate_dcache_range(desc_start, desc_end);
444 status = desc_p->txrx_status;
446 /* Check if the owner is the CPU */
447 if (!(status & DESC_RXSTS_OWNBYDMA)) {
449 length = (status & DESC_RXSTS_FRMLENMSK) >>
450 DESC_RXSTS_FRMLENSHFT;
452 /* Invalidate received data */
453 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
454 invalidate_dcache_range(data_start, data_end);
455 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
461 static int _dw_free_pkt(struct dw_eth_dev *priv)
463 u32 desc_num = priv->rx_currdescnum;
464 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
465 ulong desc_start = (ulong)desc_p;
466 ulong desc_end = desc_start +
467 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
470 * Make the current descriptor valid again and go to
473 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
475 /* Flush only status field - others weren't changed */
476 flush_dcache_range(desc_start, desc_end);
478 /* Test the wrap-around condition. */
479 if (++desc_num >= CONFIG_RX_DESCR_NUM)
481 priv->rx_currdescnum = desc_num;
486 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
488 struct phy_device *phydev;
489 int phy_addr = -1, ret;
491 #ifdef CONFIG_PHY_ADDR
492 phy_addr = CONFIG_PHY_ADDR;
495 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
499 phydev->supported &= PHY_GBIT_FEATURES;
500 if (priv->max_speed) {
501 ret = phy_set_supported(phydev, priv->max_speed);
505 phydev->advertising = phydev->supported;
507 priv->phydev = phydev;
513 #ifndef CONFIG_DM_ETH
514 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
518 ret = designware_eth_init(dev->priv, dev->enetaddr);
520 ret = designware_eth_enable(dev->priv);
525 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
527 return _dw_eth_send(dev->priv, packet, length);
530 static int dw_eth_recv(struct eth_device *dev)
535 length = _dw_eth_recv(dev->priv, &packet);
536 if (length == -EAGAIN)
538 net_process_received_packet(packet, length);
540 _dw_free_pkt(dev->priv);
545 static void dw_eth_halt(struct eth_device *dev)
547 return _dw_eth_halt(dev->priv);
550 static int dw_write_hwaddr(struct eth_device *dev)
552 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
555 int designware_initialize(ulong base_addr, u32 interface)
557 struct eth_device *dev;
558 struct dw_eth_dev *priv;
560 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
565 * Since the priv structure contains the descriptors which need a strict
566 * buswidth alignment, memalign is used to allocate memory
568 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
569 sizeof(struct dw_eth_dev));
575 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
576 printf("designware: buffers are outside DMA memory\n");
580 memset(dev, 0, sizeof(struct eth_device));
581 memset(priv, 0, sizeof(struct dw_eth_dev));
583 sprintf(dev->name, "dwmac.%lx", base_addr);
584 dev->iobase = (int)base_addr;
588 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
589 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
592 dev->init = dw_eth_init;
593 dev->send = dw_eth_send;
594 dev->recv = dw_eth_recv;
595 dev->halt = dw_eth_halt;
596 dev->write_hwaddr = dw_write_hwaddr;
600 priv->interface = interface;
602 dw_mdio_init(dev->name, priv->mac_regs_p);
603 priv->bus = miiphy_get_dev_by_name(dev->name);
605 return dw_phy_init(priv, dev);
610 static int designware_eth_start(struct udevice *dev)
612 struct eth_pdata *pdata = dev_get_platdata(dev);
613 struct dw_eth_dev *priv = dev_get_priv(dev);
616 ret = designware_eth_init(priv, pdata->enetaddr);
619 ret = designware_eth_enable(priv);
626 int designware_eth_send(struct udevice *dev, void *packet, int length)
628 struct dw_eth_dev *priv = dev_get_priv(dev);
630 return _dw_eth_send(priv, packet, length);
633 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
635 struct dw_eth_dev *priv = dev_get_priv(dev);
637 return _dw_eth_recv(priv, packetp);
640 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
642 struct dw_eth_dev *priv = dev_get_priv(dev);
644 return _dw_free_pkt(priv);
647 void designware_eth_stop(struct udevice *dev)
649 struct dw_eth_dev *priv = dev_get_priv(dev);
651 return _dw_eth_halt(priv);
654 int designware_eth_write_hwaddr(struct udevice *dev)
656 struct eth_pdata *pdata = dev_get_platdata(dev);
657 struct dw_eth_dev *priv = dev_get_priv(dev);
659 return _dw_write_hwaddr(priv, pdata->enetaddr);
662 static int designware_eth_bind(struct udevice *dev)
665 static int num_cards;
668 /* Create a unique device name for PCI type devices */
669 if (device_is_on_pci_bus(dev)) {
670 sprintf(name, "eth_designware#%u", num_cards++);
671 device_set_name(dev, name);
678 int designware_eth_probe(struct udevice *dev)
680 struct eth_pdata *pdata = dev_get_platdata(dev);
681 struct dw_eth_dev *priv = dev_get_priv(dev);
682 u32 iobase = pdata->iobase;
685 struct reset_ctl_bulk reset_bulk;
689 priv->clock_count = 0;
690 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
692 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
697 for (i = 0; i < clock_nb; i++) {
698 err = clk_get_by_index(dev, i, &priv->clocks[i]);
702 err = clk_enable(&priv->clocks[i]);
703 if (err && err != -ENOSYS && err != -ENOTSUPP) {
704 pr_err("failed to enable clock %d\n", i);
705 clk_free(&priv->clocks[i]);
710 } else if (clock_nb != -ENOENT) {
711 pr_err("failed to get clock phandle(%d)\n", clock_nb);
716 #if defined(CONFIG_DM_REGULATOR)
717 struct udevice *phy_supply;
719 ret = device_get_supply_regulator(dev, "phy-supply",
722 debug("%s: No phy supply\n", dev->name);
724 ret = regulator_set_enable(phy_supply, true);
726 puts("Error enabling phy supply\n");
732 ret = reset_get_bulk(dev, &reset_bulk);
734 dev_warn(dev, "Can't get reset: %d\n", ret);
736 reset_deassert_bulk(&reset_bulk);
740 * If we are on PCI bus, either directly attached to a PCI root port,
741 * or via a PCI bridge, fill in platdata before we probe the hardware.
743 if (device_is_on_pci_bus(dev)) {
744 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
745 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
746 iobase = dm_pci_mem_to_phys(dev, iobase);
748 pdata->iobase = iobase;
749 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
753 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
755 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
756 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
757 priv->interface = pdata->phy_interface;
758 priv->max_speed = pdata->max_speed;
760 ret = dw_mdio_init(dev->name, dev);
765 priv->bus = miiphy_get_dev_by_name(dev->name);
767 ret = dw_phy_init(priv, dev);
768 debug("%s, ret=%d\n", __func__, ret);
772 /* continue here for cleanup if no PHY found */
774 mdio_unregister(priv->bus);
775 mdio_free(priv->bus);
780 ret = clk_release_all(priv->clocks, priv->clock_count);
782 pr_err("failed to disable all clocks\n");
788 static int designware_eth_remove(struct udevice *dev)
790 struct dw_eth_dev *priv = dev_get_priv(dev);
793 mdio_unregister(priv->bus);
794 mdio_free(priv->bus);
797 return clk_release_all(priv->clocks, priv->clock_count);
803 const struct eth_ops designware_eth_ops = {
804 .start = designware_eth_start,
805 .send = designware_eth_send,
806 .recv = designware_eth_recv,
807 .free_pkt = designware_eth_free_pkt,
808 .stop = designware_eth_stop,
809 .write_hwaddr = designware_eth_write_hwaddr,
812 int designware_eth_ofdata_to_platdata(struct udevice *dev)
814 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
815 #if CONFIG_IS_ENABLED(DM_GPIO)
816 struct dw_eth_dev *priv = dev_get_priv(dev);
818 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
819 const char *phy_mode;
820 #if CONFIG_IS_ENABLED(DM_GPIO)
821 int reset_flags = GPIOD_IS_OUT;
825 pdata->iobase = dev_read_addr(dev);
826 pdata->phy_interface = -1;
827 phy_mode = dev_read_string(dev, "phy-mode");
829 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
830 if (pdata->phy_interface == -1) {
831 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
835 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
837 #if CONFIG_IS_ENABLED(DM_GPIO)
838 if (dev_read_bool(dev, "snps,reset-active-low"))
839 reset_flags |= GPIOD_ACTIVE_LOW;
841 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
842 &priv->reset_gpio, reset_flags);
844 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
845 dw_pdata->reset_delays, 3);
846 } else if (ret == -ENOENT) {
854 static const struct udevice_id designware_eth_ids[] = {
855 { .compatible = "allwinner,sun7i-a20-gmac" },
856 { .compatible = "amlogic,meson6-dwmac" },
857 { .compatible = "amlogic,meson-gx-dwmac" },
858 { .compatible = "amlogic,meson-gxbb-dwmac" },
859 { .compatible = "amlogic,meson-axg-dwmac" },
860 { .compatible = "st,stm32-dwmac" },
861 { .compatible = "snps,arc-dwmac-3.70a" },
865 U_BOOT_DRIVER(eth_designware) = {
866 .name = "eth_designware",
868 .of_match = designware_eth_ids,
869 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
870 .bind = designware_eth_bind,
871 .probe = designware_eth_probe,
872 .remove = designware_eth_remove,
873 .ops = &designware_eth_ops,
874 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
875 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
876 .flags = DM_FLAG_ALLOC_PRIV_DMA,
879 static struct pci_device_id supported[] = {
880 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
884 U_BOOT_PCI_DEVICE(eth_designware, supported);