1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * Designware ethernet IP driver for U-Boot
19 #include <linux/compiler.h>
20 #include <linux/err.h>
21 #include <linux/kernel.h>
23 #include <power/regulator.h>
24 #include "designware.h"
26 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
29 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
30 struct eth_mac_regs *mac_p = priv->mac_regs_p;
32 struct eth_mac_regs *mac_p = bus->priv;
36 int timeout = CONFIG_MDIO_TIMEOUT;
38 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
39 ((reg << MIIREGSHIFT) & MII_REGMSK);
41 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
44 while (get_timer(start) < timeout) {
45 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
46 return readl(&mac_p->miidata);
53 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
57 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
58 struct eth_mac_regs *mac_p = priv->mac_regs_p;
60 struct eth_mac_regs *mac_p = bus->priv;
64 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
66 writel(val, &mac_p->miidata);
67 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
68 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
70 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
73 while (get_timer(start) < timeout) {
74 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
84 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
85 static int dw_mdio_reset(struct mii_dev *bus)
87 struct udevice *dev = bus->priv;
88 struct dw_eth_dev *priv = dev_get_priv(dev);
89 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
92 if (!dm_gpio_is_valid(&priv->reset_gpio))
96 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
100 udelay(pdata->reset_delays[0]);
102 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
106 udelay(pdata->reset_delays[1]);
108 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
112 udelay(pdata->reset_delays[2]);
118 static int dw_mdio_init(const char *name, void *priv)
120 struct mii_dev *bus = mdio_alloc();
123 printf("Failed to allocate MDIO bus\n");
127 bus->read = dw_mdio_read;
128 bus->write = dw_mdio_write;
129 snprintf(bus->name, sizeof(bus->name), "%s", name);
130 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
131 bus->reset = dw_mdio_reset;
136 return mdio_register(bus);
139 static void tx_descs_init(struct dw_eth_dev *priv)
141 struct eth_dma_regs *dma_p = priv->dma_regs_p;
142 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
143 char *txbuffs = &priv->txbuffs[0];
144 struct dmamacdescr *desc_p;
147 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
148 desc_p = &desc_table_p[idx];
149 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
150 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
152 #if defined(CONFIG_DW_ALTDESCRIPTOR)
153 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
154 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
155 DESC_TXSTS_TXCHECKINSCTRL |
156 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
158 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
159 desc_p->dmamac_cntl = 0;
160 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
162 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
163 desc_p->txrx_status = 0;
167 /* Correcting the last pointer of the chain */
168 desc_p->dmamac_next = (ulong)&desc_table_p[0];
170 /* Flush all Tx buffer descriptors at once */
171 flush_dcache_range((ulong)priv->tx_mac_descrtable,
172 (ulong)priv->tx_mac_descrtable +
173 sizeof(priv->tx_mac_descrtable));
175 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
176 priv->tx_currdescnum = 0;
179 static void rx_descs_init(struct dw_eth_dev *priv)
181 struct eth_dma_regs *dma_p = priv->dma_regs_p;
182 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
183 char *rxbuffs = &priv->rxbuffs[0];
184 struct dmamacdescr *desc_p;
187 /* Before passing buffers to GMAC we need to make sure zeros
188 * written there right after "priv" structure allocation were
190 * Otherwise there's a chance to get some of them flushed in RAM when
191 * GMAC is already pushing data to RAM via DMA. This way incoming from
192 * GMAC data will be corrupted. */
193 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
195 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
196 desc_p = &desc_table_p[idx];
197 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
198 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
200 desc_p->dmamac_cntl =
201 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
204 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
207 /* Correcting the last pointer of the chain */
208 desc_p->dmamac_next = (ulong)&desc_table_p[0];
210 /* Flush all Rx buffer descriptors at once */
211 flush_dcache_range((ulong)priv->rx_mac_descrtable,
212 (ulong)priv->rx_mac_descrtable +
213 sizeof(priv->rx_mac_descrtable));
215 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
216 priv->rx_currdescnum = 0;
219 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
221 struct eth_mac_regs *mac_p = priv->mac_regs_p;
222 u32 macid_lo, macid_hi;
224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
226 macid_hi = mac_id[4] + (mac_id[5] << 8);
228 writel(macid_hi, &mac_p->macaddr0hi);
229 writel(macid_lo, &mac_p->macaddr0lo);
234 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
235 struct phy_device *phydev)
237 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
240 printf("%s: No link.\n", phydev->dev->name);
244 if (phydev->speed != 1000)
245 conf |= MII_PORTSELECT;
247 conf &= ~MII_PORTSELECT;
249 if (phydev->speed == 100)
253 conf |= FULLDPLXMODE;
255 writel(conf, &mac_p->conf);
257 printf("Speed: %d, %s duplex%s\n", phydev->speed,
258 (phydev->duplex) ? "full" : "half",
259 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
264 static void _dw_eth_halt(struct dw_eth_dev *priv)
266 struct eth_mac_regs *mac_p = priv->mac_regs_p;
267 struct eth_dma_regs *dma_p = priv->dma_regs_p;
269 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
270 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
272 phy_shutdown(priv->phydev);
275 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
277 struct eth_mac_regs *mac_p = priv->mac_regs_p;
278 struct eth_dma_regs *dma_p = priv->dma_regs_p;
282 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
285 * When a MII PHY is used, we must set the PS bit for the DMA
288 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
289 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
291 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
293 start = get_timer(0);
294 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
295 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
296 printf("DMA reset timeout\n");
304 * Soft reset above clears HW address registers.
305 * So we have to set it here once again.
307 _dw_write_hwaddr(priv, enetaddr);
312 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
314 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
315 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
318 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
322 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
324 #ifdef CONFIG_DW_AXI_BURST_LEN
325 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
328 /* Start up the PHY */
329 ret = phy_startup(priv->phydev);
331 printf("Could not initialize PHY %s\n",
332 priv->phydev->dev->name);
336 ret = dw_adjust_link(priv, mac_p, priv->phydev);
343 int designware_eth_enable(struct dw_eth_dev *priv)
345 struct eth_mac_regs *mac_p = priv->mac_regs_p;
347 if (!priv->phydev->link)
350 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
357 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
359 struct eth_dma_regs *dma_p = priv->dma_regs_p;
360 u32 desc_num = priv->tx_currdescnum;
361 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
362 ulong desc_start = (ulong)desc_p;
363 ulong desc_end = desc_start +
364 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
365 ulong data_start = desc_p->dmamac_addr;
366 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
368 * Strictly we only need to invalidate the "txrx_status" field
369 * for the following check, but on some platforms we cannot
370 * invalidate only 4 bytes, so we flush the entire descriptor,
371 * which is 16 bytes in total. This is safe because the
372 * individual descriptors in the array are each aligned to
373 * ARCH_DMA_MINALIGN and padded appropriately.
375 invalidate_dcache_range(desc_start, desc_end);
377 /* Check if the descriptor is owned by CPU */
378 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
379 printf("CPU not owner of tx frame\n");
383 length = max(length, ETH_ZLEN);
385 memcpy((void *)data_start, packet, length);
387 /* Flush data to be sent */
388 flush_dcache_range(data_start, data_end);
390 #if defined(CONFIG_DW_ALTDESCRIPTOR)
391 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
392 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
393 ((length << DESC_TXCTRL_SIZE1SHFT) &
394 DESC_TXCTRL_SIZE1MASK);
396 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
397 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
399 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
400 ((length << DESC_TXCTRL_SIZE1SHFT) &
401 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
404 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
407 /* Flush modified buffer descriptor */
408 flush_dcache_range(desc_start, desc_end);
410 /* Test the wrap-around condition. */
411 if (++desc_num >= CONFIG_TX_DESCR_NUM)
414 priv->tx_currdescnum = desc_num;
416 /* Start the transmission */
417 writel(POLL_DATA, &dma_p->txpolldemand);
422 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
424 u32 status, desc_num = priv->rx_currdescnum;
425 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
426 int length = -EAGAIN;
427 ulong desc_start = (ulong)desc_p;
428 ulong desc_end = desc_start +
429 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
430 ulong data_start = desc_p->dmamac_addr;
433 /* Invalidate entire buffer descriptor */
434 invalidate_dcache_range(desc_start, desc_end);
436 status = desc_p->txrx_status;
438 /* Check if the owner is the CPU */
439 if (!(status & DESC_RXSTS_OWNBYDMA)) {
441 length = (status & DESC_RXSTS_FRMLENMSK) >>
442 DESC_RXSTS_FRMLENSHFT;
444 /* Invalidate received data */
445 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
446 invalidate_dcache_range(data_start, data_end);
447 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
453 static int _dw_free_pkt(struct dw_eth_dev *priv)
455 u32 desc_num = priv->rx_currdescnum;
456 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
457 ulong desc_start = (ulong)desc_p;
458 ulong desc_end = desc_start +
459 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
462 * Make the current descriptor valid again and go to
465 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
467 /* Flush only status field - others weren't changed */
468 flush_dcache_range(desc_start, desc_end);
470 /* Test the wrap-around condition. */
471 if (++desc_num >= CONFIG_RX_DESCR_NUM)
473 priv->rx_currdescnum = desc_num;
478 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
480 struct phy_device *phydev;
481 int mask = 0xffffffff, ret;
483 #ifdef CONFIG_PHY_ADDR
484 mask = 1 << CONFIG_PHY_ADDR;
487 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
491 phy_connect_dev(phydev, dev);
493 phydev->supported &= PHY_GBIT_FEATURES;
494 if (priv->max_speed) {
495 ret = phy_set_supported(phydev, priv->max_speed);
499 phydev->advertising = phydev->supported;
501 priv->phydev = phydev;
507 #ifndef CONFIG_DM_ETH
508 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
512 ret = designware_eth_init(dev->priv, dev->enetaddr);
514 ret = designware_eth_enable(dev->priv);
519 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
521 return _dw_eth_send(dev->priv, packet, length);
524 static int dw_eth_recv(struct eth_device *dev)
529 length = _dw_eth_recv(dev->priv, &packet);
530 if (length == -EAGAIN)
532 net_process_received_packet(packet, length);
534 _dw_free_pkt(dev->priv);
539 static void dw_eth_halt(struct eth_device *dev)
541 return _dw_eth_halt(dev->priv);
544 static int dw_write_hwaddr(struct eth_device *dev)
546 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
549 int designware_initialize(ulong base_addr, u32 interface)
551 struct eth_device *dev;
552 struct dw_eth_dev *priv;
554 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
559 * Since the priv structure contains the descriptors which need a strict
560 * buswidth alignment, memalign is used to allocate memory
562 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
563 sizeof(struct dw_eth_dev));
569 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
570 printf("designware: buffers are outside DMA memory\n");
574 memset(dev, 0, sizeof(struct eth_device));
575 memset(priv, 0, sizeof(struct dw_eth_dev));
577 sprintf(dev->name, "dwmac.%lx", base_addr);
578 dev->iobase = (int)base_addr;
582 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
583 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
586 dev->init = dw_eth_init;
587 dev->send = dw_eth_send;
588 dev->recv = dw_eth_recv;
589 dev->halt = dw_eth_halt;
590 dev->write_hwaddr = dw_write_hwaddr;
594 priv->interface = interface;
596 dw_mdio_init(dev->name, priv->mac_regs_p);
597 priv->bus = miiphy_get_dev_by_name(dev->name);
599 return dw_phy_init(priv, dev);
604 static int designware_eth_start(struct udevice *dev)
606 struct eth_pdata *pdata = dev_get_platdata(dev);
607 struct dw_eth_dev *priv = dev_get_priv(dev);
610 ret = designware_eth_init(priv, pdata->enetaddr);
613 ret = designware_eth_enable(priv);
620 int designware_eth_send(struct udevice *dev, void *packet, int length)
622 struct dw_eth_dev *priv = dev_get_priv(dev);
624 return _dw_eth_send(priv, packet, length);
627 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
629 struct dw_eth_dev *priv = dev_get_priv(dev);
631 return _dw_eth_recv(priv, packetp);
634 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
636 struct dw_eth_dev *priv = dev_get_priv(dev);
638 return _dw_free_pkt(priv);
641 void designware_eth_stop(struct udevice *dev)
643 struct dw_eth_dev *priv = dev_get_priv(dev);
645 return _dw_eth_halt(priv);
648 int designware_eth_write_hwaddr(struct udevice *dev)
650 struct eth_pdata *pdata = dev_get_platdata(dev);
651 struct dw_eth_dev *priv = dev_get_priv(dev);
653 return _dw_write_hwaddr(priv, pdata->enetaddr);
656 static int designware_eth_bind(struct udevice *dev)
659 static int num_cards;
662 /* Create a unique device name for PCI type devices */
663 if (device_is_on_pci_bus(dev)) {
664 sprintf(name, "eth_designware#%u", num_cards++);
665 device_set_name(dev, name);
672 int designware_eth_probe(struct udevice *dev)
674 struct eth_pdata *pdata = dev_get_platdata(dev);
675 struct dw_eth_dev *priv = dev_get_priv(dev);
676 u32 iobase = pdata->iobase;
679 struct reset_ctl_bulk reset_bulk;
681 int i, err, clock_nb;
683 priv->clock_count = 0;
684 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
686 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
691 for (i = 0; i < clock_nb; i++) {
692 err = clk_get_by_index(dev, i, &priv->clocks[i]);
696 err = clk_enable(&priv->clocks[i]);
697 if (err && err != -ENOSYS && err != -ENOTSUPP) {
698 pr_err("failed to enable clock %d\n", i);
699 clk_free(&priv->clocks[i]);
704 } else if (clock_nb != -ENOENT) {
705 pr_err("failed to get clock phandle(%d)\n", clock_nb);
710 #if defined(CONFIG_DM_REGULATOR)
711 struct udevice *phy_supply;
713 ret = device_get_supply_regulator(dev, "phy-supply",
716 debug("%s: No phy supply\n", dev->name);
718 ret = regulator_set_enable(phy_supply, true);
720 puts("Error enabling phy supply\n");
726 ret = reset_get_bulk(dev, &reset_bulk);
728 dev_warn(dev, "Can't get reset: %d\n", ret);
730 reset_deassert_bulk(&reset_bulk);
734 * If we are on PCI bus, either directly attached to a PCI root port,
735 * or via a PCI bridge, fill in platdata before we probe the hardware.
737 if (device_is_on_pci_bus(dev)) {
738 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
739 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
740 iobase = dm_pci_mem_to_phys(dev, iobase);
742 pdata->iobase = iobase;
743 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
747 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
749 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
750 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
751 priv->interface = pdata->phy_interface;
752 priv->max_speed = pdata->max_speed;
754 dw_mdio_init(dev->name, dev);
755 priv->bus = miiphy_get_dev_by_name(dev->name);
757 ret = dw_phy_init(priv, dev);
758 debug("%s, ret=%d\n", __func__, ret);
764 ret = clk_release_all(priv->clocks, priv->clock_count);
766 pr_err("failed to disable all clocks\n");
772 static int designware_eth_remove(struct udevice *dev)
774 struct dw_eth_dev *priv = dev_get_priv(dev);
777 mdio_unregister(priv->bus);
778 mdio_free(priv->bus);
781 return clk_release_all(priv->clocks, priv->clock_count);
787 const struct eth_ops designware_eth_ops = {
788 .start = designware_eth_start,
789 .send = designware_eth_send,
790 .recv = designware_eth_recv,
791 .free_pkt = designware_eth_free_pkt,
792 .stop = designware_eth_stop,
793 .write_hwaddr = designware_eth_write_hwaddr,
796 int designware_eth_ofdata_to_platdata(struct udevice *dev)
798 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
799 #ifdef CONFIG_DM_GPIO
800 struct dw_eth_dev *priv = dev_get_priv(dev);
802 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
803 const char *phy_mode;
804 #ifdef CONFIG_DM_GPIO
805 int reset_flags = GPIOD_IS_OUT;
809 pdata->iobase = dev_read_addr(dev);
810 pdata->phy_interface = -1;
811 phy_mode = dev_read_string(dev, "phy-mode");
813 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
814 if (pdata->phy_interface == -1) {
815 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
819 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
821 #ifdef CONFIG_DM_GPIO
822 if (dev_read_bool(dev, "snps,reset-active-low"))
823 reset_flags |= GPIOD_ACTIVE_LOW;
825 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
826 &priv->reset_gpio, reset_flags);
828 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
829 dw_pdata->reset_delays, 3);
830 } else if (ret == -ENOENT) {
838 static const struct udevice_id designware_eth_ids[] = {
839 { .compatible = "allwinner,sun7i-a20-gmac" },
840 { .compatible = "altr,socfpga-stmmac" },
841 { .compatible = "amlogic,meson6-dwmac" },
842 { .compatible = "amlogic,meson-gx-dwmac" },
843 { .compatible = "amlogic,meson-gxbb-dwmac" },
844 { .compatible = "amlogic,meson-axg-dwmac" },
845 { .compatible = "st,stm32-dwmac" },
849 U_BOOT_DRIVER(eth_designware) = {
850 .name = "eth_designware",
852 .of_match = designware_eth_ids,
853 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
854 .bind = designware_eth_bind,
855 .probe = designware_eth_probe,
856 .remove = designware_eth_remove,
857 .ops = &designware_eth_ops,
858 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
859 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
860 .flags = DM_FLAG_ALLOC_PRIV_DMA,
863 static struct pci_device_id supported[] = {
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
868 U_BOOT_PCI_DEVICE(eth_designware, supported);