3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
17 #include <linux/compiler.h>
18 #include <linux/err.h>
20 #include "designware.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 #if !defined(CONFIG_PHYLIB)
25 # error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
28 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
30 struct eth_mac_regs *mac_p = bus->priv;
33 int timeout = CONFIG_MDIO_TIMEOUT;
35 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
36 ((reg << MIIREGSHIFT) & MII_REGMSK);
38 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
41 while (get_timer(start) < timeout) {
42 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
43 return readl(&mac_p->miidata);
50 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
53 struct eth_mac_regs *mac_p = bus->priv;
56 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
58 writel(val, &mac_p->miidata);
59 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
60 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
62 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
65 while (get_timer(start) < timeout) {
66 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
76 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
78 struct mii_dev *bus = mdio_alloc();
81 printf("Failed to allocate MDIO bus\n");
85 bus->read = dw_mdio_read;
86 bus->write = dw_mdio_write;
87 snprintf(bus->name, sizeof(bus->name), name);
89 bus->priv = (void *)mac_regs_p;
91 return mdio_register(bus);
94 static void tx_descs_init(struct dw_eth_dev *priv)
96 struct eth_dma_regs *dma_p = priv->dma_regs_p;
97 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
98 char *txbuffs = &priv->txbuffs[0];
99 struct dmamacdescr *desc_p;
102 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
103 desc_p = &desc_table_p[idx];
104 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
105 desc_p->dmamac_next = &desc_table_p[idx + 1];
107 #if defined(CONFIG_DW_ALTDESCRIPTOR)
108 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
109 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
110 DESC_TXSTS_TXCHECKINSCTRL | \
111 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
113 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
114 desc_p->dmamac_cntl = 0;
115 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
117 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
118 desc_p->txrx_status = 0;
122 /* Correcting the last pointer of the chain */
123 desc_p->dmamac_next = &desc_table_p[0];
125 /* Flush all Tx buffer descriptors at once */
126 flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
127 (unsigned int)priv->tx_mac_descrtable +
128 sizeof(priv->tx_mac_descrtable));
130 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
131 priv->tx_currdescnum = 0;
134 static void rx_descs_init(struct dw_eth_dev *priv)
136 struct eth_dma_regs *dma_p = priv->dma_regs_p;
137 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
138 char *rxbuffs = &priv->rxbuffs[0];
139 struct dmamacdescr *desc_p;
142 /* Before passing buffers to GMAC we need to make sure zeros
143 * written there right after "priv" structure allocation were
145 * Otherwise there's a chance to get some of them flushed in RAM when
146 * GMAC is already pushing data to RAM via DMA. This way incoming from
147 * GMAC data will be corrupted. */
148 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
151 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
152 desc_p = &desc_table_p[idx];
153 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
154 desc_p->dmamac_next = &desc_table_p[idx + 1];
156 desc_p->dmamac_cntl =
157 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
160 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
163 /* Correcting the last pointer of the chain */
164 desc_p->dmamac_next = &desc_table_p[0];
166 /* Flush all Rx buffer descriptors at once */
167 flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
168 (unsigned int)priv->rx_mac_descrtable +
169 sizeof(priv->rx_mac_descrtable));
171 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
172 priv->rx_currdescnum = 0;
175 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
177 struct eth_mac_regs *mac_p = priv->mac_regs_p;
178 u32 macid_lo, macid_hi;
180 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
182 macid_hi = mac_id[4] + (mac_id[5] << 8);
184 writel(macid_hi, &mac_p->macaddr0hi);
185 writel(macid_lo, &mac_p->macaddr0lo);
190 static void dw_adjust_link(struct eth_mac_regs *mac_p,
191 struct phy_device *phydev)
193 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
196 printf("%s: No link.\n", phydev->dev->name);
200 if (phydev->speed != 1000)
201 conf |= MII_PORTSELECT;
203 if (phydev->speed == 100)
207 conf |= FULLDPLXMODE;
209 writel(conf, &mac_p->conf);
211 printf("Speed: %d, %s duplex%s\n", phydev->speed,
212 (phydev->duplex) ? "full" : "half",
213 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
216 static void _dw_eth_halt(struct dw_eth_dev *priv)
218 struct eth_mac_regs *mac_p = priv->mac_regs_p;
219 struct eth_dma_regs *dma_p = priv->dma_regs_p;
221 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
222 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
224 phy_shutdown(priv->phydev);
227 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
229 struct eth_mac_regs *mac_p = priv->mac_regs_p;
230 struct eth_dma_regs *dma_p = priv->dma_regs_p;
234 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
236 start = get_timer(0);
237 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
238 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
239 printf("DMA reset timeout\n");
246 /* Soft reset above clears HW address registers.
247 * So we have to set it here once again */
248 _dw_write_hwaddr(priv, enetaddr);
253 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
255 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
256 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
259 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
263 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
265 #ifdef CONFIG_DW_AXI_BURST_LEN
266 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
269 /* Start up the PHY */
270 ret = phy_startup(priv->phydev);
272 printf("Could not initialize PHY %s\n",
273 priv->phydev->dev->name);
277 dw_adjust_link(mac_p, priv->phydev);
279 if (!priv->phydev->link)
282 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
287 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
289 struct eth_dma_regs *dma_p = priv->dma_regs_p;
290 u32 desc_num = priv->tx_currdescnum;
291 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
292 uint32_t desc_start = (uint32_t)desc_p;
293 uint32_t desc_end = desc_start +
294 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
295 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
296 uint32_t data_end = data_start +
297 roundup(length, ARCH_DMA_MINALIGN);
299 * Strictly we only need to invalidate the "txrx_status" field
300 * for the following check, but on some platforms we cannot
301 * invalidate only 4 bytes, so we flush the entire descriptor,
302 * which is 16 bytes in total. This is safe because the
303 * individual descriptors in the array are each aligned to
304 * ARCH_DMA_MINALIGN and padded appropriately.
306 invalidate_dcache_range(desc_start, desc_end);
308 /* Check if the descriptor is owned by CPU */
309 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
310 printf("CPU not owner of tx frame\n");
314 memcpy(desc_p->dmamac_addr, packet, length);
316 /* Flush data to be sent */
317 flush_dcache_range(data_start, data_end);
319 #if defined(CONFIG_DW_ALTDESCRIPTOR)
320 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
321 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
322 DESC_TXCTRL_SIZE1MASK;
324 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
325 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
327 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
328 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
331 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
334 /* Flush modified buffer descriptor */
335 flush_dcache_range(desc_start, desc_end);
337 /* Test the wrap-around condition. */
338 if (++desc_num >= CONFIG_TX_DESCR_NUM)
341 priv->tx_currdescnum = desc_num;
343 /* Start the transmission */
344 writel(POLL_DATA, &dma_p->txpolldemand);
349 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
351 u32 status, desc_num = priv->rx_currdescnum;
352 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
353 int length = -EAGAIN;
354 uint32_t desc_start = (uint32_t)desc_p;
355 uint32_t desc_end = desc_start +
356 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
357 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
360 /* Invalidate entire buffer descriptor */
361 invalidate_dcache_range(desc_start, desc_end);
363 status = desc_p->txrx_status;
365 /* Check if the owner is the CPU */
366 if (!(status & DESC_RXSTS_OWNBYDMA)) {
368 length = (status & DESC_RXSTS_FRMLENMSK) >> \
369 DESC_RXSTS_FRMLENSHFT;
371 /* Invalidate received data */
372 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
373 invalidate_dcache_range(data_start, data_end);
374 *packetp = desc_p->dmamac_addr;
380 static int _dw_free_pkt(struct dw_eth_dev *priv)
382 u32 desc_num = priv->rx_currdescnum;
383 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
384 uint32_t desc_start = (uint32_t)desc_p;
385 uint32_t desc_end = desc_start +
386 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
389 * Make the current descriptor valid again and go to
392 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
394 /* Flush only status field - others weren't changed */
395 flush_dcache_range(desc_start, desc_end);
397 /* Test the wrap-around condition. */
398 if (++desc_num >= CONFIG_RX_DESCR_NUM)
400 priv->rx_currdescnum = desc_num;
405 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
407 struct phy_device *phydev;
408 int mask = 0xffffffff;
410 #ifdef CONFIG_PHY_ADDR
411 mask = 1 << CONFIG_PHY_ADDR;
414 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
418 phy_connect_dev(phydev, dev);
420 phydev->supported &= PHY_GBIT_FEATURES;
421 phydev->advertising = phydev->supported;
423 priv->phydev = phydev;
429 #ifndef CONFIG_DM_ETH
430 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
432 return _dw_eth_init(dev->priv, dev->enetaddr);
435 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
437 return _dw_eth_send(dev->priv, packet, length);
440 static int dw_eth_recv(struct eth_device *dev)
445 length = _dw_eth_recv(dev->priv, &packet);
446 if (length == -EAGAIN)
448 net_process_received_packet(packet, length);
450 _dw_free_pkt(dev->priv);
455 static void dw_eth_halt(struct eth_device *dev)
457 return _dw_eth_halt(dev->priv);
460 static int dw_write_hwaddr(struct eth_device *dev)
462 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
465 int designware_initialize(ulong base_addr, u32 interface)
467 struct eth_device *dev;
468 struct dw_eth_dev *priv;
470 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
475 * Since the priv structure contains the descriptors which need a strict
476 * buswidth alignment, memalign is used to allocate memory
478 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
479 sizeof(struct dw_eth_dev));
485 memset(dev, 0, sizeof(struct eth_device));
486 memset(priv, 0, sizeof(struct dw_eth_dev));
488 sprintf(dev->name, "dwmac.%lx", base_addr);
489 dev->iobase = (int)base_addr;
493 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
494 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
497 dev->init = dw_eth_init;
498 dev->send = dw_eth_send;
499 dev->recv = dw_eth_recv;
500 dev->halt = dw_eth_halt;
501 dev->write_hwaddr = dw_write_hwaddr;
505 priv->interface = interface;
507 dw_mdio_init(dev->name, priv->mac_regs_p);
508 priv->bus = miiphy_get_dev_by_name(dev->name);
510 return dw_phy_init(priv, dev);
515 static int designware_eth_start(struct udevice *dev)
517 struct eth_pdata *pdata = dev_get_platdata(dev);
519 return _dw_eth_init(dev->priv, pdata->enetaddr);
522 static int designware_eth_send(struct udevice *dev, void *packet, int length)
524 struct dw_eth_dev *priv = dev_get_priv(dev);
526 return _dw_eth_send(priv, packet, length);
529 static int designware_eth_recv(struct udevice *dev, uchar **packetp)
531 struct dw_eth_dev *priv = dev_get_priv(dev);
533 return _dw_eth_recv(priv, packetp);
536 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
539 struct dw_eth_dev *priv = dev_get_priv(dev);
541 return _dw_free_pkt(priv);
544 static void designware_eth_stop(struct udevice *dev)
546 struct dw_eth_dev *priv = dev_get_priv(dev);
548 return _dw_eth_halt(priv);
551 static int designware_eth_write_hwaddr(struct udevice *dev)
553 struct eth_pdata *pdata = dev_get_platdata(dev);
554 struct dw_eth_dev *priv = dev_get_priv(dev);
556 return _dw_write_hwaddr(priv, pdata->enetaddr);
559 static int designware_eth_probe(struct udevice *dev)
561 struct eth_pdata *pdata = dev_get_platdata(dev);
562 struct dw_eth_dev *priv = dev_get_priv(dev);
565 debug("%s, iobase=%lx, priv=%p\n", __func__, pdata->iobase, priv);
566 priv->mac_regs_p = (struct eth_mac_regs *)pdata->iobase;
567 priv->dma_regs_p = (struct eth_dma_regs *)(pdata->iobase +
569 priv->interface = pdata->phy_interface;
571 dw_mdio_init(dev->name, priv->mac_regs_p);
572 priv->bus = miiphy_get_dev_by_name(dev->name);
574 ret = dw_phy_init(priv, dev);
575 debug("%s, ret=%d\n", __func__, ret);
580 static const struct eth_ops designware_eth_ops = {
581 .start = designware_eth_start,
582 .send = designware_eth_send,
583 .recv = designware_eth_recv,
584 .free_pkt = designware_eth_free_pkt,
585 .stop = designware_eth_stop,
586 .write_hwaddr = designware_eth_write_hwaddr,
589 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
591 struct eth_pdata *pdata = dev_get_platdata(dev);
592 const char *phy_mode;
594 pdata->iobase = dev_get_addr(dev);
595 pdata->phy_interface = -1;
596 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
598 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
599 if (pdata->phy_interface == -1) {
600 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
607 static const struct udevice_id designware_eth_ids[] = {
608 { .compatible = "allwinner,sun7i-a20-gmac" },
612 U_BOOT_DRIVER(eth_sandbox) = {
613 .name = "eth_designware",
615 .of_match = designware_eth_ids,
616 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
617 .probe = designware_eth_probe,
618 .ops = &designware_eth_ops,
619 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
620 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
621 .flags = DM_FLAG_ALLOC_PRIV_DMA,