3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Designware ethernet IP driver for u-boot
31 #include <linux/err.h>
33 #include "designware.h"
35 static int configure_phy(struct eth_device *dev);
37 static void tx_descs_init(struct eth_device *dev)
39 struct dw_eth_dev *priv = dev->priv;
40 struct eth_dma_regs *dma_p = priv->dma_regs_p;
41 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
42 char *txbuffs = &priv->txbuffs[0];
43 struct dmamacdescr *desc_p;
46 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
47 desc_p = &desc_table_p[idx];
48 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
49 desc_p->dmamac_next = &desc_table_p[idx + 1];
51 #if defined(CONFIG_DW_ALTDESCRIPTOR)
52 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
53 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
54 DESC_TXSTS_TXCHECKINSCTRL | \
55 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
57 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
58 desc_p->dmamac_cntl = 0;
59 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
61 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
62 desc_p->txrx_status = 0;
66 /* Correcting the last pointer of the chain */
67 desc_p->dmamac_next = &desc_table_p[0];
69 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
72 static void rx_descs_init(struct eth_device *dev)
74 struct dw_eth_dev *priv = dev->priv;
75 struct eth_dma_regs *dma_p = priv->dma_regs_p;
76 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
77 char *rxbuffs = &priv->rxbuffs[0];
78 struct dmamacdescr *desc_p;
81 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
82 desc_p = &desc_table_p[idx];
83 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
84 desc_p->dmamac_next = &desc_table_p[idx + 1];
87 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
90 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
93 /* Correcting the last pointer of the chain */
94 desc_p->dmamac_next = &desc_table_p[0];
96 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
99 static void descs_init(struct eth_device *dev)
105 static int mac_reset(struct eth_device *dev)
107 struct dw_eth_dev *priv = dev->priv;
108 struct eth_mac_regs *mac_p = priv->mac_regs_p;
109 struct eth_dma_regs *dma_p = priv->dma_regs_p;
111 int timeout = CONFIG_MACRESET_TIMEOUT;
113 writel(DMAMAC_SRST, &dma_p->busmode);
114 writel(MII_PORTSELECT, &mac_p->conf);
117 if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
125 static int dw_write_hwaddr(struct eth_device *dev)
127 struct dw_eth_dev *priv = dev->priv;
128 struct eth_mac_regs *mac_p = priv->mac_regs_p;
129 u32 macid_lo, macid_hi;
130 u8 *mac_id = &dev->enetaddr[0];
132 macid_lo = mac_id[0] + (mac_id[1] << 8) + \
133 (mac_id[2] << 16) + (mac_id[3] << 24);
134 macid_hi = mac_id[4] + (mac_id[5] << 8);
136 writel(macid_hi, &mac_p->macaddr0hi);
137 writel(macid_lo, &mac_p->macaddr0lo);
142 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
144 struct dw_eth_dev *priv = dev->priv;
145 struct eth_mac_regs *mac_p = priv->mac_regs_p;
146 struct eth_dma_regs *dma_p = priv->dma_regs_p;
149 if (priv->phy_configured != 1)
152 /* Reset ethernet hardware */
153 if (mac_reset(dev) < 0)
156 /* Resore the HW MAC address as it has been lost during MAC reset */
157 dw_write_hwaddr(dev);
159 writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
162 writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
163 writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
165 conf = FRAMEBURSTENABLE | DISABLERXOWN;
167 if (priv->speed != SPEED_1000M)
168 conf |= MII_PORTSELECT;
170 if (priv->duplex == FULL_DUPLEX)
171 conf |= FULLDPLXMODE;
173 writel(conf, &mac_p->conf);
178 * Start/Enable xfer at dma as well as mac level
180 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
181 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
183 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
188 static int dw_eth_send(struct eth_device *dev, volatile void *packet,
191 struct dw_eth_dev *priv = dev->priv;
192 struct eth_dma_regs *dma_p = priv->dma_regs_p;
193 u32 desc_num = priv->tx_currdescnum;
194 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
196 /* Check if the descriptor is owned by CPU */
197 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
198 printf("CPU not owner of tx frame\n");
202 memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
204 #if defined(CONFIG_DW_ALTDESCRIPTOR)
205 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
206 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
207 DESC_TXCTRL_SIZE1MASK;
209 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
210 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
212 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
213 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
216 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
219 /* Test the wrap-around condition. */
220 if (++desc_num >= CONFIG_TX_DESCR_NUM)
223 priv->tx_currdescnum = desc_num;
225 /* Start the transmission */
226 writel(POLL_DATA, &dma_p->txpolldemand);
231 static int dw_eth_recv(struct eth_device *dev)
233 struct dw_eth_dev *priv = dev->priv;
234 u32 desc_num = priv->rx_currdescnum;
235 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
237 u32 status = desc_p->txrx_status;
240 /* Check if the owner is the CPU */
241 if (!(status & DESC_RXSTS_OWNBYDMA)) {
243 length = (status & DESC_RXSTS_FRMLENMSK) >> \
244 DESC_RXSTS_FRMLENSHFT;
246 NetReceive(desc_p->dmamac_addr, length);
249 * Make the current descriptor valid again and go to
252 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
254 /* Test the wrap-around condition. */
255 if (++desc_num >= CONFIG_RX_DESCR_NUM)
259 priv->rx_currdescnum = desc_num;
264 static void dw_eth_halt(struct eth_device *dev)
266 struct dw_eth_dev *priv = dev->priv;
269 priv->tx_currdescnum = priv->rx_currdescnum = 0;
272 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
274 struct dw_eth_dev *priv = dev->priv;
275 struct eth_mac_regs *mac_p = priv->mac_regs_p;
277 int timeout = CONFIG_MDIO_TIMEOUT;
279 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
280 ((reg << MIIREGSHIFT) & MII_REGMSK);
282 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
285 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
286 *val = readl(&mac_p->miidata);
295 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
297 struct dw_eth_dev *priv = dev->priv;
298 struct eth_mac_regs *mac_p = priv->mac_regs_p;
300 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
303 writel(val, &mac_p->miidata);
304 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
305 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
307 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
310 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
317 /* Needed as a fix for ST-Phy */
318 eth_mdio_read(dev, addr, reg, &value);
323 #if defined(CONFIG_DW_SEARCH_PHY)
324 static int find_phy(struct eth_device *dev)
330 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
331 oldctrl = ctrl & BMCR_ANENABLE;
333 ctrl ^= BMCR_ANENABLE;
334 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
335 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
336 ctrl &= BMCR_ANENABLE;
338 if (ctrl == oldctrl) {
341 ctrl ^= BMCR_ANENABLE;
342 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
346 } while (phy_addr < 32);
352 static int dw_reset_phy(struct eth_device *dev)
354 struct dw_eth_dev *priv = dev->priv;
356 int timeout = CONFIG_PHYRESET_TIMEOUT;
357 u32 phy_addr = priv->address;
359 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
361 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
362 if (!(ctrl & BMCR_RESET))
370 #ifdef CONFIG_PHY_RESET_DELAY
371 udelay(CONFIG_PHY_RESET_DELAY);
376 static int configure_phy(struct eth_device *dev)
378 struct dw_eth_dev *priv = dev->priv;
381 #if defined(CONFIG_DW_AUTONEG)
389 #if defined(CONFIG_DW_SEARCH_PHY)
390 phy_addr = find_phy(dev);
392 priv->address = phy_addr;
396 phy_addr = priv->address;
398 if (dw_reset_phy(dev) < 0)
401 #if defined(CONFIG_DW_AUTONEG)
402 /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
403 eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
405 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
407 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
409 #if defined(CONFIG_DW_SPEED10M)
410 bmcr &= ~BMCR_SPEED100;
412 #if defined(CONFIG_DW_DUPLEXHALF)
413 bmcr &= ~BMCR_FULLDPLX;
416 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
419 /* Read the phy status register and populate priv structure */
420 #if defined(CONFIG_DW_AUTONEG)
421 timeout = CONFIG_AUTONEG_TIMEOUT;
423 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
424 if (bmsr & BMSR_ANEGCOMPLETE)
429 eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
430 eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
432 if (bmsr & BMSR_ANEGCOMPLETE) {
433 if (btsr & PHY_1000BTSR_1000FD) {
434 priv->speed = SPEED_1000M;
435 bmcr |= BMCR_SPEED1000;
436 priv->duplex = FULL_DUPLEX;
437 bmcr |= BMCR_FULLDPLX;
438 } else if (btsr & PHY_1000BTSR_1000HD) {
439 priv->speed = SPEED_1000M;
440 bmcr |= BMCR_SPEED1000;
441 priv->duplex = HALF_DUPLEX;
442 bmcr &= ~BMCR_FULLDPLX;
443 } else if (anlpar & LPA_100FULL) {
444 priv->speed = SPEED_100M;
445 bmcr |= BMCR_SPEED100;
446 priv->duplex = FULL_DUPLEX;
447 bmcr |= BMCR_FULLDPLX;
448 } else if (anlpar & LPA_100HALF) {
449 priv->speed = SPEED_100M;
450 bmcr |= BMCR_SPEED100;
451 priv->duplex = HALF_DUPLEX;
452 bmcr &= ~BMCR_FULLDPLX;
453 } else if (anlpar & LPA_10FULL) {
454 priv->speed = SPEED_10M;
455 bmcr &= ~BMCR_SPEED100;
456 priv->duplex = FULL_DUPLEX;
457 bmcr |= BMCR_FULLDPLX;
459 priv->speed = SPEED_10M;
460 bmcr &= ~BMCR_SPEED100;
461 priv->duplex = HALF_DUPLEX;
462 bmcr &= ~BMCR_FULLDPLX;
464 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
469 if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
472 if (ctrl & BMCR_FULLDPLX)
473 priv->duplex = FULL_DUPLEX;
475 priv->duplex = HALF_DUPLEX;
477 if (ctrl & BMCR_SPEED1000)
478 priv->speed = SPEED_1000M;
479 else if (ctrl & BMCR_SPEED100)
480 priv->speed = SPEED_100M;
482 priv->speed = SPEED_10M;
484 priv->phy_configured = 1;
489 #if defined(CONFIG_MII)
490 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
492 struct eth_device *dev;
494 dev = eth_get_dev_by_name(devname);
496 eth_mdio_read(dev, addr, reg, val);
501 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
503 struct eth_device *dev;
505 dev = eth_get_dev_by_name(devname);
507 eth_mdio_write(dev, addr, reg, val);
513 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
515 struct eth_device *dev;
516 struct dw_eth_dev *priv;
518 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
523 * Since the priv structure contains the descriptors which need a strict
524 * buswidth alignment, memalign is used to allocate memory
526 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
532 memset(dev, 0, sizeof(struct eth_device));
533 memset(priv, 0, sizeof(struct dw_eth_dev));
535 sprintf(dev->name, "mii%d", id);
536 dev->iobase = (int)base_addr;
539 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
542 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
543 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
545 priv->address = phy_addr;
546 priv->phy_configured = 0;
548 if (mac_reset(dev) < 0)
553 dev->init = dw_eth_init;
554 dev->send = dw_eth_send;
555 dev->recv = dw_eth_recv;
556 dev->halt = dw_eth_halt;
557 dev->write_hwaddr = dw_write_hwaddr;
561 #if defined(CONFIG_MII)
562 miiphy_register(dev->name, dw_mii_read, dw_mii_write);