1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * Designware ethernet IP driver for U-Boot
22 #include <asm/cache.h>
23 #include <dm/device_compat.h>
24 #include <dm/device-internal.h>
25 #include <dm/devres.h>
27 #include <linux/compiler.h>
28 #include <linux/delay.h>
29 #include <linux/err.h>
30 #include <linux/kernel.h>
32 #include <power/regulator.h>
33 #include "designware.h"
35 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
38 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
39 struct eth_mac_regs *mac_p = priv->mac_regs_p;
41 struct eth_mac_regs *mac_p = bus->priv;
45 int timeout = CONFIG_MDIO_TIMEOUT;
47 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
48 ((reg << MIIREGSHIFT) & MII_REGMSK);
50 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
53 while (get_timer(start) < timeout) {
54 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
55 return readl(&mac_p->miidata);
62 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
66 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
67 struct eth_mac_regs *mac_p = priv->mac_regs_p;
69 struct eth_mac_regs *mac_p = bus->priv;
73 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
75 writel(val, &mac_p->miidata);
76 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
77 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
79 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
82 while (get_timer(start) < timeout) {
83 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
93 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
94 static int __dw_mdio_reset(struct udevice *dev)
96 struct dw_eth_dev *priv = dev_get_priv(dev);
97 struct dw_eth_pdata *pdata = dev_get_plat(dev);
100 if (!dm_gpio_is_valid(&priv->reset_gpio))
104 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
108 udelay(pdata->reset_delays[0]);
110 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
114 udelay(pdata->reset_delays[1]);
116 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
120 udelay(pdata->reset_delays[2]);
125 static int dw_mdio_reset(struct mii_dev *bus)
127 struct udevice *dev = bus->priv;
129 return __dw_mdio_reset(dev);
133 #if IS_ENABLED(CONFIG_DM_MDIO)
134 int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
136 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
138 return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
141 int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
143 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
145 return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
148 #if CONFIG_IS_ENABLED(DM_GPIO)
149 int designware_eth_mdio_reset(struct udevice *mdio_dev)
151 struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
152 struct udevice *dev = mdio_pdata->mii_bus->priv;
154 return __dw_mdio_reset(dev->parent);
158 static const struct mdio_ops designware_eth_mdio_ops = {
159 .read = designware_eth_mdio_read,
160 .write = designware_eth_mdio_write,
161 #if CONFIG_IS_ENABLED(DM_GPIO)
162 .reset = designware_eth_mdio_reset,
166 static int designware_eth_mdio_probe(struct udevice *dev)
168 /* Use the priv data of parent */
169 dev_set_priv(dev, dev_get_priv(dev->parent));
174 U_BOOT_DRIVER(designware_eth_mdio) = {
175 .name = "eth_designware_mdio",
177 .probe = designware_eth_mdio_probe,
178 .ops = &designware_eth_mdio_ops,
179 .plat_auto = sizeof(struct mdio_perdev_priv),
183 static int dw_mdio_init(const char *name, void *priv)
185 struct mii_dev *bus = mdio_alloc();
188 printf("Failed to allocate MDIO bus\n");
192 bus->read = dw_mdio_read;
193 bus->write = dw_mdio_write;
194 snprintf(bus->name, sizeof(bus->name), "%s", name);
195 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
196 bus->reset = dw_mdio_reset;
201 return mdio_register(bus);
204 #if IS_ENABLED(CONFIG_DM_MDIO)
205 static int dw_dm_mdio_init(const char *name, void *priv)
207 struct udevice *dev = priv;
211 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
212 const char *subnode_name = ofnode_get_name(node);
213 struct udevice *mdiodev;
215 if (strcmp(subnode_name, "mdio"))
218 ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
219 subnode_name, node, &mdiodev);
221 debug("%s: not able to bind mdio device node\n", __func__);
226 printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
228 return dw_mdio_init(name, priv);
232 static void tx_descs_init(struct dw_eth_dev *priv)
234 struct eth_dma_regs *dma_p = priv->dma_regs_p;
235 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
236 char *txbuffs = &priv->txbuffs[0];
237 struct dmamacdescr *desc_p;
240 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
241 desc_p = &desc_table_p[idx];
242 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
243 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
245 #if defined(CONFIG_DW_ALTDESCRIPTOR)
246 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
247 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
248 DESC_TXSTS_TXCHECKINSCTRL |
249 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
251 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
252 desc_p->dmamac_cntl = 0;
253 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
255 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
256 desc_p->txrx_status = 0;
260 /* Correcting the last pointer of the chain */
261 desc_p->dmamac_next = (ulong)&desc_table_p[0];
263 /* Flush all Tx buffer descriptors at once */
264 flush_dcache_range((ulong)priv->tx_mac_descrtable,
265 (ulong)priv->tx_mac_descrtable +
266 sizeof(priv->tx_mac_descrtable));
268 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
269 priv->tx_currdescnum = 0;
272 static void rx_descs_init(struct dw_eth_dev *priv)
274 struct eth_dma_regs *dma_p = priv->dma_regs_p;
275 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
276 char *rxbuffs = &priv->rxbuffs[0];
277 struct dmamacdescr *desc_p;
280 /* Before passing buffers to GMAC we need to make sure zeros
281 * written there right after "priv" structure allocation were
283 * Otherwise there's a chance to get some of them flushed in RAM when
284 * GMAC is already pushing data to RAM via DMA. This way incoming from
285 * GMAC data will be corrupted. */
286 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
288 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
289 desc_p = &desc_table_p[idx];
290 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
291 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
293 desc_p->dmamac_cntl =
294 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
297 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
300 /* Correcting the last pointer of the chain */
301 desc_p->dmamac_next = (ulong)&desc_table_p[0];
303 /* Flush all Rx buffer descriptors at once */
304 flush_dcache_range((ulong)priv->rx_mac_descrtable,
305 (ulong)priv->rx_mac_descrtable +
306 sizeof(priv->rx_mac_descrtable));
308 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
309 priv->rx_currdescnum = 0;
312 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
314 struct eth_mac_regs *mac_p = priv->mac_regs_p;
315 u32 macid_lo, macid_hi;
317 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
319 macid_hi = mac_id[4] + (mac_id[5] << 8);
321 writel(macid_hi, &mac_p->macaddr0hi);
322 writel(macid_lo, &mac_p->macaddr0lo);
327 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
328 struct phy_device *phydev)
330 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
333 printf("%s: No link.\n", phydev->dev->name);
337 if (phydev->speed != 1000)
338 conf |= MII_PORTSELECT;
340 conf &= ~MII_PORTSELECT;
342 if (phydev->speed == 100)
346 conf |= FULLDPLXMODE;
348 writel(conf, &mac_p->conf);
350 printf("Speed: %d, %s duplex%s\n", phydev->speed,
351 (phydev->duplex) ? "full" : "half",
352 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
357 static void _dw_eth_halt(struct dw_eth_dev *priv)
359 struct eth_mac_regs *mac_p = priv->mac_regs_p;
360 struct eth_dma_regs *dma_p = priv->dma_regs_p;
362 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
363 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
365 phy_shutdown(priv->phydev);
368 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
370 struct eth_mac_regs *mac_p = priv->mac_regs_p;
371 struct eth_dma_regs *dma_p = priv->dma_regs_p;
375 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
378 * When a MII PHY is used, we must set the PS bit for the DMA
381 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
382 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
384 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
386 start = get_timer(0);
387 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
388 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
389 printf("DMA reset timeout\n");
397 * Soft reset above clears HW address registers.
398 * So we have to set it here once again.
400 _dw_write_hwaddr(priv, enetaddr);
405 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
407 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
408 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
411 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
415 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
417 #ifdef CONFIG_DW_AXI_BURST_LEN
418 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
421 /* Start up the PHY */
422 ret = phy_startup(priv->phydev);
424 printf("Could not initialize PHY %s\n",
425 priv->phydev->dev->name);
429 ret = dw_adjust_link(priv, mac_p, priv->phydev);
436 int designware_eth_enable(struct dw_eth_dev *priv)
438 struct eth_mac_regs *mac_p = priv->mac_regs_p;
440 if (!priv->phydev->link)
443 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
450 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
452 struct eth_dma_regs *dma_p = priv->dma_regs_p;
453 u32 desc_num = priv->tx_currdescnum;
454 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
455 ulong desc_start = (ulong)desc_p;
456 ulong desc_end = desc_start +
457 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
458 ulong data_start = desc_p->dmamac_addr;
459 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
461 * Strictly we only need to invalidate the "txrx_status" field
462 * for the following check, but on some platforms we cannot
463 * invalidate only 4 bytes, so we flush the entire descriptor,
464 * which is 16 bytes in total. This is safe because the
465 * individual descriptors in the array are each aligned to
466 * ARCH_DMA_MINALIGN and padded appropriately.
468 invalidate_dcache_range(desc_start, desc_end);
470 /* Check if the descriptor is owned by CPU */
471 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
472 printf("CPU not owner of tx frame\n");
476 memcpy((void *)data_start, packet, length);
477 if (length < ETH_ZLEN) {
478 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
482 /* Flush data to be sent */
483 flush_dcache_range(data_start, data_end);
485 #if defined(CONFIG_DW_ALTDESCRIPTOR)
486 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
487 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
488 ((length << DESC_TXCTRL_SIZE1SHFT) &
489 DESC_TXCTRL_SIZE1MASK);
491 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
492 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
494 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
495 ((length << DESC_TXCTRL_SIZE1SHFT) &
496 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
499 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
502 /* Flush modified buffer descriptor */
503 flush_dcache_range(desc_start, desc_end);
505 /* Test the wrap-around condition. */
506 if (++desc_num >= CONFIG_TX_DESCR_NUM)
509 priv->tx_currdescnum = desc_num;
511 /* Start the transmission */
512 writel(POLL_DATA, &dma_p->txpolldemand);
517 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
519 u32 status, desc_num = priv->rx_currdescnum;
520 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
521 int length = -EAGAIN;
522 ulong desc_start = (ulong)desc_p;
523 ulong desc_end = desc_start +
524 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
525 ulong data_start = desc_p->dmamac_addr;
528 /* Invalidate entire buffer descriptor */
529 invalidate_dcache_range(desc_start, desc_end);
531 status = desc_p->txrx_status;
533 /* Check if the owner is the CPU */
534 if (!(status & DESC_RXSTS_OWNBYDMA)) {
536 length = (status & DESC_RXSTS_FRMLENMSK) >>
537 DESC_RXSTS_FRMLENSHFT;
539 /* Invalidate received data */
540 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
541 invalidate_dcache_range(data_start, data_end);
542 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
548 static int _dw_free_pkt(struct dw_eth_dev *priv)
550 u32 desc_num = priv->rx_currdescnum;
551 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
552 ulong desc_start = (ulong)desc_p;
553 ulong desc_end = desc_start +
554 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
557 * Make the current descriptor valid again and go to
560 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
562 /* Flush only status field - others weren't changed */
563 flush_dcache_range(desc_start, desc_end);
565 /* Test the wrap-around condition. */
566 if (++desc_num >= CONFIG_RX_DESCR_NUM)
568 priv->rx_currdescnum = desc_num;
573 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
575 struct phy_device *phydev;
578 #if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
579 phydev = dm_eth_phy_connect(dev);
585 #ifdef CONFIG_PHY_ADDR
586 phy_addr = CONFIG_PHY_ADDR;
589 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
594 phydev->supported &= PHY_GBIT_FEATURES;
595 if (priv->max_speed) {
596 ret = phy_set_supported(phydev, priv->max_speed);
600 phydev->advertising = phydev->supported;
602 priv->phydev = phydev;
608 #ifndef CONFIG_DM_ETH
609 static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
613 ret = designware_eth_init(dev->priv, dev->enetaddr);
615 ret = designware_eth_enable(dev->priv);
620 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
622 return _dw_eth_send(dev->priv, packet, length);
625 static int dw_eth_recv(struct eth_device *dev)
630 length = _dw_eth_recv(dev->priv, &packet);
631 if (length == -EAGAIN)
633 net_process_received_packet(packet, length);
635 _dw_free_pkt(dev->priv);
640 static void dw_eth_halt(struct eth_device *dev)
642 return _dw_eth_halt(dev->priv);
645 static int dw_write_hwaddr(struct eth_device *dev)
647 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
650 int designware_initialize(ulong base_addr, u32 interface)
652 struct eth_device *dev;
653 struct dw_eth_dev *priv;
655 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
660 * Since the priv structure contains the descriptors which need a strict
661 * buswidth alignment, memalign is used to allocate memory
663 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
664 sizeof(struct dw_eth_dev));
670 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
671 printf("designware: buffers are outside DMA memory\n");
675 memset(dev, 0, sizeof(struct eth_device));
676 memset(priv, 0, sizeof(struct dw_eth_dev));
678 sprintf(dev->name, "dwmac.%lx", base_addr);
679 dev->iobase = (int)base_addr;
683 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
684 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
687 dev->init = dw_eth_init;
688 dev->send = dw_eth_send;
689 dev->recv = dw_eth_recv;
690 dev->halt = dw_eth_halt;
691 dev->write_hwaddr = dw_write_hwaddr;
695 priv->interface = interface;
697 dw_mdio_init(dev->name, priv->mac_regs_p);
698 priv->bus = miiphy_get_dev_by_name(dev->name);
700 return dw_phy_init(priv, dev);
705 static int designware_eth_start(struct udevice *dev)
707 struct eth_pdata *pdata = dev_get_plat(dev);
708 struct dw_eth_dev *priv = dev_get_priv(dev);
711 ret = designware_eth_init(priv, pdata->enetaddr);
714 ret = designware_eth_enable(priv);
721 int designware_eth_send(struct udevice *dev, void *packet, int length)
723 struct dw_eth_dev *priv = dev_get_priv(dev);
725 return _dw_eth_send(priv, packet, length);
728 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
730 struct dw_eth_dev *priv = dev_get_priv(dev);
732 return _dw_eth_recv(priv, packetp);
735 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
737 struct dw_eth_dev *priv = dev_get_priv(dev);
739 return _dw_free_pkt(priv);
742 void designware_eth_stop(struct udevice *dev)
744 struct dw_eth_dev *priv = dev_get_priv(dev);
746 return _dw_eth_halt(priv);
749 int designware_eth_write_hwaddr(struct udevice *dev)
751 struct eth_pdata *pdata = dev_get_plat(dev);
752 struct dw_eth_dev *priv = dev_get_priv(dev);
754 return _dw_write_hwaddr(priv, pdata->enetaddr);
757 static int designware_eth_bind(struct udevice *dev)
759 if (IS_ENABLED(CONFIG_PCI)) {
760 static int num_cards;
763 /* Create a unique device name for PCI type devices */
764 if (device_is_on_pci_bus(dev)) {
765 sprintf(name, "eth_designware#%u", num_cards++);
766 device_set_name(dev, name);
773 int designware_eth_probe(struct udevice *dev)
775 struct eth_pdata *pdata = dev_get_plat(dev);
776 struct dw_eth_dev *priv = dev_get_priv(dev);
777 u32 iobase = pdata->iobase;
780 struct reset_ctl_bulk reset_bulk;
784 priv->clock_count = 0;
785 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
788 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
793 for (i = 0; i < clock_nb; i++) {
794 err = clk_get_by_index(dev, i, &priv->clocks[i]);
798 err = clk_enable(&priv->clocks[i]);
799 if (err && err != -ENOSYS && err != -ENOTSUPP) {
800 pr_err("failed to enable clock %d\n", i);
801 clk_free(&priv->clocks[i]);
806 } else if (clock_nb != -ENOENT) {
807 pr_err("failed to get clock phandle(%d)\n", clock_nb);
812 #if defined(CONFIG_DM_REGULATOR)
813 struct udevice *phy_supply;
815 ret = device_get_supply_regulator(dev, "phy-supply",
818 debug("%s: No phy supply\n", dev->name);
820 ret = regulator_set_enable(phy_supply, true);
822 puts("Error enabling phy supply\n");
828 ret = reset_get_bulk(dev, &reset_bulk);
830 dev_warn(dev, "Can't get reset: %d\n", ret);
832 reset_deassert_bulk(&reset_bulk);
835 * If we are on PCI bus, either directly attached to a PCI root port,
836 * or via a PCI bridge, fill in plat before we probe the hardware.
838 if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
839 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
840 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
841 iobase = dm_pci_mem_to_phys(dev, iobase);
843 pdata->iobase = iobase;
844 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
847 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
849 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
850 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
851 priv->interface = pdata->phy_interface;
852 priv->max_speed = pdata->max_speed;
854 #if IS_ENABLED(CONFIG_DM_MDIO)
855 ret = dw_dm_mdio_init(dev->name, dev);
857 ret = dw_mdio_init(dev->name, dev);
863 priv->bus = miiphy_get_dev_by_name(dev->name);
865 ret = dw_phy_init(priv, dev);
866 debug("%s, ret=%d\n", __func__, ret);
870 /* continue here for cleanup if no PHY found */
872 mdio_unregister(priv->bus);
873 mdio_free(priv->bus);
878 ret = clk_release_all(priv->clocks, priv->clock_count);
880 pr_err("failed to disable all clocks\n");
886 static int designware_eth_remove(struct udevice *dev)
888 struct dw_eth_dev *priv = dev_get_priv(dev);
891 mdio_unregister(priv->bus);
892 mdio_free(priv->bus);
895 return clk_release_all(priv->clocks, priv->clock_count);
901 const struct eth_ops designware_eth_ops = {
902 .start = designware_eth_start,
903 .send = designware_eth_send,
904 .recv = designware_eth_recv,
905 .free_pkt = designware_eth_free_pkt,
906 .stop = designware_eth_stop,
907 .write_hwaddr = designware_eth_write_hwaddr,
910 int designware_eth_of_to_plat(struct udevice *dev)
912 struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
913 #if CONFIG_IS_ENABLED(DM_GPIO)
914 struct dw_eth_dev *priv = dev_get_priv(dev);
916 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
917 #if CONFIG_IS_ENABLED(DM_GPIO)
918 int reset_flags = GPIOD_IS_OUT;
922 pdata->iobase = dev_read_addr(dev);
923 pdata->phy_interface = dev_read_phy_mode(dev);
924 if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
927 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
929 #if CONFIG_IS_ENABLED(DM_GPIO)
930 if (dev_read_bool(dev, "snps,reset-active-low"))
931 reset_flags |= GPIOD_ACTIVE_LOW;
933 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
934 &priv->reset_gpio, reset_flags);
936 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
937 dw_pdata->reset_delays, 3);
938 } else if (ret == -ENOENT) {
946 static const struct udevice_id designware_eth_ids[] = {
947 { .compatible = "allwinner,sun7i-a20-gmac" },
948 { .compatible = "amlogic,meson6-dwmac" },
949 { .compatible = "st,stm32-dwmac" },
950 { .compatible = "snps,arc-dwmac-3.70a" },
954 U_BOOT_DRIVER(eth_designware) = {
955 .name = "eth_designware",
957 .of_match = designware_eth_ids,
958 .of_to_plat = designware_eth_of_to_plat,
959 .bind = designware_eth_bind,
960 .probe = designware_eth_probe,
961 .remove = designware_eth_remove,
962 .ops = &designware_eth_ops,
963 .priv_auto = sizeof(struct dw_eth_dev),
964 .plat_auto = sizeof(struct dw_eth_pdata),
965 .flags = DM_FLAG_ALLOC_PRIV_DMA,
968 static struct pci_device_id supported[] = {
969 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
973 U_BOOT_PCI_DEVICE(eth_designware, supported);