1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
16 #define PCI_CFDA_PSM 0x43
18 #define CFRV_RN 0x000000f0 /* Revision Number */
20 #define WAKEUP 0x00 /* Power Saving Wakeup */
21 #define SLEEP 0x80 /* Power Saving Sleep Mode */
23 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
25 /* Ethernet chip registers. */
26 #define DE4X5_BMR 0x000 /* Bus Mode Register */
27 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
28 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
29 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
30 #define DE4X5_STS 0x028 /* Status Register */
31 #define DE4X5_OMR 0x030 /* Operation Mode Register */
32 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
33 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
36 #define BMR_SWR 0x00000001 /* Software Reset */
37 #define STS_TS 0x00700000 /* Transmit Process State */
38 #define STS_RS 0x000e0000 /* Receive Process State */
39 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
40 #define OMR_SR 0x00000002 /* Start/Stop Receive */
41 #define OMR_PS 0x00040000 /* Port Select */
42 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
43 #define OMR_PM 0x00000080 /* Pass All Multicast */
45 /* Descriptor bits. */
46 #define R_OWN 0x80000000 /* Own Bit */
47 #define RD_RER 0x02000000 /* Receive End Of Ring */
48 #define RD_LS 0x00000100 /* Last Descriptor */
49 #define RD_ES 0x00008000 /* Error Summary */
50 #define TD_TER 0x02000000 /* Transmit End Of Ring */
51 #define T_OWN 0x80000000 /* Own Bit */
52 #define TD_LS 0x40000000 /* Last Segment */
53 #define TD_FS 0x20000000 /* First Segment */
54 #define TD_ES 0x00008000 /* Error Summary */
55 #define TD_SET 0x08000000 /* Setup Packet */
57 /* The EEPROM commands include the alway-set leading bit. */
58 #define SROM_WRITE_CMD 5
59 #define SROM_READ_CMD 6
60 #define SROM_ERASE_CMD 7
62 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
63 #define SROM_RD 0x00004000 /* Read from Boot ROM */
64 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
65 #define EE_WRITE_0 0x4801
66 #define EE_WRITE_1 0x4805
67 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
68 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
70 #define DT_IN 0x00000004 /* Serial Data In */
71 #define DT_CLK 0x00000002 /* Serial ROM Clock */
72 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
76 #define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
78 #define NUM_RX_DESC PKTBUFSRX
79 #define NUM_TX_DESC 1 /* Number of TX descriptors */
80 #define RX_BUFF_SZ PKTSIZE_ALIGN
82 #define TOUT_LOOP 1000000
84 #define SETUP_FRAME_LEN 192
94 struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
95 struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
96 int rx_new; /* RX descriptor ring pointer */
97 int tx_new; /* TX descriptor ring pointer */
100 struct udevice *devno;
102 void __iomem *iobase;
106 /* RX and TX descriptor ring */
107 static u32 dc2114x_inl(struct dc2114x_priv *priv, u32 addr)
109 return le32_to_cpu(readl(priv->iobase + addr));
112 static void dc2114x_outl(struct dc2114x_priv *priv, u32 command, u32 addr)
114 writel(cpu_to_le32(command), priv->iobase + addr);
117 static void reset_de4x5(struct dc2114x_priv *priv)
121 i = dc2114x_inl(priv, DE4X5_BMR);
123 dc2114x_outl(priv, i | BMR_SWR, DE4X5_BMR);
125 dc2114x_outl(priv, i, DE4X5_BMR);
128 for (i = 0; i < 5; i++) {
129 dc2114x_inl(priv, DE4X5_BMR);
136 static void start_de4x5(struct dc2114x_priv *priv)
140 omr = dc2114x_inl(priv, DE4X5_OMR);
141 omr |= OMR_ST | OMR_SR;
142 dc2114x_outl(priv, omr, DE4X5_OMR); /* Enable the TX and/or RX */
145 static void stop_de4x5(struct dc2114x_priv *priv)
149 omr = dc2114x_inl(priv, DE4X5_OMR);
150 omr &= ~(OMR_ST | OMR_SR);
151 dc2114x_outl(priv, omr, DE4X5_OMR); /* Disable the TX and/or RX */
154 /* SROM Read and write routines. */
155 static void sendto_srom(struct dc2114x_priv *priv, u_int command, u_long addr)
157 dc2114x_outl(priv, command, addr);
161 static int getfrom_srom(struct dc2114x_priv *priv, u_long addr)
163 u32 tmp = dc2114x_inl(priv, addr);
169 /* Note: this routine returns extra data bits for size detection. */
170 static int do_read_eeprom(struct dc2114x_priv *priv, u_long ioaddr, int location,
173 int read_cmd = location | (SROM_READ_CMD << addr_len);
174 unsigned int retval = 0;
177 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
178 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
180 debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
182 /* Shift the read command bits out. */
183 for (i = 4 + addr_len; i >= 0; i--) {
184 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
186 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval,
189 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
192 debug_cond(SROM_DLEVEL >= 2, "%X",
193 getfrom_srom(priv, ioaddr) & 15);
194 retval = (retval << 1) |
195 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
198 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
200 debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(priv, ioaddr) & 15);
202 for (i = 16; i > 0; i--) {
203 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
205 debug_cond(SROM_DLEVEL >= 2, "%X",
206 getfrom_srom(priv, ioaddr) & 15);
207 retval = (retval << 1) |
208 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
209 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
213 /* Terminate the EEPROM access. */
214 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
216 debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
223 * This executes a generic EEPROM command, typically a write or write
224 * enable. It returns the data output from the EEPROM, and thus may
225 * also be used for reads.
227 static int do_eeprom_cmd(struct dc2114x_priv *priv, u_long ioaddr, int cmd,
230 unsigned int retval = 0;
232 debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
234 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
236 /* Shift the command bits out. */
238 short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
240 sendto_srom(priv, dataval, ioaddr);
243 debug_cond(SROM_DLEVEL >= 2, "%X",
244 getfrom_srom(priv, ioaddr) & 15);
246 sendto_srom(priv, dataval | DT_CLK, ioaddr);
248 retval = (retval << 1) |
249 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
250 } while (--cmd_len >= 0);
252 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
254 /* Terminate the EEPROM access. */
255 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
257 debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
262 static int read_srom(struct dc2114x_priv *priv, u_long ioaddr, int index)
266 ee_addr_size = (do_read_eeprom(priv, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
268 return do_eeprom_cmd(priv, ioaddr, 0xffff |
269 (((SROM_READ_CMD << ee_addr_size) | index) << 16),
270 3 + ee_addr_size + 16);
273 static void send_setup_frame(struct dc2114x_priv *priv)
275 char setup_frame[SETUP_FRAME_LEN];
276 char *pa = &setup_frame[0];
279 memset(pa, 0xff, SETUP_FRAME_LEN);
281 for (i = 0; i < ETH_ALEN; i++) {
282 *(pa + (i & 1)) = priv->enetaddr[i];
287 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
291 printf("%s: tx error buffer not ready\n", priv->name);
295 priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
296 (u32)&setup_frame[0]));
297 priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
298 priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
300 dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
302 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
306 printf("%s: tx buffer not ready\n", priv->name);
310 if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
311 printf("TX error status2 = 0x%08X\n",
312 le32_to_cpu(priv->tx_ring[priv->tx_new].status));
315 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
318 static int dc21x4x_send_common(struct dc2114x_priv *priv, void *packet, int length)
324 printf("%s: bad packet size: %d\n", priv->name, length);
328 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
332 printf("%s: tx error buffer not ready\n", priv->name);
336 priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
338 priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
339 priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
341 dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
343 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
347 printf(".%s: tx buffer not ready\n", priv->name);
351 if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
352 priv->tx_ring[priv->tx_new].status = 0x0;
359 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
363 static int dc21x4x_recv_check(struct dc2114x_priv *priv)
368 status = le32_to_cpu(priv->rx_ring[priv->rx_new].status);
373 if (status & RD_LS) {
374 /* Valid frame status. */
375 if (status & RD_ES) {
376 /* There was an error. */
377 printf("RX error status = 0x%08X\n", status);
380 /* A valid frame received. */
381 length = (le32_to_cpu(priv->rx_ring[priv->rx_new].status)
391 static int dc21x4x_init_common(struct dc2114x_priv *priv)
397 if (dc2114x_inl(priv, DE4X5_STS) & (STS_TS | STS_RS)) {
398 printf("Error: Cannot reset ethernet controller.\n");
402 dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
404 for (i = 0; i < NUM_RX_DESC; i++) {
405 priv->rx_ring[i].status = cpu_to_le32(R_OWN);
406 priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
407 priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
408 (u32)net_rx_packets[i]));
409 priv->rx_ring[i].next = 0;
412 for (i = 0; i < NUM_TX_DESC; i++) {
413 priv->tx_ring[i].status = 0;
414 priv->tx_ring[i].des1 = 0;
415 priv->tx_ring[i].buf = 0;
416 priv->tx_ring[i].next = 0;
419 priv->rx_ring_size = NUM_RX_DESC;
420 priv->tx_ring_size = NUM_TX_DESC;
422 /* Write the end of list marker to the descriptor lists. */
423 priv->rx_ring[priv->rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
424 priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
426 /* Tell the adapter where the TX/RX rings are located. */
427 dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
429 dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
437 send_setup_frame(priv);
442 static void dc21x4x_halt_common(struct dc2114x_priv *priv)
445 dc2114x_outl(priv, 0, DE4X5_SICR);
448 static void read_hw_addr(struct dc2114x_priv *priv)
450 u_short tmp, *p = (u_short *)(&priv->enetaddr[0]);
453 for (i = 0; i < (ETH_ALEN >> 1); i++) {
454 tmp = read_srom(priv, DE4X5_APROM, (SROM_HWADD >> 1) + i);
455 *p = le16_to_cpu(tmp);
459 if (!j || j == 0x2fffd) {
460 memset(priv->enetaddr, 0, ETH_ALEN);
461 debug("Warning: can't read HW address from SROM.\n");
465 static struct pci_device_id supported[] = {
466 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
467 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
471 static int dc2114x_start(struct udevice *dev)
473 struct eth_pdata *plat = dev_get_plat(dev);
474 struct dc2114x_priv *priv = dev_get_priv(dev);
476 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
478 /* Ensure we're not sleeping. */
479 dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
481 return dc21x4x_init_common(priv);
484 static void dc2114x_stop(struct udevice *dev)
486 struct dc2114x_priv *priv = dev_get_priv(dev);
488 dc21x4x_halt_common(priv);
490 dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
493 static int dc2114x_send(struct udevice *dev, void *packet, int length)
495 struct dc2114x_priv *priv = dev_get_priv(dev);
498 ret = dc21x4x_send_common(priv, packet, length);
500 return ret ? 0 : -ETIMEDOUT;
503 static int dc2114x_recv(struct udevice *dev, int flags, uchar **packetp)
505 struct dc2114x_priv *priv = dev_get_priv(dev);
508 ret = dc21x4x_recv_check(priv);
511 /* Update entry information. */
512 priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
519 *packetp = net_rx_packets[priv->rx_new];
524 static int dc2114x_free_pkt(struct udevice *dev, uchar *packet, int length)
526 struct dc2114x_priv *priv = dev_get_priv(dev);
528 priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
530 /* Update entry information. */
531 priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
536 static int dc2114x_read_rom_hwaddr(struct udevice *dev)
538 struct dc2114x_priv *priv = dev_get_priv(dev);
545 static int dc2114x_bind(struct udevice *dev)
547 static int card_number;
550 sprintf(name, "dc2114x#%u", card_number++);
552 return device_set_name(dev, name);
555 static int dc2114x_probe(struct udevice *dev)
557 struct eth_pdata *plat = dev_get_plat(dev);
558 struct dc2114x_priv *priv = dev_get_priv(dev);
562 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
565 debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
568 priv->enetaddr = plat->enetaddr;
569 priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
571 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
572 dm_pci_write_config16(dev, PCI_COMMAND, command);
573 dm_pci_read_config16(dev, PCI_COMMAND, &status);
574 if ((status & command) != command) {
575 printf("dc2114x: Couldn't enable IO access or Bus Mastering\n");
579 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
584 static const struct eth_ops dc2114x_ops = {
585 .start = dc2114x_start,
586 .send = dc2114x_send,
587 .recv = dc2114x_recv,
588 .stop = dc2114x_stop,
589 .free_pkt = dc2114x_free_pkt,
590 .read_rom_hwaddr = dc2114x_read_rom_hwaddr,
593 U_BOOT_DRIVER(eth_dc2114x) = {
594 .name = "eth_dc2114x",
596 .bind = dc2114x_bind,
597 .probe = dc2114x_probe,
599 .priv_auto = sizeof(struct dc2114x_priv),
600 .plat_auto = sizeof(struct eth_pdata),
603 U_BOOT_PCI_DEVICE(eth_dc2114x, supported);