Merge branch 'hs@denx.de' of git://git.denx.de/u-boot-staging
[platform/kernel/u-boot.git] / drivers / net / davinci_emac.c
1 /*
2  * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
3  *
4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5  *
6  * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
7  * follows:
8  *
9  * ----------------------------------------------------------------------------
10  *
11  * dm644x_emac.c
12  *
13  * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
14  *
15  * Copyright (C) 2005 Texas Instruments.
16  *
17  * ----------------------------------------------------------------------------
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  *  You should have received a copy of the GNU General Public License
30  *  along with this program; if not, write to the Free Software
31  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32  * ----------------------------------------------------------------------------
33
34  * Modifications:
35  * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
36  * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
37  *
38  */
39 #include <common.h>
40 #include <command.h>
41 #include <net.h>
42 #include <miiphy.h>
43 #include <malloc.h>
44 #include <asm/arch/emac_defs.h>
45 #include <asm/io.h>
46
47 unsigned int    emac_dbg = 0;
48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
49
50 #ifdef DAVINCI_EMAC_GIG_ENABLE
51 #define emac_gigabit_enable(phy_addr)   davinci_eth_gigabit_enable(phy_addr)
52 #else
53 #define emac_gigabit_enable(phy_addr)   /* no gigabit to enable */
54 #endif
55
56 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
57 #define CONFIG_SYS_EMAC_TI_CLKDIV       ((EMAC_MDIO_BUS_FREQ / \
58                 EMAC_MDIO_CLOCK_FREQ) - 1)
59 #endif
60
61 static void davinci_eth_mdio_enable(void);
62
63 static int gen_init_phy(int phy_addr);
64 static int gen_is_phy_connected(int phy_addr);
65 static int gen_get_link_speed(int phy_addr);
66 static int gen_auto_negotiate(int phy_addr);
67
68 void eth_mdio_enable(void)
69 {
70         davinci_eth_mdio_enable();
71 }
72
73 /* EMAC Addresses */
74 static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
75 static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
76 static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
77
78 /* EMAC descriptors */
79 static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
80 static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
81 static volatile emac_desc       *emac_rx_active_head = 0;
82 static volatile emac_desc       *emac_rx_active_tail = 0;
83 static int                      emac_rx_queue_active = 0;
84
85 /* Receive packet buffers */
86 static unsigned char            emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
87
88 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
89 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT       3
90 #endif
91
92 /* PHY address for a discovered PHY (0xff - not found) */
93 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
94
95 /* number of PHY found active */
96 static u_int8_t num_phy;
97
98 phy_t                           phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
99
100 static int davinci_eth_set_mac_addr(struct eth_device *dev)
101 {
102         unsigned long           mac_hi;
103         unsigned long           mac_lo;
104
105         /*
106          * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
107          * receive)
108          *  Using channel 0 only - other channels are disabled
109          *  */
110         writel(0, &adap_emac->MACINDEX);
111         mac_hi = (dev->enetaddr[3] << 24) |
112                  (dev->enetaddr[2] << 16) |
113                  (dev->enetaddr[1] << 8)  |
114                  (dev->enetaddr[0]);
115         mac_lo = (dev->enetaddr[5] << 8) |
116                  (dev->enetaddr[4]);
117
118         writel(mac_hi, &adap_emac->MACADDRHI);
119 #if defined(DAVINCI_EMAC_VERSION2)
120         writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
121                &adap_emac->MACADDRLO);
122 #else
123         writel(mac_lo, &adap_emac->MACADDRLO);
124 #endif
125
126         writel(0, &adap_emac->MACHASH1);
127         writel(0, &adap_emac->MACHASH2);
128
129         /* Set source MAC address - REQUIRED */
130         writel(mac_hi, &adap_emac->MACSRCADDRHI);
131         writel(mac_lo, &adap_emac->MACSRCADDRLO);
132
133
134         return 0;
135 }
136
137 static void davinci_eth_mdio_enable(void)
138 {
139         u_int32_t       clkdiv;
140
141         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
142
143         writel((clkdiv & 0xff) |
144                MDIO_CONTROL_ENABLE |
145                MDIO_CONTROL_FAULT |
146                MDIO_CONTROL_FAULT_ENABLE,
147                &adap_mdio->CONTROL);
148
149         while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
150                 ;
151 }
152
153 /*
154  * Tries to find an active connected PHY. Returns 1 if address if found.
155  * If no active PHY (or more than one PHY) found returns 0.
156  * Sets active_phy_addr variable.
157  */
158 static int davinci_eth_phy_detect(void)
159 {
160         u_int32_t       phy_act_state;
161         int             i;
162         int             j;
163         unsigned int    count = 0;
164
165         for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
166                 active_phy_addr[i] = 0xff;
167
168         udelay(1000);
169         phy_act_state = readl(&adap_mdio->ALIVE);
170
171         if (phy_act_state == 0)
172                 return 0;               /* No active PHYs */
173
174         debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
175
176         for (i = 0, j = 0; i < 32; i++)
177                 if (phy_act_state & (1 << i)) {
178                         count++;
179                         if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
180                                 active_phy_addr[j++] = i;
181                         } else {
182                                 printf("%s: to many PHYs detected.\n",
183                                         __func__);
184                                 count = 0;
185                                 break;
186                         }
187                 }
188
189         num_phy = count;
190
191         return count;
192 }
193
194
195 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
196 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
197 {
198         int     tmp;
199
200         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
201                 ;
202
203         writel(MDIO_USERACCESS0_GO |
204                MDIO_USERACCESS0_WRITE_READ |
205                ((reg_num & 0x1f) << 21) |
206                ((phy_addr & 0x1f) << 16),
207                &adap_mdio->USERACCESS0);
208
209         /* Wait for command to complete */
210         while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
211                 ;
212
213         if (tmp & MDIO_USERACCESS0_ACK) {
214                 *data = tmp & 0xffff;
215                 return(1);
216         }
217
218         *data = -1;
219         return(0);
220 }
221
222 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
223 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
224 {
225
226         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
227                 ;
228
229         writel(MDIO_USERACCESS0_GO |
230                MDIO_USERACCESS0_WRITE_WRITE |
231                ((reg_num & 0x1f) << 21) |
232                ((phy_addr & 0x1f) << 16) |
233                (data & 0xffff),
234                &adap_mdio->USERACCESS0);
235
236         /* Wait for command to complete */
237         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
238                 ;
239
240         return(1);
241 }
242
243 /* PHY functions for a generic PHY */
244 static int gen_init_phy(int phy_addr)
245 {
246         int     ret = 1;
247
248         if (gen_get_link_speed(phy_addr)) {
249                 /* Try another time */
250                 ret = gen_get_link_speed(phy_addr);
251         }
252
253         return(ret);
254 }
255
256 static int gen_is_phy_connected(int phy_addr)
257 {
258         u_int16_t       dummy;
259
260         return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
261 }
262
263 static int get_active_phy(void)
264 {
265         int i;
266
267         for (i = 0; i < num_phy; i++)
268                 if (phy[i].get_link_speed(active_phy_addr[i]))
269                         return i;
270
271         return -1;      /* Return error if no link */
272 }
273
274 static int gen_get_link_speed(int phy_addr)
275 {
276         u_int16_t       tmp;
277
278         if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
279                         (tmp & 0x04)) {
280 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
281                 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
282                 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
283
284                 /* Speed doesn't matter, there is no setting for it in EMAC. */
285                 if (tmp & (LPA_100FULL | LPA_10FULL)) {
286                         /* set EMAC for Full Duplex  */
287                         writel(EMAC_MACCONTROL_MIIEN_ENABLE |
288                                         EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
289                                         &adap_emac->MACCONTROL);
290                 } else {
291                         /*set EMAC for Half Duplex  */
292                         writel(EMAC_MACCONTROL_MIIEN_ENABLE,
293                                         &adap_emac->MACCONTROL);
294                 }
295
296                 if (tmp & (LPA_100FULL | LPA_100HALF))
297                         writel(readl(&adap_emac->MACCONTROL) |
298                                         EMAC_MACCONTROL_RMIISPEED_100,
299                                          &adap_emac->MACCONTROL);
300                 else
301                         writel(readl(&adap_emac->MACCONTROL) &
302                                         ~EMAC_MACCONTROL_RMIISPEED_100,
303                                          &adap_emac->MACCONTROL);
304 #endif
305                 return(1);
306         }
307
308         return(0);
309 }
310
311 static int gen_auto_negotiate(int phy_addr)
312 {
313         u_int16_t       tmp;
314         u_int16_t       val;
315         unsigned long   cntr = 0;
316
317         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
318                 return 0;
319
320         val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
321                                                 BMCR_SPEED100;
322         davinci_eth_phy_write(phy_addr, MII_BMCR, val);
323
324         if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
325                 return 0;
326
327         val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
328                                                         ADVERTISE_10HALF);
329         davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
330
331         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
332                 return(0);
333
334         /* Restart Auto_negotiation  */
335         tmp |= BMCR_ANRESTART;
336         davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
337
338         /*check AutoNegotiate complete */
339         do {
340                 udelay(40000);
341                 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
342                         return 0;
343
344                 if (tmp & BMSR_ANEGCOMPLETE)
345                         break;
346
347                 cntr++;
348         } while (cntr < 200);
349
350         if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
351                 return(0);
352
353         if (!(tmp & BMSR_ANEGCOMPLETE))
354                 return(0);
355
356         return(gen_get_link_speed(phy_addr));
357 }
358 /* End of generic PHY functions */
359
360
361 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
362 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
363 {
364         return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
365 }
366
367 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
368 {
369         return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
370 }
371 #endif
372
373 static void  __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
374 {
375         u_int16_t data;
376
377         if (davinci_eth_phy_read(phy_addr, 0, &data)) {
378                 if (data & (1 << 6)) { /* speed selection MSB */
379                         /*
380                          * Check if link detected is giga-bit
381                          * If Gigabit mode detected, enable gigbit in MAC
382                          */
383                         writel(readl(&adap_emac->MACCONTROL) |
384                                 EMAC_MACCONTROL_GIGFORCE |
385                                 EMAC_MACCONTROL_GIGABIT_ENABLE,
386                                 &adap_emac->MACCONTROL);
387                 }
388         }
389 }
390
391 /* Eth device open */
392 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
393 {
394         dv_reg_p                addr;
395         u_int32_t               clkdiv, cnt;
396         volatile emac_desc      *rx_desc;
397         int                     index;
398
399         debug_emac("+ emac_open\n");
400
401         /* Reset EMAC module and disable interrupts in wrapper */
402         writel(1, &adap_emac->SOFTRESET);
403         while (readl(&adap_emac->SOFTRESET) != 0)
404                 ;
405 #if defined(DAVINCI_EMAC_VERSION2)
406         writel(1, &adap_ewrap->softrst);
407         while (readl(&adap_ewrap->softrst) != 0)
408                 ;
409 #else
410         writel(0, &adap_ewrap->EWCTL);
411         for (cnt = 0; cnt < 5; cnt++) {
412                 clkdiv = readl(&adap_ewrap->EWCTL);
413         }
414 #endif
415
416 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
417         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
418         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
419         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
420         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
421 #endif
422         rx_desc = emac_rx_desc;
423
424         writel(1, &adap_emac->TXCONTROL);
425         writel(1, &adap_emac->RXCONTROL);
426
427         davinci_eth_set_mac_addr(dev);
428
429         /* Set DMA 8 TX / 8 RX Head pointers to 0 */
430         addr = &adap_emac->TX0HDP;
431         for(cnt = 0; cnt < 16; cnt++)
432                 writel(0, addr++);
433
434         addr = &adap_emac->RX0HDP;
435         for(cnt = 0; cnt < 16; cnt++)
436                 writel(0, addr++);
437
438         /* Clear Statistics (do this before setting MacControl register) */
439         addr = &adap_emac->RXGOODFRAMES;
440         for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
441                 writel(0, addr++);
442
443         /* No multicast addressing */
444         writel(0, &adap_emac->MACHASH1);
445         writel(0, &adap_emac->MACHASH2);
446
447         /* Create RX queue and set receive process in place */
448         emac_rx_active_head = emac_rx_desc;
449         for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
450                 rx_desc->next = (u_int32_t)(rx_desc + 1);
451                 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
452                 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
453                 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
454                 rx_desc++;
455         }
456
457         /* Finalize the rx desc list */
458         rx_desc--;
459         rx_desc->next = 0;
460         emac_rx_active_tail = rx_desc;
461         emac_rx_queue_active = 1;
462
463         /* Enable TX/RX */
464         writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
465         writel(0, &adap_emac->RXBUFFEROFFSET);
466
467         /*
468          * No fancy configs - Use this for promiscous debug
469          *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
470          */
471         writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
472
473         /* Enable ch 0 only */
474         writel(1, &adap_emac->RXUNICASTSET);
475
476         /* Enable MII interface and Full duplex mode */
477 #ifdef CONFIG_SOC_DA8XX
478         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
479                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
480                 EMAC_MACCONTROL_RMIISPEED_100),
481                &adap_emac->MACCONTROL);
482 #else
483         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
484                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
485                &adap_emac->MACCONTROL);
486 #endif
487
488         /* Init MDIO & get link state */
489         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
490         writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
491                &adap_mdio->CONTROL);
492
493         /* We need to wait for MDIO to start */
494         udelay(1000);
495
496         index = get_active_phy();
497         if (index == -1)
498                 return(0);
499
500         emac_gigabit_enable(active_phy_addr[index]);
501
502         /* Start receive process */
503         writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
504
505         debug_emac("- emac_open\n");
506
507         return(1);
508 }
509
510 /* EMAC Channel Teardown */
511 static void davinci_eth_ch_teardown(int ch)
512 {
513         dv_reg          dly = 0xff;
514         dv_reg          cnt;
515
516         debug_emac("+ emac_ch_teardown\n");
517
518         if (ch == EMAC_CH_TX) {
519                 /* Init TX channel teardown */
520                 writel(0, &adap_emac->TXTEARDOWN);
521                 do {
522                         /*
523                          * Wait here for Tx teardown completion interrupt to
524                          * occur. Note: A task delay can be called here to pend
525                          * rather than occupying CPU cycles - anyway it has
526                          * been found that teardown takes very few cpu cycles
527                          * and does not affect functionality
528                          */
529                         dly--;
530                         udelay(1);
531                         if (dly == 0)
532                                 break;
533                         cnt = readl(&adap_emac->TX0CP);
534                 } while (cnt != 0xfffffffc);
535                 writel(cnt, &adap_emac->TX0CP);
536                 writel(0, &adap_emac->TX0HDP);
537         } else {
538                 /* Init RX channel teardown */
539                 writel(0, &adap_emac->RXTEARDOWN);
540                 do {
541                         /*
542                          * Wait here for Rx teardown completion interrupt to
543                          * occur. Note: A task delay can be called here to pend
544                          * rather than occupying CPU cycles - anyway it has
545                          * been found that teardown takes very few cpu cycles
546                          * and does not affect functionality
547                          */
548                         dly--;
549                         udelay(1);
550                         if (dly == 0)
551                                 break;
552                         cnt = readl(&adap_emac->RX0CP);
553                 } while (cnt != 0xfffffffc);
554                 writel(cnt, &adap_emac->RX0CP);
555                 writel(0, &adap_emac->RX0HDP);
556         }
557
558         debug_emac("- emac_ch_teardown\n");
559 }
560
561 /* Eth device close */
562 static void davinci_eth_close(struct eth_device *dev)
563 {
564         debug_emac("+ emac_close\n");
565
566         davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
567         davinci_eth_ch_teardown(EMAC_CH_RX);    /* RX Channel teardown */
568
569         /* Reset EMAC module and disable interrupts in wrapper */
570         writel(1, &adap_emac->SOFTRESET);
571 #if defined(DAVINCI_EMAC_VERSION2)
572         writel(1, &adap_ewrap->softrst);
573 #else
574         writel(0, &adap_ewrap->EWCTL);
575 #endif
576
577 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
578         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
579         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
580         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
581         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
582 #endif
583         debug_emac("- emac_close\n");
584 }
585
586 static int tx_send_loop = 0;
587
588 /*
589  * This function sends a single packet on the network and returns
590  * positive number (number of bytes transmitted) or negative for error
591  */
592 static int davinci_eth_send_packet (struct eth_device *dev,
593                                         volatile void *packet, int length)
594 {
595         int ret_status = -1;
596         int index;
597         tx_send_loop = 0;
598
599         index = get_active_phy();
600         if (index == -1) {
601                 printf(" WARN: emac_send_packet: No link\n");
602                 return (ret_status);
603         }
604
605         emac_gigabit_enable(active_phy_addr[index]);
606
607         /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
608         if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
609                 length = EMAC_MIN_ETHERNET_PKT_SIZE;
610         }
611
612         /* Populate the TX descriptor */
613         emac_tx_desc->next = 0;
614         emac_tx_desc->buffer = (u_int8_t *) packet;
615         emac_tx_desc->buff_off_len = (length & 0xffff);
616         emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
617                                       EMAC_CPPI_SOP_BIT |
618                                       EMAC_CPPI_OWNERSHIP_BIT |
619                                       EMAC_CPPI_EOP_BIT);
620         /* Send the packet */
621         writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
622
623         /* Wait for packet to complete or link down */
624         while (1) {
625                 if (!phy[index].get_link_speed(active_phy_addr[index])) {
626                         davinci_eth_ch_teardown (EMAC_CH_TX);
627                         return (ret_status);
628                 }
629
630                 emac_gigabit_enable(active_phy_addr[index]);
631
632                 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
633                         ret_status = length;
634                         break;
635                 }
636                 tx_send_loop++;
637         }
638
639         return (ret_status);
640 }
641
642 /*
643  * This function handles receipt of a packet from the network
644  */
645 static int davinci_eth_rcv_packet (struct eth_device *dev)
646 {
647         volatile emac_desc *rx_curr_desc;
648         volatile emac_desc *curr_desc;
649         volatile emac_desc *tail_desc;
650         int status, ret = -1;
651
652         rx_curr_desc = emac_rx_active_head;
653         status = rx_curr_desc->pkt_flag_len;
654         if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
655                 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
656                         /* Error in packet - discard it and requeue desc */
657                         printf ("WARN: emac_rcv_pkt: Error in packet\n");
658                 } else {
659                         NetReceive (rx_curr_desc->buffer,
660                                     (rx_curr_desc->buff_off_len & 0xffff));
661                         ret = rx_curr_desc->buff_off_len & 0xffff;
662                 }
663
664                 /* Ack received packet descriptor */
665                 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
666                 curr_desc = rx_curr_desc;
667                 emac_rx_active_head =
668                         (volatile emac_desc *) rx_curr_desc->next;
669
670                 if (status & EMAC_CPPI_EOQ_BIT) {
671                         if (emac_rx_active_head) {
672                                 writel((unsigned long)emac_rx_active_head,
673                                        &adap_emac->RX0HDP);
674                         } else {
675                                 emac_rx_queue_active = 0;
676                                 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
677                         }
678                 }
679
680                 /* Recycle RX descriptor */
681                 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
682                 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
683                 rx_curr_desc->next = 0;
684
685                 if (emac_rx_active_head == 0) {
686                         printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
687                         emac_rx_active_head = curr_desc;
688                         emac_rx_active_tail = curr_desc;
689                         if (emac_rx_queue_active != 0) {
690                                 writel((unsigned long)emac_rx_active_head,
691                                        &adap_emac->RX0HDP);
692                                 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
693                                 emac_rx_queue_active = 1;
694                         }
695                 } else {
696                         tail_desc = emac_rx_active_tail;
697                         emac_rx_active_tail = curr_desc;
698                         tail_desc->next = (unsigned int) curr_desc;
699                         status = tail_desc->pkt_flag_len;
700                         if (status & EMAC_CPPI_EOQ_BIT) {
701                                 writel((unsigned long)curr_desc,
702                                        &adap_emac->RX0HDP);
703                                 status &= ~EMAC_CPPI_EOQ_BIT;
704                                 tail_desc->pkt_flag_len = status;
705                         }
706                 }
707                 return (ret);
708         }
709         return (0);
710 }
711
712 /*
713  * This function initializes the emac hardware. It does NOT initialize
714  * EMAC modules power or pin multiplexors, that is done by board_init()
715  * much earlier in bootup process. Returns 1 on success, 0 otherwise.
716  */
717 int davinci_emac_initialize(void)
718 {
719         u_int32_t       phy_id;
720         u_int16_t       tmp;
721         int             i;
722         int             ret;
723         struct eth_device *dev;
724
725         dev = malloc(sizeof *dev);
726
727         if (dev == NULL)
728                 return -1;
729
730         memset(dev, 0, sizeof *dev);
731         sprintf(dev->name, "DaVinci-EMAC");
732
733         dev->iobase = 0;
734         dev->init = davinci_eth_open;
735         dev->halt = davinci_eth_close;
736         dev->send = davinci_eth_send_packet;
737         dev->recv = davinci_eth_rcv_packet;
738         dev->write_hwaddr = davinci_eth_set_mac_addr;
739
740         eth_register(dev);
741
742         davinci_eth_mdio_enable();
743
744         /* let the EMAC detect the PHYs */
745         udelay(5000);
746
747         for (i = 0; i < 256; i++) {
748                 if (readl(&adap_mdio->ALIVE))
749                         break;
750                 udelay(1000);
751         }
752
753         if (i >= 256) {
754                 printf("No ETH PHY detected!!!\n");
755                 return(0);
756         }
757
758         /* Find if PHY(s) is/are connected */
759         ret = davinci_eth_phy_detect();
760         if (!ret)
761                 return(0);
762         else
763                 debug_emac(" %d ETH PHY detected\n", ret);
764
765         /* Get PHY ID and initialize phy_ops for a detected PHY */
766         for (i = 0; i < num_phy; i++) {
767                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
768                                                         &tmp)) {
769                         active_phy_addr[i] = 0xff;
770                         continue;
771                 }
772
773                 phy_id = (tmp << 16) & 0xffff0000;
774
775                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
776                                                         &tmp)) {
777                         active_phy_addr[i] = 0xff;
778                         continue;
779                 }
780
781                 phy_id |= tmp & 0x0000ffff;
782
783                 switch (phy_id) {
784                 case PHY_KSZ8873:
785                         sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
786                                                 active_phy_addr[i]);
787                         phy[i].init = ksz8873_init_phy;
788                         phy[i].is_phy_connected = ksz8873_is_phy_connected;
789                         phy[i].get_link_speed = ksz8873_get_link_speed;
790                         phy[i].auto_negotiate = ksz8873_auto_negotiate;
791                         break;
792                 case PHY_LXT972:
793                         sprintf(phy[i].name, "LXT972 @ 0x%02x",
794                                                 active_phy_addr[i]);
795                         phy[i].init = lxt972_init_phy;
796                         phy[i].is_phy_connected = lxt972_is_phy_connected;
797                         phy[i].get_link_speed = lxt972_get_link_speed;
798                         phy[i].auto_negotiate = lxt972_auto_negotiate;
799                         break;
800                 case PHY_DP83848:
801                         sprintf(phy[i].name, "DP83848 @ 0x%02x",
802                                                 active_phy_addr[i]);
803                         phy[i].init = dp83848_init_phy;
804                         phy[i].is_phy_connected = dp83848_is_phy_connected;
805                         phy[i].get_link_speed = dp83848_get_link_speed;
806                         phy[i].auto_negotiate = dp83848_auto_negotiate;
807                         break;
808                 case PHY_ET1011C:
809                         sprintf(phy[i].name, "ET1011C @ 0x%02x",
810                                                 active_phy_addr[i]);
811                         phy[i].init = gen_init_phy;
812                         phy[i].is_phy_connected = gen_is_phy_connected;
813                         phy[i].get_link_speed = et1011c_get_link_speed;
814                         phy[i].auto_negotiate = gen_auto_negotiate;
815                         break;
816                 default:
817                         sprintf(phy[i].name, "GENERIC @ 0x%02x",
818                                                 active_phy_addr[i]);
819                         phy[i].init = gen_init_phy;
820                         phy[i].is_phy_connected = gen_is_phy_connected;
821                         phy[i].get_link_speed = gen_get_link_speed;
822                         phy[i].auto_negotiate = gen_auto_negotiate;
823                 }
824
825                 debug("Ethernet PHY: %s\n", phy[i].name);
826
827                 miiphy_register(phy[i].name, davinci_mii_phy_read,
828                                                 davinci_mii_phy_write);
829         }
830         return(1);
831 }