davinci: emac: add support for more than 1 PHYs
[platform/kernel/u-boot.git] / drivers / net / davinci_emac.c
1 /*
2  * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
3  *
4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5  *
6  * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
7  * follows:
8  *
9  * ----------------------------------------------------------------------------
10  *
11  * dm644x_emac.c
12  *
13  * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
14  *
15  * Copyright (C) 2005 Texas Instruments.
16  *
17  * ----------------------------------------------------------------------------
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  *  You should have received a copy of the GNU General Public License
30  *  along with this program; if not, write to the Free Software
31  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32  * ----------------------------------------------------------------------------
33
34  * Modifications:
35  * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
36  * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
37  *
38  */
39 #include <common.h>
40 #include <command.h>
41 #include <net.h>
42 #include <miiphy.h>
43 #include <malloc.h>
44 #include <asm/arch/emac_defs.h>
45 #include <asm/io.h>
46
47 unsigned int    emac_dbg = 0;
48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
49
50 #ifdef DAVINCI_EMAC_GIG_ENABLE
51 #define emac_gigabit_enable()   davinci_eth_gigabit_enable()
52 #else
53 #define emac_gigabit_enable()   /* no gigabit to enable */
54 #endif
55
56 static void davinci_eth_mdio_enable(void);
57
58 static int gen_init_phy(int phy_addr);
59 static int gen_is_phy_connected(int phy_addr);
60 static int gen_get_link_speed(int phy_addr);
61 static int gen_auto_negotiate(int phy_addr);
62
63 void eth_mdio_enable(void)
64 {
65         davinci_eth_mdio_enable();
66 }
67
68 /* EMAC Addresses */
69 static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
70 static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
71 static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
72
73 /* EMAC descriptors */
74 static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
75 static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
76 static volatile emac_desc       *emac_rx_active_head = 0;
77 static volatile emac_desc       *emac_rx_active_tail = 0;
78 static int                      emac_rx_queue_active = 0;
79
80 /* Receive packet buffers */
81 static unsigned char            emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
82
83 #define MAX_PHY         3
84
85 /* PHY address for a discovered PHY (0xff - not found) */
86 static u_int8_t active_phy_addr[MAX_PHY] = { 0xff, 0xff, 0xff };
87
88 /* number of PHY found active */
89 static u_int8_t num_phy;
90
91 phy_t                           phy[MAX_PHY];
92
93 static int davinci_eth_set_mac_addr(struct eth_device *dev)
94 {
95         unsigned long           mac_hi;
96         unsigned long           mac_lo;
97
98         /*
99          * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
100          * receive)
101          *  Using channel 0 only - other channels are disabled
102          *  */
103         writel(0, &adap_emac->MACINDEX);
104         mac_hi = (dev->enetaddr[3] << 24) |
105                  (dev->enetaddr[2] << 16) |
106                  (dev->enetaddr[1] << 8)  |
107                  (dev->enetaddr[0]);
108         mac_lo = (dev->enetaddr[5] << 8) |
109                  (dev->enetaddr[4]);
110
111         writel(mac_hi, &adap_emac->MACADDRHI);
112 #if defined(DAVINCI_EMAC_VERSION2)
113         writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
114                &adap_emac->MACADDRLO);
115 #else
116         writel(mac_lo, &adap_emac->MACADDRLO);
117 #endif
118
119         writel(0, &adap_emac->MACHASH1);
120         writel(0, &adap_emac->MACHASH2);
121
122         /* Set source MAC address - REQUIRED */
123         writel(mac_hi, &adap_emac->MACSRCADDRHI);
124         writel(mac_lo, &adap_emac->MACSRCADDRLO);
125
126
127         return 0;
128 }
129
130 static void davinci_eth_mdio_enable(void)
131 {
132         u_int32_t       clkdiv;
133
134         clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
135
136         writel((clkdiv & 0xff) |
137                MDIO_CONTROL_ENABLE |
138                MDIO_CONTROL_FAULT |
139                MDIO_CONTROL_FAULT_ENABLE,
140                &adap_mdio->CONTROL);
141
142         while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
143                 ;
144 }
145
146 /*
147  * Tries to find an active connected PHY. Returns 1 if address if found.
148  * If no active PHY (or more than one PHY) found returns 0.
149  * Sets active_phy_addr variable.
150  */
151 static int davinci_eth_phy_detect(void)
152 {
153         u_int32_t       phy_act_state;
154         int             i;
155         int             j;
156         unsigned int    count = 0;
157
158         active_phy_addr[0] = 0xff;
159         active_phy_addr[1] = 0xff;
160         active_phy_addr[2] = 0xff;
161
162         udelay(1000);
163         phy_act_state = readl(&adap_mdio->ALIVE);
164
165         if (phy_act_state == 0)
166                 return 0;               /* No active PHYs */
167
168         debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
169
170         for (i = 0, j = 0; i < 32; i++)
171                 if (phy_act_state & (1 << i)) {
172                         count++;
173                         active_phy_addr[j++] = i;
174                 }
175
176         num_phy = count;
177
178         return count;
179 }
180
181
182 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
183 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
184 {
185         int     tmp;
186
187         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
188                 ;
189
190         writel(MDIO_USERACCESS0_GO |
191                MDIO_USERACCESS0_WRITE_READ |
192                ((reg_num & 0x1f) << 21) |
193                ((phy_addr & 0x1f) << 16),
194                &adap_mdio->USERACCESS0);
195
196         /* Wait for command to complete */
197         while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
198                 ;
199
200         if (tmp & MDIO_USERACCESS0_ACK) {
201                 *data = tmp & 0xffff;
202                 return(1);
203         }
204
205         *data = -1;
206         return(0);
207 }
208
209 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
210 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
211 {
212
213         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
214                 ;
215
216         writel(MDIO_USERACCESS0_GO |
217                MDIO_USERACCESS0_WRITE_WRITE |
218                ((reg_num & 0x1f) << 21) |
219                ((phy_addr & 0x1f) << 16) |
220                (data & 0xffff),
221                &adap_mdio->USERACCESS0);
222
223         /* Wait for command to complete */
224         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
225                 ;
226
227         return(1);
228 }
229
230 /* PHY functions for a generic PHY */
231 static int gen_init_phy(int phy_addr)
232 {
233         int     ret = 1;
234
235         if (gen_get_link_speed(phy_addr)) {
236                 /* Try another time */
237                 ret = gen_get_link_speed(phy_addr);
238         }
239
240         return(ret);
241 }
242
243 static int gen_is_phy_connected(int phy_addr)
244 {
245         u_int16_t       dummy;
246
247         return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
248 }
249
250 static int get_active_phy(void)
251 {
252         int i;
253
254         for (i = 0; i < num_phy; i++)
255                 if (phy[i].get_link_speed(active_phy_addr[i]))
256                         return i;
257
258         return -1;      /* Return error if no link */
259 }
260
261 static int gen_get_link_speed(int phy_addr)
262 {
263         u_int16_t       tmp;
264
265         if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
266                         (tmp & 0x04)) {
267 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
268                 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
269                 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
270
271                 /* Speed doesn't matter, there is no setting for it in EMAC. */
272                 if (tmp & (LPA_100FULL | LPA_10FULL)) {
273                         /* set EMAC for Full Duplex  */
274                         writel(EMAC_MACCONTROL_MIIEN_ENABLE |
275                                         EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
276                                         &adap_emac->MACCONTROL);
277                 } else {
278                         /*set EMAC for Half Duplex  */
279                         writel(EMAC_MACCONTROL_MIIEN_ENABLE,
280                                         &adap_emac->MACCONTROL);
281                 }
282
283                 if (tmp & (LPA_100FULL | LPA_100HALF))
284                         writel(readl(&adap_emac->MACCONTROL) |
285                                         EMAC_MACCONTROL_RMIISPEED_100,
286                                          &adap_emac->MACCONTROL);
287                 else
288                         writel(readl(&adap_emac->MACCONTROL) &
289                                         ~EMAC_MACCONTROL_RMIISPEED_100,
290                                          &adap_emac->MACCONTROL);
291 #endif
292                 return(1);
293         }
294
295         return(0);
296 }
297
298 static int gen_auto_negotiate(int phy_addr)
299 {
300         u_int16_t       tmp;
301         u_int16_t       val;
302         unsigned long   cntr = 0;
303
304         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
305                 return 0;
306
307         val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
308                                                 BMCR_SPEED100;
309         davinci_eth_phy_write(phy_addr, MII_BMCR, val);
310
311         if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
312                 return 0;
313
314         val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
315                                                         ADVERTISE_10HALF);
316         davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
317
318         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
319                 return(0);
320
321         /* Restart Auto_negotiation  */
322         tmp |= BMCR_ANRESTART;
323         davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
324
325         /*check AutoNegotiate complete */
326         do {
327                 udelay(40000);
328                 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
329                         return 0;
330
331                 if (tmp & BMSR_ANEGCOMPLETE)
332                         break;
333
334                 cntr++;
335         } while (cntr < 200);
336
337         if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
338                 return(0);
339
340         if (!(tmp & BMSR_ANEGCOMPLETE))
341                 return(0);
342
343         return(gen_get_link_speed(phy_addr));
344 }
345 /* End of generic PHY functions */
346
347
348 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
349 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
350 {
351         return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
352 }
353
354 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
355 {
356         return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
357 }
358 #endif
359
360 static void  __attribute__((unused)) davinci_eth_gigabit_enable(void)
361 {
362         u_int16_t data;
363
364         if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) {
365                 if (data & (1 << 6)) { /* speed selection MSB */
366                         /*
367                          * Check if link detected is giga-bit
368                          * If Gigabit mode detected, enable gigbit in MAC
369                          */
370                         writel(readl(&adap_emac->MACCONTROL) |
371                                 EMAC_MACCONTROL_GIGFORCE |
372                                 EMAC_MACCONTROL_GIGABIT_ENABLE,
373                                 &adap_emac->MACCONTROL);
374                 }
375         }
376 }
377
378 /* Eth device open */
379 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
380 {
381         dv_reg_p                addr;
382         u_int32_t               clkdiv, cnt;
383         volatile emac_desc      *rx_desc;
384         int                     index;
385
386         debug_emac("+ emac_open\n");
387
388         /* Reset EMAC module and disable interrupts in wrapper */
389         writel(1, &adap_emac->SOFTRESET);
390         while (readl(&adap_emac->SOFTRESET) != 0)
391                 ;
392 #if defined(DAVINCI_EMAC_VERSION2)
393         writel(1, &adap_ewrap->softrst);
394         while (readl(&adap_ewrap->softrst) != 0)
395                 ;
396 #else
397         writel(0, &adap_ewrap->EWCTL);
398         for (cnt = 0; cnt < 5; cnt++) {
399                 clkdiv = readl(&adap_ewrap->EWCTL);
400         }
401 #endif
402
403 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
404         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
405         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
406         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
407         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
408 #endif
409         rx_desc = emac_rx_desc;
410
411         writel(1, &adap_emac->TXCONTROL);
412         writel(1, &adap_emac->RXCONTROL);
413
414         davinci_eth_set_mac_addr(dev);
415
416         /* Set DMA 8 TX / 8 RX Head pointers to 0 */
417         addr = &adap_emac->TX0HDP;
418         for(cnt = 0; cnt < 16; cnt++)
419                 writel(0, addr++);
420
421         addr = &adap_emac->RX0HDP;
422         for(cnt = 0; cnt < 16; cnt++)
423                 writel(0, addr++);
424
425         /* Clear Statistics (do this before setting MacControl register) */
426         addr = &adap_emac->RXGOODFRAMES;
427         for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
428                 writel(0, addr++);
429
430         /* No multicast addressing */
431         writel(0, &adap_emac->MACHASH1);
432         writel(0, &adap_emac->MACHASH2);
433
434         /* Create RX queue and set receive process in place */
435         emac_rx_active_head = emac_rx_desc;
436         for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
437                 rx_desc->next = (u_int32_t)(rx_desc + 1);
438                 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
439                 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
440                 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
441                 rx_desc++;
442         }
443
444         /* Finalize the rx desc list */
445         rx_desc--;
446         rx_desc->next = 0;
447         emac_rx_active_tail = rx_desc;
448         emac_rx_queue_active = 1;
449
450         /* Enable TX/RX */
451         writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
452         writel(0, &adap_emac->RXBUFFEROFFSET);
453
454         /*
455          * No fancy configs - Use this for promiscous debug
456          *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
457          */
458         writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
459
460         /* Enable ch 0 only */
461         writel(1, &adap_emac->RXUNICASTSET);
462
463         /* Enable MII interface and Full duplex mode */
464 #ifdef CONFIG_SOC_DA8XX
465         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
466                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
467                 EMAC_MACCONTROL_RMIISPEED_100),
468                &adap_emac->MACCONTROL);
469 #else
470         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
471                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
472                &adap_emac->MACCONTROL);
473 #endif
474
475         /* Init MDIO & get link state */
476         clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
477         writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
478                &adap_mdio->CONTROL);
479
480         /* We need to wait for MDIO to start */
481         udelay(1000);
482
483         index = get_active_phy();
484         if (index == -1)
485                 return(0);
486
487         emac_gigabit_enable();
488
489         /* Start receive process */
490         writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
491
492         debug_emac("- emac_open\n");
493
494         return(1);
495 }
496
497 /* EMAC Channel Teardown */
498 static void davinci_eth_ch_teardown(int ch)
499 {
500         dv_reg          dly = 0xff;
501         dv_reg          cnt;
502
503         debug_emac("+ emac_ch_teardown\n");
504
505         if (ch == EMAC_CH_TX) {
506                 /* Init TX channel teardown */
507                 writel(0, &adap_emac->TXTEARDOWN);
508                 do {
509                         /*
510                          * Wait here for Tx teardown completion interrupt to
511                          * occur. Note: A task delay can be called here to pend
512                          * rather than occupying CPU cycles - anyway it has
513                          * been found that teardown takes very few cpu cycles
514                          * and does not affect functionality
515                          */
516                         dly--;
517                         udelay(1);
518                         if (dly == 0)
519                                 break;
520                         cnt = readl(&adap_emac->TX0CP);
521                 } while (cnt != 0xfffffffc);
522                 writel(cnt, &adap_emac->TX0CP);
523                 writel(0, &adap_emac->TX0HDP);
524         } else {
525                 /* Init RX channel teardown */
526                 writel(0, &adap_emac->RXTEARDOWN);
527                 do {
528                         /*
529                          * Wait here for Rx teardown completion interrupt to
530                          * occur. Note: A task delay can be called here to pend
531                          * rather than occupying CPU cycles - anyway it has
532                          * been found that teardown takes very few cpu cycles
533                          * and does not affect functionality
534                          */
535                         dly--;
536                         udelay(1);
537                         if (dly == 0)
538                                 break;
539                         cnt = readl(&adap_emac->RX0CP);
540                 } while (cnt != 0xfffffffc);
541                 writel(cnt, &adap_emac->RX0CP);
542                 writel(0, &adap_emac->RX0HDP);
543         }
544
545         debug_emac("- emac_ch_teardown\n");
546 }
547
548 /* Eth device close */
549 static void davinci_eth_close(struct eth_device *dev)
550 {
551         debug_emac("+ emac_close\n");
552
553         davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
554         davinci_eth_ch_teardown(EMAC_CH_RX);    /* RX Channel teardown */
555
556         /* Reset EMAC module and disable interrupts in wrapper */
557         writel(1, &adap_emac->SOFTRESET);
558 #if defined(DAVINCI_EMAC_VERSION2)
559         writel(1, &adap_ewrap->softrst);
560 #else
561         writel(0, &adap_ewrap->EWCTL);
562 #endif
563
564 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
565         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
566         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
567         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
568         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
569 #endif
570         debug_emac("- emac_close\n");
571 }
572
573 static int tx_send_loop = 0;
574
575 /*
576  * This function sends a single packet on the network and returns
577  * positive number (number of bytes transmitted) or negative for error
578  */
579 static int davinci_eth_send_packet (struct eth_device *dev,
580                                         volatile void *packet, int length)
581 {
582         int ret_status = -1;
583         int index;
584         tx_send_loop = 0;
585
586         index = get_active_phy();
587         if (index == -1) {
588                 printf(" WARN: emac_send_packet: No link\n");
589                 return (ret_status);
590         }
591
592         emac_gigabit_enable();
593
594         /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
595         if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
596                 length = EMAC_MIN_ETHERNET_PKT_SIZE;
597         }
598
599         /* Populate the TX descriptor */
600         emac_tx_desc->next = 0;
601         emac_tx_desc->buffer = (u_int8_t *) packet;
602         emac_tx_desc->buff_off_len = (length & 0xffff);
603         emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
604                                       EMAC_CPPI_SOP_BIT |
605                                       EMAC_CPPI_OWNERSHIP_BIT |
606                                       EMAC_CPPI_EOP_BIT);
607         /* Send the packet */
608         writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
609
610         /* Wait for packet to complete or link down */
611         while (1) {
612                 if (!phy[index].get_link_speed(active_phy_addr[index])) {
613                         davinci_eth_ch_teardown (EMAC_CH_TX);
614                         return (ret_status);
615                 }
616
617                 emac_gigabit_enable();
618
619                 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
620                         ret_status = length;
621                         break;
622                 }
623                 tx_send_loop++;
624         }
625
626         return (ret_status);
627 }
628
629 /*
630  * This function handles receipt of a packet from the network
631  */
632 static int davinci_eth_rcv_packet (struct eth_device *dev)
633 {
634         volatile emac_desc *rx_curr_desc;
635         volatile emac_desc *curr_desc;
636         volatile emac_desc *tail_desc;
637         int status, ret = -1;
638
639         rx_curr_desc = emac_rx_active_head;
640         status = rx_curr_desc->pkt_flag_len;
641         if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
642                 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
643                         /* Error in packet - discard it and requeue desc */
644                         printf ("WARN: emac_rcv_pkt: Error in packet\n");
645                 } else {
646                         NetReceive (rx_curr_desc->buffer,
647                                     (rx_curr_desc->buff_off_len & 0xffff));
648                         ret = rx_curr_desc->buff_off_len & 0xffff;
649                 }
650
651                 /* Ack received packet descriptor */
652                 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
653                 curr_desc = rx_curr_desc;
654                 emac_rx_active_head =
655                         (volatile emac_desc *) rx_curr_desc->next;
656
657                 if (status & EMAC_CPPI_EOQ_BIT) {
658                         if (emac_rx_active_head) {
659                                 writel((unsigned long)emac_rx_active_head,
660                                        &adap_emac->RX0HDP);
661                         } else {
662                                 emac_rx_queue_active = 0;
663                                 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
664                         }
665                 }
666
667                 /* Recycle RX descriptor */
668                 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
669                 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
670                 rx_curr_desc->next = 0;
671
672                 if (emac_rx_active_head == 0) {
673                         printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
674                         emac_rx_active_head = curr_desc;
675                         emac_rx_active_tail = curr_desc;
676                         if (emac_rx_queue_active != 0) {
677                                 writel((unsigned long)emac_rx_active_head,
678                                        &adap_emac->RX0HDP);
679                                 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
680                                 emac_rx_queue_active = 1;
681                         }
682                 } else {
683                         tail_desc = emac_rx_active_tail;
684                         emac_rx_active_tail = curr_desc;
685                         tail_desc->next = (unsigned int) curr_desc;
686                         status = tail_desc->pkt_flag_len;
687                         if (status & EMAC_CPPI_EOQ_BIT) {
688                                 writel((unsigned long)curr_desc,
689                                        &adap_emac->RX0HDP);
690                                 status &= ~EMAC_CPPI_EOQ_BIT;
691                                 tail_desc->pkt_flag_len = status;
692                         }
693                 }
694                 return (ret);
695         }
696         return (0);
697 }
698
699 /*
700  * This function initializes the emac hardware. It does NOT initialize
701  * EMAC modules power or pin multiplexors, that is done by board_init()
702  * much earlier in bootup process. Returns 1 on success, 0 otherwise.
703  */
704 int davinci_emac_initialize(void)
705 {
706         u_int32_t       phy_id;
707         u_int16_t       tmp;
708         int             i;
709         int             ret;
710         struct eth_device *dev;
711
712         dev = malloc(sizeof *dev);
713
714         if (dev == NULL)
715                 return -1;
716
717         memset(dev, 0, sizeof *dev);
718         sprintf(dev->name, "DaVinci-EMAC");
719
720         dev->iobase = 0;
721         dev->init = davinci_eth_open;
722         dev->halt = davinci_eth_close;
723         dev->send = davinci_eth_send_packet;
724         dev->recv = davinci_eth_rcv_packet;
725         dev->write_hwaddr = davinci_eth_set_mac_addr;
726
727         eth_register(dev);
728
729         davinci_eth_mdio_enable();
730
731         /* let the EMAC detect the PHYs */
732         udelay(5000);
733
734         for (i = 0; i < 256; i++) {
735                 if (readl(&adap_mdio->ALIVE))
736                         break;
737                 udelay(1000);
738         }
739
740         if (i >= 256) {
741                 printf("No ETH PHY detected!!!\n");
742                 return(0);
743         }
744
745         /* Find if PHY(s) is/are connected */
746         ret = davinci_eth_phy_detect();
747         if (!ret)
748                 return(0);
749         else
750                 printf(" %d ETH PHY detected\n", ret);
751
752         /* Get PHY ID and initialize phy_ops for a detected PHY */
753         for (i = 0; i < num_phy; i++) {
754                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
755                                                         &tmp)) {
756                         active_phy_addr[i] = 0xff;
757                         continue;
758                 }
759
760                 phy_id = (tmp << 16) & 0xffff0000;
761
762                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
763                                                         &tmp)) {
764                         active_phy_addr[i] = 0xff;
765                         continue;
766                 }
767
768                 phy_id |= tmp & 0x0000ffff;
769
770                 switch (phy_id) {
771                 case PHY_KSZ8873:
772                         sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
773                                                 active_phy_addr[i]);
774                         phy[i].init = ksz8873_init_phy;
775                         phy[i].is_phy_connected = ksz8873_is_phy_connected;
776                         phy[i].get_link_speed = ksz8873_get_link_speed;
777                         phy[i].auto_negotiate = ksz8873_auto_negotiate;
778                         break;
779                 case PHY_LXT972:
780                         sprintf(phy[i].name, "LXT972 @ 0x%02x",
781                                                 active_phy_addr[i]);
782                         phy[i].init = lxt972_init_phy;
783                         phy[i].is_phy_connected = lxt972_is_phy_connected;
784                         phy[i].get_link_speed = lxt972_get_link_speed;
785                         phy[i].auto_negotiate = lxt972_auto_negotiate;
786                         break;
787                 case PHY_DP83848:
788                         sprintf(phy[i].name, "DP83848 @ 0x%02x",
789                                                 active_phy_addr[i]);
790                         phy[i].init = dp83848_init_phy;
791                         phy[i].is_phy_connected = dp83848_is_phy_connected;
792                         phy[i].get_link_speed = dp83848_get_link_speed;
793                         phy[i].auto_negotiate = dp83848_auto_negotiate;
794                         break;
795                 case PHY_ET1011C:
796                         sprintf(phy[i].name, "ET1011C @ 0x%02x",
797                                                 active_phy_addr[i]);
798                         phy[i].init = gen_init_phy;
799                         phy[i].is_phy_connected = gen_is_phy_connected;
800                         phy[i].get_link_speed = et1011c_get_link_speed;
801                         phy[i].auto_negotiate = gen_auto_negotiate;
802                         break;
803                 default:
804                         sprintf(phy[i].name, "GENERIC @ 0x%02x",
805                                                 active_phy_addr[i]);
806                         phy[i].init = gen_init_phy;
807                         phy[i].is_phy_connected = gen_is_phy_connected;
808                         phy[i].get_link_speed = gen_get_link_speed;
809                         phy[i].auto_negotiate = gen_auto_negotiate;
810                 }
811
812                 debug("Ethernet PHY: %s\n", phy.name);
813
814                 miiphy_register(phy[i].name, davinci_mii_phy_read,
815                                                 davinci_mii_phy_write);
816         }
817         return(1);
818 }