2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
40 #include <linux/mdio.h>
41 #include <linux/sockios.h>
42 #include <linux/workqueue.h>
43 #include <linux/proc_fs.h>
44 #include <linux/rtnetlink.h>
45 #include <linux/firmware.h>
46 #include <linux/log2.h>
47 #include <linux/stringify.h>
48 #include <linux/sched.h>
49 #include <linux/slab.h>
50 #include <asm/uaccess.h>
53 #include "cxgb3_ioctl.h"
55 #include "cxgb3_offload.h"
58 #include "cxgb3_ctl_defs.h"
60 #include "firmware_exports.h"
63 MAX_TXQ_ENTRIES = 16384,
64 MAX_CTRL_TXQ_ENTRIES = 1024,
65 MAX_RSPQ_ENTRIES = 16384,
66 MAX_RX_BUFFERS = 16384,
67 MAX_RX_JUMBO_BUFFERS = 16384,
69 MIN_CTRL_TXQ_ENTRIES = 4,
70 MIN_RSPQ_ENTRIES = 32,
74 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
76 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
78 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
80 #define EEPROM_MAGIC 0x38E2F10C
82 #define CH_DEVICE(devid, idx) \
83 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
85 static DEFINE_PCI_DEVICE_TABLE(cxgb3_pci_tbl) = {
86 CH_DEVICE(0x20, 0), /* PE9000 */
87 CH_DEVICE(0x21, 1), /* T302E */
88 CH_DEVICE(0x22, 2), /* T310E */
89 CH_DEVICE(0x23, 3), /* T320X */
90 CH_DEVICE(0x24, 1), /* T302X */
91 CH_DEVICE(0x25, 3), /* T320E */
92 CH_DEVICE(0x26, 2), /* T310X */
93 CH_DEVICE(0x30, 2), /* T3B10 */
94 CH_DEVICE(0x31, 3), /* T3B20 */
95 CH_DEVICE(0x32, 1), /* T3B02 */
96 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
97 CH_DEVICE(0x36, 3), /* S320E-CR */
98 CH_DEVICE(0x37, 7), /* N320E-G2 */
102 MODULE_DESCRIPTION(DRV_DESC);
103 MODULE_AUTHOR("Chelsio Communications");
104 MODULE_LICENSE("Dual BSD/GPL");
105 MODULE_VERSION(DRV_VERSION);
106 MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
108 static int dflt_msg_enable = DFLT_MSG_ENABLE;
110 module_param(dflt_msg_enable, int, 0644);
111 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
114 * The driver uses the best interrupt scheme available on a platform in the
115 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
116 * of these schemes the driver may consider as follows:
118 * msi = 2: choose from among all three options
119 * msi = 1: only consider MSI and pin interrupts
120 * msi = 0: force pin interrupts
124 module_param(msi, int, 0644);
125 MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
128 * The driver enables offload as a default.
129 * To disable it, use ofld_disable = 1.
132 static int ofld_disable = 0;
134 module_param(ofld_disable, int, 0644);
135 MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
138 * We have work elements that we need to cancel when an interface is taken
139 * down. Normally the work elements would be executed by keventd but that
140 * can deadlock because of linkwatch. If our close method takes the rtnl
141 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
142 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
143 * for our work to complete. Get our own work queue to solve this.
145 struct workqueue_struct *cxgb3_wq;
148 * link_report - show link status and link speed/duplex
149 * @p: the port whose settings are to be reported
151 * Shows the link status, speed, and duplex of a port.
153 static void link_report(struct net_device *dev)
155 if (!netif_carrier_ok(dev))
156 printk(KERN_INFO "%s: link down\n", dev->name);
158 const char *s = "10Mbps";
159 const struct port_info *p = netdev_priv(dev);
161 switch (p->link_config.speed) {
173 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
174 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
178 static void enable_tx_fifo_drain(struct adapter *adapter,
179 struct port_info *pi)
181 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
183 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
184 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
185 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
188 static void disable_tx_fifo_drain(struct adapter *adapter,
189 struct port_info *pi)
191 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
195 void t3_os_link_fault(struct adapter *adap, int port_id, int state)
197 struct net_device *dev = adap->port[port_id];
198 struct port_info *pi = netdev_priv(dev);
200 if (state == netif_carrier_ok(dev))
204 struct cmac *mac = &pi->mac;
206 netif_carrier_on(dev);
208 disable_tx_fifo_drain(adap, pi);
210 /* Clear local faults */
211 t3_xgm_intr_disable(adap, pi->port_id);
212 t3_read_reg(adap, A_XGM_INT_STATUS +
215 A_XGM_INT_CAUSE + pi->mac.offset,
218 t3_set_reg_field(adap,
221 F_XGM_INT, F_XGM_INT);
222 t3_xgm_intr_enable(adap, pi->port_id);
224 t3_mac_enable(mac, MAC_DIRECTION_TX);
226 netif_carrier_off(dev);
229 enable_tx_fifo_drain(adap, pi);
235 * t3_os_link_changed - handle link status changes
236 * @adapter: the adapter associated with the link change
237 * @port_id: the port index whose limk status has changed
238 * @link_stat: the new status of the link
239 * @speed: the new speed setting
240 * @duplex: the new duplex setting
241 * @pause: the new flow-control setting
243 * This is the OS-dependent handler for link status changes. The OS
244 * neutral handler takes care of most of the processing for these events,
245 * then calls this handler for any OS-specific processing.
247 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
248 int speed, int duplex, int pause)
250 struct net_device *dev = adapter->port[port_id];
251 struct port_info *pi = netdev_priv(dev);
252 struct cmac *mac = &pi->mac;
254 /* Skip changes from disabled ports. */
255 if (!netif_running(dev))
258 if (link_stat != netif_carrier_ok(dev)) {
260 disable_tx_fifo_drain(adapter, pi);
262 t3_mac_enable(mac, MAC_DIRECTION_RX);
264 /* Clear local faults */
265 t3_xgm_intr_disable(adapter, pi->port_id);
266 t3_read_reg(adapter, A_XGM_INT_STATUS +
268 t3_write_reg(adapter,
269 A_XGM_INT_CAUSE + pi->mac.offset,
272 t3_set_reg_field(adapter,
273 A_XGM_INT_ENABLE + pi->mac.offset,
274 F_XGM_INT, F_XGM_INT);
275 t3_xgm_intr_enable(adapter, pi->port_id);
277 netif_carrier_on(dev);
279 netif_carrier_off(dev);
281 t3_xgm_intr_disable(adapter, pi->port_id);
282 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
283 t3_set_reg_field(adapter,
284 A_XGM_INT_ENABLE + pi->mac.offset,
288 pi->phy.ops->power_down(&pi->phy, 1);
290 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
291 t3_mac_disable(mac, MAC_DIRECTION_RX);
292 t3_link_start(&pi->phy, mac, &pi->link_config);
295 enable_tx_fifo_drain(adapter, pi);
303 * t3_os_phymod_changed - handle PHY module changes
304 * @phy: the PHY reporting the module change
305 * @mod_type: new module type
307 * This is the OS-dependent handler for PHY module changes. It is
308 * invoked when a PHY module is removed or inserted for any OS-specific
311 void t3_os_phymod_changed(struct adapter *adap, int port_id)
313 static const char *mod_str[] = {
314 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
317 const struct net_device *dev = adap->port[port_id];
318 const struct port_info *pi = netdev_priv(dev);
320 if (pi->phy.modtype == phy_modtype_none)
321 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
323 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
324 mod_str[pi->phy.modtype]);
327 static void cxgb_set_rxmode(struct net_device *dev)
329 struct port_info *pi = netdev_priv(dev);
331 t3_mac_set_rx_mode(&pi->mac, dev);
335 * link_start - enable a port
336 * @dev: the device to enable
338 * Performs the MAC and PHY actions needed to enable a port.
340 static void link_start(struct net_device *dev)
342 struct port_info *pi = netdev_priv(dev);
343 struct cmac *mac = &pi->mac;
346 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
347 t3_mac_set_mtu(mac, dev->mtu);
348 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
349 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
350 t3_mac_set_rx_mode(mac, dev);
351 t3_link_start(&pi->phy, mac, &pi->link_config);
352 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
355 static inline void cxgb_disable_msi(struct adapter *adapter)
357 if (adapter->flags & USING_MSIX) {
358 pci_disable_msix(adapter->pdev);
359 adapter->flags &= ~USING_MSIX;
360 } else if (adapter->flags & USING_MSI) {
361 pci_disable_msi(adapter->pdev);
362 adapter->flags &= ~USING_MSI;
367 * Interrupt handler for asynchronous events used with MSI-X.
369 static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
371 t3_slow_intr_handler(cookie);
376 * Name the MSI-X interrupts.
378 static void name_msix_vecs(struct adapter *adap)
380 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
382 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
383 adap->msix_info[0].desc[n] = 0;
385 for_each_port(adap, j) {
386 struct net_device *d = adap->port[j];
387 const struct port_info *pi = netdev_priv(d);
389 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
390 snprintf(adap->msix_info[msi_idx].desc, n,
391 "%s-%d", d->name, pi->first_qset + i);
392 adap->msix_info[msi_idx].desc[n] = 0;
397 static int request_msix_data_irqs(struct adapter *adap)
399 int i, j, err, qidx = 0;
401 for_each_port(adap, i) {
402 int nqsets = adap2pinfo(adap, i)->nqsets;
404 for (j = 0; j < nqsets; ++j) {
405 err = request_irq(adap->msix_info[qidx + 1].vec,
406 t3_intr_handler(adap,
409 adap->msix_info[qidx + 1].desc,
410 &adap->sge.qs[qidx]);
413 free_irq(adap->msix_info[qidx + 1].vec,
414 &adap->sge.qs[qidx]);
423 static void free_irq_resources(struct adapter *adapter)
425 if (adapter->flags & USING_MSIX) {
428 free_irq(adapter->msix_info[0].vec, adapter);
429 for_each_port(adapter, i)
430 n += adap2pinfo(adapter, i)->nqsets;
432 for (i = 0; i < n; ++i)
433 free_irq(adapter->msix_info[i + 1].vec,
434 &adapter->sge.qs[i]);
436 free_irq(adapter->pdev->irq, adapter);
439 static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
444 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
452 static int init_tp_parity(struct adapter *adap)
456 struct cpl_set_tcb_field *greq;
457 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
459 t3_tp_set_offload_mode(adap, 1);
461 for (i = 0; i < 16; i++) {
462 struct cpl_smt_write_req *req;
464 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
466 skb = adap->nofail_skb;
470 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
471 memset(req, 0, sizeof(*req));
472 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
473 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
474 req->mtu_idx = NMTUS - 1;
476 t3_mgmt_tx(adap, skb);
477 if (skb == adap->nofail_skb) {
478 await_mgmt_replies(adap, cnt, i + 1);
479 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
480 if (!adap->nofail_skb)
485 for (i = 0; i < 2048; i++) {
486 struct cpl_l2t_write_req *req;
488 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
490 skb = adap->nofail_skb;
494 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
495 memset(req, 0, sizeof(*req));
496 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
497 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
498 req->params = htonl(V_L2T_W_IDX(i));
499 t3_mgmt_tx(adap, skb);
500 if (skb == adap->nofail_skb) {
501 await_mgmt_replies(adap, cnt, 16 + i + 1);
502 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
503 if (!adap->nofail_skb)
508 for (i = 0; i < 2048; i++) {
509 struct cpl_rte_write_req *req;
511 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
513 skb = adap->nofail_skb;
517 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
518 memset(req, 0, sizeof(*req));
519 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
520 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
521 req->l2t_idx = htonl(V_L2T_W_IDX(i));
522 t3_mgmt_tx(adap, skb);
523 if (skb == adap->nofail_skb) {
524 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
525 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
526 if (!adap->nofail_skb)
531 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
533 skb = adap->nofail_skb;
537 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
538 memset(greq, 0, sizeof(*greq));
539 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
540 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
541 greq->mask = cpu_to_be64(1);
542 t3_mgmt_tx(adap, skb);
544 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
545 if (skb == adap->nofail_skb) {
546 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
547 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
550 t3_tp_set_offload_mode(adap, 0);
554 t3_tp_set_offload_mode(adap, 0);
559 * setup_rss - configure RSS
562 * Sets up RSS to distribute packets to multiple receive queues. We
563 * configure the RSS CPU lookup table to distribute to the number of HW
564 * receive queues, and the response queue lookup table to narrow that
565 * down to the response queues actually configured for each port.
566 * We always configure the RSS mapping for two ports since the mapping
567 * table has plenty of entries.
569 static void setup_rss(struct adapter *adap)
572 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
573 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
574 u8 cpus[SGE_QSETS + 1];
575 u16 rspq_map[RSS_TABLE_SIZE];
577 for (i = 0; i < SGE_QSETS; ++i)
579 cpus[SGE_QSETS] = 0xff; /* terminator */
581 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
582 rspq_map[i] = i % nq0;
583 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
586 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
587 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
588 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
591 static void ring_dbs(struct adapter *adap)
595 for (i = 0; i < SGE_QSETS; i++) {
596 struct sge_qset *qs = &adap->sge.qs[i];
599 for (j = 0; j < SGE_TXQ_PER_SET; j++)
600 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
604 static void init_napi(struct adapter *adap)
608 for (i = 0; i < SGE_QSETS; i++) {
609 struct sge_qset *qs = &adap->sge.qs[i];
612 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
617 * netif_napi_add() can be called only once per napi_struct because it
618 * adds each new napi_struct to a list. Be careful not to call it a
619 * second time, e.g., during EEH recovery, by making a note of it.
621 adap->flags |= NAPI_INIT;
625 * Wait until all NAPI handlers are descheduled. This includes the handlers of
626 * both netdevices representing interfaces and the dummy ones for the extra
629 static void quiesce_rx(struct adapter *adap)
633 for (i = 0; i < SGE_QSETS; i++)
634 if (adap->sge.qs[i].adap)
635 napi_disable(&adap->sge.qs[i].napi);
638 static void enable_all_napi(struct adapter *adap)
641 for (i = 0; i < SGE_QSETS; i++)
642 if (adap->sge.qs[i].adap)
643 napi_enable(&adap->sge.qs[i].napi);
647 * set_qset_lro - Turn a queue set's LRO capability on and off
648 * @dev: the device the qset is attached to
649 * @qset_idx: the queue set index
650 * @val: the LRO switch
652 * Sets LRO on or off for a particular queue set.
653 * the device's features flag is updated to reflect the LRO
654 * capability when all queues belonging to the device are
657 static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
659 struct port_info *pi = netdev_priv(dev);
660 struct adapter *adapter = pi->adapter;
662 adapter->params.sge.qset[qset_idx].lro = !!val;
663 adapter->sge.qs[qset_idx].lro_enabled = !!val;
667 * setup_sge_qsets - configure SGE Tx/Rx/response queues
670 * Determines how many sets of SGE queues to use and initializes them.
671 * We support multiple queue sets per port if we have MSI-X, otherwise
672 * just one queue set per port.
674 static int setup_sge_qsets(struct adapter *adap)
676 int i, j, err, irq_idx = 0, qset_idx = 0;
677 unsigned int ntxq = SGE_TXQ_PER_SET;
679 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
682 for_each_port(adap, i) {
683 struct net_device *dev = adap->port[i];
684 struct port_info *pi = netdev_priv(dev);
686 pi->qs = &adap->sge.qs[pi->first_qset];
687 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
688 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
689 err = t3_sge_alloc_qset(adap, qset_idx, 1,
690 (adap->flags & USING_MSIX) ? qset_idx + 1 :
692 &adap->params.sge.qset[qset_idx], ntxq, dev,
693 netdev_get_tx_queue(dev, j));
695 t3_free_sge_resources(adap);
704 static ssize_t attr_show(struct device *d, char *buf,
705 ssize_t(*format) (struct net_device *, char *))
709 /* Synchronize with ioctls that may shut down the device */
711 len = (*format) (to_net_dev(d), buf);
716 static ssize_t attr_store(struct device *d,
717 const char *buf, size_t len,
718 ssize_t(*set) (struct net_device *, unsigned int),
719 unsigned int min_val, unsigned int max_val)
725 if (!capable(CAP_NET_ADMIN))
728 val = simple_strtoul(buf, &endp, 0);
729 if (endp == buf || val < min_val || val > max_val)
733 ret = (*set) (to_net_dev(d), val);
740 #define CXGB3_SHOW(name, val_expr) \
741 static ssize_t format_##name(struct net_device *dev, char *buf) \
743 struct port_info *pi = netdev_priv(dev); \
744 struct adapter *adap = pi->adapter; \
745 return sprintf(buf, "%u\n", val_expr); \
747 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
750 return attr_show(d, buf, format_##name); \
753 static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
755 struct port_info *pi = netdev_priv(dev);
756 struct adapter *adap = pi->adapter;
757 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
759 if (adap->flags & FULL_INIT_DONE)
761 if (val && adap->params.rev == 0)
763 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
766 adap->params.mc5.nfilters = val;
770 static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
771 const char *buf, size_t len)
773 return attr_store(d, buf, len, set_nfilters, 0, ~0);
776 static ssize_t set_nservers(struct net_device *dev, unsigned int val)
778 struct port_info *pi = netdev_priv(dev);
779 struct adapter *adap = pi->adapter;
781 if (adap->flags & FULL_INIT_DONE)
783 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
786 adap->params.mc5.nservers = val;
790 static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
791 const char *buf, size_t len)
793 return attr_store(d, buf, len, set_nservers, 0, ~0);
796 #define CXGB3_ATTR_R(name, val_expr) \
797 CXGB3_SHOW(name, val_expr) \
798 static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
800 #define CXGB3_ATTR_RW(name, val_expr, store_method) \
801 CXGB3_SHOW(name, val_expr) \
802 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
804 CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
805 CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
806 CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
808 static struct attribute *cxgb3_attrs[] = {
809 &dev_attr_cam_size.attr,
810 &dev_attr_nfilters.attr,
811 &dev_attr_nservers.attr,
815 static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
817 static ssize_t tm_attr_show(struct device *d,
818 char *buf, int sched)
820 struct port_info *pi = netdev_priv(to_net_dev(d));
821 struct adapter *adap = pi->adapter;
822 unsigned int v, addr, bpt, cpt;
825 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
827 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
828 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
831 bpt = (v >> 8) & 0xff;
834 len = sprintf(buf, "disabled\n");
836 v = (adap->params.vpd.cclk * 1000) / cpt;
837 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
843 static ssize_t tm_attr_store(struct device *d,
844 const char *buf, size_t len, int sched)
846 struct port_info *pi = netdev_priv(to_net_dev(d));
847 struct adapter *adap = pi->adapter;
852 if (!capable(CAP_NET_ADMIN))
855 val = simple_strtoul(buf, &endp, 0);
856 if (endp == buf || val > 10000000)
860 ret = t3_config_sched(adap, val, sched);
867 #define TM_ATTR(name, sched) \
868 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
871 return tm_attr_show(d, buf, sched); \
873 static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
874 const char *buf, size_t len) \
876 return tm_attr_store(d, buf, len, sched); \
878 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
889 static struct attribute *offload_attrs[] = {
890 &dev_attr_sched0.attr,
891 &dev_attr_sched1.attr,
892 &dev_attr_sched2.attr,
893 &dev_attr_sched3.attr,
894 &dev_attr_sched4.attr,
895 &dev_attr_sched5.attr,
896 &dev_attr_sched6.attr,
897 &dev_attr_sched7.attr,
901 static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
904 * Sends an sk_buff to an offload queue driver
905 * after dealing with any active network taps.
907 static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
912 ret = t3_offload_tx(tdev, skb);
917 static int write_smt_entry(struct adapter *adapter, int idx)
919 struct cpl_smt_write_req *req;
920 struct port_info *pi = netdev_priv(adapter->port[idx]);
921 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
926 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
927 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
928 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
929 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
931 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
932 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
934 offload_tx(&adapter->tdev, skb);
938 static int init_smt(struct adapter *adapter)
942 for_each_port(adapter, i)
943 write_smt_entry(adapter, i);
947 static void init_port_mtus(struct adapter *adapter)
949 unsigned int mtus = adapter->port[0]->mtu;
951 if (adapter->port[1])
952 mtus |= adapter->port[1]->mtu << 16;
953 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
956 static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
960 struct mngt_pktsched_wr *req;
963 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
965 skb = adap->nofail_skb;
969 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
970 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
971 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
977 ret = t3_mgmt_tx(adap, skb);
978 if (skb == adap->nofail_skb) {
979 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
981 if (!adap->nofail_skb)
988 static int bind_qsets(struct adapter *adap)
992 for_each_port(adap, i) {
993 const struct port_info *pi = adap2pinfo(adap, i);
995 for (j = 0; j < pi->nqsets; ++j) {
996 int ret = send_pktsched_cmd(adap, 1,
997 pi->first_qset + j, -1,
1007 #define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
1008 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
1009 #define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
1010 #define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
1011 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
1012 #define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
1013 #define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1014 #define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
1015 #define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
1016 MODULE_FIRMWARE(FW_FNAME);
1017 MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1018 MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1019 MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1020 MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1021 MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
1023 static inline const char *get_edc_fw_name(int edc_idx)
1025 const char *fw_name = NULL;
1028 case EDC_OPT_AEL2005:
1029 fw_name = AEL2005_OPT_EDC_NAME;
1031 case EDC_TWX_AEL2005:
1032 fw_name = AEL2005_TWX_EDC_NAME;
1034 case EDC_TWX_AEL2020:
1035 fw_name = AEL2020_TWX_EDC_NAME;
1041 int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1043 struct adapter *adapter = phy->adapter;
1044 const struct firmware *fw;
1048 u16 *cache = phy->phy_cache;
1051 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1053 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1055 dev_err(&adapter->pdev->dev,
1056 "could not upgrade firmware: unable to load %s\n",
1061 /* check size, take checksum in account */
1062 if (fw->size > size + 4) {
1063 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1064 (unsigned int)fw->size, size + 4);
1068 /* compute checksum */
1069 p = (const __be32 *)fw->data;
1070 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1071 csum += ntohl(p[i]);
1073 if (csum != 0xffffffff) {
1074 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1079 for (i = 0; i < size / 4 ; i++) {
1080 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1081 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1084 release_firmware(fw);
1089 static int upgrade_fw(struct adapter *adap)
1092 const struct firmware *fw;
1093 struct device *dev = &adap->pdev->dev;
1095 ret = request_firmware(&fw, FW_FNAME, dev);
1097 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
1101 ret = t3_load_fw(adap, fw->data, fw->size);
1102 release_firmware(fw);
1105 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1106 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1108 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1109 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1114 static inline char t3rev2char(struct adapter *adapter)
1118 switch(adapter->params.rev) {
1130 static int update_tpsram(struct adapter *adap)
1132 const struct firmware *tpsram;
1134 struct device *dev = &adap->pdev->dev;
1138 rev = t3rev2char(adap);
1142 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
1144 ret = request_firmware(&tpsram, buf, dev);
1146 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1151 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1153 goto release_tpsram;
1155 ret = t3_set_proto_sram(adap, tpsram->data);
1158 "successful update of protocol engine "
1160 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1162 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1163 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1165 dev_err(dev, "loading protocol SRAM failed\n");
1168 release_firmware(tpsram);
1174 * cxgb_up - enable the adapter
1175 * @adapter: adapter being enabled
1177 * Called when the first port is enabled, this function performs the
1178 * actions necessary to make an adapter operational, such as completing
1179 * the initialization of HW modules, and enabling interrupts.
1181 * Must be called with the rtnl lock held.
1183 static int cxgb_up(struct adapter *adap)
1187 if (!(adap->flags & FULL_INIT_DONE)) {
1188 err = t3_check_fw_version(adap);
1189 if (err == -EINVAL) {
1190 err = upgrade_fw(adap);
1191 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1192 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1193 FW_VERSION_MICRO, err ? "failed" : "succeeded");
1196 err = t3_check_tpsram_version(adap);
1197 if (err == -EINVAL) {
1198 err = update_tpsram(adap);
1199 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1200 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1201 TP_VERSION_MICRO, err ? "failed" : "succeeded");
1205 * Clear interrupts now to catch errors if t3_init_hw fails.
1206 * We clear them again later as initialization may trigger
1207 * conditions that can interrupt.
1209 t3_intr_clear(adap);
1211 err = t3_init_hw(adap, 0);
1215 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1216 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1218 err = setup_sge_qsets(adap);
1223 if (!(adap->flags & NAPI_INIT))
1226 t3_start_sge_timers(adap);
1227 adap->flags |= FULL_INIT_DONE;
1230 t3_intr_clear(adap);
1232 if (adap->flags & USING_MSIX) {
1233 name_msix_vecs(adap);
1234 err = request_irq(adap->msix_info[0].vec,
1235 t3_async_intr_handler, 0,
1236 adap->msix_info[0].desc, adap);
1240 err = request_msix_data_irqs(adap);
1242 free_irq(adap->msix_info[0].vec, adap);
1245 } else if ((err = request_irq(adap->pdev->irq,
1246 t3_intr_handler(adap,
1247 adap->sge.qs[0].rspq.
1249 (adap->flags & USING_MSI) ?
1254 enable_all_napi(adap);
1256 t3_intr_enable(adap);
1258 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1259 is_offload(adap) && init_tp_parity(adap) == 0)
1260 adap->flags |= TP_PARITY_INIT;
1262 if (adap->flags & TP_PARITY_INIT) {
1263 t3_write_reg(adap, A_TP_INT_CAUSE,
1264 F_CMCACHEPERR | F_ARPLUTPERR);
1265 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1268 if (!(adap->flags & QUEUES_BOUND)) {
1269 err = bind_qsets(adap);
1271 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1272 t3_intr_disable(adap);
1273 free_irq_resources(adap);
1276 adap->flags |= QUEUES_BOUND;
1282 CH_ERR(adap, "request_irq failed, err %d\n", err);
1287 * Release resources when all the ports and offloading have been stopped.
1289 static void cxgb_down(struct adapter *adapter)
1291 t3_sge_stop(adapter);
1292 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1293 t3_intr_disable(adapter);
1294 spin_unlock_irq(&adapter->work_lock);
1296 free_irq_resources(adapter);
1297 quiesce_rx(adapter);
1298 t3_sge_stop(adapter);
1299 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
1302 static void schedule_chk_task(struct adapter *adap)
1306 timeo = adap->params.linkpoll_period ?
1307 (HZ * adap->params.linkpoll_period) / 10 :
1308 adap->params.stats_update_period * HZ;
1310 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1313 static int offload_open(struct net_device *dev)
1315 struct port_info *pi = netdev_priv(dev);
1316 struct adapter *adapter = pi->adapter;
1317 struct t3cdev *tdev = dev2t3cdev(dev);
1318 int adap_up = adapter->open_device_map & PORT_MASK;
1321 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1324 if (!adap_up && (err = cxgb_up(adapter)) < 0)
1327 t3_tp_set_offload_mode(adapter, 1);
1328 tdev->lldev = adapter->port[0];
1329 err = cxgb3_offload_activate(adapter);
1333 init_port_mtus(adapter);
1334 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1335 adapter->params.b_wnd,
1336 adapter->params.rev == 0 ?
1337 adapter->port[0]->mtu : 0xffff);
1340 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1341 dev_dbg(&dev->dev, "cannot create sysfs group\n");
1343 /* Call back all registered clients */
1344 cxgb3_add_clients(tdev);
1347 /* restore them in case the offload module has changed them */
1349 t3_tp_set_offload_mode(adapter, 0);
1350 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1351 cxgb3_set_dummy_ops(tdev);
1356 static int offload_close(struct t3cdev *tdev)
1358 struct adapter *adapter = tdev2adap(tdev);
1360 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1363 /* Call back all registered clients */
1364 cxgb3_remove_clients(tdev);
1366 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
1368 /* Flush work scheduled while releasing TIDs */
1369 flush_scheduled_work();
1372 cxgb3_set_dummy_ops(tdev);
1373 t3_tp_set_offload_mode(adapter, 0);
1374 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1376 if (!adapter->open_device_map)
1379 cxgb3_offload_deactivate(adapter);
1383 static int cxgb_open(struct net_device *dev)
1385 struct port_info *pi = netdev_priv(dev);
1386 struct adapter *adapter = pi->adapter;
1387 int other_ports = adapter->open_device_map & PORT_MASK;
1390 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
1393 set_bit(pi->port_id, &adapter->open_device_map);
1394 if (is_offload(adapter) && !ofld_disable) {
1395 err = offload_open(dev);
1398 "Could not initialize offload capabilities\n");
1401 dev->real_num_tx_queues = pi->nqsets;
1403 t3_port_intr_enable(adapter, pi->port_id);
1404 netif_tx_start_all_queues(dev);
1406 schedule_chk_task(adapter);
1408 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
1412 static int cxgb_close(struct net_device *dev)
1414 struct port_info *pi = netdev_priv(dev);
1415 struct adapter *adapter = pi->adapter;
1418 if (!adapter->open_device_map)
1421 /* Stop link fault interrupts */
1422 t3_xgm_intr_disable(adapter, pi->port_id);
1423 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1425 t3_port_intr_disable(adapter, pi->port_id);
1426 netif_tx_stop_all_queues(dev);
1427 pi->phy.ops->power_down(&pi->phy, 1);
1428 netif_carrier_off(dev);
1429 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
1431 spin_lock_irq(&adapter->work_lock); /* sync with update task */
1432 clear_bit(pi->port_id, &adapter->open_device_map);
1433 spin_unlock_irq(&adapter->work_lock);
1435 if (!(adapter->open_device_map & PORT_MASK))
1436 cancel_delayed_work_sync(&adapter->adap_check_task);
1438 if (!adapter->open_device_map)
1441 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
1445 static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1447 struct port_info *pi = netdev_priv(dev);
1448 struct adapter *adapter = pi->adapter;
1449 struct net_device_stats *ns = &pi->netstats;
1450 const struct mac_stats *pstats;
1452 spin_lock(&adapter->stats_lock);
1453 pstats = t3_mac_update_stats(&pi->mac);
1454 spin_unlock(&adapter->stats_lock);
1456 ns->tx_bytes = pstats->tx_octets;
1457 ns->tx_packets = pstats->tx_frames;
1458 ns->rx_bytes = pstats->rx_octets;
1459 ns->rx_packets = pstats->rx_frames;
1460 ns->multicast = pstats->rx_mcast_frames;
1462 ns->tx_errors = pstats->tx_underrun;
1463 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1464 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1465 pstats->rx_fifo_ovfl;
1467 /* detailed rx_errors */
1468 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1469 ns->rx_over_errors = 0;
1470 ns->rx_crc_errors = pstats->rx_fcs_errs;
1471 ns->rx_frame_errors = pstats->rx_symbol_errs;
1472 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1473 ns->rx_missed_errors = pstats->rx_cong_drops;
1475 /* detailed tx_errors */
1476 ns->tx_aborted_errors = 0;
1477 ns->tx_carrier_errors = 0;
1478 ns->tx_fifo_errors = pstats->tx_underrun;
1479 ns->tx_heartbeat_errors = 0;
1480 ns->tx_window_errors = 0;
1484 static u32 get_msglevel(struct net_device *dev)
1486 struct port_info *pi = netdev_priv(dev);
1487 struct adapter *adapter = pi->adapter;
1489 return adapter->msg_enable;
1492 static void set_msglevel(struct net_device *dev, u32 val)
1494 struct port_info *pi = netdev_priv(dev);
1495 struct adapter *adapter = pi->adapter;
1497 adapter->msg_enable = val;
1500 static char stats_strings[][ETH_GSTRING_LEN] = {
1503 "TxMulticastFramesOK",
1504 "TxBroadcastFramesOK",
1511 "TxFrames128To255 ",
1512 "TxFrames256To511 ",
1513 "TxFrames512To1023 ",
1514 "TxFrames1024To1518 ",
1515 "TxFrames1519ToMax ",
1519 "RxMulticastFramesOK",
1520 "RxBroadcastFramesOK",
1531 "RxFrames128To255 ",
1532 "RxFrames256To511 ",
1533 "RxFrames512To1023 ",
1534 "RxFrames1024To1518 ",
1535 "RxFrames1519ToMax ",
1548 "CheckTXEnToggled ",
1554 static int get_sset_count(struct net_device *dev, int sset)
1558 return ARRAY_SIZE(stats_strings);
1564 #define T3_REGMAP_SIZE (3 * 1024)
1566 static int get_regs_len(struct net_device *dev)
1568 return T3_REGMAP_SIZE;
1571 static int get_eeprom_len(struct net_device *dev)
1576 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1578 struct port_info *pi = netdev_priv(dev);
1579 struct adapter *adapter = pi->adapter;
1583 spin_lock(&adapter->stats_lock);
1584 t3_get_fw_version(adapter, &fw_vers);
1585 t3_get_tp_version(adapter, &tp_vers);
1586 spin_unlock(&adapter->stats_lock);
1588 strcpy(info->driver, DRV_NAME);
1589 strcpy(info->version, DRV_VERSION);
1590 strcpy(info->bus_info, pci_name(adapter->pdev));
1592 strcpy(info->fw_version, "N/A");
1594 snprintf(info->fw_version, sizeof(info->fw_version),
1595 "%s %u.%u.%u TP %u.%u.%u",
1596 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1597 G_FW_VERSION_MAJOR(fw_vers),
1598 G_FW_VERSION_MINOR(fw_vers),
1599 G_FW_VERSION_MICRO(fw_vers),
1600 G_TP_VERSION_MAJOR(tp_vers),
1601 G_TP_VERSION_MINOR(tp_vers),
1602 G_TP_VERSION_MICRO(tp_vers));
1606 static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1608 if (stringset == ETH_SS_STATS)
1609 memcpy(data, stats_strings, sizeof(stats_strings));
1612 static unsigned long collect_sge_port_stats(struct adapter *adapter,
1613 struct port_info *p, int idx)
1616 unsigned long tot = 0;
1618 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1619 tot += adapter->sge.qs[i].port_stats[idx];
1623 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1626 struct port_info *pi = netdev_priv(dev);
1627 struct adapter *adapter = pi->adapter;
1628 const struct mac_stats *s;
1630 spin_lock(&adapter->stats_lock);
1631 s = t3_mac_update_stats(&pi->mac);
1632 spin_unlock(&adapter->stats_lock);
1634 *data++ = s->tx_octets;
1635 *data++ = s->tx_frames;
1636 *data++ = s->tx_mcast_frames;
1637 *data++ = s->tx_bcast_frames;
1638 *data++ = s->tx_pause;
1639 *data++ = s->tx_underrun;
1640 *data++ = s->tx_fifo_urun;
1642 *data++ = s->tx_frames_64;
1643 *data++ = s->tx_frames_65_127;
1644 *data++ = s->tx_frames_128_255;
1645 *data++ = s->tx_frames_256_511;
1646 *data++ = s->tx_frames_512_1023;
1647 *data++ = s->tx_frames_1024_1518;
1648 *data++ = s->tx_frames_1519_max;
1650 *data++ = s->rx_octets;
1651 *data++ = s->rx_frames;
1652 *data++ = s->rx_mcast_frames;
1653 *data++ = s->rx_bcast_frames;
1654 *data++ = s->rx_pause;
1655 *data++ = s->rx_fcs_errs;
1656 *data++ = s->rx_symbol_errs;
1657 *data++ = s->rx_short;
1658 *data++ = s->rx_jabber;
1659 *data++ = s->rx_too_long;
1660 *data++ = s->rx_fifo_ovfl;
1662 *data++ = s->rx_frames_64;
1663 *data++ = s->rx_frames_65_127;
1664 *data++ = s->rx_frames_128_255;
1665 *data++ = s->rx_frames_256_511;
1666 *data++ = s->rx_frames_512_1023;
1667 *data++ = s->rx_frames_1024_1518;
1668 *data++ = s->rx_frames_1519_max;
1670 *data++ = pi->phy.fifo_errors;
1672 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1673 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1674 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1675 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1676 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1680 *data++ = s->rx_cong_drops;
1682 *data++ = s->num_toggled;
1683 *data++ = s->num_resets;
1685 *data++ = s->link_faults;
1688 static inline void reg_block_dump(struct adapter *ap, void *buf,
1689 unsigned int start, unsigned int end)
1691 u32 *p = buf + start;
1693 for (; start <= end; start += sizeof(u32))
1694 *p++ = t3_read_reg(ap, start);
1697 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1700 struct port_info *pi = netdev_priv(dev);
1701 struct adapter *ap = pi->adapter;
1705 * bits 0..9: chip version
1706 * bits 10..15: chip revision
1707 * bit 31: set for PCIe cards
1709 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1712 * We skip the MAC statistics registers because they are clear-on-read.
1713 * Also reading multi-register stats would need to synchronize with the
1714 * periodic mac stats accumulation. Hard to justify the complexity.
1716 memset(buf, 0, T3_REGMAP_SIZE);
1717 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1718 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1719 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1720 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1721 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1722 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1723 XGM_REG(A_XGM_SERDES_STAT3, 1));
1724 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1725 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1728 static int restart_autoneg(struct net_device *dev)
1730 struct port_info *p = netdev_priv(dev);
1732 if (!netif_running(dev))
1734 if (p->link_config.autoneg != AUTONEG_ENABLE)
1736 p->phy.ops->autoneg_restart(&p->phy);
1740 static int cxgb3_phys_id(struct net_device *dev, u32 data)
1742 struct port_info *pi = netdev_priv(dev);
1743 struct adapter *adapter = pi->adapter;
1749 for (i = 0; i < data * 2; i++) {
1750 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1751 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1752 if (msleep_interruptible(500))
1755 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1760 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1762 struct port_info *p = netdev_priv(dev);
1764 cmd->supported = p->link_config.supported;
1765 cmd->advertising = p->link_config.advertising;
1767 if (netif_carrier_ok(dev)) {
1768 cmd->speed = p->link_config.speed;
1769 cmd->duplex = p->link_config.duplex;
1775 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1776 cmd->phy_address = p->phy.mdio.prtad;
1777 cmd->transceiver = XCVR_EXTERNAL;
1778 cmd->autoneg = p->link_config.autoneg;
1784 static int speed_duplex_to_caps(int speed, int duplex)
1790 if (duplex == DUPLEX_FULL)
1791 cap = SUPPORTED_10baseT_Full;
1793 cap = SUPPORTED_10baseT_Half;
1796 if (duplex == DUPLEX_FULL)
1797 cap = SUPPORTED_100baseT_Full;
1799 cap = SUPPORTED_100baseT_Half;
1802 if (duplex == DUPLEX_FULL)
1803 cap = SUPPORTED_1000baseT_Full;
1805 cap = SUPPORTED_1000baseT_Half;
1808 if (duplex == DUPLEX_FULL)
1809 cap = SUPPORTED_10000baseT_Full;
1814 #define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1815 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1816 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1817 ADVERTISED_10000baseT_Full)
1819 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1821 struct port_info *p = netdev_priv(dev);
1822 struct link_config *lc = &p->link_config;
1824 if (!(lc->supported & SUPPORTED_Autoneg)) {
1826 * PHY offers a single speed/duplex. See if that's what's
1829 if (cmd->autoneg == AUTONEG_DISABLE) {
1830 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1831 if (lc->supported & cap)
1837 if (cmd->autoneg == AUTONEG_DISABLE) {
1838 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1840 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1842 lc->requested_speed = cmd->speed;
1843 lc->requested_duplex = cmd->duplex;
1844 lc->advertising = 0;
1846 cmd->advertising &= ADVERTISED_MASK;
1847 cmd->advertising &= lc->supported;
1848 if (!cmd->advertising)
1850 lc->requested_speed = SPEED_INVALID;
1851 lc->requested_duplex = DUPLEX_INVALID;
1852 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1854 lc->autoneg = cmd->autoneg;
1855 if (netif_running(dev))
1856 t3_link_start(&p->phy, &p->mac, lc);
1860 static void get_pauseparam(struct net_device *dev,
1861 struct ethtool_pauseparam *epause)
1863 struct port_info *p = netdev_priv(dev);
1865 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1866 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1867 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1870 static int set_pauseparam(struct net_device *dev,
1871 struct ethtool_pauseparam *epause)
1873 struct port_info *p = netdev_priv(dev);
1874 struct link_config *lc = &p->link_config;
1876 if (epause->autoneg == AUTONEG_DISABLE)
1877 lc->requested_fc = 0;
1878 else if (lc->supported & SUPPORTED_Autoneg)
1879 lc->requested_fc = PAUSE_AUTONEG;
1883 if (epause->rx_pause)
1884 lc->requested_fc |= PAUSE_RX;
1885 if (epause->tx_pause)
1886 lc->requested_fc |= PAUSE_TX;
1887 if (lc->autoneg == AUTONEG_ENABLE) {
1888 if (netif_running(dev))
1889 t3_link_start(&p->phy, &p->mac, lc);
1891 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1892 if (netif_running(dev))
1893 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1898 static u32 get_rx_csum(struct net_device *dev)
1900 struct port_info *p = netdev_priv(dev);
1902 return p->rx_offload & T3_RX_CSUM;
1905 static int set_rx_csum(struct net_device *dev, u32 data)
1907 struct port_info *p = netdev_priv(dev);
1910 p->rx_offload |= T3_RX_CSUM;
1914 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
1915 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1916 set_qset_lro(dev, i, 0);
1921 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1923 struct port_info *pi = netdev_priv(dev);
1924 struct adapter *adapter = pi->adapter;
1925 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
1927 e->rx_max_pending = MAX_RX_BUFFERS;
1928 e->rx_mini_max_pending = 0;
1929 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1930 e->tx_max_pending = MAX_TXQ_ENTRIES;
1932 e->rx_pending = q->fl_size;
1933 e->rx_mini_pending = q->rspq_size;
1934 e->rx_jumbo_pending = q->jumbo_size;
1935 e->tx_pending = q->txq_size[0];
1938 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1940 struct port_info *pi = netdev_priv(dev);
1941 struct adapter *adapter = pi->adapter;
1942 struct qset_params *q;
1945 if (e->rx_pending > MAX_RX_BUFFERS ||
1946 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1947 e->tx_pending > MAX_TXQ_ENTRIES ||
1948 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1949 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1950 e->rx_pending < MIN_FL_ENTRIES ||
1951 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1952 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1955 if (adapter->flags & FULL_INIT_DONE)
1958 q = &adapter->params.sge.qset[pi->first_qset];
1959 for (i = 0; i < pi->nqsets; ++i, ++q) {
1960 q->rspq_size = e->rx_mini_pending;
1961 q->fl_size = e->rx_pending;
1962 q->jumbo_size = e->rx_jumbo_pending;
1963 q->txq_size[0] = e->tx_pending;
1964 q->txq_size[1] = e->tx_pending;
1965 q->txq_size[2] = e->tx_pending;
1970 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1972 struct port_info *pi = netdev_priv(dev);
1973 struct adapter *adapter = pi->adapter;
1974 struct qset_params *qsp = &adapter->params.sge.qset[0];
1975 struct sge_qset *qs = &adapter->sge.qs[0];
1977 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1980 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1981 t3_update_qset_coalesce(qs, qsp);
1985 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1987 struct port_info *pi = netdev_priv(dev);
1988 struct adapter *adapter = pi->adapter;
1989 struct qset_params *q = adapter->params.sge.qset;
1991 c->rx_coalesce_usecs = q->coalesce_usecs;
1995 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1998 struct port_info *pi = netdev_priv(dev);
1999 struct adapter *adapter = pi->adapter;
2002 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2006 e->magic = EEPROM_MAGIC;
2007 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2008 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
2011 memcpy(data, buf + e->offset, e->len);
2016 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2019 struct port_info *pi = netdev_priv(dev);
2020 struct adapter *adapter = pi->adapter;
2021 u32 aligned_offset, aligned_len;
2026 if (eeprom->magic != EEPROM_MAGIC)
2029 aligned_offset = eeprom->offset & ~3;
2030 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2032 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2033 buf = kmalloc(aligned_len, GFP_KERNEL);
2036 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
2037 if (!err && aligned_len > 4)
2038 err = t3_seeprom_read(adapter,
2039 aligned_offset + aligned_len - 4,
2040 (__le32 *) & buf[aligned_len - 4]);
2043 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2047 err = t3_seeprom_wp(adapter, 0);
2051 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
2052 err = t3_seeprom_write(adapter, aligned_offset, *p);
2053 aligned_offset += 4;
2057 err = t3_seeprom_wp(adapter, 1);
2064 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2068 memset(&wol->sopass, 0, sizeof(wol->sopass));
2071 static const struct ethtool_ops cxgb_ethtool_ops = {
2072 .get_settings = get_settings,
2073 .set_settings = set_settings,
2074 .get_drvinfo = get_drvinfo,
2075 .get_msglevel = get_msglevel,
2076 .set_msglevel = set_msglevel,
2077 .get_ringparam = get_sge_param,
2078 .set_ringparam = set_sge_param,
2079 .get_coalesce = get_coalesce,
2080 .set_coalesce = set_coalesce,
2081 .get_eeprom_len = get_eeprom_len,
2082 .get_eeprom = get_eeprom,
2083 .set_eeprom = set_eeprom,
2084 .get_pauseparam = get_pauseparam,
2085 .set_pauseparam = set_pauseparam,
2086 .get_rx_csum = get_rx_csum,
2087 .set_rx_csum = set_rx_csum,
2088 .set_tx_csum = ethtool_op_set_tx_csum,
2089 .set_sg = ethtool_op_set_sg,
2090 .get_link = ethtool_op_get_link,
2091 .get_strings = get_strings,
2092 .phys_id = cxgb3_phys_id,
2093 .nway_reset = restart_autoneg,
2094 .get_sset_count = get_sset_count,
2095 .get_ethtool_stats = get_stats,
2096 .get_regs_len = get_regs_len,
2097 .get_regs = get_regs,
2099 .set_tso = ethtool_op_set_tso,
2102 static int in_range(int val, int lo, int hi)
2104 return val < 0 || (val <= hi && val >= lo);
2107 static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2109 struct port_info *pi = netdev_priv(dev);
2110 struct adapter *adapter = pi->adapter;
2114 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2118 case CHELSIO_SET_QSET_PARAMS:{
2120 struct qset_params *q;
2121 struct ch_qset_params t;
2122 int q1 = pi->first_qset;
2123 int nqsets = pi->nqsets;
2125 if (!capable(CAP_NET_ADMIN))
2127 if (copy_from_user(&t, useraddr, sizeof(t)))
2129 if (t.qset_idx >= SGE_QSETS)
2131 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
2132 !in_range(t.cong_thres, 0, 255) ||
2133 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2135 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2137 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2138 MAX_CTRL_TXQ_ENTRIES) ||
2139 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2141 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2142 MAX_RX_JUMBO_BUFFERS) ||
2143 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2147 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2148 for_each_port(adapter, i) {
2149 pi = adap2pinfo(adapter, i);
2150 if (t.qset_idx >= pi->first_qset &&
2151 t.qset_idx < pi->first_qset + pi->nqsets &&
2152 !(pi->rx_offload & T3_RX_CSUM))
2156 if ((adapter->flags & FULL_INIT_DONE) &&
2157 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2158 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2159 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2160 t.polling >= 0 || t.cong_thres >= 0))
2163 /* Allow setting of any available qset when offload enabled */
2164 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2166 for_each_port(adapter, i) {
2167 pi = adap2pinfo(adapter, i);
2168 nqsets += pi->first_qset + pi->nqsets;
2172 if (t.qset_idx < q1)
2174 if (t.qset_idx > q1 + nqsets - 1)
2177 q = &adapter->params.sge.qset[t.qset_idx];
2179 if (t.rspq_size >= 0)
2180 q->rspq_size = t.rspq_size;
2181 if (t.fl_size[0] >= 0)
2182 q->fl_size = t.fl_size[0];
2183 if (t.fl_size[1] >= 0)
2184 q->jumbo_size = t.fl_size[1];
2185 if (t.txq_size[0] >= 0)
2186 q->txq_size[0] = t.txq_size[0];
2187 if (t.txq_size[1] >= 0)
2188 q->txq_size[1] = t.txq_size[1];
2189 if (t.txq_size[2] >= 0)
2190 q->txq_size[2] = t.txq_size[2];
2191 if (t.cong_thres >= 0)
2192 q->cong_thres = t.cong_thres;
2193 if (t.intr_lat >= 0) {
2194 struct sge_qset *qs =
2195 &adapter->sge.qs[t.qset_idx];
2197 q->coalesce_usecs = t.intr_lat;
2198 t3_update_qset_coalesce(qs, q);
2200 if (t.polling >= 0) {
2201 if (adapter->flags & USING_MSIX)
2202 q->polling = t.polling;
2204 /* No polling with INTx for T3A */
2205 if (adapter->params.rev == 0 &&
2206 !(adapter->flags & USING_MSI))
2209 for (i = 0; i < SGE_QSETS; i++) {
2210 q = &adapter->params.sge.
2212 q->polling = t.polling;
2217 set_qset_lro(dev, t.qset_idx, t.lro);
2221 case CHELSIO_GET_QSET_PARAMS:{
2222 struct qset_params *q;
2223 struct ch_qset_params t;
2224 int q1 = pi->first_qset;
2225 int nqsets = pi->nqsets;
2228 if (copy_from_user(&t, useraddr, sizeof(t)))
2231 /* Display qsets for all ports when offload enabled */
2232 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2234 for_each_port(adapter, i) {
2235 pi = adap2pinfo(adapter, i);
2236 nqsets = pi->first_qset + pi->nqsets;
2240 if (t.qset_idx >= nqsets)
2243 q = &adapter->params.sge.qset[q1 + t.qset_idx];
2244 t.rspq_size = q->rspq_size;
2245 t.txq_size[0] = q->txq_size[0];
2246 t.txq_size[1] = q->txq_size[1];
2247 t.txq_size[2] = q->txq_size[2];
2248 t.fl_size[0] = q->fl_size;
2249 t.fl_size[1] = q->jumbo_size;
2250 t.polling = q->polling;
2252 t.intr_lat = q->coalesce_usecs;
2253 t.cong_thres = q->cong_thres;
2256 if (adapter->flags & USING_MSIX)
2257 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2259 t.vector = adapter->pdev->irq;
2261 if (copy_to_user(useraddr, &t, sizeof(t)))
2265 case CHELSIO_SET_QSET_NUM:{
2266 struct ch_reg edata;
2267 unsigned int i, first_qset = 0, other_qsets = 0;
2269 if (!capable(CAP_NET_ADMIN))
2271 if (adapter->flags & FULL_INIT_DONE)
2273 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2275 if (edata.val < 1 ||
2276 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2279 for_each_port(adapter, i)
2280 if (adapter->port[i] && adapter->port[i] != dev)
2281 other_qsets += adap2pinfo(adapter, i)->nqsets;
2283 if (edata.val + other_qsets > SGE_QSETS)
2286 pi->nqsets = edata.val;
2288 for_each_port(adapter, i)
2289 if (adapter->port[i]) {
2290 pi = adap2pinfo(adapter, i);
2291 pi->first_qset = first_qset;
2292 first_qset += pi->nqsets;
2296 case CHELSIO_GET_QSET_NUM:{
2297 struct ch_reg edata;
2299 memset(&edata, 0, sizeof(struct ch_reg));
2301 edata.cmd = CHELSIO_GET_QSET_NUM;
2302 edata.val = pi->nqsets;
2303 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2307 case CHELSIO_LOAD_FW:{
2309 struct ch_mem_range t;
2311 if (!capable(CAP_SYS_RAWIO))
2313 if (copy_from_user(&t, useraddr, sizeof(t)))
2315 /* Check t.len sanity ? */
2316 fw_data = memdup_user(useraddr + sizeof(t), t.len);
2317 if (IS_ERR(fw_data))
2318 return PTR_ERR(fw_data);
2320 ret = t3_load_fw(adapter, fw_data, t.len);
2326 case CHELSIO_SETMTUTAB:{
2330 if (!is_offload(adapter))
2332 if (!capable(CAP_NET_ADMIN))
2334 if (offload_running(adapter))
2336 if (copy_from_user(&m, useraddr, sizeof(m)))
2338 if (m.nmtus != NMTUS)
2340 if (m.mtus[0] < 81) /* accommodate SACK */
2343 /* MTUs must be in ascending order */
2344 for (i = 1; i < NMTUS; ++i)
2345 if (m.mtus[i] < m.mtus[i - 1])
2348 memcpy(adapter->params.mtus, m.mtus,
2349 sizeof(adapter->params.mtus));
2352 case CHELSIO_GET_PM:{
2353 struct tp_params *p = &adapter->params.tp;
2354 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2356 if (!is_offload(adapter))
2358 m.tx_pg_sz = p->tx_pg_size;
2359 m.tx_num_pg = p->tx_num_pgs;
2360 m.rx_pg_sz = p->rx_pg_size;
2361 m.rx_num_pg = p->rx_num_pgs;
2362 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2363 if (copy_to_user(useraddr, &m, sizeof(m)))
2367 case CHELSIO_SET_PM:{
2369 struct tp_params *p = &adapter->params.tp;
2371 if (!is_offload(adapter))
2373 if (!capable(CAP_NET_ADMIN))
2375 if (adapter->flags & FULL_INIT_DONE)
2377 if (copy_from_user(&m, useraddr, sizeof(m)))
2379 if (!is_power_of_2(m.rx_pg_sz) ||
2380 !is_power_of_2(m.tx_pg_sz))
2381 return -EINVAL; /* not power of 2 */
2382 if (!(m.rx_pg_sz & 0x14000))
2383 return -EINVAL; /* not 16KB or 64KB */
2384 if (!(m.tx_pg_sz & 0x1554000))
2386 if (m.tx_num_pg == -1)
2387 m.tx_num_pg = p->tx_num_pgs;
2388 if (m.rx_num_pg == -1)
2389 m.rx_num_pg = p->rx_num_pgs;
2390 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2392 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2393 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2395 p->rx_pg_size = m.rx_pg_sz;
2396 p->tx_pg_size = m.tx_pg_sz;
2397 p->rx_num_pgs = m.rx_num_pg;
2398 p->tx_num_pgs = m.tx_num_pg;
2401 case CHELSIO_GET_MEM:{
2402 struct ch_mem_range t;
2406 if (!is_offload(adapter))
2408 if (!(adapter->flags & FULL_INIT_DONE))
2409 return -EIO; /* need the memory controllers */
2410 if (copy_from_user(&t, useraddr, sizeof(t)))
2412 if ((t.addr & 7) || (t.len & 7))
2414 if (t.mem_id == MEM_CM)
2416 else if (t.mem_id == MEM_PMRX)
2417 mem = &adapter->pmrx;
2418 else if (t.mem_id == MEM_PMTX)
2419 mem = &adapter->pmtx;
2425 * bits 0..9: chip version
2426 * bits 10..15: chip revision
2428 t.version = 3 | (adapter->params.rev << 10);
2429 if (copy_to_user(useraddr, &t, sizeof(t)))
2433 * Read 256 bytes at a time as len can be large and we don't
2434 * want to use huge intermediate buffers.
2436 useraddr += sizeof(t); /* advance to start of buffer */
2438 unsigned int chunk =
2439 min_t(unsigned int, t.len, sizeof(buf));
2442 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2446 if (copy_to_user(useraddr, buf, chunk))
2454 case CHELSIO_SET_TRACE_FILTER:{
2456 const struct trace_params *tp;
2458 if (!capable(CAP_NET_ADMIN))
2460 if (!offload_running(adapter))
2462 if (copy_from_user(&t, useraddr, sizeof(t)))
2465 tp = (const struct trace_params *)&t.sip;
2467 t3_config_trace_filter(adapter, tp, 0,
2471 t3_config_trace_filter(adapter, tp, 1,
2482 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2484 struct mii_ioctl_data *data = if_mii(req);
2485 struct port_info *pi = netdev_priv(dev);
2486 struct adapter *adapter = pi->adapter;
2491 /* Convert phy_id from older PRTAD/DEVAD format */
2492 if (is_10G(adapter) &&
2493 !mdio_phy_id_is_c45(data->phy_id) &&
2494 (data->phy_id & 0x1f00) &&
2495 !(data->phy_id & 0xe0e0))
2496 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2497 data->phy_id & 0x1f);
2500 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
2502 return cxgb_extension_ioctl(dev, req->ifr_data);
2508 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2510 struct port_info *pi = netdev_priv(dev);
2511 struct adapter *adapter = pi->adapter;
2514 if (new_mtu < 81) /* accommodate SACK */
2516 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2519 init_port_mtus(adapter);
2520 if (adapter->params.rev == 0 && offload_running(adapter))
2521 t3_load_mtus(adapter, adapter->params.mtus,
2522 adapter->params.a_wnd, adapter->params.b_wnd,
2523 adapter->port[0]->mtu);
2527 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2529 struct port_info *pi = netdev_priv(dev);
2530 struct adapter *adapter = pi->adapter;
2531 struct sockaddr *addr = p;
2533 if (!is_valid_ether_addr(addr->sa_data))
2536 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2537 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
2538 if (offload_running(adapter))
2539 write_smt_entry(adapter, pi->port_id);
2544 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2545 * @adap: the adapter
2548 * Ensures that current Rx processing on any of the queues associated with
2549 * the given port completes before returning. We do this by acquiring and
2550 * releasing the locks of the response queues associated with the port.
2552 static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2556 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2557 struct sge_rspq *q = &adap->sge.qs[i].rspq;
2559 spin_lock_irq(&q->lock);
2560 spin_unlock_irq(&q->lock);
2564 static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2566 struct port_info *pi = netdev_priv(dev);
2567 struct adapter *adapter = pi->adapter;
2570 if (adapter->params.rev > 0)
2571 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2573 /* single control for all ports */
2574 unsigned int i, have_vlans = 0;
2575 for_each_port(adapter, i)
2576 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2578 t3_set_vlan_accel(adapter, 1, have_vlans);
2580 t3_synchronize_rx(adapter, pi);
2583 #ifdef CONFIG_NET_POLL_CONTROLLER
2584 static void cxgb_netpoll(struct net_device *dev)
2586 struct port_info *pi = netdev_priv(dev);
2587 struct adapter *adapter = pi->adapter;
2590 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2591 struct sge_qset *qs = &adapter->sge.qs[qidx];
2594 if (adapter->flags & USING_MSIX)
2599 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2605 * Periodic accumulation of MAC statistics.
2607 static void mac_stats_update(struct adapter *adapter)
2611 for_each_port(adapter, i) {
2612 struct net_device *dev = adapter->port[i];
2613 struct port_info *p = netdev_priv(dev);
2615 if (netif_running(dev)) {
2616 spin_lock(&adapter->stats_lock);
2617 t3_mac_update_stats(&p->mac);
2618 spin_unlock(&adapter->stats_lock);
2623 static void check_link_status(struct adapter *adapter)
2627 for_each_port(adapter, i) {
2628 struct net_device *dev = adapter->port[i];
2629 struct port_info *p = netdev_priv(dev);
2632 spin_lock_irq(&adapter->work_lock);
2633 link_fault = p->link_fault;
2634 spin_unlock_irq(&adapter->work_lock);
2637 t3_link_fault(adapter, i);
2641 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2642 t3_xgm_intr_disable(adapter, i);
2643 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2645 t3_link_changed(adapter, i);
2646 t3_xgm_intr_enable(adapter, i);
2651 static void check_t3b2_mac(struct adapter *adapter)
2655 if (!rtnl_trylock()) /* synchronize with ifdown */
2658 for_each_port(adapter, i) {
2659 struct net_device *dev = adapter->port[i];
2660 struct port_info *p = netdev_priv(dev);
2663 if (!netif_running(dev))
2667 if (netif_running(dev) && netif_carrier_ok(dev))
2668 status = t3b2_mac_watchdog_task(&p->mac);
2670 p->mac.stats.num_toggled++;
2671 else if (status == 2) {
2672 struct cmac *mac = &p->mac;
2674 t3_mac_set_mtu(mac, dev->mtu);
2675 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
2676 cxgb_set_rxmode(dev);
2677 t3_link_start(&p->phy, mac, &p->link_config);
2678 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2679 t3_port_intr_enable(adapter, p->port_id);
2680 p->mac.stats.num_resets++;
2687 static void t3_adap_check_task(struct work_struct *work)
2689 struct adapter *adapter = container_of(work, struct adapter,
2690 adap_check_task.work);
2691 const struct adapter_params *p = &adapter->params;
2693 unsigned int v, status, reset;
2695 adapter->check_task_cnt++;
2697 check_link_status(adapter);
2699 /* Accumulate MAC stats if needed */
2700 if (!p->linkpoll_period ||
2701 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2702 p->stats_update_period) {
2703 mac_stats_update(adapter);
2704 adapter->check_task_cnt = 0;
2707 if (p->rev == T3_REV_B2)
2708 check_t3b2_mac(adapter);
2711 * Scan the XGMAC's to check for various conditions which we want to
2712 * monitor in a periodic polling manner rather than via an interrupt
2713 * condition. This is used for conditions which would otherwise flood
2714 * the system with interrupts and we only really need to know that the
2715 * conditions are "happening" ... For each condition we count the
2716 * detection of the condition and reset it for the next polling loop.
2718 for_each_port(adapter, port) {
2719 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2722 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2724 if (cause & F_RXFIFO_OVERFLOW) {
2725 mac->stats.rx_fifo_ovfl++;
2726 reset |= F_RXFIFO_OVERFLOW;
2729 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2733 * We do the same as above for FL_EMPTY interrupts.
2735 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2738 if (status & F_FLEMPTY) {
2739 struct sge_qset *qs = &adapter->sge.qs[0];
2744 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2748 qs->fl[i].empty += (v & 1);
2756 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2758 /* Schedule the next check update if any port is active. */
2759 spin_lock_irq(&adapter->work_lock);
2760 if (adapter->open_device_map & PORT_MASK)
2761 schedule_chk_task(adapter);
2762 spin_unlock_irq(&adapter->work_lock);
2765 static void db_full_task(struct work_struct *work)
2767 struct adapter *adapter = container_of(work, struct adapter,
2770 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2773 static void db_empty_task(struct work_struct *work)
2775 struct adapter *adapter = container_of(work, struct adapter,
2778 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2781 static void db_drop_task(struct work_struct *work)
2783 struct adapter *adapter = container_of(work, struct adapter,
2785 unsigned long delay = 1000;
2788 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2791 * Sleep a while before ringing the driver qset dbs.
2792 * The delay is between 1000-2023 usecs.
2794 get_random_bytes(&r, 2);
2796 set_current_state(TASK_UNINTERRUPTIBLE);
2797 schedule_timeout(usecs_to_jiffies(delay));
2802 * Processes external (PHY) interrupts in process context.
2804 static void ext_intr_task(struct work_struct *work)
2806 struct adapter *adapter = container_of(work, struct adapter,
2807 ext_intr_handler_task);
2810 /* Disable link fault interrupts */
2811 for_each_port(adapter, i) {
2812 struct net_device *dev = adapter->port[i];
2813 struct port_info *p = netdev_priv(dev);
2815 t3_xgm_intr_disable(adapter, i);
2816 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2819 /* Re-enable link fault interrupts */
2820 t3_phy_intr_handler(adapter);
2822 for_each_port(adapter, i)
2823 t3_xgm_intr_enable(adapter, i);
2825 /* Now reenable external interrupts */
2826 spin_lock_irq(&adapter->work_lock);
2827 if (adapter->slow_intr_mask) {
2828 adapter->slow_intr_mask |= F_T3DBG;
2829 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2830 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2831 adapter->slow_intr_mask);
2833 spin_unlock_irq(&adapter->work_lock);
2837 * Interrupt-context handler for external (PHY) interrupts.
2839 void t3_os_ext_intr_handler(struct adapter *adapter)
2842 * Schedule a task to handle external interrupts as they may be slow
2843 * and we use a mutex to protect MDIO registers. We disable PHY
2844 * interrupts in the meantime and let the task reenable them when
2847 spin_lock(&adapter->work_lock);
2848 if (adapter->slow_intr_mask) {
2849 adapter->slow_intr_mask &= ~F_T3DBG;
2850 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2851 adapter->slow_intr_mask);
2852 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2854 spin_unlock(&adapter->work_lock);
2857 void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2859 struct net_device *netdev = adapter->port[port_id];
2860 struct port_info *pi = netdev_priv(netdev);
2862 spin_lock(&adapter->work_lock);
2864 spin_unlock(&adapter->work_lock);
2867 static int t3_adapter_error(struct adapter *adapter, int reset)
2871 if (is_offload(adapter) &&
2872 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2873 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2874 offload_close(&adapter->tdev);
2877 /* Stop all ports */
2878 for_each_port(adapter, i) {
2879 struct net_device *netdev = adapter->port[i];
2881 if (netif_running(netdev))
2885 /* Stop SGE timers */
2886 t3_stop_sge_timers(adapter);
2888 adapter->flags &= ~FULL_INIT_DONE;
2891 ret = t3_reset_adapter(adapter);
2893 pci_disable_device(adapter->pdev);
2898 static int t3_reenable_adapter(struct adapter *adapter)
2900 if (pci_enable_device(adapter->pdev)) {
2901 dev_err(&adapter->pdev->dev,
2902 "Cannot re-enable PCI device after reset.\n");
2905 pci_set_master(adapter->pdev);
2906 pci_restore_state(adapter->pdev);
2907 pci_save_state(adapter->pdev);
2909 /* Free sge resources */
2910 t3_free_sge_resources(adapter);
2912 if (t3_replay_prep_adapter(adapter))
2920 static void t3_resume_ports(struct adapter *adapter)
2924 /* Restart the ports */
2925 for_each_port(adapter, i) {
2926 struct net_device *netdev = adapter->port[i];
2928 if (netif_running(netdev)) {
2929 if (cxgb_open(netdev)) {
2930 dev_err(&adapter->pdev->dev,
2931 "can't bring device back up"
2938 if (is_offload(adapter) && !ofld_disable)
2939 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
2943 * processes a fatal error.
2944 * Bring the ports down, reset the chip, bring the ports back up.
2946 static void fatal_error_task(struct work_struct *work)
2948 struct adapter *adapter = container_of(work, struct adapter,
2949 fatal_error_handler_task);
2953 err = t3_adapter_error(adapter, 1);
2955 err = t3_reenable_adapter(adapter);
2957 t3_resume_ports(adapter);
2959 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2963 void t3_fatal_err(struct adapter *adapter)
2965 unsigned int fw_status[4];
2967 if (adapter->flags & FULL_INIT_DONE) {
2968 t3_sge_stop(adapter);
2969 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2970 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2971 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2972 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
2974 spin_lock(&adapter->work_lock);
2975 t3_intr_disable(adapter);
2976 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2977 spin_unlock(&adapter->work_lock);
2979 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2980 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2981 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2982 fw_status[0], fw_status[1],
2983 fw_status[2], fw_status[3]);
2987 * t3_io_error_detected - called when PCI error is detected
2988 * @pdev: Pointer to PCI device
2989 * @state: The current pci connection state
2991 * This function is called after a PCI bus error affecting
2992 * this device has been detected.
2994 static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2995 pci_channel_state_t state)
2997 struct adapter *adapter = pci_get_drvdata(pdev);
3000 if (state == pci_channel_io_perm_failure)
3001 return PCI_ERS_RESULT_DISCONNECT;
3003 ret = t3_adapter_error(adapter, 0);
3005 /* Request a slot reset. */
3006 return PCI_ERS_RESULT_NEED_RESET;
3010 * t3_io_slot_reset - called after the pci bus has been reset.
3011 * @pdev: Pointer to PCI device
3013 * Restart the card from scratch, as if from a cold-boot.
3015 static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3017 struct adapter *adapter = pci_get_drvdata(pdev);
3019 if (!t3_reenable_adapter(adapter))
3020 return PCI_ERS_RESULT_RECOVERED;
3022 return PCI_ERS_RESULT_DISCONNECT;
3026 * t3_io_resume - called when traffic can start flowing again.
3027 * @pdev: Pointer to PCI device
3029 * This callback is called when the error recovery driver tells us that
3030 * its OK to resume normal operation.
3032 static void t3_io_resume(struct pci_dev *pdev)
3034 struct adapter *adapter = pci_get_drvdata(pdev);
3036 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3037 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3039 t3_resume_ports(adapter);
3042 static struct pci_error_handlers t3_err_handler = {
3043 .error_detected = t3_io_error_detected,
3044 .slot_reset = t3_io_slot_reset,
3045 .resume = t3_io_resume,
3049 * Set the number of qsets based on the number of CPUs and the number of ports,
3050 * not to exceed the number of available qsets, assuming there are enough qsets
3053 static void set_nqsets(struct adapter *adap)
3056 int num_cpus = num_online_cpus();
3057 int hwports = adap->params.nports;
3058 int nqsets = adap->msix_nvectors - 1;
3060 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
3062 (hwports * nqsets > SGE_QSETS ||
3063 num_cpus >= nqsets / hwports))
3065 if (nqsets > num_cpus)
3067 if (nqsets < 1 || hwports == 4)
3072 for_each_port(adap, i) {
3073 struct port_info *pi = adap2pinfo(adap, i);
3076 pi->nqsets = nqsets;
3077 j = pi->first_qset + nqsets;
3079 dev_info(&adap->pdev->dev,
3080 "Port %d using %d queue sets.\n", i, nqsets);
3084 static int __devinit cxgb_enable_msix(struct adapter *adap)
3086 struct msix_entry entries[SGE_QSETS + 1];
3090 vectors = ARRAY_SIZE(entries);
3091 for (i = 0; i < vectors; ++i)
3092 entries[i].entry = i;
3094 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3098 pci_disable_msix(adap->pdev);
3100 if (!err && vectors < (adap->params.nports + 1)) {
3101 pci_disable_msix(adap->pdev);
3106 for (i = 0; i < vectors; ++i)
3107 adap->msix_info[i].vec = entries[i].vector;
3108 adap->msix_nvectors = vectors;
3114 static void __devinit print_port_info(struct adapter *adap,
3115 const struct adapter_info *ai)
3117 static const char *pci_variant[] = {
3118 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3125 snprintf(buf, sizeof(buf), "%s x%d",
3126 pci_variant[adap->params.pci.variant],
3127 adap->params.pci.width);
3129 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3130 pci_variant[adap->params.pci.variant],
3131 adap->params.pci.speed, adap->params.pci.width);
3133 for_each_port(adap, i) {
3134 struct net_device *dev = adap->port[i];
3135 const struct port_info *pi = netdev_priv(dev);
3137 if (!test_bit(i, &adap->registered_device_map))
3139 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
3140 dev->name, ai->desc, pi->phy.desc,
3141 is_offload(adap) ? "R" : "", adap->params.rev, buf,
3142 (adap->flags & USING_MSIX) ? " MSI-X" :
3143 (adap->flags & USING_MSI) ? " MSI" : "");
3144 if (adap->name == dev->name && adap->params.vpd.mclk)
3146 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
3147 adap->name, t3_mc7_size(&adap->cm) >> 20,
3148 t3_mc7_size(&adap->pmtx) >> 20,
3149 t3_mc7_size(&adap->pmrx) >> 20,
3150 adap->params.vpd.sn);
3154 static const struct net_device_ops cxgb_netdev_ops = {
3155 .ndo_open = cxgb_open,
3156 .ndo_stop = cxgb_close,
3157 .ndo_start_xmit = t3_eth_xmit,
3158 .ndo_get_stats = cxgb_get_stats,
3159 .ndo_validate_addr = eth_validate_addr,
3160 .ndo_set_multicast_list = cxgb_set_rxmode,
3161 .ndo_do_ioctl = cxgb_ioctl,
3162 .ndo_change_mtu = cxgb_change_mtu,
3163 .ndo_set_mac_address = cxgb_set_mac_addr,
3164 .ndo_vlan_rx_register = vlan_rx_register,
3165 #ifdef CONFIG_NET_POLL_CONTROLLER
3166 .ndo_poll_controller = cxgb_netpoll,
3170 static void __devinit cxgb3_init_iscsi_mac(struct net_device *dev)
3172 struct port_info *pi = netdev_priv(dev);
3174 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3175 pi->iscsic.mac_addr[3] |= 0x80;
3178 static int __devinit init_one(struct pci_dev *pdev,
3179 const struct pci_device_id *ent)
3181 static int version_printed;
3183 int i, err, pci_using_dac = 0;
3184 resource_size_t mmio_start, mmio_len;
3185 const struct adapter_info *ai;
3186 struct adapter *adapter = NULL;
3187 struct port_info *pi;
3189 if (!version_printed) {
3190 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3195 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3197 printk(KERN_ERR DRV_NAME
3198 ": cannot initialize work queue\n");
3203 err = pci_enable_device(pdev);
3205 dev_err(&pdev->dev, "cannot enable PCI device\n");
3209 err = pci_request_regions(pdev, DRV_NAME);
3211 /* Just info, some other driver may have claimed the device. */
3212 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3213 goto out_disable_device;
3216 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3218 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3220 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3221 "coherent allocations\n");
3222 goto out_release_regions;
3224 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3225 dev_err(&pdev->dev, "no usable DMA configuration\n");
3226 goto out_release_regions;
3229 pci_set_master(pdev);
3230 pci_save_state(pdev);
3232 mmio_start = pci_resource_start(pdev, 0);
3233 mmio_len = pci_resource_len(pdev, 0);
3234 ai = t3_get_adapter_info(ent->driver_data);
3236 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3239 goto out_release_regions;
3242 adapter->nofail_skb =
3243 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3244 if (!adapter->nofail_skb) {
3245 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3247 goto out_free_adapter;
3250 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3251 if (!adapter->regs) {
3252 dev_err(&pdev->dev, "cannot map device registers\n");
3254 goto out_free_adapter;
3257 adapter->pdev = pdev;
3258 adapter->name = pci_name(pdev);
3259 adapter->msg_enable = dflt_msg_enable;
3260 adapter->mmio_len = mmio_len;
3262 mutex_init(&adapter->mdio_lock);
3263 spin_lock_init(&adapter->work_lock);
3264 spin_lock_init(&adapter->stats_lock);
3266 INIT_LIST_HEAD(&adapter->adapter_list);
3267 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
3268 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
3270 INIT_WORK(&adapter->db_full_task, db_full_task);
3271 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3272 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3274 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3276 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
3277 struct net_device *netdev;
3279 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
3285 SET_NETDEV_DEV(netdev, &pdev->dev);
3287 adapter->port[i] = netdev;
3288 pi = netdev_priv(netdev);
3289 pi->adapter = adapter;
3290 pi->rx_offload = T3_RX_CSUM | T3_LRO;
3292 netif_carrier_off(netdev);
3293 netif_tx_stop_all_queues(netdev);
3294 netdev->irq = pdev->irq;
3295 netdev->mem_start = mmio_start;
3296 netdev->mem_end = mmio_start + mmio_len - 1;
3297 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3298 netdev->features |= NETIF_F_GRO;
3300 netdev->features |= NETIF_F_HIGHDMA;
3302 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3303 netdev->netdev_ops = &cxgb_netdev_ops;
3304 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3307 pci_set_drvdata(pdev, adapter);
3308 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3314 * The card is now ready to go. If any errors occur during device
3315 * registration we do not fail the whole card but rather proceed only
3316 * with the ports we manage to register successfully. However we must
3317 * register at least one net device.
3319 for_each_port(adapter, i) {
3320 err = register_netdev(adapter->port[i]);
3322 dev_warn(&pdev->dev,
3323 "cannot register net device %s, skipping\n",
3324 adapter->port[i]->name);
3327 * Change the name we use for messages to the name of
3328 * the first successfully registered interface.
3330 if (!adapter->registered_device_map)
3331 adapter->name = adapter->port[i]->name;
3333 __set_bit(i, &adapter->registered_device_map);
3336 if (!adapter->registered_device_map) {
3337 dev_err(&pdev->dev, "could not register any net devices\n");
3341 for_each_port(adapter, i)
3342 cxgb3_init_iscsi_mac(adapter->port[i]);
3344 /* Driver's ready. Reflect it on LEDs */
3345 t3_led_ready(adapter);
3347 if (is_offload(adapter)) {
3348 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3349 cxgb3_adapter_ofld(adapter);
3352 /* See what interrupts we'll be using */
3353 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3354 adapter->flags |= USING_MSIX;
3355 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3356 adapter->flags |= USING_MSI;
3358 set_nqsets(adapter);
3360 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
3363 print_port_info(adapter, ai);
3367 iounmap(adapter->regs);
3368 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
3369 if (adapter->port[i])
3370 free_netdev(adapter->port[i]);
3375 out_release_regions:
3376 pci_release_regions(pdev);
3378 pci_disable_device(pdev);
3379 pci_set_drvdata(pdev, NULL);
3384 static void __devexit remove_one(struct pci_dev *pdev)
3386 struct adapter *adapter = pci_get_drvdata(pdev);
3391 t3_sge_stop(adapter);
3392 sysfs_remove_group(&adapter->port[0]->dev.kobj,
3395 if (is_offload(adapter)) {
3396 cxgb3_adapter_unofld(adapter);
3397 if (test_bit(OFFLOAD_DEVMAP_BIT,
3398 &adapter->open_device_map))
3399 offload_close(&adapter->tdev);
3402 for_each_port(adapter, i)
3403 if (test_bit(i, &adapter->registered_device_map))
3404 unregister_netdev(adapter->port[i]);
3406 t3_stop_sge_timers(adapter);
3407 t3_free_sge_resources(adapter);
3408 cxgb_disable_msi(adapter);
3410 for_each_port(adapter, i)
3411 if (adapter->port[i])
3412 free_netdev(adapter->port[i]);
3414 iounmap(adapter->regs);
3415 if (adapter->nofail_skb)
3416 kfree_skb(adapter->nofail_skb);
3418 pci_release_regions(pdev);
3419 pci_disable_device(pdev);
3420 pci_set_drvdata(pdev, NULL);
3424 static struct pci_driver driver = {
3426 .id_table = cxgb3_pci_tbl,
3428 .remove = __devexit_p(remove_one),
3429 .err_handler = &t3_err_handler,
3432 static int __init cxgb3_init_module(void)
3436 cxgb3_offload_init();
3438 ret = pci_register_driver(&driver);
3442 static void __exit cxgb3_cleanup_module(void)
3444 pci_unregister_driver(&driver);
3446 destroy_workqueue(cxgb3_wq);
3449 module_init(cxgb3_init_module);
3450 module_exit(cxgb3_cleanup_module);