drivers/net/can/rcar/rcar_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Renesas R-Car CAN FD device driver
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  */
   6
   7 /* The R-Car CAN FD controller can operate in either one of the below two modes
   8  *  - CAN FD only mode
   9  *  - Classical CAN (CAN 2.0) only mode
  10  *
  11  * This driver puts the controller in CAN FD only mode by default. In this
  12  * mode, the controller acts as a CAN FD node that can also interoperate with
  13  * CAN 2.0 nodes.
  14  *
  15  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17  * also required to switch modes.
  18  *
  19  * Note: The h/w manual register naming convention is clumsy and not acceptable
  20  * to use as it is in the driver. However, those names are added as comments
  21  * wherever it is modified to a readable name.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/errno.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/can/dev.h>
  33 #include <linux/clk.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/bitmap.h>
  37 #include <linux/bitops.h>
  38 #include <linux/iopoll.h>
  39 #include <linux/reset.h>
  40
  41 #define RCANFD_DRV_NAME                 "rcar_canfd"
  42
  43 enum rcanfd_chip_id {
  44         RENESAS_RCAR_GEN3 = 0,
  45         RENESAS_RZG2L,
  46         RENESAS_R8A779A0,
  47 };
  48
  49 /* Global register bits */
  50
  51 /* RSCFDnCFDGRMCFG */
  52 #define RCANFD_GRMCFG_RCMC              BIT(0)
  53
  54 /* RSCFDnCFDGCFG / RSCFDnGCFG */
  55 #define RCANFD_GCFG_EEFE                BIT(6)
  56 #define RCANFD_GCFG_CMPOC               BIT(5)  /* CAN FD only */
  57 #define RCANFD_GCFG_DCS                 BIT(4)
  58 #define RCANFD_GCFG_DCE                 BIT(1)
  59 #define RCANFD_GCFG_TPRI                BIT(0)
  60
  61 /* RSCFDnCFDGCTR / RSCFDnGCTR */
  62 #define RCANFD_GCTR_TSRST               BIT(16)
  63 #define RCANFD_GCTR_CFMPOFIE            BIT(11) /* CAN FD only */
  64 #define RCANFD_GCTR_THLEIE              BIT(10)
  65 #define RCANFD_GCTR_MEIE                BIT(9)
  66 #define RCANFD_GCTR_DEIE                BIT(8)
  67 #define RCANFD_GCTR_GSLPR               BIT(2)
  68 #define RCANFD_GCTR_GMDC_MASK           (0x3)
  69 #define RCANFD_GCTR_GMDC_GOPM           (0x0)
  70 #define RCANFD_GCTR_GMDC_GRESET         (0x1)
  71 #define RCANFD_GCTR_GMDC_GTEST          (0x2)
  72
  73 /* RSCFDnCFDGSTS / RSCFDnGSTS */
  74 #define RCANFD_GSTS_GRAMINIT            BIT(3)
  75 #define RCANFD_GSTS_GSLPSTS             BIT(2)
  76 #define RCANFD_GSTS_GHLTSTS             BIT(1)
  77 #define RCANFD_GSTS_GRSTSTS             BIT(0)
  78 /* Non-operational status */
  79 #define RCANFD_GSTS_GNOPM               (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  80
  81 /* RSCFDnCFDGERFL / RSCFDnGERFL */
  82 #define RCANFD_GERFL_EEF0_7             GENMASK(23, 16)
  83 #define RCANFD_GERFL_EEF1               BIT(17)
  84 #define RCANFD_GERFL_EEF0               BIT(16)
  85 #define RCANFD_GERFL_CMPOF              BIT(3)  /* CAN FD only */
  86 #define RCANFD_GERFL_THLES              BIT(2)
  87 #define RCANFD_GERFL_MES                BIT(1)
  88 #define RCANFD_GERFL_DEF                BIT(0)
  89
  90 #define RCANFD_GERFL_ERR(gpriv, x) \
  91         ((x) & (reg_v3u(gpriv, RCANFD_GERFL_EEF0_7, \
  92                         RCANFD_GERFL_EEF0 | RCANFD_GERFL_EEF1) | \
  93                 RCANFD_GERFL_MES | \
  94                 ((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
  95
  96 /* AFL Rx rules registers */
  97
  98 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  99 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
 100         (((x) & reg_v3u(gpriv, 0x1ff, 0xff)) << \
 101          (reg_v3u(gpriv, 16, 24) - (n) * reg_v3u(gpriv, 16, 8)))
 102
 103 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
 104         (((x) >> (reg_v3u(gpriv, 16, 24) - (n) * reg_v3u(gpriv, 16, 8))) & \
 105          reg_v3u(gpriv, 0x1ff, 0xff))
 106
 107 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 108 #define RCANFD_GAFLECTR_AFLDAE          BIT(8)
 109 #define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & reg_v3u(gpriv, 0x7f, 0x1f))
 110
 111 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 112 #define RCANFD_GAFLID_GAFLLB            BIT(29)
 113
 114 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 115 #define RCANFD_GAFLP1_GAFLFDP(x)        (1 << (x))
 116
 117 /* Channel register bits */
 118
 119 /* RSCFDnCmCFG - Classical CAN only */
 120 #define RCANFD_CFG_SJW(x)               (((x) & 0x3) << 24)
 121 #define RCANFD_CFG_TSEG2(x)             (((x) & 0x7) << 20)
 122 #define RCANFD_CFG_TSEG1(x)             (((x) & 0xf) << 16)
 123 #define RCANFD_CFG_BRP(x)               (((x) & 0x3ff) << 0)
 124
 125 /* RSCFDnCFDCmNCFG - CAN FD only */
 126 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
 127         (((x) & reg_v3u(gpriv, 0x7f, 0x1f)) << reg_v3u(gpriv, 25, 24))
 128
 129 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
 130         (((x) & reg_v3u(gpriv, 0xff, 0x7f)) << reg_v3u(gpriv, 17, 16))
 131
 132 #define RCANFD_NCFG_NSJW(gpriv, x) \
 133         (((x) & reg_v3u(gpriv, 0x7f, 0x1f)) << reg_v3u(gpriv, 10, 11))
 134
 135 #define RCANFD_NCFG_NBRP(x)             (((x) & 0x3ff) << 0)
 136
 137 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 138 #define RCANFD_CCTR_CTME                BIT(24)
 139 #define RCANFD_CCTR_ERRD                BIT(23)
 140 #define RCANFD_CCTR_BOM_MASK            (0x3 << 21)
 141 #define RCANFD_CCTR_BOM_ISO             (0x0 << 21)
 142 #define RCANFD_CCTR_BOM_BENTRY          (0x1 << 21)
 143 #define RCANFD_CCTR_BOM_BEND            (0x2 << 21)
 144 #define RCANFD_CCTR_TDCVFIE             BIT(19)
 145 #define RCANFD_CCTR_SOCOIE              BIT(18)
 146 #define RCANFD_CCTR_EOCOIE              BIT(17)
 147 #define RCANFD_CCTR_TAIE                BIT(16)
 148 #define RCANFD_CCTR_ALIE                BIT(15)
 149 #define RCANFD_CCTR_BLIE                BIT(14)
 150 #define RCANFD_CCTR_OLIE                BIT(13)
 151 #define RCANFD_CCTR_BORIE               BIT(12)
 152 #define RCANFD_CCTR_BOEIE               BIT(11)
 153 #define RCANFD_CCTR_EPIE                BIT(10)
 154 #define RCANFD_CCTR_EWIE                BIT(9)
 155 #define RCANFD_CCTR_BEIE                BIT(8)
 156 #define RCANFD_CCTR_CSLPR               BIT(2)
 157 #define RCANFD_CCTR_CHMDC_MASK          (0x3)
 158 #define RCANFD_CCTR_CHDMC_COPM          (0x0)
 159 #define RCANFD_CCTR_CHDMC_CRESET        (0x1)
 160 #define RCANFD_CCTR_CHDMC_CHLT          (0x2)
 161
 162 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 163 #define RCANFD_CSTS_COMSTS              BIT(7)
 164 #define RCANFD_CSTS_RECSTS              BIT(6)
 165 #define RCANFD_CSTS_TRMSTS              BIT(5)
 166 #define RCANFD_CSTS_BOSTS               BIT(4)
 167 #define RCANFD_CSTS_EPSTS               BIT(3)
 168 #define RCANFD_CSTS_SLPSTS              BIT(2)
 169 #define RCANFD_CSTS_HLTSTS              BIT(1)
 170 #define RCANFD_CSTS_CRSTSTS             BIT(0)
 171
 172 #define RCANFD_CSTS_TECCNT(x)           (((x) >> 24) & 0xff)
 173 #define RCANFD_CSTS_RECCNT(x)           (((x) >> 16) & 0xff)
 174
 175 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 176 #define RCANFD_CERFL_ADERR              BIT(14)
 177 #define RCANFD_CERFL_B0ERR              BIT(13)
 178 #define RCANFD_CERFL_B1ERR              BIT(12)
 179 #define RCANFD_CERFL_CERR               BIT(11)
 180 #define RCANFD_CERFL_AERR               BIT(10)
 181 #define RCANFD_CERFL_FERR               BIT(9)
 182 #define RCANFD_CERFL_SERR               BIT(8)
 183 #define RCANFD_CERFL_ALF                BIT(7)
 184 #define RCANFD_CERFL_BLF                BIT(6)
 185 #define RCANFD_CERFL_OVLF               BIT(5)
 186 #define RCANFD_CERFL_BORF               BIT(4)
 187 #define RCANFD_CERFL_BOEF               BIT(3)
 188 #define RCANFD_CERFL_EPF                BIT(2)
 189 #define RCANFD_CERFL_EWF                BIT(1)
 190 #define RCANFD_CERFL_BEF                BIT(0)
 191
 192 #define RCANFD_CERFL_ERR(x)             ((x) & (0x7fff)) /* above bits 14:0 */
 193
 194 /* RSCFDnCFDCmDCFG */
 195 #define RCANFD_DCFG_DSJW(x)             (((x) & 0x7) << 24)
 196
 197 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
 198         (((x) & reg_v3u(gpriv, 0x0f, 0x7)) << reg_v3u(gpriv, 16, 20))
 199
 200 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
 201         (((x) & reg_v3u(gpriv, 0x1f, 0xf)) << reg_v3u(gpriv, 8, 16))
 202
 203 #define RCANFD_DCFG_DBRP(x)             (((x) & 0xff) << 0)
 204
 205 /* RSCFDnCFDCmFDCFG */
 206 #define RCANFD_FDCFG_CLOE               BIT(30)
 207 #define RCANFD_FDCFG_FDOE               BIT(28)
 208 #define RCANFD_FDCFG_TDCE               BIT(9)
 209 #define RCANFD_FDCFG_TDCOC              BIT(8)
 210 #define RCANFD_FDCFG_TDCO(x)            (((x) & 0x7f) >> 16)
 211
 212 /* RSCFDnCFDRFCCx */
 213 #define RCANFD_RFCC_RFIM                BIT(12)
 214 #define RCANFD_RFCC_RFDC(x)             (((x) & 0x7) << 8)
 215 #define RCANFD_RFCC_RFPLS(x)            (((x) & 0x7) << 4)
 216 #define RCANFD_RFCC_RFIE                BIT(1)
 217 #define RCANFD_RFCC_RFE                 BIT(0)
 218
 219 /* RSCFDnCFDRFSTSx */
 220 #define RCANFD_RFSTS_RFIF               BIT(3)
 221 #define RCANFD_RFSTS_RFMLT              BIT(2)
 222 #define RCANFD_RFSTS_RFFLL              BIT(1)
 223 #define RCANFD_RFSTS_RFEMP              BIT(0)
 224
 225 /* RSCFDnCFDRFIDx */
 226 #define RCANFD_RFID_RFIDE               BIT(31)
 227 #define RCANFD_RFID_RFRTR               BIT(30)
 228
 229 /* RSCFDnCFDRFPTRx */
 230 #define RCANFD_RFPTR_RFDLC(x)           (((x) >> 28) & 0xf)
 231 #define RCANFD_RFPTR_RFPTR(x)           (((x) >> 16) & 0xfff)
 232 #define RCANFD_RFPTR_RFTS(x)            (((x) >> 0) & 0xffff)
 233
 234 /* RSCFDnCFDRFFDSTSx */
 235 #define RCANFD_RFFDSTS_RFFDF            BIT(2)
 236 #define RCANFD_RFFDSTS_RFBRS            BIT(1)
 237 #define RCANFD_RFFDSTS_RFESI            BIT(0)
 238
 239 /* Common FIFO bits */
 240
 241 /* RSCFDnCFDCFCCk */
 242 #define RCANFD_CFCC_CFTML(gpriv, x)     (((x) & 0xf) << reg_v3u(gpriv, 16, 20))
 243 #define RCANFD_CFCC_CFM(gpriv, x)       (((x) & 0x3) << reg_v3u(gpriv,  8, 16))
 244 #define RCANFD_CFCC_CFIM                BIT(12)
 245 #define RCANFD_CFCC_CFDC(gpriv, x)      (((x) & 0x7) << reg_v3u(gpriv, 21,  8))
 246 #define RCANFD_CFCC_CFPLS(x)            (((x) & 0x7) << 4)
 247 #define RCANFD_CFCC_CFTXIE              BIT(2)
 248 #define RCANFD_CFCC_CFE                 BIT(0)
 249
 250 /* RSCFDnCFDCFSTSk */
 251 #define RCANFD_CFSTS_CFMC(x)            (((x) >> 8) & 0xff)
 252 #define RCANFD_CFSTS_CFTXIF             BIT(4)
 253 #define RCANFD_CFSTS_CFMLT              BIT(2)
 254 #define RCANFD_CFSTS_CFFLL              BIT(1)
 255 #define RCANFD_CFSTS_CFEMP              BIT(0)
 256
 257 /* RSCFDnCFDCFIDk */
 258 #define RCANFD_CFID_CFIDE               BIT(31)
 259 #define RCANFD_CFID_CFRTR               BIT(30)
 260 #define RCANFD_CFID_CFID_MASK(x)        ((x) & 0x1fffffff)
 261
 262 /* RSCFDnCFDCFPTRk */
 263 #define RCANFD_CFPTR_CFDLC(x)           (((x) & 0xf) << 28)
 264 #define RCANFD_CFPTR_CFPTR(x)           (((x) & 0xfff) << 16)
 265 #define RCANFD_CFPTR_CFTS(x)            (((x) & 0xff) << 0)
 266
 267 /* RSCFDnCFDCFFDCSTSk */
 268 #define RCANFD_CFFDCSTS_CFFDF           BIT(2)
 269 #define RCANFD_CFFDCSTS_CFBRS           BIT(1)
 270 #define RCANFD_CFFDCSTS_CFESI           BIT(0)
 271
 272 /* This controller supports either Classical CAN only mode or CAN FD only mode.
 273  * These modes are supported in two separate set of register maps & names.
 274  * However, some of the register offsets are common for both modes. Those
 275  * offsets are listed below as Common registers.
 276  *
 277  * The CAN FD only mode specific registers & Classical CAN only mode specific
 278  * registers are listed separately. Their register names starts with
 279  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 280  */
 281
 282 /* Common registers */
 283
 284 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 285 #define RCANFD_CCFG(m)                  (0x0000 + (0x10 * (m)))
 286 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 287 #define RCANFD_CCTR(m)                  (0x0004 + (0x10 * (m)))
 288 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 289 #define RCANFD_CSTS(m)                  (0x0008 + (0x10 * (m)))
 290 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 291 #define RCANFD_CERFL(m)                 (0x000C + (0x10 * (m)))
 292
 293 /* RSCFDnCFDGCFG / RSCFDnGCFG */
 294 #define RCANFD_GCFG                     (0x0084)
 295 /* RSCFDnCFDGCTR / RSCFDnGCTR */
 296 #define RCANFD_GCTR                     (0x0088)
 297 /* RSCFDnCFDGCTS / RSCFDnGCTS */
 298 #define RCANFD_GSTS                     (0x008c)
 299 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 300 #define RCANFD_GERFL                    (0x0090)
 301 /* RSCFDnCFDGTSC / RSCFDnGTSC */
 302 #define RCANFD_GTSC                     (0x0094)
 303 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 304 #define RCANFD_GAFLECTR                 (0x0098)
 305 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
 306 #define RCANFD_GAFLCFG(ch)              (0x009c + (0x04 * ((ch) / 2)))
 307 /* RSCFDnCFDRMNB / RSCFDnRMNB */
 308 #define RCANFD_RMNB                     (0x00a4)
 309 /* RSCFDnCFDRMND / RSCFDnRMND */
 310 #define RCANFD_RMND(y)                  (0x00a8 + (0x04 * (y)))
 311
 312 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 313 #define RCANFD_RFCC(gpriv, x)           (reg_v3u(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
 314 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 315 #define RCANFD_RFSTS(gpriv, x)          (RCANFD_RFCC(gpriv, x) + 0x20)
 316 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 317 #define RCANFD_RFPCTR(gpriv, x)         (RCANFD_RFCC(gpriv, x) + 0x40)
 318
 319 /* Common FIFO Control registers */
 320
 321 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 322 #define RCANFD_CFCC(gpriv, ch, idx) \
 323         (reg_v3u(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
 324 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 325 #define RCANFD_CFSTS(gpriv, ch, idx) \
 326         (reg_v3u(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
 327 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 328 #define RCANFD_CFPCTR(gpriv, ch, idx) \
 329         (reg_v3u(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
 330
 331 /* RSCFDnCFDFESTS / RSCFDnFESTS */
 332 #define RCANFD_FESTS                    (0x0238)
 333 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 334 #define RCANFD_FFSTS                    (0x023c)
 335 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 336 #define RCANFD_FMSTS                    (0x0240)
 337 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 338 #define RCANFD_RFISTS                   (0x0244)
 339 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 340 #define RCANFD_CFRISTS                  (0x0248)
 341 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 342 #define RCANFD_CFTISTS                  (0x024c)
 343
 344 /* RSCFDnCFDTMCp / RSCFDnTMCp */
 345 #define RCANFD_TMC(p)                   (0x0250 + (0x01 * (p)))
 346 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 347 #define RCANFD_TMSTS(p)                 (0x02d0 + (0x01 * (p)))
 348
 349 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 350 #define RCANFD_TMTRSTS(y)               (0x0350 + (0x04 * (y)))
 351 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 352 #define RCANFD_TMTARSTS(y)              (0x0360 + (0x04 * (y)))
 353 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 354 #define RCANFD_TMTCSTS(y)               (0x0370 + (0x04 * (y)))
 355 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 356 #define RCANFD_TMTASTS(y)               (0x0380 + (0x04 * (y)))
 357 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 358 #define RCANFD_TMIEC(y)                 (0x0390 + (0x04 * (y)))
 359
 360 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 361 #define RCANFD_TXQCC(m)                 (0x03a0 + (0x04 * (m)))
 362 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 363 #define RCANFD_TXQSTS(m)                (0x03c0 + (0x04 * (m)))
 364 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 365 #define RCANFD_TXQPCTR(m)               (0x03e0 + (0x04 * (m)))
 366
 367 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 368 #define RCANFD_THLCC(m)                 (0x0400 + (0x04 * (m)))
 369 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 370 #define RCANFD_THLSTS(m)                (0x0420 + (0x04 * (m)))
 371 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 372 #define RCANFD_THLPCTR(m)               (0x0440 + (0x04 * (m)))
 373
 374 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 375 #define RCANFD_GTINTSTS0                (0x0460)
 376 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 377 #define RCANFD_GTINTSTS1                (0x0464)
 378 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 379 #define RCANFD_GTSTCFG                  (0x0468)
 380 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 381 #define RCANFD_GTSTCTR                  (0x046c)
 382 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 383 #define RCANFD_GLOCKK                   (0x047c)
 384 /* RSCFDnCFDGRMCFG */
 385 #define RCANFD_GRMCFG                   (0x04fc)
 386
 387 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 388 #define RCANFD_GAFLID(offset, j)        ((offset) + (0x10 * (j)))
 389 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 390 #define RCANFD_GAFLM(offset, j)         ((offset) + 0x04 + (0x10 * (j)))
 391 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 392 #define RCANFD_GAFLP0(offset, j)        ((offset) + 0x08 + (0x10 * (j)))
 393 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 394 #define RCANFD_GAFLP1(offset, j)        ((offset) + 0x0c + (0x10 * (j)))
 395
 396 /* Classical CAN only mode register map */
 397
 398 /* RSCFDnGAFLXXXj offset */
 399 #define RCANFD_C_GAFL_OFFSET            (0x0500)
 400
 401 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 402 #define RCANFD_C_RMID(q)                (0x0600 + (0x10 * (q)))
 403 #define RCANFD_C_RMPTR(q)               (0x0604 + (0x10 * (q)))
 404 #define RCANFD_C_RMDF0(q)               (0x0608 + (0x10 * (q)))
 405 #define RCANFD_C_RMDF1(q)               (0x060c + (0x10 * (q)))
 406
 407 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 408 #define RCANFD_C_RFOFFSET       (0x0e00)
 409 #define RCANFD_C_RFID(x)        (RCANFD_C_RFOFFSET + (0x10 * (x)))
 410 #define RCANFD_C_RFPTR(x)       (RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
 411 #define RCANFD_C_RFDF(x, df) \
 412                 (RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
 413
 414 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 415 #define RCANFD_C_CFOFFSET               (0x0e80)
 416
 417 #define RCANFD_C_CFID(ch, idx) \
 418         (RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
 419
 420 #define RCANFD_C_CFPTR(ch, idx) \
 421         (RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
 422
 423 #define RCANFD_C_CFDF(ch, idx, df) \
 424         (RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
 425
 426 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 427 #define RCANFD_C_TMID(p)                (0x1000 + (0x10 * (p)))
 428 #define RCANFD_C_TMPTR(p)               (0x1004 + (0x10 * (p)))
 429 #define RCANFD_C_TMDF0(p)               (0x1008 + (0x10 * (p)))
 430 #define RCANFD_C_TMDF1(p)               (0x100c + (0x10 * (p)))
 431
 432 /* RSCFDnTHLACCm */
 433 #define RCANFD_C_THLACC(m)              (0x1800 + (0x04 * (m)))
 434 /* RSCFDnRPGACCr */
 435 #define RCANFD_C_RPGACC(r)              (0x1900 + (0x04 * (r)))
 436
 437 /* R-Car V3U Classical and CAN FD mode specific register map */
 438 #define RCANFD_V3U_CFDCFG               (0x1314)
 439 #define RCANFD_V3U_DCFG(m)              (0x1400 + (0x20 * (m)))
 440
 441 #define RCANFD_V3U_GAFL_OFFSET          (0x1800)
 442
 443 /* CAN FD mode specific register map */
 444
 445 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 446 #define RCANFD_F_DCFG(m)                (0x0500 + (0x20 * (m)))
 447 #define RCANFD_F_CFDCFG(m)              (0x0504 + (0x20 * (m)))
 448 #define RCANFD_F_CFDCTR(m)              (0x0508 + (0x20 * (m)))
 449 #define RCANFD_F_CFDSTS(m)              (0x050c + (0x20 * (m)))
 450 #define RCANFD_F_CFDCRC(m)              (0x0510 + (0x20 * (m)))
 451
 452 /* RSCFDnCFDGAFLXXXj offset */
 453 #define RCANFD_F_GAFL_OFFSET            (0x1000)
 454
 455 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 456 #define RCANFD_F_RMID(q)                (0x2000 + (0x20 * (q)))
 457 #define RCANFD_F_RMPTR(q)               (0x2004 + (0x20 * (q)))
 458 #define RCANFD_F_RMFDSTS(q)             (0x2008 + (0x20 * (q)))
 459 #define RCANFD_F_RMDF(q, b)             (0x200c + (0x04 * (b)) + (0x20 * (q)))
 460
 461 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 462 #define RCANFD_F_RFOFFSET(gpriv)        reg_v3u(gpriv, 0x6000, 0x3000)
 463 #define RCANFD_F_RFID(gpriv, x)         (RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
 464 #define RCANFD_F_RFPTR(gpriv, x)        (RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
 465 #define RCANFD_F_RFFDSTS(gpriv, x)      (RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
 466 #define RCANFD_F_RFDF(gpriv, x, df) \
 467         (RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
 468
 469 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 470 #define RCANFD_F_CFOFFSET(gpriv)        reg_v3u(gpriv, 0x6400, 0x3400)
 471
 472 #define RCANFD_F_CFID(gpriv, ch, idx) \
 473         (RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
 474
 475 #define RCANFD_F_CFPTR(gpriv, ch, idx) \
 476         (RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
 477
 478 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
 479         (RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
 480
 481 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \
 482         (RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
 483          (0x04 * (df)))
 484
 485 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 486 #define RCANFD_F_TMID(p)                (0x4000 + (0x20 * (p)))
 487 #define RCANFD_F_TMPTR(p)               (0x4004 + (0x20 * (p)))
 488 #define RCANFD_F_TMFDCTR(p)             (0x4008 + (0x20 * (p)))
 489 #define RCANFD_F_TMDF(p, b)             (0x400c + (0x20 * (p)) + (0x04 * (b)))
 490
 491 /* RSCFDnCFDTHLACCm */
 492 #define RCANFD_F_THLACC(m)              (0x6000 + (0x04 * (m)))
 493 /* RSCFDnCFDRPGACCr */
 494 #define RCANFD_F_RPGACC(r)              (0x6400 + (0x04 * (r)))
 495
 496 /* Constants */
 497 #define RCANFD_FIFO_DEPTH               8       /* Tx FIFO depth */
 498 #define RCANFD_NAPI_WEIGHT              8       /* Rx poll quota */
 499
 500 #define RCANFD_NUM_CHANNELS             8       /* Eight channels max */
 501 #define RCANFD_CHANNELS_MASK            BIT((RCANFD_NUM_CHANNELS) - 1)
 502
 503 #define RCANFD_GAFL_PAGENUM(entry)      ((entry) / 16)
 504 #define RCANFD_CHANNEL_NUMRULES         1       /* only one rule per channel */
 505
 506 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 507  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 508  * number is added to RFFIFO index.
 509  */
 510 #define RCANFD_RFFIFO_IDX               0
 511
 512 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 513  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 514  */
 515 #define RCANFD_CFFIFO_IDX               0
 516
 517 /* fCAN clock select register settings */
 518 enum rcar_canfd_fcanclk {
 519         RCANFD_CANFDCLK = 0,            /* CANFD clock */
 520         RCANFD_EXTCLK,                  /* Externally input clock */
 521 };
 522
 523 struct rcar_canfd_global;
 524
 525 /* Channel priv data */
 526 struct rcar_canfd_channel {
 527         struct can_priv can;                    /* Must be the first member */
 528         struct net_device *ndev;
 529         struct rcar_canfd_global *gpriv;        /* Controller reference */
 530         void __iomem *base;                     /* Register base address */
 531         struct napi_struct napi;
 532         u32 tx_head;                            /* Incremented on xmit */
 533         u32 tx_tail;                            /* Incremented on xmit done */
 534         u32 channel;                            /* Channel number */
 535         spinlock_t tx_lock;                     /* To protect tx path */
 536 };
 537
 538 /* Global priv data */
 539 struct rcar_canfd_global {
 540         struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 541         void __iomem *base;             /* Register base address */
 542         struct platform_device *pdev;   /* Respective platform device */
 543         struct clk *clkp;               /* Peripheral clock */
 544         struct clk *can_clk;            /* fCAN clock */
 545         enum rcar_canfd_fcanclk fcan;   /* CANFD or Ext clock */
 546         unsigned long channels_mask;    /* Enabled channels mask */
 547         bool fdmode;                    /* CAN FD or Classical CAN only mode */
 548         struct reset_control *rstc1;
 549         struct reset_control *rstc2;
 550         enum rcanfd_chip_id chip_id;
 551         u32 max_channels;
 552 };
 553
 554 /* CAN FD mode nominal rate constants */
 555 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 556         .name = RCANFD_DRV_NAME,
 557         .tseg1_min = 2,
 558         .tseg1_max = 128,
 559         .tseg2_min = 2,
 560         .tseg2_max = 32,
 561         .sjw_max = 32,
 562         .brp_min = 1,
 563         .brp_max = 1024,
 564         .brp_inc = 1,
 565 };
 566
 567 /* CAN FD mode data rate constants */
 568 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 569         .name = RCANFD_DRV_NAME,
 570         .tseg1_min = 2,
 571         .tseg1_max = 16,
 572         .tseg2_min = 2,
 573         .tseg2_max = 8,
 574         .sjw_max = 8,
 575         .brp_min = 1,
 576         .brp_max = 256,
 577         .brp_inc = 1,
 578 };
 579
 580 /* Classical CAN mode bitrate constants */
 581 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 582         .name = RCANFD_DRV_NAME,
 583         .tseg1_min = 4,
 584         .tseg1_max = 16,
 585         .tseg2_min = 2,
 586         .tseg2_max = 8,
 587         .sjw_max = 4,
 588         .brp_min = 1,
 589         .brp_max = 1024,
 590         .brp_inc = 1,
 591 };
 592
 593 /* Helper functions */
 594 static inline bool is_v3u(struct rcar_canfd_global *gpriv)
 595 {
 596         return gpriv->chip_id == RENESAS_R8A779A0;
 597 }
 598
 599 static inline u32 reg_v3u(struct rcar_canfd_global *gpriv,
 600                           u32 v3u, u32 not_v3u)
 601 {
 602         return is_v3u(gpriv) ? v3u : not_v3u;
 603 }
 604
 605 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 606 {
 607         u32 data = readl(reg);
 608
 609         data &= ~mask;
 610         data |= (val & mask);
 611         writel(data, reg);
 612 }
 613
 614 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 615 {
 616         return readl(base + (offset));
 617 }
 618
 619 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 620 {
 621         writel(val, base + (offset));
 622 }
 623
 624 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 625 {
 626         rcar_canfd_update(val, val, base + (reg));
 627 }
 628
 629 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 630 {
 631         rcar_canfd_update(val, 0, base + (reg));
 632 }
 633
 634 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 635                                   u32 mask, u32 val)
 636 {
 637         rcar_canfd_update(mask, val, base + (reg));
 638 }
 639
 640 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 641                                 struct canfd_frame *cf, u32 off)
 642 {
 643         u32 i, lwords;
 644
 645         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 646         for (i = 0; i < lwords; i++)
 647                 *((u32 *)cf->data + i) =
 648                         rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 649 }
 650
 651 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 652                                 struct canfd_frame *cf, u32 off)
 653 {
 654         u32 i, lwords;
 655
 656         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 657         for (i = 0; i < lwords; i++)
 658                 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 659                                  *((u32 *)cf->data + i));
 660 }
 661
 662 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 663 {
 664         u32 i;
 665
 666         for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 667                 can_free_echo_skb(ndev, i, NULL);
 668 }
 669
 670 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
 671 {
 672         if (is_v3u(gpriv)) {
 673                 if (gpriv->fdmode)
 674                         rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG,
 675                                            RCANFD_FDCFG_FDOE);
 676                 else
 677                         rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG,
 678                                            RCANFD_FDCFG_CLOE);
 679         } else {
 680                 if (gpriv->fdmode)
 681                         rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 682                                            RCANFD_GRMCFG_RCMC);
 683                 else
 684                         rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 685                                              RCANFD_GRMCFG_RCMC);
 686         }
 687 }
 688
 689 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 690 {
 691         u32 sts, ch;
 692         int err;
 693
 694         /* Check RAMINIT flag as CAN RAM initialization takes place
 695          * after the MCU reset
 696          */
 697         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 698                                  !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 699         if (err) {
 700                 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 701                 return err;
 702         }
 703
 704         /* Transition to Global Reset mode */
 705         rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 706         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 707                               RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 708
 709         /* Ensure Global reset mode */
 710         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 711                                  (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 712         if (err) {
 713                 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 714                 return err;
 715         }
 716
 717         /* Reset Global error flags */
 718         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 719
 720         /* Set the controller into appropriate mode */
 721         rcar_canfd_set_mode(gpriv);
 722
 723         /* Transition all Channels to reset mode */
 724         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
 725                 rcar_canfd_clear_bit(gpriv->base,
 726                                      RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 727
 728                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 729                                       RCANFD_CCTR_CHMDC_MASK,
 730                                       RCANFD_CCTR_CHDMC_CRESET);
 731
 732                 /* Ensure Channel reset mode */
 733                 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 734                                          (sts & RCANFD_CSTS_CRSTSTS),
 735                                          2, 500000);
 736                 if (err) {
 737                         dev_dbg(&gpriv->pdev->dev,
 738                                 "channel %u reset failed\n", ch);
 739                         return err;
 740                 }
 741         }
 742         return 0;
 743 }
 744
 745 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 746 {
 747         u32 cfg, ch;
 748
 749         /* Global configuration settings */
 750
 751         /* ECC Error flag Enable */
 752         cfg = RCANFD_GCFG_EEFE;
 753
 754         if (gpriv->fdmode)
 755                 /* Truncate payload to configured message size RFPLS */
 756                 cfg |= RCANFD_GCFG_CMPOC;
 757
 758         /* Set External Clock if selected */
 759         if (gpriv->fcan != RCANFD_CANFDCLK)
 760                 cfg |= RCANFD_GCFG_DCS;
 761
 762         rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 763
 764         /* Channel configuration settings */
 765         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
 766                 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 767                                    RCANFD_CCTR_ERRD);
 768                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 769                                       RCANFD_CCTR_BOM_MASK,
 770                                       RCANFD_CCTR_BOM_BENTRY);
 771         }
 772 }
 773
 774 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 775                                            u32 ch)
 776 {
 777         u32 cfg;
 778         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 779         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 780
 781         if (ch == 0) {
 782                 start = 0; /* Channel 0 always starts from 0th rule */
 783         } else {
 784                 /* Get number of Channel 0 rules and adjust */
 785                 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG(ch));
 786                 start = RCANFD_GAFLCFG_GETRNC(gpriv, 0, cfg);
 787         }
 788
 789         /* Enable write access to entry */
 790         page = RCANFD_GAFL_PAGENUM(start);
 791         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 792                            (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
 793                             RCANFD_GAFLECTR_AFLDAE));
 794
 795         /* Write number of rules for channel */
 796         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
 797                            RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
 798         if (is_v3u(gpriv))
 799                 offset = RCANFD_V3U_GAFL_OFFSET;
 800         else if (gpriv->fdmode)
 801                 offset = RCANFD_F_GAFL_OFFSET;
 802         else
 803                 offset = RCANFD_C_GAFL_OFFSET;
 804
 805         /* Accept all IDs */
 806         rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 807         /* IDE or RTR is not considered for matching */
 808         rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 809         /* Any data length accepted */
 810         rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 811         /* Place the msg in corresponding Rx FIFO entry */
 812         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, start),
 813                            RCANFD_GAFLP1_GAFLFDP(ridx));
 814
 815         /* Disable write access to page */
 816         rcar_canfd_clear_bit(gpriv->base,
 817                              RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 818 }
 819
 820 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 821 {
 822         /* Rx FIFO is used for reception */
 823         u32 cfg;
 824         u16 rfdc, rfpls;
 825
 826         /* Select Rx FIFO based on channel */
 827         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 828
 829         rfdc = 2;               /* b010 - 8 messages Rx FIFO depth */
 830         if (gpriv->fdmode)
 831                 rfpls = 7;      /* b111 - Max 64 bytes payload */
 832         else
 833                 rfpls = 0;      /* b000 - Max 8 bytes payload */
 834
 835         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 836                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 837         rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
 838 }
 839
 840 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 841 {
 842         /* Tx/Rx(Common) FIFO configured in Tx mode is
 843          * used for transmission
 844          *
 845          * Each channel has 3 Common FIFO dedicated to them.
 846          * Use the 1st (index 0) out of 3
 847          */
 848         u32 cfg;
 849         u16 cftml, cfm, cfdc, cfpls;
 850
 851         cftml = 0;              /* 0th buffer */
 852         cfm = 1;                /* b01 - Transmit mode */
 853         cfdc = 2;               /* b010 - 8 messages Tx FIFO depth */
 854         if (gpriv->fdmode)
 855                 cfpls = 7;      /* b111 - Max 64 bytes payload */
 856         else
 857                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 858
 859         cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
 860                 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
 861                 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 862         rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
 863
 864         if (gpriv->fdmode)
 865                 /* Clear FD mode specific control/status register */
 866                 rcar_canfd_write(gpriv->base,
 867                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
 868 }
 869
 870 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 871 {
 872         u32 ctr;
 873
 874         /* Clear any stray error interrupt flags */
 875         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 876
 877         /* Global interrupts setup */
 878         ctr = RCANFD_GCTR_MEIE;
 879         if (gpriv->fdmode)
 880                 ctr |= RCANFD_GCTR_CFMPOFIE;
 881
 882         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 883 }
 884
 885 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 886                                                  *gpriv)
 887 {
 888         /* Disable all interrupts */
 889         rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 890
 891         /* Clear any stray error interrupt flags */
 892         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 893 }
 894
 895 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 896                                                  *priv)
 897 {
 898         u32 ctr, ch = priv->channel;
 899
 900         /* Clear any stray error flags */
 901         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 902
 903         /* Channel interrupts setup */
 904         ctr = (RCANFD_CCTR_TAIE |
 905                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 906                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 907                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 908                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 909         rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 910 }
 911
 912 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 913                                                   *priv)
 914 {
 915         u32 ctr, ch = priv->channel;
 916
 917         ctr = (RCANFD_CCTR_TAIE |
 918                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 919                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 920                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 921                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 922         rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 923
 924         /* Clear any stray error flags */
 925         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 926 }
 927
 928 static void rcar_canfd_global_error(struct net_device *ndev)
 929 {
 930         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 931         struct rcar_canfd_global *gpriv = priv->gpriv;
 932         struct net_device_stats *stats = &ndev->stats;
 933         u32 ch = priv->channel;
 934         u32 gerfl, sts;
 935         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 936
 937         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 938         if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
 939                 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
 940                 stats->tx_dropped++;
 941         }
 942         if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
 943                 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
 944                 stats->tx_dropped++;
 945         }
 946         if (gerfl & RCANFD_GERFL_MES) {
 947                 sts = rcar_canfd_read(priv->base,
 948                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
 949                 if (sts & RCANFD_CFSTS_CFMLT) {
 950                         netdev_dbg(ndev, "Tx Message Lost flag\n");
 951                         stats->tx_dropped++;
 952                         rcar_canfd_write(priv->base,
 953                                          RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
 954                                          sts & ~RCANFD_CFSTS_CFMLT);
 955                 }
 956
 957                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
 958                 if (sts & RCANFD_RFSTS_RFMLT) {
 959                         netdev_dbg(ndev, "Rx Message Lost flag\n");
 960                         stats->rx_dropped++;
 961                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
 962                                          sts & ~RCANFD_RFSTS_RFMLT);
 963                 }
 964         }
 965         if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 966                 /* Message Lost flag will be set for respective channel
 967                  * when this condition happens with counters and flags
 968                  * already updated.
 969                  */
 970                 netdev_dbg(ndev, "global payload overflow interrupt\n");
 971         }
 972
 973         /* Clear all global error interrupts. Only affected channels bits
 974          * get cleared
 975          */
 976         rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 977 }
 978
 979 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 980                              u16 txerr, u16 rxerr)
 981 {
 982         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 983         struct net_device_stats *stats = &ndev->stats;
 984         struct can_frame *cf;
 985         struct sk_buff *skb;
 986         u32 ch = priv->channel;
 987
 988         netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
 989
 990         /* Propagate the error condition to the CAN stack */
 991         skb = alloc_can_err_skb(ndev, &cf);
 992         if (!skb) {
 993                 stats->rx_dropped++;
 994                 return;
 995         }
 996
 997         /* Channel error interrupts */
 998         if (cerfl & RCANFD_CERFL_BEF) {
 999                 netdev_dbg(ndev, "Bus error\n");
1000                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1001                 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1002                 priv->can.can_stats.bus_error++;
1003         }
1004         if (cerfl & RCANFD_CERFL_ADERR) {
1005                 netdev_dbg(ndev, "ACK Delimiter Error\n");
1006                 stats->tx_errors++;
1007                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1008         }
1009         if (cerfl & RCANFD_CERFL_B0ERR) {
1010                 netdev_dbg(ndev, "Bit Error (dominant)\n");
1011                 stats->tx_errors++;
1012                 cf->data[2] |= CAN_ERR_PROT_BIT0;
1013         }
1014         if (cerfl & RCANFD_CERFL_B1ERR) {
1015                 netdev_dbg(ndev, "Bit Error (recessive)\n");
1016                 stats->tx_errors++;
1017                 cf->data[2] |= CAN_ERR_PROT_BIT1;
1018         }
1019         if (cerfl & RCANFD_CERFL_CERR) {
1020                 netdev_dbg(ndev, "CRC Error\n");
1021                 stats->rx_errors++;
1022                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1023         }
1024         if (cerfl & RCANFD_CERFL_AERR) {
1025                 netdev_dbg(ndev, "ACK Error\n");
1026                 stats->tx_errors++;
1027                 cf->can_id |= CAN_ERR_ACK;
1028                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1029         }
1030         if (cerfl & RCANFD_CERFL_FERR) {
1031                 netdev_dbg(ndev, "Form Error\n");
1032                 stats->rx_errors++;
1033                 cf->data[2] |= CAN_ERR_PROT_FORM;
1034         }
1035         if (cerfl & RCANFD_CERFL_SERR) {
1036                 netdev_dbg(ndev, "Stuff Error\n");
1037                 stats->rx_errors++;
1038                 cf->data[2] |= CAN_ERR_PROT_STUFF;
1039         }
1040         if (cerfl & RCANFD_CERFL_ALF) {
1041                 netdev_dbg(ndev, "Arbitration lost Error\n");
1042                 priv->can.can_stats.arbitration_lost++;
1043                 cf->can_id |= CAN_ERR_LOSTARB;
1044                 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1045         }
1046         if (cerfl & RCANFD_CERFL_BLF) {
1047                 netdev_dbg(ndev, "Bus Lock Error\n");
1048                 stats->rx_errors++;
1049                 cf->can_id |= CAN_ERR_BUSERROR;
1050         }
1051         if (cerfl & RCANFD_CERFL_EWF) {
1052                 netdev_dbg(ndev, "Error warning interrupt\n");
1053                 priv->can.state = CAN_STATE_ERROR_WARNING;
1054                 priv->can.can_stats.error_warning++;
1055                 cf->can_id |= CAN_ERR_CRTL;
1056                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1057                         CAN_ERR_CRTL_RX_WARNING;
1058                 cf->data[6] = txerr;
1059                 cf->data[7] = rxerr;
1060         }
1061         if (cerfl & RCANFD_CERFL_EPF) {
1062                 netdev_dbg(ndev, "Error passive interrupt\n");
1063                 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1064                 priv->can.can_stats.error_passive++;
1065                 cf->can_id |= CAN_ERR_CRTL;
1066                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1067                         CAN_ERR_CRTL_RX_PASSIVE;
1068                 cf->data[6] = txerr;
1069                 cf->data[7] = rxerr;
1070         }
1071         if (cerfl & RCANFD_CERFL_BOEF) {
1072                 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1073                 rcar_canfd_tx_failure_cleanup(ndev);
1074                 priv->can.state = CAN_STATE_BUS_OFF;
1075                 priv->can.can_stats.bus_off++;
1076                 can_bus_off(ndev);
1077                 cf->can_id |= CAN_ERR_BUSOFF;
1078         }
1079         if (cerfl & RCANFD_CERFL_OVLF) {
1080                 netdev_dbg(ndev,
1081                            "Overload Frame Transmission error interrupt\n");
1082                 stats->tx_errors++;
1083                 cf->can_id |= CAN_ERR_PROT;
1084                 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1085         }
1086
1087         /* Clear channel error interrupts that are handled */
1088         rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1089                          RCANFD_CERFL_ERR(~cerfl));
1090         netif_rx(skb);
1091 }
1092
1093 static void rcar_canfd_tx_done(struct net_device *ndev)
1094 {
1095         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1096         struct rcar_canfd_global *gpriv = priv->gpriv;
1097         struct net_device_stats *stats = &ndev->stats;
1098         u32 sts;
1099         unsigned long flags;
1100         u32 ch = priv->channel;
1101
1102         do {
1103                 u8 unsent, sent;
1104
1105                 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1106                 stats->tx_packets++;
1107                 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1108
1109                 spin_lock_irqsave(&priv->tx_lock, flags);
1110                 priv->tx_tail++;
1111                 sts = rcar_canfd_read(priv->base,
1112                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1113                 unsent = RCANFD_CFSTS_CFMC(sts);
1114
1115                 /* Wake producer only when there is room */
1116                 if (unsent != RCANFD_FIFO_DEPTH)
1117                         netif_wake_queue(ndev);
1118
1119                 if (priv->tx_head - priv->tx_tail <= unsent) {
1120                         spin_unlock_irqrestore(&priv->tx_lock, flags);
1121                         break;
1122                 }
1123                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1124
1125         } while (1);
1126
1127         /* Clear interrupt */
1128         rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1129                          sts & ~RCANFD_CFSTS_CFTXIF);
1130 }
1131
1132 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1133 {
1134         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1135         struct net_device *ndev = priv->ndev;
1136         u32 gerfl;
1137
1138         /* Handle global error interrupts */
1139         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1140         if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1141                 rcar_canfd_global_error(ndev);
1142 }
1143
1144 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1145 {
1146         struct rcar_canfd_global *gpriv = dev_id;
1147         u32 ch;
1148
1149         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
1150                 rcar_canfd_handle_global_err(gpriv, ch);
1151
1152         return IRQ_HANDLED;
1153 }
1154
1155 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1156 {
1157         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1158         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1159         u32 sts;
1160
1161         /* Handle Rx interrupts */
1162         sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1163         if (likely(sts & RCANFD_RFSTS_RFIF)) {
1164                 if (napi_schedule_prep(&priv->napi)) {
1165                         /* Disable Rx FIFO interrupts */
1166                         rcar_canfd_clear_bit(priv->base,
1167                                              RCANFD_RFCC(gpriv, ridx),
1168                                              RCANFD_RFCC_RFIE);
1169                         __napi_schedule(&priv->napi);
1170                 }
1171         }
1172 }
1173
1174 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1175 {
1176         struct rcar_canfd_global *gpriv = dev_id;
1177         u32 ch;
1178
1179         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
1180                 rcar_canfd_handle_global_receive(gpriv, ch);
1181
1182         return IRQ_HANDLED;
1183 }
1184
1185 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1186 {
1187         struct rcar_canfd_global *gpriv = dev_id;
1188         u32 ch;
1189
1190         /* Global error interrupts still indicate a condition specific
1191          * to a channel. RxFIFO interrupt is a global interrupt.
1192          */
1193         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
1194                 rcar_canfd_handle_global_err(gpriv, ch);
1195                 rcar_canfd_handle_global_receive(gpriv, ch);
1196         }
1197         return IRQ_HANDLED;
1198 }
1199
1200 static void rcar_canfd_state_change(struct net_device *ndev,
1201                                     u16 txerr, u16 rxerr)
1202 {
1203         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1204         struct net_device_stats *stats = &ndev->stats;
1205         enum can_state rx_state, tx_state, state = priv->can.state;
1206         struct can_frame *cf;
1207         struct sk_buff *skb;
1208
1209         /* Handle transition from error to normal states */
1210         if (txerr < 96 && rxerr < 96)
1211                 state = CAN_STATE_ERROR_ACTIVE;
1212         else if (txerr < 128 && rxerr < 128)
1213                 state = CAN_STATE_ERROR_WARNING;
1214
1215         if (state != priv->can.state) {
1216                 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1217                            state, priv->can.state, txerr, rxerr);
1218                 skb = alloc_can_err_skb(ndev, &cf);
1219                 if (!skb) {
1220                         stats->rx_dropped++;
1221                         return;
1222                 }
1223                 tx_state = txerr >= rxerr ? state : 0;
1224                 rx_state = txerr <= rxerr ? state : 0;
1225
1226                 can_change_state(ndev, cf, tx_state, rx_state);
1227                 netif_rx(skb);
1228         }
1229 }
1230
1231 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1232 {
1233         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1234         struct net_device *ndev = priv->ndev;
1235         u32 sts;
1236
1237         /* Handle Tx interrupts */
1238         sts = rcar_canfd_read(priv->base,
1239                               RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1240         if (likely(sts & RCANFD_CFSTS_CFTXIF))
1241                 rcar_canfd_tx_done(ndev);
1242 }
1243
1244 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1245 {
1246         struct rcar_canfd_global *gpriv = dev_id;
1247         u32 ch;
1248
1249         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
1250                 rcar_canfd_handle_channel_tx(gpriv, ch);
1251
1252         return IRQ_HANDLED;
1253 }
1254
1255 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1256 {
1257         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1258         struct net_device *ndev = priv->ndev;
1259         u16 txerr, rxerr;
1260         u32 sts, cerfl;
1261
1262         /* Handle channel error interrupts */
1263         cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1264         sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1265         txerr = RCANFD_CSTS_TECCNT(sts);
1266         rxerr = RCANFD_CSTS_RECCNT(sts);
1267         if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1268                 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1269
1270         /* Handle state change to lower states */
1271         if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1272                      priv->can.state != CAN_STATE_BUS_OFF))
1273                 rcar_canfd_state_change(ndev, txerr, rxerr);
1274 }
1275
1276 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1277 {
1278         struct rcar_canfd_global *gpriv = dev_id;
1279         u32 ch;
1280
1281         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
1282                 rcar_canfd_handle_channel_err(gpriv, ch);
1283
1284         return IRQ_HANDLED;
1285 }
1286
1287 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1288 {
1289         struct rcar_canfd_global *gpriv = dev_id;
1290         u32 ch;
1291
1292         /* Common FIFO is a per channel resource */
1293         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
1294                 rcar_canfd_handle_channel_err(gpriv, ch);
1295                 rcar_canfd_handle_channel_tx(gpriv, ch);
1296         }
1297
1298         return IRQ_HANDLED;
1299 }
1300
1301 static void rcar_canfd_set_bittiming(struct net_device *dev)
1302 {
1303         struct rcar_canfd_channel *priv = netdev_priv(dev);
1304         struct rcar_canfd_global *gpriv = priv->gpriv;
1305         const struct can_bittiming *bt = &priv->can.bittiming;
1306         const struct can_bittiming *dbt = &priv->can.data_bittiming;
1307         u16 brp, sjw, tseg1, tseg2;
1308         u32 cfg;
1309         u32 ch = priv->channel;
1310
1311         /* Nominal bit timing settings */
1312         brp = bt->brp - 1;
1313         sjw = bt->sjw - 1;
1314         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1315         tseg2 = bt->phase_seg2 - 1;
1316
1317         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1318                 /* CAN FD only mode */
1319                 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1320                        RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1321
1322                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1323                 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1324                            brp, sjw, tseg1, tseg2);
1325
1326                 /* Data bit timing settings */
1327                 brp = dbt->brp - 1;
1328                 sjw = dbt->sjw - 1;
1329                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1330                 tseg2 = dbt->phase_seg2 - 1;
1331
1332                 cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1333                        RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1334
1335                 if (is_v3u(gpriv))
1336                         rcar_canfd_write(priv->base, RCANFD_V3U_DCFG(ch), cfg);
1337                 else
1338                         rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1339                 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1340                            brp, sjw, tseg1, tseg2);
1341         } else {
1342                 /* Classical CAN only mode */
1343                 if (is_v3u(gpriv)) {
1344                         cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1345                                RCANFD_NCFG_NBRP(brp) |
1346                                RCANFD_NCFG_NSJW(gpriv, sjw) |
1347                                RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1348                 } else {
1349                         cfg = (RCANFD_CFG_TSEG1(tseg1) |
1350                                RCANFD_CFG_BRP(brp) |
1351                                RCANFD_CFG_SJW(sjw) |
1352                                RCANFD_CFG_TSEG2(tseg2));
1353                 }
1354
1355                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1356                 netdev_dbg(priv->ndev,
1357                            "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1358                            brp, sjw, tseg1, tseg2);
1359         }
1360 }
1361
1362 static int rcar_canfd_start(struct net_device *ndev)
1363 {
1364         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1365         struct rcar_canfd_global *gpriv = priv->gpriv;
1366         int err = -EOPNOTSUPP;
1367         u32 sts, ch = priv->channel;
1368         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1369
1370         rcar_canfd_set_bittiming(ndev);
1371
1372         rcar_canfd_enable_channel_interrupts(priv);
1373
1374         /* Set channel to Operational mode */
1375         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1376                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1377
1378         /* Verify channel mode change */
1379         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1380                                  (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1381         if (err) {
1382                 netdev_err(ndev, "channel %u communication state failed\n", ch);
1383                 goto fail_mode_change;
1384         }
1385
1386         /* Enable Common & Rx FIFO */
1387         rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1388                            RCANFD_CFCC_CFE);
1389         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1390
1391         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1392         return 0;
1393
1394 fail_mode_change:
1395         rcar_canfd_disable_channel_interrupts(priv);
1396         return err;
1397 }
1398
1399 static int rcar_canfd_open(struct net_device *ndev)
1400 {
1401         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1402         struct rcar_canfd_global *gpriv = priv->gpriv;
1403         int err;
1404
1405         /* Peripheral clock is already enabled in probe */
1406         err = clk_prepare_enable(gpriv->can_clk);
1407         if (err) {
1408                 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1409                 goto out_clock;
1410         }
1411
1412         err = open_candev(ndev);
1413         if (err) {
1414                 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1415                 goto out_can_clock;
1416         }
1417
1418         napi_enable(&priv->napi);
1419         err = rcar_canfd_start(ndev);
1420         if (err)
1421                 goto out_close;
1422         netif_start_queue(ndev);
1423         return 0;
1424 out_close:
1425         napi_disable(&priv->napi);
1426         close_candev(ndev);
1427 out_can_clock:
1428         clk_disable_unprepare(gpriv->can_clk);
1429 out_clock:
1430         return err;
1431 }
1432
1433 static void rcar_canfd_stop(struct net_device *ndev)
1434 {
1435         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1436         struct rcar_canfd_global *gpriv = priv->gpriv;
1437         int err;
1438         u32 sts, ch = priv->channel;
1439         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1440
1441         /* Transition to channel reset mode  */
1442         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1443                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1444
1445         /* Check Channel reset mode */
1446         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1447                                  (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1448         if (err)
1449                 netdev_err(ndev, "channel %u reset failed\n", ch);
1450
1451         rcar_canfd_disable_channel_interrupts(priv);
1452
1453         /* Disable Common & Rx FIFO */
1454         rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1455                              RCANFD_CFCC_CFE);
1456         rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1457
1458         /* Set the state as STOPPED */
1459         priv->can.state = CAN_STATE_STOPPED;
1460 }
1461
1462 static int rcar_canfd_close(struct net_device *ndev)
1463 {
1464         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1465         struct rcar_canfd_global *gpriv = priv->gpriv;
1466
1467         netif_stop_queue(ndev);
1468         rcar_canfd_stop(ndev);
1469         napi_disable(&priv->napi);
1470         clk_disable_unprepare(gpriv->can_clk);
1471         close_candev(ndev);
1472         return 0;
1473 }
1474
1475 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1476                                          struct net_device *ndev)
1477 {
1478         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1479         struct rcar_canfd_global *gpriv = priv->gpriv;
1480         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1481         u32 sts = 0, id, dlc;
1482         unsigned long flags;
1483         u32 ch = priv->channel;
1484
1485         if (can_dropped_invalid_skb(ndev, skb))
1486                 return NETDEV_TX_OK;
1487
1488         if (cf->can_id & CAN_EFF_FLAG) {
1489                 id = cf->can_id & CAN_EFF_MASK;
1490                 id |= RCANFD_CFID_CFIDE;
1491         } else {
1492                 id = cf->can_id & CAN_SFF_MASK;
1493         }
1494
1495         if (cf->can_id & CAN_RTR_FLAG)
1496                 id |= RCANFD_CFID_CFRTR;
1497
1498         dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1499
1500         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_v3u(gpriv)) {
1501                 rcar_canfd_write(priv->base,
1502                                  RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1503                 rcar_canfd_write(priv->base,
1504                                  RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1505
1506                 if (can_is_canfd_skb(skb)) {
1507                         /* CAN FD frame format */
1508                         sts |= RCANFD_CFFDCSTS_CFFDF;
1509                         if (cf->flags & CANFD_BRS)
1510                                 sts |= RCANFD_CFFDCSTS_CFBRS;
1511
1512                         if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1513                                 sts |= RCANFD_CFFDCSTS_CFESI;
1514                 }
1515
1516                 rcar_canfd_write(priv->base,
1517                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1518
1519                 rcar_canfd_put_data(priv, cf,
1520                                     RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1521         } else {
1522                 rcar_canfd_write(priv->base,
1523                                  RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1524                 rcar_canfd_write(priv->base,
1525                                  RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1526                 rcar_canfd_put_data(priv, cf,
1527                                     RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1528         }
1529
1530         can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1531
1532         spin_lock_irqsave(&priv->tx_lock, flags);
1533         priv->tx_head++;
1534
1535         /* Stop the queue if we've filled all FIFO entries */
1536         if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1537                 netif_stop_queue(ndev);
1538
1539         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1540          * pointer for the Common FIFO
1541          */
1542         rcar_canfd_write(priv->base,
1543                          RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1544
1545         spin_unlock_irqrestore(&priv->tx_lock, flags);
1546         return NETDEV_TX_OK;
1547 }
1548
1549 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1550 {
1551         struct net_device_stats *stats = &priv->ndev->stats;
1552         struct rcar_canfd_global *gpriv = priv->gpriv;
1553         struct canfd_frame *cf;
1554         struct sk_buff *skb;
1555         u32 sts = 0, id, dlc;
1556         u32 ch = priv->channel;
1557         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1558
1559         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_v3u(gpriv)) {
1560                 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1561                 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1562
1563                 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1564
1565                 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1566                     sts & RCANFD_RFFDSTS_RFFDF)
1567                         skb = alloc_canfd_skb(priv->ndev, &cf);
1568                 else
1569                         skb = alloc_can_skb(priv->ndev,
1570                                             (struct can_frame **)&cf);
1571         } else {
1572                 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1573                 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1574                 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1575         }
1576
1577         if (!skb) {
1578                 stats->rx_dropped++;
1579                 return;
1580         }
1581
1582         if (id & RCANFD_RFID_RFIDE)
1583                 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1584         else
1585                 cf->can_id = id & CAN_SFF_MASK;
1586
1587         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1588                 if (sts & RCANFD_RFFDSTS_RFFDF)
1589                         cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1590                 else
1591                         cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1592
1593                 if (sts & RCANFD_RFFDSTS_RFESI) {
1594                         cf->flags |= CANFD_ESI;
1595                         netdev_dbg(priv->ndev, "ESI Error\n");
1596                 }
1597
1598                 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1599                         cf->can_id |= CAN_RTR_FLAG;
1600                 } else {
1601                         if (sts & RCANFD_RFFDSTS_RFBRS)
1602                                 cf->flags |= CANFD_BRS;
1603
1604                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1605                 }
1606         } else {
1607                 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1608                 if (id & RCANFD_RFID_RFRTR)
1609                         cf->can_id |= CAN_RTR_FLAG;
1610                 else if (is_v3u(gpriv))
1611                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1612                 else
1613                         rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1614         }
1615
1616         /* Write 0xff to RFPC to increment the CPU-side
1617          * pointer of the Rx FIFO
1618          */
1619         rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1620
1621         if (!(cf->can_id & CAN_RTR_FLAG))
1622                 stats->rx_bytes += cf->len;
1623         stats->rx_packets++;
1624         netif_receive_skb(skb);
1625 }
1626
1627 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1628 {
1629         struct rcar_canfd_channel *priv =
1630                 container_of(napi, struct rcar_canfd_channel, napi);
1631         struct rcar_canfd_global *gpriv = priv->gpriv;
1632         int num_pkts;
1633         u32 sts;
1634         u32 ch = priv->channel;
1635         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1636
1637         for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1638                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1639                 /* Check FIFO empty condition */
1640                 if (sts & RCANFD_RFSTS_RFEMP)
1641                         break;
1642
1643                 rcar_canfd_rx_pkt(priv);
1644
1645                 /* Clear interrupt bit */
1646                 if (sts & RCANFD_RFSTS_RFIF)
1647                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1648                                          sts & ~RCANFD_RFSTS_RFIF);
1649         }
1650
1651         /* All packets processed */
1652         if (num_pkts < quota) {
1653                 if (napi_complete_done(napi, num_pkts)) {
1654                         /* Enable Rx FIFO interrupts */
1655                         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1656                                            RCANFD_RFCC_RFIE);
1657                 }
1658         }
1659         return num_pkts;
1660 }
1661
1662 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1663 {
1664         int err;
1665
1666         switch (mode) {
1667         case CAN_MODE_START:
1668                 err = rcar_canfd_start(ndev);
1669                 if (err)
1670                         return err;
1671                 netif_wake_queue(ndev);
1672                 return 0;
1673         default:
1674                 return -EOPNOTSUPP;
1675         }
1676 }
1677
1678 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1679                                        struct can_berr_counter *bec)
1680 {
1681         struct rcar_canfd_channel *priv = netdev_priv(dev);
1682         u32 val, ch = priv->channel;
1683
1684         /* Peripheral clock is already enabled in probe */
1685         val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1686         bec->txerr = RCANFD_CSTS_TECCNT(val);
1687         bec->rxerr = RCANFD_CSTS_RECCNT(val);
1688         return 0;
1689 }
1690
1691 static const struct net_device_ops rcar_canfd_netdev_ops = {
1692         .ndo_open = rcar_canfd_open,
1693         .ndo_stop = rcar_canfd_close,
1694         .ndo_start_xmit = rcar_canfd_start_xmit,
1695         .ndo_change_mtu = can_change_mtu,
1696 };
1697
1698 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1699                                     u32 fcan_freq)
1700 {
1701         struct platform_device *pdev = gpriv->pdev;
1702         struct rcar_canfd_channel *priv;
1703         struct net_device *ndev;
1704         int err = -ENODEV;
1705
1706         ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1707         if (!ndev) {
1708                 dev_err(&pdev->dev, "alloc_candev() failed\n");
1709                 return -ENOMEM;
1710         }
1711         priv = netdev_priv(ndev);
1712
1713         ndev->netdev_ops = &rcar_canfd_netdev_ops;
1714         ndev->flags |= IFF_ECHO;
1715         priv->ndev = ndev;
1716         priv->base = gpriv->base;
1717         priv->channel = ch;
1718         priv->can.clock.freq = fcan_freq;
1719         dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1720
1721         if (gpriv->chip_id == RENESAS_RZG2L) {
1722                 char *irq_name;
1723                 int err_irq;
1724                 int tx_irq;
1725
1726                 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1727                 if (err_irq < 0) {
1728                         err = err_irq;
1729                         goto fail;
1730                 }
1731
1732                 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1733                 if (tx_irq < 0) {
1734                         err = tx_irq;
1735                         goto fail;
1736                 }
1737
1738                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1739                                           "canfd.ch%d_err", ch);
1740                 if (!irq_name) {
1741                         err = -ENOMEM;
1742                         goto fail;
1743                 }
1744                 err = devm_request_irq(&pdev->dev, err_irq,
1745                                        rcar_canfd_channel_err_interrupt, 0,
1746                                        irq_name, gpriv);
1747                 if (err) {
1748                         dev_err(&pdev->dev, "devm_request_irq CH Err(%d) failed, error %d\n",
1749                                 err_irq, err);
1750                         goto fail;
1751                 }
1752                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1753                                           "canfd.ch%d_trx", ch);
1754                 if (!irq_name) {
1755                         err = -ENOMEM;
1756                         goto fail;
1757                 }
1758                 err = devm_request_irq(&pdev->dev, tx_irq,
1759                                        rcar_canfd_channel_tx_interrupt, 0,
1760                                        irq_name, gpriv);
1761                 if (err) {
1762                         dev_err(&pdev->dev, "devm_request_irq Tx (%d) failed, error %d\n",
1763                                 tx_irq, err);
1764                         goto fail;
1765                 }
1766         }
1767
1768         if (gpriv->fdmode) {
1769                 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1770                 priv->can.data_bittiming_const =
1771                         &rcar_canfd_data_bittiming_const;
1772
1773                 /* Controller starts in CAN FD only mode */
1774                 err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1775                 if (err)
1776                         goto fail;
1777                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1778         } else {
1779                 /* Controller starts in Classical CAN only mode */
1780                 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1781                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1782         }
1783
1784         priv->can.do_set_mode = rcar_canfd_do_set_mode;
1785         priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1786         priv->gpriv = gpriv;
1787         SET_NETDEV_DEV(ndev, &pdev->dev);
1788
1789         netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1790                               RCANFD_NAPI_WEIGHT);
1791         spin_lock_init(&priv->tx_lock);
1792         gpriv->ch[priv->channel] = priv;
1793         err = register_candev(ndev);
1794         if (err) {
1795                 dev_err(&pdev->dev,
1796                         "register_candev() failed, error %d\n", err);
1797                 goto fail_candev;
1798         }
1799         dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1800         return 0;
1801
1802 fail_candev:
1803         netif_napi_del(&priv->napi);
1804 fail:
1805         free_candev(ndev);
1806         return err;
1807 }
1808
1809 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1810 {
1811         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1812
1813         if (priv) {
1814                 unregister_candev(priv->ndev);
1815                 netif_napi_del(&priv->napi);
1816                 free_candev(priv->ndev);
1817         }
1818 }
1819
1820 static int rcar_canfd_probe(struct platform_device *pdev)
1821 {
1822         void __iomem *addr;
1823         u32 sts, ch, fcan_freq;
1824         struct rcar_canfd_global *gpriv;
1825         struct device_node *of_child;
1826         unsigned long channels_mask = 0;
1827         int err, ch_irq, g_irq;
1828         int g_err_irq, g_recc_irq;
1829         bool fdmode = true;                     /* CAN FD only mode - default */
1830         enum rcanfd_chip_id chip_id;
1831         int max_channels;
1832         char name[9] = "channelX";
1833         int i;
1834
1835         chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1836         max_channels = chip_id == RENESAS_R8A779A0 ? 8 : 2;
1837
1838         if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1839                 fdmode = false;                 /* Classical CAN only mode */
1840
1841         for (i = 0; i < max_channels; ++i) {
1842                 name[7] = '0' + i;
1843                 of_child = of_get_child_by_name(pdev->dev.of_node, name);
1844                 if (of_child && of_device_is_available(of_child))
1845                         channels_mask |= BIT(i);
1846                 of_node_put(of_child);
1847         }
1848
1849         if (chip_id != RENESAS_RZG2L) {
1850                 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1851                 if (ch_irq < 0) {
1852                         /* For backward compatibility get irq by index */
1853                         ch_irq = platform_get_irq(pdev, 0);
1854                         if (ch_irq < 0)
1855                                 return ch_irq;
1856                 }
1857
1858                 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1859                 if (g_irq < 0) {
1860                         /* For backward compatibility get irq by index */
1861                         g_irq = platform_get_irq(pdev, 1);
1862                         if (g_irq < 0)
1863                                 return g_irq;
1864                 }
1865         } else {
1866                 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1867                 if (g_err_irq < 0)
1868                         return g_err_irq;
1869
1870                 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1871                 if (g_recc_irq < 0)
1872                         return g_recc_irq;
1873         }
1874
1875         /* Global controller context */
1876         gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1877         if (!gpriv) {
1878                 err = -ENOMEM;
1879                 goto fail_dev;
1880         }
1881         gpriv->pdev = pdev;
1882         gpriv->channels_mask = channels_mask;
1883         gpriv->fdmode = fdmode;
1884         gpriv->chip_id = chip_id;
1885         gpriv->max_channels = max_channels;
1886
1887         if (gpriv->chip_id == RENESAS_RZG2L) {
1888                 gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
1889                 if (IS_ERR(gpriv->rstc1))
1890                         return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
1891                                              "failed to get rstp_n\n");
1892
1893                 gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
1894                 if (IS_ERR(gpriv->rstc2))
1895                         return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
1896                                              "failed to get rstc_n\n");
1897         }
1898
1899         /* Peripheral clock */
1900         gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1901         if (IS_ERR(gpriv->clkp)) {
1902                 err = PTR_ERR(gpriv->clkp);
1903                 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1904                         err);
1905                 goto fail_dev;
1906         }
1907
1908         /* fCAN clock: Pick External clock. If not available fallback to
1909          * CANFD clock
1910          */
1911         gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1912         if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1913                 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1914                 if (IS_ERR(gpriv->can_clk)) {
1915                         err = PTR_ERR(gpriv->can_clk);
1916                         dev_err(&pdev->dev,
1917                                 "cannot get canfd clock, error %d\n", err);
1918                         goto fail_dev;
1919                 }
1920                 gpriv->fcan = RCANFD_CANFDCLK;
1921
1922         } else {
1923                 gpriv->fcan = RCANFD_EXTCLK;
1924         }
1925         fcan_freq = clk_get_rate(gpriv->can_clk);
1926
1927         if (gpriv->fcan == RCANFD_CANFDCLK && gpriv->chip_id != RENESAS_RZG2L)
1928                 /* CANFD clock is further divided by (1/2) within the IP */
1929                 fcan_freq /= 2;
1930
1931         addr = devm_platform_ioremap_resource(pdev, 0);
1932         if (IS_ERR(addr)) {
1933                 err = PTR_ERR(addr);
1934                 goto fail_dev;
1935         }
1936         gpriv->base = addr;
1937
1938         /* Request IRQ that's common for both channels */
1939         if (gpriv->chip_id != RENESAS_RZG2L) {
1940                 err = devm_request_irq(&pdev->dev, ch_irq,
1941                                        rcar_canfd_channel_interrupt, 0,
1942                                        "canfd.ch_int", gpriv);
1943                 if (err) {
1944                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1945                                 ch_irq, err);
1946                         goto fail_dev;
1947                 }
1948
1949                 err = devm_request_irq(&pdev->dev, g_irq,
1950                                        rcar_canfd_global_interrupt, 0,
1951                                        "canfd.g_int", gpriv);
1952                 if (err) {
1953                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1954                                 g_irq, err);
1955                         goto fail_dev;
1956                 }
1957         } else {
1958                 err = devm_request_irq(&pdev->dev, g_recc_irq,
1959                                        rcar_canfd_global_receive_fifo_interrupt, 0,
1960                                        "canfd.g_recc", gpriv);
1961
1962                 if (err) {
1963                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1964                                 g_recc_irq, err);
1965                         goto fail_dev;
1966                 }
1967
1968                 err = devm_request_irq(&pdev->dev, g_err_irq,
1969                                        rcar_canfd_global_err_interrupt, 0,
1970                                        "canfd.g_err", gpriv);
1971                 if (err) {
1972                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1973                                 g_err_irq, err);
1974                         goto fail_dev;
1975                 }
1976         }
1977
1978         err = reset_control_reset(gpriv->rstc1);
1979         if (err)
1980                 goto fail_dev;
1981         err = reset_control_reset(gpriv->rstc2);
1982         if (err) {
1983                 reset_control_assert(gpriv->rstc1);
1984                 goto fail_dev;
1985         }
1986
1987         /* Enable peripheral clock for register access */
1988         err = clk_prepare_enable(gpriv->clkp);
1989         if (err) {
1990                 dev_err(&pdev->dev,
1991                         "failed to enable peripheral clock, error %d\n", err);
1992                 goto fail_reset;
1993         }
1994
1995         err = rcar_canfd_reset_controller(gpriv);
1996         if (err) {
1997                 dev_err(&pdev->dev, "reset controller failed\n");
1998                 goto fail_clk;
1999         }
2000
2001         /* Controller in Global reset & Channel reset mode */
2002         rcar_canfd_configure_controller(gpriv);
2003
2004         /* Configure per channel attributes */
2005         for_each_set_bit(ch, &gpriv->channels_mask, max_channels) {
2006                 /* Configure Channel's Rx fifo */
2007                 rcar_canfd_configure_rx(gpriv, ch);
2008
2009                 /* Configure Channel's Tx (Common) fifo */
2010                 rcar_canfd_configure_tx(gpriv, ch);
2011
2012                 /* Configure receive rules */
2013                 rcar_canfd_configure_afl_rules(gpriv, ch);
2014         }
2015
2016         /* Configure common interrupts */
2017         rcar_canfd_enable_global_interrupts(gpriv);
2018
2019         /* Start Global operation mode */
2020         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2021                               RCANFD_GCTR_GMDC_GOPM);
2022
2023         /* Verify mode change */
2024         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2025                                  !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2026         if (err) {
2027                 dev_err(&pdev->dev, "global operational mode failed\n");
2028                 goto fail_mode;
2029         }
2030
2031         for_each_set_bit(ch, &gpriv->channels_mask, max_channels) {
2032                 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
2033                 if (err)
2034                         goto fail_channel;
2035         }
2036
2037         platform_set_drvdata(pdev, gpriv);
2038         dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
2039                  gpriv->fcan, gpriv->fdmode);
2040         return 0;
2041
2042 fail_channel:
2043         for_each_set_bit(ch, &gpriv->channels_mask, max_channels)
2044                 rcar_canfd_channel_remove(gpriv, ch);
2045 fail_mode:
2046         rcar_canfd_disable_global_interrupts(gpriv);
2047 fail_clk:
2048         clk_disable_unprepare(gpriv->clkp);
2049 fail_reset:
2050         reset_control_assert(gpriv->rstc1);
2051         reset_control_assert(gpriv->rstc2);
2052 fail_dev:
2053         return err;
2054 }
2055
2056 static int rcar_canfd_remove(struct platform_device *pdev)
2057 {
2058         struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2059         u32 ch;
2060
2061         rcar_canfd_reset_controller(gpriv);
2062         rcar_canfd_disable_global_interrupts(gpriv);
2063
2064         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
2065                 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2066                 rcar_canfd_channel_remove(gpriv, ch);
2067         }
2068
2069         /* Enter global sleep mode */
2070         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2071         clk_disable_unprepare(gpriv->clkp);
2072         reset_control_assert(gpriv->rstc1);
2073         reset_control_assert(gpriv->rstc2);
2074
2075         return 0;
2076 }
2077
2078 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2079 {
2080         return 0;
2081 }
2082
2083 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2084 {
2085         return 0;
2086 }
2087
2088 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2089                          rcar_canfd_resume);
2090
2091 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2092         { .compatible = "renesas,rcar-gen3-canfd", .data = (void *)RENESAS_RCAR_GEN3 },
2093         { .compatible = "renesas,rzg2l-canfd", .data = (void *)RENESAS_RZG2L },
2094         { .compatible = "renesas,r8a779a0-canfd", .data = (void *)RENESAS_R8A779A0 },
2095         { }
2096 };
2097
2098 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2099
2100 static struct platform_driver rcar_canfd_driver = {
2101         .driver = {
2102                 .name = RCANFD_DRV_NAME,
2103                 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2104                 .pm = &rcar_canfd_pm_ops,
2105         },
2106         .probe = rcar_canfd_probe,
2107         .remove = rcar_canfd_remove,
2108 };
2109
2110 module_platform_driver(rcar_canfd_driver);
2111
2112 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2113 MODULE_LICENSE("GPL");
2114 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2115 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);