drivers/net/can/ipms_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2021 StarFive, Inc <jenny.zhang@starfivetech.com>
   4  *
   5  * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
   6  * CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER
   7  * FOR THEM TO SAVE TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE
   8  * FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
   9  * CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE
  10  * BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION
  11  * WITH THEIR PRODUCTS.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/reset.h>
  16 #include <linux/errno.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/skbuff.h>
  26 #include <linux/string.h>
  27 #include <linux/types.h>
  28 #include <linux/can/dev.h>
  29 #include <linux/can/error.h>
  30 #include <linux/can/led.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of_device.h>
  33
  34 #define DRIVER_NAME "ipms_canfd"
  35
  36 /* CAN registers set */
  37 enum canfd_device_reg {
  38         CANFD_RUBF_OFFSET           =   0x00,   /* Receive Buffer Registers 0x00-0x4f */
  39         CANFD_RUBF_ID_OFFSET        =   0x00,
  40         CANFD_RBUF_CTL_OFFSET       =   0x04,
  41         CANFD_RBUF_DATA_OFFSET      =   0x08,
  42         CANFD_TBUF_OFFSET           =   0x50,   /* Transmit Buffer Registers 0x50-0x97 */
  43         CANFD_TBUF_ID_OFFSET        =   0x50,
  44         CANFD_TBUF_CTL_OFFSET       =   0x54,
  45         CANFD_TBUF_DATA_OFFSET      =   0x58,
  46         CANFD_TTS_OFFSET            =   0x98,   /* Transmission Time Stamp 0x98-0x9f */
  47         CANFD_CFG_STAT_OFFSET       =   0xa0,
  48         CANFD_TCMD_OFFSET           =   0xa1,
  49         CANFD_TCTRL_OFFSET          =   0xa2,
  50         CANFD_RCTRL_OFFSET          =   0xa3,
  51         CANFD_RTIE_OFFSET           =   0xa4,
  52         CANFD_RTIF_OFFSET           =   0xa5,
  53         CANFD_ERRINT_OFFSET         =   0xa6,
  54         CANFD_LIMIT_OFFSET          =   0xa7,
  55         CANFD_S_SEG_1_OFFSET        =   0xa8,
  56         CANFD_S_SEG_2_OFFSET        =   0xa9,
  57         CANFD_S_SJW_OFFSET          =   0xaa,
  58         CANFD_S_PRESC_OFFSET        =   0xab,
  59         CANFD_F_SEG_1_OFFSET        =   0xac,
  60         CANFD_F_SEG_2_OFFSET        =   0xad,
  61         CANFD_F_SJW_OFFSET          =   0xae,
  62         CANFD_F_PRESC_OFFSET        =   0xaf,
  63         CANFD_EALCAP_OFFSET         =   0xb0,
  64         CANFD_RECNT_OFFSET          =   0xb2,
  65         CANFD_TECNT_OFFSET          =   0xb3,
  66 };
  67
  68 enum canfd_reg_bitchange {
  69         CAN_FD_SET_RST_MASK         =   0x80,   /* Set Reset Bit */
  70         CAN_FD_OFF_RST_MASK         =   0x7f,   /* Reset Off Bit */
  71         CAN_FD_SET_FULLCAN_MASK     =   0x10,   /* set TTTBM as 1->full TTCAN mode */
  72         CAN_FD_OFF_FULLCAN_MASK     =   0xef,   /* set TTTBM as 0->separate PTB and STB mode */
  73         CAN_FD_SET_FIFO_MASK        =   0x20,   /* set TSMODE as 1->FIFO mode */
  74         CAN_FD_OFF_FIFO_MASK        =   0xdf,   /* set TSMODE as 0->Priority mode */
  75         CAN_FD_SET_TSONE_MASK       =   0x04,
  76         CAN_FD_OFF_TSONE_MASK       =   0xfb,
  77         CAN_FD_SET_TSALL_MASK       =   0x02,
  78         CAN_FD_OFF_TSALL_MASK       =   0xfd,
  79         CAN_FD_LBMEMOD_MASK         =   0x40,   /* set loop back mode, external */
  80         CAN_FD_LBMIMOD_MASK         =   0x20,   /* set loopback internal mode */
  81         CAN_FD_SET_BUSOFF_MASK      =   0x01,
  82         CAN_FD_OFF_BUSOFF_MASK      =   0xfe,
  83         CAN_FD_SET_TTSEN_MASK       =   0x80,   /* set ttsen, tts update enable */
  84         CAN_FD_SET_BRS_MASK         =   0x10,   /* can fd Bit Rate Switch mask */
  85         CAN_FD_OFF_BRS_MASK         =   0xef,
  86         CAN_FD_SET_EDL_MASK         =   0x20,   /* Extended Data Length */
  87         CAN_FD_OFF_EDL_MASK         =   0xdf,
  88         CAN_FD_SET_DLC_MASK         =   0x0f,
  89         CAN_FD_SET_TENEXT_MASK      =   0x40,
  90         CAN_FD_SET_IDE_MASK         =   0x80,
  91         CAN_FD_OFF_IDE_MASK         =   0x7f,
  92         CAN_FD_SET_RTR_MASK         =   0x40,
  93         CAN_FD_OFF_RTR_MASK         =   0xbf,
  94         CAN_FD_INTR_ALL_MASK        =   0xff,   /* all interrupts enable mask */
  95         CAN_FD_SET_RIE_MASK         =   0x80,
  96         CAN_FD_OFF_RIE_MASK         =   0x7f,
  97         CAN_FD_SET_RFIE_MASK        =   0x20,
  98         CAN_FD_OFF_RFIE_MASK        =   0xdf,
  99         CAN_FD_SET_RAFIE_MASK       =   0x10,
 100         CAN_FD_OFF_RAFIE_MASK       =   0xef,
 101         CAN_FD_SET_EIE_MASK         =   0x02,
 102         CAN_FD_OFF_EIE_MASK         =   0xfd,
 103         CAN_FD_TASCTIVE_MASK        =   0x02,
 104         CAN_FD_RASCTIVE_MASK        =   0x04,
 105         CAN_FD_SET_TBSEL_MASK       =   0x80,   /* message writen in STB */
 106         CAN_FD_OFF_TBSEL_MASK       =   0x7f,   /* message writen in PTB */
 107         CAN_FD_SET_STBY_MASK        =   0x20,
 108         CAN_FD_OFF_STBY_MASK        =   0xdf,
 109         CAN_FD_SET_TPE_MASK         =   0x10,   /* Transmit primary enable */
 110         CAN_FD_SET_TPA_MASK         =   0x08,
 111         CAN_FD_SET_SACK_MASK        =   0x80,
 112         CAN_FD_SET_RREL_MASK        =   0x10,
 113         CAN_FD_RSTAT_NOT_EMPTY_MASK =   0x03,
 114         CAN_FD_SET_RIF_MASK         =   0x80,
 115         CAN_FD_OFF_RIF_MASK         =   0x7f,
 116         CAN_FD_SET_RAFIF_MASK       =   0x10,
 117         CAN_FD_SET_RFIF_MASK        =   0x20,
 118         CAN_FD_SET_TPIF_MASK        =   0x08,   /* Transmission Primary Interrupt Flag */
 119         CAN_FD_SET_TSIF_MASK        =   0x04,
 120         CAN_FD_SET_EIF_MASK         =   0x02,
 121         CAN_FD_SET_AIF_MASK         =   0x01,
 122         CAN_FD_SET_EWARN_MASK       =   0x80,
 123         CAN_FD_SET_EPASS_MASK       =   0x40,
 124         CAN_FD_SET_EPIE_MASK        =   0x20,
 125         CAN_FD_SET_EPIF_MASK        =   0x10,
 126         CAN_FD_SET_ALIE_MASK        =   0x08,
 127         CAN_FD_SET_ALIF_MASK        =   0x04,
 128         CAN_FD_SET_BEIE_MASK        =   0x02,
 129         CAN_FD_SET_BEIF_MASK        =   0x01,
 130         CAN_FD_OFF_EPIE_MASK        =   0xdf,
 131         CAN_FD_OFF_BEIE_MASK        =   0xfd,
 132         CAN_FD_SET_AFWL_MASK        =   0x40,
 133         CAN_FD_SET_EWL_MASK         =   0x0b,
 134         CAN_FD_SET_KOER_MASK        =   0xe0,
 135         CAN_FD_SET_BIT_ERROR_MASK   =   0x20,
 136         CAN_FD_SET_FORM_ERROR_MASK  =   0x40,
 137         CAN_FD_SET_STUFF_ERROR_MASK =   0x60,
 138         CAN_FD_SET_ACK_ERROR_MASK   =   0x80,
 139         CAN_FD_SET_CRC_ERROR_MASK   =   0xa0,
 140         CAN_FD_SET_OTH_ERROR_MASK   =   0xc0,
 141 };
 142
 143 /* seg1,seg2,sjw,prescaler all have 8 bits */
 144 #define BITS_OF_BITTIMING_REG           8
 145
 146 /* in can_bittiming strucure every field has 32 bits---->u32 */
 147 #define FBITS_IN_BITTIMING_STR          32
 148 #define SEG_1_SHIFT                     0
 149 #define SEG_2_SHIFT                     8
 150 #define SJW_SHIFT                       16
 151 #define PRESC_SHIFT                     24
 152
 153 /* TTSEN bit used for 32 bit register read or write */
 154 #define TTSEN_8_32_SHIFT                24
 155 #define RTR_32_8_SHIFT                  24
 156
 157 /* transmit mode */
 158 #define XMIT_FULL                       0
 159 #define XMIT_SEP_FIFO                   1
 160 #define XMIT_SEP_PRIO                   2
 161 #define XMIT_PTB_MODE                   3
 162
 163 struct ipms_canfd_priv {
 164         struct can_priv can;
 165         struct napi_struct napi;
 166         struct device *dev;
 167         void __iomem *reg_base;
 168         void __iomem *syscon_base;
 169         u32 (*read_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg);
 170         void (*write_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg, u32 val);
 171         struct clk *can_clk;
 172         unsigned int tx_mode;
 173         struct clk_bulk_data *clks;
 174         int nr_clks;
 175         struct reset_control_bulk_data *resets;
 176         int nr_rstcs;
 177         unsigned int syscon_offset;
 178         unsigned int syscon_mask;
 179         bool enable_canfd;
 180 };
 181
 182 static struct can_bittiming_const canfd_bittiming_const = {
 183         .name = DRIVER_NAME,
 184         .tseg1_min = 2,
 185         .tseg1_max = 17,
 186         .tseg2_min = 1,
 187         .tseg2_max = 8,
 188         .sjw_max = 8,
 189         .brp_min = 1,
 190         .brp_max = 512,
 191         .brp_inc = 1,
 192
 193 };
 194
 195 static struct can_bittiming_const canfd_data_bittiming_const = {
 196         .name = DRIVER_NAME,
 197         .tseg1_min = 2,
 198         .tseg1_max = 65,
 199         .tseg2_min = 1,
 200         .tseg2_max = 8,
 201         .sjw_max = 16,
 202         .brp_min = 1,
 203         .brp_max = 512,
 204         .brp_inc = 1,
 205 };
 206
 207 struct reset_control_bulk_data can_resets[] = {
 208         { .id = "rst_apb" },
 209         { .id = "rst_core" },
 210         { .id = "rst_timer" },
 211 };
 212
 213 struct clk_bulk_data can_clks[] = {
 214         { .id = "apb_clk" },
 215         { .id = "core_clk" },
 216         { .id = "timer_clk" },
 217 };
 218
 219 static void canfd_write_reg_le(const struct ipms_canfd_priv *priv,
 220                                 enum canfd_device_reg reg, u32 val)
 221 {
 222         iowrite32(val, priv->reg_base + reg);
 223 }
 224
 225 static u32 canfd_read_reg_le(const struct ipms_canfd_priv *priv,
 226                                 enum canfd_device_reg reg)
 227 {
 228         return ioread32(priv->reg_base + reg);
 229 }
 230
 231 static inline unsigned char can_ioread8(const void  *addr)
 232 {
 233         void  *addr_down;
 234         union val {
 235                 u8 val_8[4];
 236                 u32 val_32;
 237         } val;
 238         u32 offset = 0;
 239
 240         addr_down = (void  *)ALIGN_DOWN((unsigned long)addr, 4);
 241         offset = addr - addr_down;
 242         val.val_32 = ioread32(addr_down);
 243         return val.val_8[offset];
 244 }
 245
 246 static inline void can_iowrite8(unsigned char value, void  *addr)
 247 {
 248         void  *addr_down;
 249         union val {
 250                 u8 val_8[4];
 251                 u32 val_32;
 252         } val;
 253         u8 offset = 0;
 254
 255         addr_down = (void *)ALIGN_DOWN((unsigned long)addr, 4);
 256         offset = addr - addr_down;
 257         val.val_32 = ioread32(addr_down);
 258         val.val_8[offset] = value;
 259         iowrite32(val.val_32, addr_down);
 260 }
 261
 262 static void canfd_reigister_set_bit(const struct ipms_canfd_priv *priv,
 263                                         enum canfd_device_reg reg,
 264                                         enum canfd_reg_bitchange set_mask)
 265 {
 266         void  *addr_down;
 267         union val {
 268                 u8 val_8[4];
 269                 u32 val_32;
 270         } val;
 271         u8 offset = 0;
 272
 273         addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
 274         offset = (priv->reg_base + reg) - addr_down;
 275         val.val_32 = ioread32(addr_down);
 276         val.val_8[offset] |= set_mask;
 277         iowrite32(val.val_32, addr_down);
 278 }
 279
 280 static void canfd_reigister_off_bit(const struct ipms_canfd_priv *priv,
 281                                         enum canfd_device_reg reg,
 282                                         enum canfd_reg_bitchange set_mask)
 283 {
 284         void  *addr_down;
 285         union val {
 286                 u8 val_8[4];
 287                 u32 val_32;
 288         } val;
 289         u8 offset = 0;
 290
 291         addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
 292         offset = (priv->reg_base + reg) - addr_down;
 293         val.val_32 = ioread32(addr_down);
 294         val.val_8[offset] &= set_mask;
 295         iowrite32(val.val_32, addr_down);
 296 }
 297
 298 static int canfd_device_driver_bittime_configuration(struct net_device *ndev)
 299 {
 300         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 301         struct can_bittiming *bt = &priv->can.bittiming;
 302         struct can_bittiming *dbt = &priv->can.data_bittiming;
 303         u32 reset_test, bittiming_temp, dat_bittiming;
 304
 305         reset_test = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 306
 307         if (!(reset_test & CAN_FD_SET_RST_MASK)) {
 308                 netdev_alert(ndev, "Not in reset mode, cannot set bit timing\n");
 309                 return -EPERM;
 310         }
 311
 312         bittiming_temp = ((bt->phase_seg1 + bt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
 313                          ((bt->phase_seg2 - 1) << SEG_2_SHIFT) |
 314                          ((bt->sjw - 1) << SJW_SHIFT) |
 315                          ((bt->brp - 1) << PRESC_SHIFT);
 316
 317         /* Check the bittime parameter */
 318         if ((((int)(bt->phase_seg1 + bt->prop_seg + 1) - 2) < 0) ||
 319                 (((int)(bt->phase_seg2) - 1) < 0) ||
 320                 (((int)(bt->sjw) - 1) < 0) ||
 321                 (((int)(bt->brp) - 1) < 0))
 322                 return -EINVAL;
 323
 324         priv->write_reg(priv, CANFD_S_SEG_1_OFFSET, bittiming_temp);
 325
 326         if (priv->enable_canfd) {
 327                 dat_bittiming = ((dbt->phase_seg1 + dbt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
 328                                 ((dbt->phase_seg2 - 1) << SEG_2_SHIFT) |
 329                                 ((dbt->sjw - 1) << SJW_SHIFT) |
 330                                 ((dbt->brp - 1) << PRESC_SHIFT);
 331
 332                 if ((((int)(dbt->phase_seg1 + dbt->prop_seg + 1) - 2) < 0) ||
 333                         (((int)(dbt->phase_seg2) - 1) < 0) ||
 334                         (((int)(dbt->sjw) - 1) < 0) ||
 335                         (((int)(dbt->brp) - 1) < 0))
 336                         return -EINVAL;
 337
 338                 priv->write_reg(priv, CANFD_F_SEG_1_OFFSET, dat_bittiming);
 339         }
 340
 341         canfd_reigister_off_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_OFF_RST_MASK);
 342
 343         netdev_dbg(ndev, "Slow bit rate: %08x\n", priv->read_reg(priv, CANFD_S_SEG_1_OFFSET));
 344         netdev_dbg(ndev, "Fast bit rate: %08x\n", priv->read_reg(priv, CANFD_F_SEG_1_OFFSET));
 345
 346         return 0;
 347 }
 348
 349 int canfd_get_freebuffer(struct ipms_canfd_priv *priv)
 350 {
 351         /* Get next transmit buffer */
 352         canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_TENEXT_MASK);
 353
 354         if (can_ioread8(priv->reg_base + CANFD_TCTRL_OFFSET) & CAN_FD_SET_TENEXT_MASK)
 355                 return -1;
 356
 357         return 0;
 358 }
 359
 360 static void canfd_tx_interrupt(struct net_device *ndev, u8 isr)
 361 {
 362         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 363
 364         /* wait till transmission of the PTB or STB finished */
 365         while (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
 366                 if (isr & CAN_FD_SET_TPIF_MASK)
 367                         canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TPIF_MASK);
 368
 369                 if (isr & CAN_FD_SET_TSIF_MASK)
 370                         canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TSIF_MASK);
 371
 372                 isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
 373         }
 374         netif_wake_queue(ndev);
 375 }
 376
 377 static int can_rx(struct net_device *ndev)
 378 {
 379         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 380         struct net_device_stats *stats = &ndev->stats;
 381         struct can_frame *cf;
 382         struct sk_buff *skb;
 383         u32 can_id;
 384         u8  dlc, control, rx_status;
 385
 386         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 387
 388         if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
 389                 return 0;
 390         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 391         can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
 392         dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
 393
 394         skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
 395         if (!skb) {
 396                 stats->rx_dropped++;
 397                 return 0;
 398         }
 399         cf->can_dlc = can_cc_dlc2len(dlc);
 400
 401         /* change the CANFD id into socketcan id format */
 402         if (control & CAN_FD_SET_IDE_MASK) {
 403                 cf->can_id = can_id;
 404                 cf->can_id |= CAN_EFF_FLAG;
 405         } else {
 406                 cf->can_id = can_id;
 407                 cf->can_id &= (~CAN_EFF_FLAG);
 408         }
 409
 410         if (control & CAN_FD_SET_RTR_MASK)
 411                 cf->can_id |= CAN_RTR_FLAG;
 412
 413         if (!(control & CAN_FD_SET_RTR_MASK)) {
 414                 *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
 415                 *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
 416         }
 417
 418         canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
 419         stats->rx_bytes += can_fd_dlc2len(cf->can_dlc);
 420         stats->rx_packets++;
 421         netif_receive_skb(skb);
 422
 423         return 1;
 424 }
 425
 426 static int canfd_rx(struct net_device *ndev)
 427 {
 428         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 429         struct net_device_stats *stats = &ndev->stats;
 430         struct canfd_frame *cf;
 431         struct sk_buff *skb;
 432         u32 can_id;
 433         u8  dlc, control, rx_status;
 434         int i;
 435
 436         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 437
 438         if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
 439                 return 0;
 440         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 441         can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
 442         dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
 443
 444         if (control & CAN_FD_SET_EDL_MASK)
 445                 /* allocate sk_buffer for canfd frame */
 446                 skb = alloc_canfd_skb(ndev, &cf);
 447         else
 448                 /* allocate sk_buffer for can frame */
 449                 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
 450
 451         if (!skb) {
 452                 stats->rx_dropped++;
 453                 return 0;
 454         }
 455
 456         /* change the CANFD or CAN2.0 data into socketcan data format */
 457         if (control & CAN_FD_SET_EDL_MASK)
 458                 cf->len = can_fd_dlc2len(dlc);
 459         else
 460                 cf->len = can_cc_dlc2len(dlc);
 461
 462         /* change the CANFD id into socketcan id format */
 463         if (control & CAN_FD_SET_EDL_MASK) {
 464                 cf->can_id = can_id;
 465                 if (control & CAN_FD_SET_IDE_MASK)
 466                         cf->can_id |= CAN_EFF_FLAG;
 467                 else
 468                         cf->can_id &= (~CAN_EFF_FLAG);
 469         } else {
 470                 cf->can_id = can_id;
 471                 if (control & CAN_FD_SET_IDE_MASK)
 472                         cf->can_id |= CAN_EFF_FLAG;
 473                 else
 474                         cf->can_id &= (~CAN_EFF_FLAG);
 475
 476                 if (control & CAN_FD_SET_RTR_MASK)
 477                         cf->can_id |= CAN_RTR_FLAG;
 478         }
 479
 480         /* CANFD frames handed over to SKB */
 481         if (control & CAN_FD_SET_EDL_MASK) {
 482                 for (i = 0; i < cf->len; i += 4)
 483                         *((u32 *)(cf->data + i)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + i);
 484         } else {
 485                 /* skb reads the received datas, if the RTR bit not set */
 486                 if (!(control & CAN_FD_SET_RTR_MASK)) {
 487                         *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
 488                         *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
 489                 }
 490         }
 491
 492         canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
 493
 494         stats->rx_bytes += cf->len;
 495         stats->rx_packets++;
 496         netif_receive_skb(skb);
 497
 498         return 1;
 499 }
 500
 501 static int canfd_rx_poll(struct napi_struct *napi, int quota)
 502 {
 503         struct net_device *ndev = napi->dev;
 504         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 505         int work_done = 0;
 506         u8 rx_status = 0, control = 0;
 507
 508         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 509         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 510
 511         /* clear receive interrupt and deal with all the received frames */
 512         while ((rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK) && (work_done < quota)) {
 513                 (control & CAN_FD_SET_EDL_MASK) ? (work_done += canfd_rx(ndev)) : (work_done += can_rx(ndev));
 514
 515                 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 516                 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 517         }
 518         napi_complete(napi);
 519         canfd_reigister_set_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_SET_RIE_MASK);
 520         return work_done;
 521 }
 522
 523 static void canfd_rxfull_interrupt(struct net_device *ndev, u8 isr)
 524 {
 525         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 526
 527         if (isr & CAN_FD_SET_RAFIF_MASK)
 528                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RAFIF_MASK);
 529
 530         if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK))
 531                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
 532                                         (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK));
 533 }
 534
 535 static int set_canfd_xmit_mode(struct net_device *ndev)
 536 {
 537         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 538
 539         switch (priv->tx_mode) {
 540         case XMIT_FULL:
 541                 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FULLCAN_MASK);
 542                 break;
 543         case XMIT_SEP_FIFO:
 544                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
 545                 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FIFO_MASK);
 546                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
 547                 break;
 548         case XMIT_SEP_PRIO:
 549                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
 550                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FIFO_MASK);
 551                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
 552                 break;
 553         case XMIT_PTB_MODE:
 554                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_TBSEL_MASK);
 555                 break;
 556         default:
 557                 break;
 558         }
 559         return 0;
 560 }
 561
 562 static netdev_tx_t canfd_driver_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 563 {
 564         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 565         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
 566         struct net_device_stats *stats = &ndev->stats;
 567         u32 ttsen, id, ctl, addr_off;
 568         int i;
 569
 570         priv->tx_mode = XMIT_PTB_MODE;
 571
 572         switch (priv->tx_mode) {
 573         case XMIT_FULL:
 574                 return NETDEV_TX_BUSY;
 575         case XMIT_PTB_MODE:
 576                 set_canfd_xmit_mode(ndev);
 577                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_STBY_MASK);
 578
 579                 if (cf->can_id & CAN_EFF_FLAG) {
 580                         id = (cf->can_id & CAN_EFF_MASK);
 581                         ttsen = 0 << TTSEN_8_32_SHIFT;
 582                         id |= ttsen;
 583                 } else {
 584                         id = (cf->can_id & CAN_SFF_MASK);
 585                         ttsen = 0 << TTSEN_8_32_SHIFT;
 586                         id |= ttsen;
 587                 }
 588
 589                 ctl = can_fd_len2dlc(cf->len);
 590
 591                 /* transmit can fd frame */
 592                 if (priv->enable_canfd) {
 593                         if (can_is_canfd_skb(skb)) {
 594                                 if (cf->can_id & CAN_EFF_FLAG)
 595                                         ctl |= CAN_FD_SET_IDE_MASK;
 596                                 else
 597                                         ctl &= CAN_FD_OFF_IDE_MASK;
 598
 599                                 if (cf->flags & CANFD_BRS)
 600                                         ctl |= CAN_FD_SET_BRS_MASK;
 601
 602                                 ctl |= CAN_FD_SET_EDL_MASK;
 603
 604                                 addr_off = CANFD_TBUF_DATA_OFFSET;
 605
 606                                 for (i = 0; i < cf->len; i += 4) {
 607                                         priv->write_reg(priv, addr_off,
 608                                                         *((u32 *)(cf->data + i)));
 609                                         addr_off += 4;
 610                                 }
 611                         } else {
 612                                 ctl &= CAN_FD_OFF_EDL_MASK;
 613                                 ctl &= CAN_FD_OFF_BRS_MASK;
 614
 615                                 if (cf->can_id & CAN_EFF_FLAG)
 616                                         ctl |= CAN_FD_SET_IDE_MASK;
 617                                 else
 618                                         ctl &= CAN_FD_OFF_IDE_MASK;
 619
 620                                 if (cf->can_id & CAN_RTR_FLAG) {
 621                                         ctl |= CAN_FD_SET_RTR_MASK;
 622                                         priv->write_reg(priv,
 623                                                 CANFD_TBUF_ID_OFFSET, id);
 624                                         priv->write_reg(priv,
 625                                                 CANFD_TBUF_CTL_OFFSET, ctl);
 626                                 } else {
 627                                         ctl &= CAN_FD_OFF_RTR_MASK;
 628                                         addr_off = CANFD_TBUF_DATA_OFFSET;
 629                                         priv->write_reg(priv, addr_off,
 630                                                         *((u32 *)(cf->data + 0)));
 631                                         priv->write_reg(priv, addr_off + 4,
 632                                                         *((u32 *)(cf->data + 4)));
 633                                 }
 634                         }
 635                         priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 636                         priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 637                         addr_off = CANFD_TBUF_DATA_OFFSET;
 638                 } else {
 639                         ctl &= CAN_FD_OFF_EDL_MASK;
 640                         ctl &= CAN_FD_OFF_BRS_MASK;
 641
 642                         if (cf->can_id & CAN_EFF_FLAG)
 643                                 ctl |= CAN_FD_SET_IDE_MASK;
 644                         else
 645                                 ctl &= CAN_FD_OFF_IDE_MASK;
 646
 647                         if (cf->can_id & CAN_RTR_FLAG) {
 648                                 ctl |= CAN_FD_SET_RTR_MASK;
 649                                 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 650                                 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 651                         } else {
 652                                 ctl &= CAN_FD_OFF_RTR_MASK;
 653                                 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 654                                 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 655                                 addr_off = CANFD_TBUF_DATA_OFFSET;
 656                                 priv->write_reg(priv, addr_off,
 657                                                 *((u32 *)(cf->data + 0)));
 658                                 priv->write_reg(priv, addr_off + 4,
 659                                                 *((u32 *)(cf->data + 4)));
 660                         }
 661                 }
 662                 canfd_reigister_set_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TPE_MASK);
 663                 stats->tx_bytes += cf->len;
 664                 netif_stop_queue(ndev);
 665                 break;
 666         default:
 667                 break;
 668         }
 669
 670         return NETDEV_TX_OK;
 671 }
 672
 673 static int set_reset_mode(struct net_device *ndev)
 674 {
 675         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 676         u8 ret;
 677
 678         ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 679         ret |= CAN_FD_SET_RST_MASK;
 680         can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
 681
 682         return 0;
 683 }
 684
 685 static void canfd_driver_stop(struct net_device *ndev)
 686 {
 687         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 688         int ret;
 689
 690         ret = set_reset_mode(ndev);
 691         if (ret)
 692                 netdev_err(ndev, "Mode Resetting Failed!\n");
 693
 694         priv->can.state = CAN_STATE_STOPPED;
 695 }
 696
 697 static int canfd_driver_close(struct net_device *ndev)
 698 {
 699         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 700
 701         netif_stop_queue(ndev);
 702         napi_disable(&priv->napi);
 703         canfd_driver_stop(ndev);
 704
 705         free_irq(ndev->irq, ndev);
 706         close_candev(ndev);
 707
 708         return 0;
 709 }
 710
 711 static enum can_state get_of_chip_status(struct net_device *ndev)
 712 {
 713         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 714         u8 can_stat, eir;
 715
 716         can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 717         eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
 718
 719         if (can_stat & CAN_FD_SET_BUSOFF_MASK)
 720                 return CAN_STATE_BUS_OFF;
 721
 722         if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK))
 723                 return CAN_STATE_ERROR_PASSIVE;
 724
 725         if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK))
 726                 return CAN_STATE_ERROR_WARNING;
 727
 728         if (~(eir & CAN_FD_SET_EPASS_MASK))
 729                 return CAN_STATE_ERROR_ACTIVE;
 730 }
 731
 732 static void canfd_error_interrupt(struct net_device *ndev, u8 isr, u8 eir)
 733 {
 734         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 735         struct net_device_stats *stats = &ndev->stats;
 736         struct can_frame *cf;
 737         struct sk_buff *skb;
 738         u8 koer, recnt = 0, tecnt = 0, can_stat = 0;
 739
 740         skb = alloc_can_err_skb(ndev, &cf);
 741
 742         koer = can_ioread8(priv->reg_base + CANFD_EALCAP_OFFSET) & CAN_FD_SET_KOER_MASK;
 743         recnt = can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET);
 744         tecnt = can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET);
 745
 746         /*Read can status*/
 747         can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 748
 749         /* Bus off --->active error mode */
 750         if ((isr & CAN_FD_SET_EIF_MASK) && priv->can.state == CAN_STATE_BUS_OFF)
 751                 priv->can.state = get_of_chip_status(ndev);
 752
 753         /* State selection */
 754         if (can_stat & CAN_FD_SET_BUSOFF_MASK) {
 755                 priv->can.state = get_of_chip_status(ndev);
 756                 priv->can.can_stats.bus_off++;
 757                 canfd_reigister_set_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_SET_BUSOFF_MASK);
 758                 can_bus_off(ndev);
 759                 if (skb)
 760                         cf->can_id |= CAN_ERR_BUSOFF;
 761
 762         } else if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK)) {
 763                 priv->can.state = get_of_chip_status(ndev);
 764                 priv->can.can_stats.error_passive++;
 765                 if (skb) {
 766                         cf->can_id |= CAN_ERR_CRTL;
 767                         cf->data[1] |= (recnt > 127) ? CAN_ERR_CRTL_RX_PASSIVE : 0;
 768                         cf->data[1] |= (tecnt > 127) ? CAN_ERR_CRTL_TX_PASSIVE : 0;
 769                         cf->data[6] = tecnt;
 770                         cf->data[7] = recnt;
 771                 }
 772         } else if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK)) {
 773                 priv->can.state = get_of_chip_status(ndev);
 774                 priv->can.can_stats.error_warning++;
 775                 if (skb) {
 776                         cf->can_id |= CAN_ERR_CRTL;
 777                         cf->data[1] |= (recnt > 95) ? CAN_ERR_CRTL_RX_WARNING : 0;
 778                         cf->data[1] |= (tecnt > 95) ? CAN_ERR_CRTL_TX_WARNING : 0;
 779                         cf->data[6] = tecnt;
 780                         cf->data[7] = recnt;
 781                 }
 782         }
 783
 784         /* Check for in protocol defined error interrupt */
 785         if (eir & CAN_FD_SET_BEIF_MASK) {
 786                 if (skb)
 787                         cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 788
 789                 /* bit error interrupt */
 790                 if (koer == CAN_FD_SET_BIT_ERROR_MASK) {
 791                         stats->tx_errors++;
 792                         if (skb) {
 793                                 cf->can_id |= CAN_ERR_PROT;
 794                                 cf->data[2] = CAN_ERR_PROT_BIT;
 795                         }
 796                 }
 797                 /* format error interrupt */
 798                 if (koer == CAN_FD_SET_FORM_ERROR_MASK) {
 799                         stats->rx_errors++;
 800                         if (skb) {
 801                                 cf->can_id |= CAN_ERR_PROT;
 802                                 cf->data[2] = CAN_ERR_PROT_FORM;
 803                         }
 804                 }
 805                 /* stuffing error interrupt */
 806                 if (koer == CAN_FD_SET_STUFF_ERROR_MASK) {
 807                         stats->rx_errors++;
 808                         if (skb) {
 809                                 cf->can_id |= CAN_ERR_PROT;
 810                                 cf->data[3] = CAN_ERR_PROT_STUFF;
 811                         }
 812                 }
 813                 /* ack error interrupt */
 814                 if (koer == CAN_FD_SET_ACK_ERROR_MASK) {
 815                         stats->tx_errors++;
 816                         if (skb) {
 817                                 cf->can_id |= CAN_ERR_PROT;
 818                                 cf->data[2] = CAN_ERR_PROT_LOC_ACK;
 819                         }
 820                 }
 821                 /* crc error interrupt */
 822                 if (koer == CAN_FD_SET_CRC_ERROR_MASK) {
 823                         stats->rx_errors++;
 824                         if (skb) {
 825                                 cf->can_id |= CAN_ERR_PROT;
 826                                 cf->data[2] = CAN_ERR_PROT_LOC_CRC_SEQ;
 827                         }
 828                 }
 829                 priv->can.can_stats.bus_error++;
 830         }
 831         if (skb) {
 832                 stats->rx_packets++;
 833                 stats->rx_bytes += cf->can_dlc;
 834                 netif_rx(skb);
 835         }
 836
 837         netdev_dbg(ndev, "Recnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET));
 838         netdev_dbg(ndev, "Tecnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET));
 839 }
 840
 841 static irqreturn_t canfd_interrupt(int irq, void *dev_id)
 842 {
 843         struct net_device *ndev = (struct net_device *)dev_id;
 844         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 845         u8 isr, eir;
 846         u8 isr_handled = 0, eir_handled = 0;
 847
 848         /* read the value of interrupt status register */
 849         isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
 850
 851         /* read the value of error interrupt register */
 852         eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
 853
 854         /* Check for Tx interrupt and Processing it */
 855         if (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
 856                 canfd_tx_interrupt(ndev, isr);
 857                 isr_handled |= (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK);
 858         }
 859         if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK)) {
 860                 canfd_rxfull_interrupt(ndev, isr);
 861                 isr_handled |= (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK);
 862         }
 863         /* Check Rx interrupt and Processing the receive interrupt routine */
 864         if (isr & CAN_FD_SET_RIF_MASK) {
 865                 canfd_reigister_off_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_OFF_RIE_MASK);
 866                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RIF_MASK);
 867
 868                 napi_schedule(&priv->napi);
 869                 isr_handled |= CAN_FD_SET_RIF_MASK;
 870         }
 871         if ((isr & CAN_FD_SET_EIF_MASK) | (eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK))) {
 872                 /* reset EPIF and BEIF. Reset EIF */
 873                 canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET,
 874                                         eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK));
 875                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
 876                                         isr & CAN_FD_SET_EIF_MASK);
 877
 878                 canfd_error_interrupt(ndev, isr, eir);
 879
 880                 isr_handled |= CAN_FD_SET_EIF_MASK;
 881                 eir_handled |= (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK);
 882         }
 883         if ((isr_handled == 0) && (eir_handled == 0)) {
 884                 netdev_err(ndev, "Unhandled interrupt!\n");
 885                 return IRQ_NONE;
 886         }
 887
 888         return IRQ_HANDLED;
 889 }
 890
 891 static int canfd_chip_start(struct net_device *ndev)
 892 {
 893         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 894         int err;
 895         u8 ret;
 896
 897         err = set_reset_mode(ndev);
 898         if (err) {
 899                 netdev_err(ndev, "Mode Resetting Failed!\n");
 900                 return err;
 901         }
 902
 903         err = canfd_device_driver_bittime_configuration(ndev);
 904         if (err) {
 905                 netdev_err(ndev, "Bittime Setting Failed!\n");
 906                 return err;
 907         }
 908
 909         /* Set Almost Full Warning Limit */
 910         canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_AFWL_MASK);
 911
 912         /* Programmable Error Warning Limit = (EWL+1)*8. Set EWL=11->Error Warning=96 */
 913         canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_EWL_MASK);
 914
 915         /* Interrupts enable */
 916         can_iowrite8(CAN_FD_INTR_ALL_MASK, priv->reg_base + CANFD_RTIE_OFFSET);
 917
 918         /* Error Interrupts enable(Error Passive and Bus Error) */
 919         canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET, CAN_FD_SET_EPIE_MASK);
 920
 921         ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 922
 923         /* Check whether it is loopback mode or normal mode */
 924         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
 925                 ret |= CAN_FD_LBMIMOD_MASK;
 926         } else {
 927                 ret &= ~CAN_FD_LBMEMOD_MASK;
 928                 ret &= ~CAN_FD_LBMIMOD_MASK;
 929         }
 930
 931         can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
 932
 933         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 934
 935         return 0;
 936 }
 937
 938 static int  canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
 939 {
 940         int ret;
 941
 942         switch (mode) {
 943         case CAN_MODE_START:
 944                 ret = canfd_chip_start(ndev);
 945                 if (ret) {
 946                         netdev_err(ndev, "Could Not Start CAN device !!\n");
 947                         return ret;
 948                 }
 949                 netif_wake_queue(ndev);
 950                 break;
 951         default:
 952                 ret = -EOPNOTSUPP;
 953                 break;
 954         }
 955
 956         return ret;
 957 }
 958
 959 static int canfd_driver_open(struct net_device *ndev)
 960 {
 961         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 962         int ret;
 963
 964         /* Set chip into reset mode */
 965         ret = set_reset_mode(ndev);
 966         if (ret) {
 967                 netdev_err(ndev, "Mode Resetting Failed!\n");
 968                 return ret;
 969         }
 970
 971         /* Common open */
 972         ret = open_candev(ndev);
 973         if (ret)
 974                 return ret;
 975
 976         /* Register interrupt handler */
 977         ret = request_irq(ndev->irq, canfd_interrupt, IRQF_SHARED, ndev->name, ndev);
 978         if (ret) {
 979                 netdev_err(ndev, "request_irq err: %d\n", ret);
 980                 goto exit_irq;
 981         }
 982
 983         ret = canfd_chip_start(ndev);
 984         if (ret) {
 985                 netdev_err(ndev, "Could Not Start CAN device !\n");
 986                 goto exit_can_start;
 987         }
 988
 989         napi_enable(&priv->napi);
 990         netif_start_queue(ndev);
 991
 992         return 0;
 993
 994 exit_can_start:
 995         free_irq(ndev->irq, ndev);
 996 exit_irq:
 997         close_candev(ndev);
 998         return ret;
 999 }
1000
1001 static int canfd_control_enable(struct ipms_canfd_priv *priv)
1002 {
1003         u32 value;
1004
1005         value = readl(priv->syscon_base + priv->syscon_offset);
1006         writel(value | priv->syscon_mask, priv->syscon_base + priv->syscon_offset);
1007
1008         return 0;
1009 }
1010
1011 static int canfd_control_parse_dt(struct platform_device *pdev, struct ipms_canfd_priv *priv)
1012 {
1013         struct resource *res_syscon;
1014
1015         priv->enable_canfd = false;
1016         res_syscon = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sys_syscon");
1017         priv->syscon_base = ioremap(res_syscon->start, resource_size(res_syscon));
1018         if (IS_ERR(priv->syscon_base))
1019                 return PTR_ERR(priv->syscon_base);
1020
1021         if (!(device_property_read_u32(priv->dev, "syscon,canfd-offset", &priv->syscon_offset)))
1022                 priv->enable_canfd = true;
1023
1024         if (!(device_property_read_u32(priv->dev, "syscon,canfd-mask", &priv->syscon_mask)))
1025                 priv->enable_canfd = priv->enable_canfd && true;
1026
1027         if (device_property_read_bool(priv->dev, "syscon,canfd-enable"))
1028                 priv->enable_canfd = priv->enable_canfd && true;
1029         else
1030                 priv->enable_canfd = priv->enable_canfd && false;
1031
1032         return 0;
1033 }
1034
1035 static const struct net_device_ops canfd_netdev_ops = {
1036         .ndo_open = canfd_driver_open,
1037         .ndo_stop = canfd_driver_close,
1038         .ndo_start_xmit = canfd_driver_start_xmit,
1039         .ndo_change_mtu = can_change_mtu,
1040 };
1041
1042 static int canfd_driver_probe(struct platform_device *pdev)
1043 {
1044         struct net_device *ndev;
1045         struct ipms_canfd_priv *priv;
1046         void __iomem *addr;
1047         int ret;
1048
1049         addr = devm_platform_ioremap_resource_byname(pdev, "reg_base");
1050         if (IS_ERR(addr)) {
1051                 ret = PTR_ERR(addr);
1052                 goto exit;
1053         }
1054
1055         ndev = alloc_candev(sizeof(struct ipms_canfd_priv), 1);
1056         if (!ndev) {
1057                 ret = -ENOMEM;
1058                 goto exit;
1059         }
1060
1061         priv = netdev_priv(ndev);
1062         priv->dev = &pdev->dev;
1063
1064         ret = canfd_control_parse_dt(pdev, priv);
1065         if (ret)
1066                 goto exit;
1067
1068         if (priv->enable_canfd)
1069                 canfd_control_enable(priv);
1070
1071         priv->clks = can_clks;
1072         priv->resets = can_resets;
1073         priv->nr_clks = ARRAY_SIZE(can_clks);
1074         priv->nr_rstcs = ARRAY_SIZE(can_resets);
1075         ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, priv->nr_rstcs, priv->resets);
1076         if (ret) {
1077                 dev_err(priv->dev, "failed to get can reset controls\n");
1078                 goto free_exit;
1079         }
1080
1081         ret = devm_clk_bulk_get(&pdev->dev, priv->nr_clks, priv->clks);
1082         if (ret) {
1083                 dev_err(priv->dev, "failed to get can clk controls\n");
1084                 goto free_exit;
1085         }
1086
1087         ret = clk_bulk_prepare_enable(priv->nr_clks, priv->clks);
1088         if (ret) {
1089                 dev_err(priv->dev, "enable clk error.\n");
1090                 goto free_exit;
1091         }
1092
1093         ret = reset_control_bulk_deassert(priv->nr_rstcs, priv->resets);
1094         if (ret) {
1095                 dev_err(priv->dev, "deassert can error.\n");
1096                 goto clk_exit;
1097         }
1098
1099         priv->can.bittiming_const = &canfd_bittiming_const;
1100         priv->can.data_bittiming_const = &canfd_data_bittiming_const;
1101         priv->can.do_set_mode = canfd_do_set_mode;
1102
1103         /* in user space the execution mode can be chosen */
1104         if (priv->enable_canfd)
1105                 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_FD;
1106         else
1107                 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK;
1108
1109         priv->reg_base = addr;
1110         priv->write_reg = canfd_write_reg_le;
1111         priv->read_reg = canfd_read_reg_le;
1112         priv->can_clk = devm_clk_get(&pdev->dev, "ipms_can_clk");
1113         if (IS_ERR(priv->can_clk)) {
1114                 dev_err(&pdev->dev, "Device clock not found.\n");
1115                 ret = PTR_ERR(priv->can_clk);
1116                 goto reset_exit;
1117         }
1118
1119         priv->can.clock.freq = clk_get_rate(priv->can_clk);
1120
1121         ndev->irq = platform_get_irq(pdev, 0);
1122
1123         /* we support local echo */
1124         ndev->flags |= IFF_ECHO;
1125         ndev->netdev_ops = &canfd_netdev_ops;
1126
1127         platform_set_drvdata(pdev, ndev);
1128         SET_NETDEV_DEV(ndev, &pdev->dev);
1129
1130         netif_napi_add(ndev, &priv->napi, canfd_rx_poll, 16);
1131
1132         ret = register_candev(ndev);
1133         if (ret) {
1134                 dev_err(&pdev->dev, "Fail to register failed (err=%d)\n", ret);
1135                 goto reset_exit;
1136         }
1137
1138         dev_dbg(&pdev->dev, "Driver registered: regs=%p, irp=%d, clock=%d\n",
1139                 priv->reg_base, ndev->irq, priv->can.clock.freq);
1140
1141         return 0;
1142
1143 reset_exit:
1144         reset_control_bulk_assert(priv->nr_rstcs, priv->resets);
1145 clk_exit:
1146         clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1147 free_exit:
1148         iounmap(priv->syscon_base);
1149         free_candev(ndev);
1150 exit:
1151         return ret;
1152 }
1153
1154 static int canfd_driver_remove(struct platform_device *pdev)
1155 {
1156         struct net_device *ndev = platform_get_drvdata(pdev);
1157         struct ipms_canfd_priv *priv = netdev_priv(ndev);
1158
1159         reset_control_bulk_assert(priv->nr_rstcs, priv->resets);
1160         clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1161
1162         iounmap(priv->syscon_base);
1163         unregister_candev(ndev);
1164         netif_napi_del(&priv->napi);
1165         free_candev(ndev);
1166
1167         return 0;
1168 }
1169
1170 static const struct of_device_id canfd_of_match[] = {
1171         { .compatible = "ipms,can" },
1172         { }
1173 };
1174 MODULE_DEVICE_TABLE(of, canfd_of_match);
1175
1176 static struct platform_driver can_driver = {
1177         .probe          = canfd_driver_probe,
1178         .remove         = canfd_driver_remove,
1179         .driver = {
1180                 .name  = DRIVER_NAME,
1181                 .of_match_table = canfd_of_match,
1182         },
1183 };
1184
1185 module_platform_driver(can_driver);
1186 MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
1187 MODULE_LICENSE("GPL v2");
1188 MODULE_DESCRIPTION("ipms can controller driver");