1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021 StarFive, Inc <jenny.zhang@starfivetech.com>
5 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
6 * CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER
7 * FOR THEM TO SAVE TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE
8 * FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
9 * CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE
10 * BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION
11 * WITH THEIR PRODUCTS.
14 #include <linux/clk.h>
15 #include <linux/reset.h>
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
24 #include <linux/platform_device.h>
25 #include <linux/skbuff.h>
26 #include <linux/string.h>
27 #include <linux/types.h>
28 #include <linux/can/dev.h>
29 #include <linux/can/error.h>
30 #include <linux/can/led.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
34 #define DRIVER_NAME "ipms_canfd"
36 /* CAN registers set */
37 enum canfd_device_reg {
38 CANFD_RUBF_OFFSET = 0x00, /* Receive Buffer Registers 0x00-0x4f */
39 CANFD_RUBF_ID_OFFSET = 0x00,
40 CANFD_RBUF_CTL_OFFSET = 0x04,
41 CANFD_RBUF_DATA_OFFSET = 0x08,
42 CANFD_TBUF_OFFSET = 0x50, /* Transmit Buffer Registers 0x50-0x97 */
43 CANFD_TBUF_ID_OFFSET = 0x50,
44 CANFD_TBUF_CTL_OFFSET = 0x54,
45 CANFD_TBUF_DATA_OFFSET = 0x58,
46 CANFD_TTS_OFFSET = 0x98, /* Transmission Time Stamp 0x98-0x9f */
47 CANFD_CFG_STAT_OFFSET = 0xa0,
48 CANFD_TCMD_OFFSET = 0xa1,
49 CANFD_TCTRL_OFFSET = 0xa2,
50 CANFD_RCTRL_OFFSET = 0xa3,
51 CANFD_RTIE_OFFSET = 0xa4,
52 CANFD_RTIF_OFFSET = 0xa5,
53 CANFD_ERRINT_OFFSET = 0xa6,
54 CANFD_LIMIT_OFFSET = 0xa7,
55 CANFD_S_SEG_1_OFFSET = 0xa8,
56 CANFD_S_SEG_2_OFFSET = 0xa9,
57 CANFD_S_SJW_OFFSET = 0xaa,
58 CANFD_S_PRESC_OFFSET = 0xab,
59 CANFD_F_SEG_1_OFFSET = 0xac,
60 CANFD_F_SEG_2_OFFSET = 0xad,
61 CANFD_F_SJW_OFFSET = 0xae,
62 CANFD_F_PRESC_OFFSET = 0xaf,
63 CANFD_EALCAP_OFFSET = 0xb0,
64 CANFD_RECNT_OFFSET = 0xb2,
65 CANFD_TECNT_OFFSET = 0xb3,
68 enum canfd_reg_bitchange {
69 CAN_FD_SET_RST_MASK = 0x80, /* Set Reset Bit */
70 CAN_FD_OFF_RST_MASK = 0x7f, /* Reset Off Bit */
71 CAN_FD_SET_FULLCAN_MASK = 0x10, /* set TTTBM as 1->full TTCAN mode */
72 CAN_FD_OFF_FULLCAN_MASK = 0xef, /* set TTTBM as 0->separate PTB and STB mode */
73 CAN_FD_SET_FIFO_MASK = 0x20, /* set TSMODE as 1->FIFO mode */
74 CAN_FD_OFF_FIFO_MASK = 0xdf, /* set TSMODE as 0->Priority mode */
75 CAN_FD_SET_TSONE_MASK = 0x04,
76 CAN_FD_OFF_TSONE_MASK = 0xfb,
77 CAN_FD_SET_TSALL_MASK = 0x02,
78 CAN_FD_OFF_TSALL_MASK = 0xfd,
79 CAN_FD_LBMEMOD_MASK = 0x40, /* set loop back mode, external */
80 CAN_FD_LBMIMOD_MASK = 0x20, /* set loopback internal mode */
81 CAN_FD_SET_BUSOFF_MASK = 0x01,
82 CAN_FD_OFF_BUSOFF_MASK = 0xfe,
83 CAN_FD_SET_TTSEN_MASK = 0x80, /* set ttsen, tts update enable */
84 CAN_FD_SET_BRS_MASK = 0x10, /* can fd Bit Rate Switch mask */
85 CAN_FD_OFF_BRS_MASK = 0xef,
86 CAN_FD_SET_EDL_MASK = 0x20, /* Extended Data Length */
87 CAN_FD_OFF_EDL_MASK = 0xdf,
88 CAN_FD_SET_DLC_MASK = 0x0f,
89 CAN_FD_SET_TENEXT_MASK = 0x40,
90 CAN_FD_SET_IDE_MASK = 0x80,
91 CAN_FD_OFF_IDE_MASK = 0x7f,
92 CAN_FD_SET_RTR_MASK = 0x40,
93 CAN_FD_OFF_RTR_MASK = 0xbf,
94 CAN_FD_INTR_ALL_MASK = 0xff, /* all interrupts enable mask */
95 CAN_FD_SET_RIE_MASK = 0x80,
96 CAN_FD_OFF_RIE_MASK = 0x7f,
97 CAN_FD_SET_RFIE_MASK = 0x20,
98 CAN_FD_OFF_RFIE_MASK = 0xdf,
99 CAN_FD_SET_RAFIE_MASK = 0x10,
100 CAN_FD_OFF_RAFIE_MASK = 0xef,
101 CAN_FD_SET_EIE_MASK = 0x02,
102 CAN_FD_OFF_EIE_MASK = 0xfd,
103 CAN_FD_TASCTIVE_MASK = 0x02,
104 CAN_FD_RASCTIVE_MASK = 0x04,
105 CAN_FD_SET_TBSEL_MASK = 0x80, /* message writen in STB */
106 CAN_FD_OFF_TBSEL_MASK = 0x7f, /* message writen in PTB */
107 CAN_FD_SET_STBY_MASK = 0x20,
108 CAN_FD_OFF_STBY_MASK = 0xdf,
109 CAN_FD_SET_TPE_MASK = 0x10, /* Transmit primary enable */
110 CAN_FD_SET_TPA_MASK = 0x08,
111 CAN_FD_SET_SACK_MASK = 0x80,
112 CAN_FD_SET_RREL_MASK = 0x10,
113 CAN_FD_RSTAT_NOT_EMPTY_MASK = 0x03,
114 CAN_FD_SET_RIF_MASK = 0x80,
115 CAN_FD_OFF_RIF_MASK = 0x7f,
116 CAN_FD_SET_RAFIF_MASK = 0x10,
117 CAN_FD_SET_RFIF_MASK = 0x20,
118 CAN_FD_SET_TPIF_MASK = 0x08, /* Transmission Primary Interrupt Flag */
119 CAN_FD_SET_TSIF_MASK = 0x04,
120 CAN_FD_SET_EIF_MASK = 0x02,
121 CAN_FD_SET_AIF_MASK = 0x01,
122 CAN_FD_SET_EWARN_MASK = 0x80,
123 CAN_FD_SET_EPASS_MASK = 0x40,
124 CAN_FD_SET_EPIE_MASK = 0x20,
125 CAN_FD_SET_EPIF_MASK = 0x10,
126 CAN_FD_SET_ALIE_MASK = 0x08,
127 CAN_FD_SET_ALIF_MASK = 0x04,
128 CAN_FD_SET_BEIE_MASK = 0x02,
129 CAN_FD_SET_BEIF_MASK = 0x01,
130 CAN_FD_OFF_EPIE_MASK = 0xdf,
131 CAN_FD_OFF_BEIE_MASK = 0xfd,
132 CAN_FD_SET_AFWL_MASK = 0x40,
133 CAN_FD_SET_EWL_MASK = 0x0b,
134 CAN_FD_SET_KOER_MASK = 0xe0,
135 CAN_FD_SET_BIT_ERROR_MASK = 0x20,
136 CAN_FD_SET_FORM_ERROR_MASK = 0x40,
137 CAN_FD_SET_STUFF_ERROR_MASK = 0x60,
138 CAN_FD_SET_ACK_ERROR_MASK = 0x80,
139 CAN_FD_SET_CRC_ERROR_MASK = 0xa0,
140 CAN_FD_SET_OTH_ERROR_MASK = 0xc0,
143 /* seg1,seg2,sjw,prescaler all have 8 bits */
144 #define BITS_OF_BITTIMING_REG 8
146 /* in can_bittiming strucure every field has 32 bits---->u32 */
147 #define FBITS_IN_BITTIMING_STR 32
148 #define SEG_1_SHIFT 0
149 #define SEG_2_SHIFT 8
151 #define PRESC_SHIFT 24
153 /* TTSEN bit used for 32 bit register read or write */
154 #define TTSEN_8_32_SHIFT 24
155 #define RTR_32_8_SHIFT 24
159 #define XMIT_SEP_FIFO 1
160 #define XMIT_SEP_PRIO 2
161 #define XMIT_PTB_MODE 3
163 struct ipms_canfd_priv {
165 struct napi_struct napi;
167 void __iomem *reg_base;
168 void __iomem *syscon_base;
169 u32 (*read_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg);
170 void (*write_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg, u32 val);
172 unsigned int tx_mode;
173 struct clk_bulk_data *clks;
175 struct reset_control_bulk_data *resets;
177 unsigned int syscon_offset;
178 unsigned int syscon_mask;
182 static struct can_bittiming_const canfd_bittiming_const = {
195 static struct can_bittiming_const canfd_data_bittiming_const = {
207 struct reset_control_bulk_data can_resets[] = {
209 { .id = "rst_core" },
210 { .id = "rst_timer" },
213 struct clk_bulk_data can_clks[] = {
215 { .id = "core_clk" },
216 { .id = "timer_clk" },
219 static void canfd_write_reg_le(const struct ipms_canfd_priv *priv,
220 enum canfd_device_reg reg, u32 val)
222 iowrite32(val, priv->reg_base + reg);
225 static u32 canfd_read_reg_le(const struct ipms_canfd_priv *priv,
226 enum canfd_device_reg reg)
228 return ioread32(priv->reg_base + reg);
231 static inline unsigned char can_ioread8(const void *addr)
240 addr_down = (void *)ALIGN_DOWN((unsigned long)addr, 4);
241 offset = addr - addr_down;
242 val.val_32 = ioread32(addr_down);
243 return val.val_8[offset];
246 static inline void can_iowrite8(unsigned char value, void *addr)
255 addr_down = (void *)ALIGN_DOWN((unsigned long)addr, 4);
256 offset = addr - addr_down;
257 val.val_32 = ioread32(addr_down);
258 val.val_8[offset] = value;
259 iowrite32(val.val_32, addr_down);
262 static void canfd_reigister_set_bit(const struct ipms_canfd_priv *priv,
263 enum canfd_device_reg reg,
264 enum canfd_reg_bitchange set_mask)
273 addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
274 offset = (priv->reg_base + reg) - addr_down;
275 val.val_32 = ioread32(addr_down);
276 val.val_8[offset] |= set_mask;
277 iowrite32(val.val_32, addr_down);
280 static void canfd_reigister_off_bit(const struct ipms_canfd_priv *priv,
281 enum canfd_device_reg reg,
282 enum canfd_reg_bitchange set_mask)
291 addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
292 offset = (priv->reg_base + reg) - addr_down;
293 val.val_32 = ioread32(addr_down);
294 val.val_8[offset] &= set_mask;
295 iowrite32(val.val_32, addr_down);
298 static int canfd_device_driver_bittime_configuration(struct net_device *ndev)
300 struct ipms_canfd_priv *priv = netdev_priv(ndev);
301 struct can_bittiming *bt = &priv->can.bittiming;
302 struct can_bittiming *dbt = &priv->can.data_bittiming;
303 u32 reset_test, bittiming_temp, dat_bittiming;
305 reset_test = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
307 if (!(reset_test & CAN_FD_SET_RST_MASK)) {
308 netdev_alert(ndev, "Not in reset mode, cannot set bit timing\n");
312 bittiming_temp = ((bt->phase_seg1 + bt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
313 ((bt->phase_seg2 - 1) << SEG_2_SHIFT) |
314 ((bt->sjw - 1) << SJW_SHIFT) |
315 ((bt->brp - 1) << PRESC_SHIFT);
317 /* Check the bittime parameter */
318 if ((((int)(bt->phase_seg1 + bt->prop_seg + 1) - 2) < 0) ||
319 (((int)(bt->phase_seg2) - 1) < 0) ||
320 (((int)(bt->sjw) - 1) < 0) ||
321 (((int)(bt->brp) - 1) < 0))
324 priv->write_reg(priv, CANFD_S_SEG_1_OFFSET, bittiming_temp);
326 if (priv->enable_canfd) {
327 dat_bittiming = ((dbt->phase_seg1 + dbt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
328 ((dbt->phase_seg2 - 1) << SEG_2_SHIFT) |
329 ((dbt->sjw - 1) << SJW_SHIFT) |
330 ((dbt->brp - 1) << PRESC_SHIFT);
332 if ((((int)(dbt->phase_seg1 + dbt->prop_seg + 1) - 2) < 0) ||
333 (((int)(dbt->phase_seg2) - 1) < 0) ||
334 (((int)(dbt->sjw) - 1) < 0) ||
335 (((int)(dbt->brp) - 1) < 0))
338 priv->write_reg(priv, CANFD_F_SEG_1_OFFSET, dat_bittiming);
341 canfd_reigister_off_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_OFF_RST_MASK);
343 netdev_dbg(ndev, "Slow bit rate: %08x\n", priv->read_reg(priv, CANFD_S_SEG_1_OFFSET));
344 netdev_dbg(ndev, "Fast bit rate: %08x\n", priv->read_reg(priv, CANFD_F_SEG_1_OFFSET));
349 int canfd_get_freebuffer(struct ipms_canfd_priv *priv)
351 /* Get next transmit buffer */
352 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_TENEXT_MASK);
354 if (can_ioread8(priv->reg_base + CANFD_TCTRL_OFFSET) & CAN_FD_SET_TENEXT_MASK)
360 static void canfd_tx_interrupt(struct net_device *ndev, u8 isr)
362 struct ipms_canfd_priv *priv = netdev_priv(ndev);
364 /* wait till transmission of the PTB or STB finished */
365 while (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
366 if (isr & CAN_FD_SET_TPIF_MASK)
367 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TPIF_MASK);
369 if (isr & CAN_FD_SET_TSIF_MASK)
370 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TSIF_MASK);
372 isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
374 netif_wake_queue(ndev);
377 static int can_rx(struct net_device *ndev)
379 struct ipms_canfd_priv *priv = netdev_priv(ndev);
380 struct net_device_stats *stats = &ndev->stats;
381 struct can_frame *cf;
384 u8 dlc, control, rx_status;
386 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
388 if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
390 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
391 can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
392 dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
394 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
399 cf->can_dlc = can_cc_dlc2len(dlc);
401 /* change the CANFD id into socketcan id format */
402 if (control & CAN_FD_SET_IDE_MASK) {
404 cf->can_id |= CAN_EFF_FLAG;
407 cf->can_id &= (~CAN_EFF_FLAG);
410 if (control & CAN_FD_SET_RTR_MASK)
411 cf->can_id |= CAN_RTR_FLAG;
413 if (!(control & CAN_FD_SET_RTR_MASK)) {
414 *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
415 *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
418 canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
419 stats->rx_bytes += can_fd_dlc2len(cf->can_dlc);
421 netif_receive_skb(skb);
426 static int canfd_rx(struct net_device *ndev)
428 struct ipms_canfd_priv *priv = netdev_priv(ndev);
429 struct net_device_stats *stats = &ndev->stats;
430 struct canfd_frame *cf;
433 u8 dlc, control, rx_status;
436 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
438 if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
440 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
441 can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
442 dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
444 if (control & CAN_FD_SET_EDL_MASK)
445 /* allocate sk_buffer for canfd frame */
446 skb = alloc_canfd_skb(ndev, &cf);
448 /* allocate sk_buffer for can frame */
449 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
456 /* change the CANFD or CAN2.0 data into socketcan data format */
457 if (control & CAN_FD_SET_EDL_MASK)
458 cf->len = can_fd_dlc2len(dlc);
460 cf->len = can_cc_dlc2len(dlc);
462 /* change the CANFD id into socketcan id format */
463 if (control & CAN_FD_SET_EDL_MASK) {
465 if (control & CAN_FD_SET_IDE_MASK)
466 cf->can_id |= CAN_EFF_FLAG;
468 cf->can_id &= (~CAN_EFF_FLAG);
471 if (control & CAN_FD_SET_IDE_MASK)
472 cf->can_id |= CAN_EFF_FLAG;
474 cf->can_id &= (~CAN_EFF_FLAG);
476 if (control & CAN_FD_SET_RTR_MASK)
477 cf->can_id |= CAN_RTR_FLAG;
480 /* CANFD frames handed over to SKB */
481 if (control & CAN_FD_SET_EDL_MASK) {
482 for (i = 0; i < cf->len; i += 4)
483 *((u32 *)(cf->data + i)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + i);
485 /* skb reads the received datas, if the RTR bit not set */
486 if (!(control & CAN_FD_SET_RTR_MASK)) {
487 *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
488 *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
492 canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
494 stats->rx_bytes += cf->len;
496 netif_receive_skb(skb);
501 static int canfd_rx_poll(struct napi_struct *napi, int quota)
503 struct net_device *ndev = napi->dev;
504 struct ipms_canfd_priv *priv = netdev_priv(ndev);
506 u8 rx_status = 0, control = 0;
508 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
509 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
511 /* clear receive interrupt and deal with all the received frames */
512 while ((rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK) && (work_done < quota)) {
513 (control & CAN_FD_SET_EDL_MASK) ? (work_done += canfd_rx(ndev)) : (work_done += can_rx(ndev));
515 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
516 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
519 canfd_reigister_set_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_SET_RIE_MASK);
523 static void canfd_rxfull_interrupt(struct net_device *ndev, u8 isr)
525 struct ipms_canfd_priv *priv = netdev_priv(ndev);
527 if (isr & CAN_FD_SET_RAFIF_MASK)
528 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RAFIF_MASK);
530 if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK))
531 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
532 (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK));
535 static int set_canfd_xmit_mode(struct net_device *ndev)
537 struct ipms_canfd_priv *priv = netdev_priv(ndev);
539 switch (priv->tx_mode) {
541 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FULLCAN_MASK);
544 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
545 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FIFO_MASK);
546 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
549 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
550 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FIFO_MASK);
551 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
554 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_TBSEL_MASK);
562 static netdev_tx_t canfd_driver_start_xmit(struct sk_buff *skb, struct net_device *ndev)
564 struct ipms_canfd_priv *priv = netdev_priv(ndev);
565 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
566 struct net_device_stats *stats = &ndev->stats;
567 u32 ttsen, id, ctl, addr_off;
570 priv->tx_mode = XMIT_PTB_MODE;
572 switch (priv->tx_mode) {
574 return NETDEV_TX_BUSY;
576 set_canfd_xmit_mode(ndev);
577 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_STBY_MASK);
579 if (cf->can_id & CAN_EFF_FLAG) {
580 id = (cf->can_id & CAN_EFF_MASK);
581 ttsen = 0 << TTSEN_8_32_SHIFT;
584 id = (cf->can_id & CAN_SFF_MASK);
585 ttsen = 0 << TTSEN_8_32_SHIFT;
589 ctl = can_fd_len2dlc(cf->len);
591 /* transmit can fd frame */
592 if (priv->enable_canfd) {
593 if (can_is_canfd_skb(skb)) {
594 if (cf->can_id & CAN_EFF_FLAG)
595 ctl |= CAN_FD_SET_IDE_MASK;
597 ctl &= CAN_FD_OFF_IDE_MASK;
599 if (cf->flags & CANFD_BRS)
600 ctl |= CAN_FD_SET_BRS_MASK;
602 ctl |= CAN_FD_SET_EDL_MASK;
604 addr_off = CANFD_TBUF_DATA_OFFSET;
606 for (i = 0; i < cf->len; i += 4) {
607 priv->write_reg(priv, addr_off,
608 *((u32 *)(cf->data + i)));
612 ctl &= CAN_FD_OFF_EDL_MASK;
613 ctl &= CAN_FD_OFF_BRS_MASK;
615 if (cf->can_id & CAN_EFF_FLAG)
616 ctl |= CAN_FD_SET_IDE_MASK;
618 ctl &= CAN_FD_OFF_IDE_MASK;
620 if (cf->can_id & CAN_RTR_FLAG) {
621 ctl |= CAN_FD_SET_RTR_MASK;
622 priv->write_reg(priv,
623 CANFD_TBUF_ID_OFFSET, id);
624 priv->write_reg(priv,
625 CANFD_TBUF_CTL_OFFSET, ctl);
627 ctl &= CAN_FD_OFF_RTR_MASK;
628 addr_off = CANFD_TBUF_DATA_OFFSET;
629 priv->write_reg(priv, addr_off,
630 *((u32 *)(cf->data + 0)));
631 priv->write_reg(priv, addr_off + 4,
632 *((u32 *)(cf->data + 4)));
635 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
636 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
637 addr_off = CANFD_TBUF_DATA_OFFSET;
639 ctl &= CAN_FD_OFF_EDL_MASK;
640 ctl &= CAN_FD_OFF_BRS_MASK;
642 if (cf->can_id & CAN_EFF_FLAG)
643 ctl |= CAN_FD_SET_IDE_MASK;
645 ctl &= CAN_FD_OFF_IDE_MASK;
647 if (cf->can_id & CAN_RTR_FLAG) {
648 ctl |= CAN_FD_SET_RTR_MASK;
649 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
650 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
652 ctl &= CAN_FD_OFF_RTR_MASK;
653 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
654 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
655 addr_off = CANFD_TBUF_DATA_OFFSET;
656 priv->write_reg(priv, addr_off,
657 *((u32 *)(cf->data + 0)));
658 priv->write_reg(priv, addr_off + 4,
659 *((u32 *)(cf->data + 4)));
662 canfd_reigister_set_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TPE_MASK);
663 stats->tx_bytes += cf->len;
664 netif_stop_queue(ndev);
673 static int set_reset_mode(struct net_device *ndev)
675 struct ipms_canfd_priv *priv = netdev_priv(ndev);
678 ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
679 ret |= CAN_FD_SET_RST_MASK;
680 can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
685 static void canfd_driver_stop(struct net_device *ndev)
687 struct ipms_canfd_priv *priv = netdev_priv(ndev);
690 ret = set_reset_mode(ndev);
692 netdev_err(ndev, "Mode Resetting Failed!\n");
694 priv->can.state = CAN_STATE_STOPPED;
697 static int canfd_driver_close(struct net_device *ndev)
699 struct ipms_canfd_priv *priv = netdev_priv(ndev);
701 netif_stop_queue(ndev);
702 napi_disable(&priv->napi);
703 canfd_driver_stop(ndev);
705 free_irq(ndev->irq, ndev);
711 static enum can_state get_of_chip_status(struct net_device *ndev)
713 struct ipms_canfd_priv *priv = netdev_priv(ndev);
716 can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
717 eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
719 if (can_stat & CAN_FD_SET_BUSOFF_MASK)
720 return CAN_STATE_BUS_OFF;
722 if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK))
723 return CAN_STATE_ERROR_PASSIVE;
725 if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK))
726 return CAN_STATE_ERROR_WARNING;
728 if (~(eir & CAN_FD_SET_EPASS_MASK))
729 return CAN_STATE_ERROR_ACTIVE;
732 static void canfd_error_interrupt(struct net_device *ndev, u8 isr, u8 eir)
734 struct ipms_canfd_priv *priv = netdev_priv(ndev);
735 struct net_device_stats *stats = &ndev->stats;
736 struct can_frame *cf;
738 u8 koer, recnt = 0, tecnt = 0, can_stat = 0;
740 skb = alloc_can_err_skb(ndev, &cf);
742 koer = can_ioread8(priv->reg_base + CANFD_EALCAP_OFFSET) & CAN_FD_SET_KOER_MASK;
743 recnt = can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET);
744 tecnt = can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET);
747 can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
749 /* Bus off --->active error mode */
750 if ((isr & CAN_FD_SET_EIF_MASK) && priv->can.state == CAN_STATE_BUS_OFF)
751 priv->can.state = get_of_chip_status(ndev);
753 /* State selection */
754 if (can_stat & CAN_FD_SET_BUSOFF_MASK) {
755 priv->can.state = get_of_chip_status(ndev);
756 priv->can.can_stats.bus_off++;
757 canfd_reigister_set_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_SET_BUSOFF_MASK);
760 cf->can_id |= CAN_ERR_BUSOFF;
762 } else if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK)) {
763 priv->can.state = get_of_chip_status(ndev);
764 priv->can.can_stats.error_passive++;
766 cf->can_id |= CAN_ERR_CRTL;
767 cf->data[1] |= (recnt > 127) ? CAN_ERR_CRTL_RX_PASSIVE : 0;
768 cf->data[1] |= (tecnt > 127) ? CAN_ERR_CRTL_TX_PASSIVE : 0;
772 } else if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK)) {
773 priv->can.state = get_of_chip_status(ndev);
774 priv->can.can_stats.error_warning++;
776 cf->can_id |= CAN_ERR_CRTL;
777 cf->data[1] |= (recnt > 95) ? CAN_ERR_CRTL_RX_WARNING : 0;
778 cf->data[1] |= (tecnt > 95) ? CAN_ERR_CRTL_TX_WARNING : 0;
784 /* Check for in protocol defined error interrupt */
785 if (eir & CAN_FD_SET_BEIF_MASK) {
787 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
789 /* bit error interrupt */
790 if (koer == CAN_FD_SET_BIT_ERROR_MASK) {
793 cf->can_id |= CAN_ERR_PROT;
794 cf->data[2] = CAN_ERR_PROT_BIT;
797 /* format error interrupt */
798 if (koer == CAN_FD_SET_FORM_ERROR_MASK) {
801 cf->can_id |= CAN_ERR_PROT;
802 cf->data[2] = CAN_ERR_PROT_FORM;
805 /* stuffing error interrupt */
806 if (koer == CAN_FD_SET_STUFF_ERROR_MASK) {
809 cf->can_id |= CAN_ERR_PROT;
810 cf->data[3] = CAN_ERR_PROT_STUFF;
813 /* ack error interrupt */
814 if (koer == CAN_FD_SET_ACK_ERROR_MASK) {
817 cf->can_id |= CAN_ERR_PROT;
818 cf->data[2] = CAN_ERR_PROT_LOC_ACK;
821 /* crc error interrupt */
822 if (koer == CAN_FD_SET_CRC_ERROR_MASK) {
825 cf->can_id |= CAN_ERR_PROT;
826 cf->data[2] = CAN_ERR_PROT_LOC_CRC_SEQ;
829 priv->can.can_stats.bus_error++;
833 stats->rx_bytes += cf->can_dlc;
837 netdev_dbg(ndev, "Recnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET));
838 netdev_dbg(ndev, "Tecnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET));
841 static irqreturn_t canfd_interrupt(int irq, void *dev_id)
843 struct net_device *ndev = (struct net_device *)dev_id;
844 struct ipms_canfd_priv *priv = netdev_priv(ndev);
846 u8 isr_handled = 0, eir_handled = 0;
848 /* read the value of interrupt status register */
849 isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
851 /* read the value of error interrupt register */
852 eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
854 /* Check for Tx interrupt and Processing it */
855 if (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
856 canfd_tx_interrupt(ndev, isr);
857 isr_handled |= (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK);
859 if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK)) {
860 canfd_rxfull_interrupt(ndev, isr);
861 isr_handled |= (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK);
863 /* Check Rx interrupt and Processing the receive interrupt routine */
864 if (isr & CAN_FD_SET_RIF_MASK) {
865 canfd_reigister_off_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_OFF_RIE_MASK);
866 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RIF_MASK);
868 napi_schedule(&priv->napi);
869 isr_handled |= CAN_FD_SET_RIF_MASK;
871 if ((isr & CAN_FD_SET_EIF_MASK) | (eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK))) {
872 /* reset EPIF and BEIF. Reset EIF */
873 canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET,
874 eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK));
875 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
876 isr & CAN_FD_SET_EIF_MASK);
878 canfd_error_interrupt(ndev, isr, eir);
880 isr_handled |= CAN_FD_SET_EIF_MASK;
881 eir_handled |= (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK);
883 if ((isr_handled == 0) && (eir_handled == 0)) {
884 netdev_err(ndev, "Unhandled interrupt!\n");
891 static int canfd_chip_start(struct net_device *ndev)
893 struct ipms_canfd_priv *priv = netdev_priv(ndev);
897 err = set_reset_mode(ndev);
899 netdev_err(ndev, "Mode Resetting Failed!\n");
903 err = canfd_device_driver_bittime_configuration(ndev);
905 netdev_err(ndev, "Bittime Setting Failed!\n");
909 /* Set Almost Full Warning Limit */
910 canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_AFWL_MASK);
912 /* Programmable Error Warning Limit = (EWL+1)*8. Set EWL=11->Error Warning=96 */
913 canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_EWL_MASK);
915 /* Interrupts enable */
916 can_iowrite8(CAN_FD_INTR_ALL_MASK, priv->reg_base + CANFD_RTIE_OFFSET);
918 /* Error Interrupts enable(Error Passive and Bus Error) */
919 canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET, CAN_FD_SET_EPIE_MASK);
921 ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
923 /* Check whether it is loopback mode or normal mode */
924 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
925 ret |= CAN_FD_LBMIMOD_MASK;
927 ret &= ~CAN_FD_LBMEMOD_MASK;
928 ret &= ~CAN_FD_LBMIMOD_MASK;
931 can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
933 priv->can.state = CAN_STATE_ERROR_ACTIVE;
938 static int canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
944 ret = canfd_chip_start(ndev);
946 netdev_err(ndev, "Could Not Start CAN device !!\n");
949 netif_wake_queue(ndev);
959 static int canfd_driver_open(struct net_device *ndev)
961 struct ipms_canfd_priv *priv = netdev_priv(ndev);
964 /* Set chip into reset mode */
965 ret = set_reset_mode(ndev);
967 netdev_err(ndev, "Mode Resetting Failed!\n");
972 ret = open_candev(ndev);
976 /* Register interrupt handler */
977 ret = request_irq(ndev->irq, canfd_interrupt, IRQF_SHARED, ndev->name, ndev);
979 netdev_err(ndev, "request_irq err: %d\n", ret);
983 ret = canfd_chip_start(ndev);
985 netdev_err(ndev, "Could Not Start CAN device !\n");
989 napi_enable(&priv->napi);
990 netif_start_queue(ndev);
995 free_irq(ndev->irq, ndev);
1001 static int canfd_control_enable(struct ipms_canfd_priv *priv)
1005 value = readl(priv->syscon_base + priv->syscon_offset);
1006 writel(value | priv->syscon_mask, priv->syscon_base + priv->syscon_offset);
1011 static int canfd_control_parse_dt(struct platform_device *pdev, struct ipms_canfd_priv *priv)
1013 struct resource *res_syscon;
1015 priv->enable_canfd = false;
1016 res_syscon = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sys_syscon");
1017 priv->syscon_base = ioremap(res_syscon->start, resource_size(res_syscon));
1018 if (IS_ERR(priv->syscon_base))
1019 return PTR_ERR(priv->syscon_base);
1021 if (!(device_property_read_u32(priv->dev, "syscon,canfd-offset", &priv->syscon_offset)))
1022 priv->enable_canfd = true;
1024 if (!(device_property_read_u32(priv->dev, "syscon,canfd-mask", &priv->syscon_mask)))
1025 priv->enable_canfd = priv->enable_canfd && true;
1027 if (device_property_read_bool(priv->dev, "syscon,canfd-enable"))
1028 priv->enable_canfd = priv->enable_canfd && true;
1030 priv->enable_canfd = priv->enable_canfd && false;
1035 static const struct net_device_ops canfd_netdev_ops = {
1036 .ndo_open = canfd_driver_open,
1037 .ndo_stop = canfd_driver_close,
1038 .ndo_start_xmit = canfd_driver_start_xmit,
1039 .ndo_change_mtu = can_change_mtu,
1042 static int canfd_driver_probe(struct platform_device *pdev)
1044 struct net_device *ndev;
1045 struct ipms_canfd_priv *priv;
1049 addr = devm_platform_ioremap_resource_byname(pdev, "reg_base");
1051 ret = PTR_ERR(addr);
1055 ndev = alloc_candev(sizeof(struct ipms_canfd_priv), 1);
1061 priv = netdev_priv(ndev);
1062 priv->dev = &pdev->dev;
1064 ret = canfd_control_parse_dt(pdev, priv);
1068 if (priv->enable_canfd)
1069 canfd_control_enable(priv);
1071 priv->clks = can_clks;
1072 priv->resets = can_resets;
1073 priv->nr_clks = ARRAY_SIZE(can_clks);
1074 priv->nr_rstcs = ARRAY_SIZE(can_resets);
1075 ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, priv->nr_rstcs, priv->resets);
1077 dev_err(priv->dev, "failed to get can reset controls\n");
1081 ret = devm_clk_bulk_get(&pdev->dev, priv->nr_clks, priv->clks);
1083 dev_err(priv->dev, "failed to get can clk controls\n");
1087 ret = clk_bulk_prepare_enable(priv->nr_clks, priv->clks);
1089 dev_err(priv->dev, "enable clk error.\n");
1093 ret = reset_control_bulk_deassert(priv->nr_rstcs, priv->resets);
1095 dev_err(priv->dev, "deassert can error.\n");
1099 priv->can.bittiming_const = &canfd_bittiming_const;
1100 priv->can.data_bittiming_const = &canfd_data_bittiming_const;
1101 priv->can.do_set_mode = canfd_do_set_mode;
1103 /* in user space the execution mode can be chosen */
1104 if (priv->enable_canfd)
1105 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_FD;
1107 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK;
1109 priv->reg_base = addr;
1110 priv->write_reg = canfd_write_reg_le;
1111 priv->read_reg = canfd_read_reg_le;
1112 priv->can_clk = devm_clk_get(&pdev->dev, "ipms_can_clk");
1113 if (IS_ERR(priv->can_clk)) {
1114 dev_err(&pdev->dev, "Device clock not found.\n");
1115 ret = PTR_ERR(priv->can_clk);
1119 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1121 ndev->irq = platform_get_irq(pdev, 0);
1123 /* we support local echo */
1124 ndev->flags |= IFF_ECHO;
1125 ndev->netdev_ops = &canfd_netdev_ops;
1127 platform_set_drvdata(pdev, ndev);
1128 SET_NETDEV_DEV(ndev, &pdev->dev);
1130 netif_napi_add(ndev, &priv->napi, canfd_rx_poll, 16);
1132 ret = register_candev(ndev);
1134 dev_err(&pdev->dev, "Fail to register failed (err=%d)\n", ret);
1138 dev_dbg(&pdev->dev, "Driver registered: regs=%p, irp=%d, clock=%d\n",
1139 priv->reg_base, ndev->irq, priv->can.clock.freq);
1144 reset_control_bulk_assert(priv->nr_rstcs, priv->resets);
1146 clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1148 iounmap(priv->syscon_base);
1154 static int canfd_driver_remove(struct platform_device *pdev)
1156 struct net_device *ndev = platform_get_drvdata(pdev);
1157 struct ipms_canfd_priv *priv = netdev_priv(ndev);
1159 reset_control_bulk_assert(priv->nr_rstcs, priv->resets);
1160 clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1162 iounmap(priv->syscon_base);
1163 unregister_candev(ndev);
1164 netif_napi_del(&priv->napi);
1170 static const struct of_device_id canfd_of_match[] = {
1171 { .compatible = "ipms,can" },
1174 MODULE_DEVICE_TABLE(of, canfd_of_match);
1176 static struct platform_driver can_driver = {
1177 .probe = canfd_driver_probe,
1178 .remove = canfd_driver_remove,
1180 .name = DRIVER_NAME,
1181 .of_match_table = canfd_of_match,
1185 module_platform_driver(can_driver);
1186 MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
1187 MODULE_LICENSE("GPL v2");
1188 MODULE_DESCRIPTION("ipms can controller driver");