drivers/net/can/ipms_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2021 StarFive, Inc <jenny.zhang@starfivetech.com>
   4  *
   5  * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
   6  * CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER
   7  * FOR THEM TO SAVE TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE
   8  * FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
   9  * CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE
  10  * BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION
  11  * WITH THEIR PRODUCTS.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/reset.h>
  16 #include <linux/errno.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/skbuff.h>
  26 #include <linux/string.h>
  27 #include <linux/types.h>
  28 #include <linux/can/dev.h>
  29 #include <linux/can/error.h>
  30 #include <linux/can/led.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of_device.h>
  33 #include <linux/mfd/syscon.h>
  34 #include <linux/regmap.h>
  35
  36 #define DRIVER_NAME "ipms_canfd"
  37
  38 /* CAN registers set */
  39 enum canfd_device_reg {
  40         CANFD_RUBF_OFFSET           =   0x00,   /* Receive Buffer Registers 0x00-0x4f */
  41         CANFD_RUBF_ID_OFFSET        =   0x00,
  42         CANFD_RBUF_CTL_OFFSET       =   0x04,
  43         CANFD_RBUF_DATA_OFFSET      =   0x08,
  44         CANFD_TBUF_OFFSET           =   0x50,   /* Transmit Buffer Registers 0x50-0x97 */
  45         CANFD_TBUF_ID_OFFSET        =   0x50,
  46         CANFD_TBUF_CTL_OFFSET       =   0x54,
  47         CANFD_TBUF_DATA_OFFSET      =   0x58,
  48         CANFD_TTS_OFFSET            =   0x98,   /* Transmission Time Stamp 0x98-0x9f */
  49         CANFD_CFG_STAT_OFFSET       =   0xa0,
  50         CANFD_TCMD_OFFSET           =   0xa1,
  51         CANFD_TCTRL_OFFSET          =   0xa2,
  52         CANFD_RCTRL_OFFSET          =   0xa3,
  53         CANFD_RTIE_OFFSET           =   0xa4,
  54         CANFD_RTIF_OFFSET           =   0xa5,
  55         CANFD_ERRINT_OFFSET         =   0xa6,
  56         CANFD_LIMIT_OFFSET          =   0xa7,
  57         CANFD_S_SEG_1_OFFSET        =   0xa8,
  58         CANFD_S_SEG_2_OFFSET        =   0xa9,
  59         CANFD_S_SJW_OFFSET          =   0xaa,
  60         CANFD_S_PRESC_OFFSET        =   0xab,
  61         CANFD_F_SEG_1_OFFSET        =   0xac,
  62         CANFD_F_SEG_2_OFFSET        =   0xad,
  63         CANFD_F_SJW_OFFSET          =   0xae,
  64         CANFD_F_PRESC_OFFSET        =   0xaf,
  65         CANFD_EALCAP_OFFSET         =   0xb0,
  66         CANFD_RECNT_OFFSET          =   0xb2,
  67         CANFD_TECNT_OFFSET          =   0xb3,
  68 };
  69
  70 enum canfd_reg_bitchange {
  71         CAN_FD_SET_RST_MASK         =   0x80,   /* Set Reset Bit */
  72         CAN_FD_OFF_RST_MASK         =   0x7f,   /* Reset Off Bit */
  73         CAN_FD_SET_FULLCAN_MASK     =   0x10,   /* set TTTBM as 1->full TTCAN mode */
  74         CAN_FD_OFF_FULLCAN_MASK     =   0xef,   /* set TTTBM as 0->separate PTB and STB mode */
  75         CAN_FD_SET_FIFO_MASK        =   0x20,   /* set TSMODE as 1->FIFO mode */
  76         CAN_FD_OFF_FIFO_MASK        =   0xdf,   /* set TSMODE as 0->Priority mode */
  77         CAN_FD_SET_TSONE_MASK       =   0x04,
  78         CAN_FD_OFF_TSONE_MASK       =   0xfb,
  79         CAN_FD_SET_TSALL_MASK       =   0x02,
  80         CAN_FD_OFF_TSALL_MASK       =   0xfd,
  81         CAN_FD_LBMEMOD_MASK         =   0x40,   /* set loop back mode, external */
  82         CAN_FD_LBMIMOD_MASK         =   0x20,   /* set loopback internal mode */
  83         CAN_FD_SET_BUSOFF_MASK      =   0x01,
  84         CAN_FD_OFF_BUSOFF_MASK      =   0xfe,
  85         CAN_FD_SET_TTSEN_MASK       =   0x80,   /* set ttsen, tts update enable */
  86         CAN_FD_SET_BRS_MASK         =   0x10,   /* can fd Bit Rate Switch mask */
  87         CAN_FD_OFF_BRS_MASK         =   0xef,
  88         CAN_FD_SET_EDL_MASK         =   0x20,   /* Extended Data Length */
  89         CAN_FD_OFF_EDL_MASK         =   0xdf,
  90         CAN_FD_SET_DLC_MASK         =   0x0f,
  91         CAN_FD_SET_TENEXT_MASK      =   0x40,
  92         CAN_FD_SET_IDE_MASK         =   0x80,
  93         CAN_FD_OFF_IDE_MASK         =   0x7f,
  94         CAN_FD_SET_RTR_MASK         =   0x40,
  95         CAN_FD_OFF_RTR_MASK         =   0xbf,
  96         CAN_FD_INTR_ALL_MASK        =   0xff,   /* all interrupts enable mask */
  97         CAN_FD_SET_RIE_MASK         =   0x80,
  98         CAN_FD_OFF_RIE_MASK         =   0x7f,
  99         CAN_FD_SET_RFIE_MASK        =   0x20,
 100         CAN_FD_OFF_RFIE_MASK        =   0xdf,
 101         CAN_FD_SET_RAFIE_MASK       =   0x10,
 102         CAN_FD_OFF_RAFIE_MASK       =   0xef,
 103         CAN_FD_SET_EIE_MASK         =   0x02,
 104         CAN_FD_OFF_EIE_MASK         =   0xfd,
 105         CAN_FD_TASCTIVE_MASK        =   0x02,
 106         CAN_FD_RASCTIVE_MASK        =   0x04,
 107         CAN_FD_SET_TBSEL_MASK       =   0x80,   /* message writen in STB */
 108         CAN_FD_OFF_TBSEL_MASK       =   0x7f,   /* message writen in PTB */
 109         CAN_FD_SET_STBY_MASK        =   0x20,
 110         CAN_FD_OFF_STBY_MASK        =   0xdf,
 111         CAN_FD_SET_TPE_MASK         =   0x10,   /* Transmit primary enable */
 112         CAN_FD_SET_TPA_MASK         =   0x08,
 113         CAN_FD_SET_SACK_MASK        =   0x80,
 114         CAN_FD_SET_RREL_MASK        =   0x10,
 115         CAN_FD_RSTAT_NOT_EMPTY_MASK =   0x03,
 116         CAN_FD_SET_RIF_MASK         =   0x80,
 117         CAN_FD_OFF_RIF_MASK         =   0x7f,
 118         CAN_FD_SET_RAFIF_MASK       =   0x10,
 119         CAN_FD_SET_RFIF_MASK        =   0x20,
 120         CAN_FD_SET_TPIF_MASK        =   0x08,   /* Transmission Primary Interrupt Flag */
 121         CAN_FD_SET_TSIF_MASK        =   0x04,
 122         CAN_FD_SET_EIF_MASK         =   0x02,
 123         CAN_FD_SET_AIF_MASK         =   0x01,
 124         CAN_FD_SET_EWARN_MASK       =   0x80,
 125         CAN_FD_SET_EPASS_MASK       =   0x40,
 126         CAN_FD_SET_EPIE_MASK        =   0x20,
 127         CAN_FD_SET_EPIF_MASK        =   0x10,
 128         CAN_FD_SET_ALIE_MASK        =   0x08,
 129         CAN_FD_SET_ALIF_MASK        =   0x04,
 130         CAN_FD_SET_BEIE_MASK        =   0x02,
 131         CAN_FD_SET_BEIF_MASK        =   0x01,
 132         CAN_FD_OFF_EPIE_MASK        =   0xdf,
 133         CAN_FD_OFF_BEIE_MASK        =   0xfd,
 134         CAN_FD_SET_AFWL_MASK        =   0x40,
 135         CAN_FD_SET_EWL_MASK         =   0x0b,
 136         CAN_FD_SET_KOER_MASK        =   0xe0,
 137         CAN_FD_SET_BIT_ERROR_MASK   =   0x20,
 138         CAN_FD_SET_FORM_ERROR_MASK  =   0x40,
 139         CAN_FD_SET_STUFF_ERROR_MASK =   0x60,
 140         CAN_FD_SET_ACK_ERROR_MASK   =   0x80,
 141         CAN_FD_SET_CRC_ERROR_MASK   =   0xa0,
 142         CAN_FD_SET_OTH_ERROR_MASK   =   0xc0,
 143 };
 144
 145 /* seg1,seg2,sjw,prescaler all have 8 bits */
 146 #define BITS_OF_BITTIMING_REG           8
 147
 148 /* in can_bittiming strucure every field has 32 bits---->u32 */
 149 #define FBITS_IN_BITTIMING_STR          32
 150 #define SEG_1_SHIFT                     0
 151 #define SEG_2_SHIFT                     8
 152 #define SJW_SHIFT                       16
 153 #define PRESC_SHIFT                     24
 154
 155 /* TTSEN bit used for 32 bit register read or write */
 156 #define TTSEN_8_32_SHIFT                24
 157 #define RTR_32_8_SHIFT                  24
 158
 159 /* transmit mode */
 160 #define XMIT_FULL                       0
 161 #define XMIT_SEP_FIFO                   1
 162 #define XMIT_SEP_PRIO                   2
 163 #define XMIT_PTB_MODE                   3
 164
 165 enum  IPMS_CAN_TYPE {
 166         IPMS_CAN_TYPY_CAN       = 0,
 167         IPMS_CAN_TYPE_CANFD,
 168 };
 169
 170 struct ipms_canfd_priv {
 171         struct can_priv can;
 172         struct napi_struct napi;
 173         struct device *dev;
 174         struct regmap *reg_syscon;
 175         void __iomem *reg_base;
 176         u32 (*read_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg);
 177         void (*write_reg)(const struct ipms_canfd_priv *priv, enum canfd_device_reg reg, u32 val);
 178         struct clk *can_clk;
 179         u32 tx_mode;
 180         struct reset_control *resets;
 181         struct clk_bulk_data *clks;
 182         int nr_clks;
 183         u32 can_or_canfd;
 184 };
 185
 186 static struct can_bittiming_const canfd_bittiming_const = {
 187         .name = DRIVER_NAME,
 188         .tseg1_min = 2,
 189         .tseg1_max = 65,
 190         .tseg2_min = 1,
 191         .tseg2_max = 8,
 192         .sjw_max = 16,
 193         .brp_min = 1,
 194         .brp_max = 512,
 195         .brp_inc = 1,
 196
 197 };
 198
 199 static struct can_bittiming_const canfd_data_bittiming_const = {
 200         .name = DRIVER_NAME,
 201         .tseg1_min = 2,
 202         .tseg1_max = 17,
 203         .tseg2_min = 1,
 204         .tseg2_max = 8,
 205         .sjw_max = 8,
 206         .brp_min = 1,
 207         .brp_max = 512,
 208         .brp_inc = 1,
 209 };
 210
 211 static void canfd_write_reg_le(const struct ipms_canfd_priv *priv,
 212                                 enum canfd_device_reg reg, u32 val)
 213 {
 214         iowrite32(val, priv->reg_base + reg);
 215 }
 216
 217 static u32 canfd_read_reg_le(const struct ipms_canfd_priv *priv,
 218                                 enum canfd_device_reg reg)
 219 {
 220         return ioread32(priv->reg_base + reg);
 221 }
 222
 223 static inline unsigned char can_ioread8(const void  *addr)
 224 {
 225         void  *addr_down;
 226         union val {
 227                 u8 val_8[4];
 228                 u32 val_32;
 229         } val;
 230         u32 offset = 0;
 231
 232         addr_down = (void  *)ALIGN_DOWN((unsigned long)addr, 4);
 233         offset = addr - addr_down;
 234         val.val_32 = ioread32(addr_down);
 235         return val.val_8[offset];
 236 }
 237
 238 static inline void can_iowrite8(unsigned char value, void  *addr)
 239 {
 240         void  *addr_down;
 241         union val {
 242                 u8 val_8[4];
 243                 u32 val_32;
 244         } val;
 245         u8 offset = 0;
 246
 247         addr_down = (void *)ALIGN_DOWN((unsigned long)addr, 4);
 248         offset = addr - addr_down;
 249         val.val_32 = ioread32(addr_down);
 250         val.val_8[offset] = value;
 251         iowrite32(val.val_32, addr_down);
 252 }
 253
 254 static void canfd_reigister_set_bit(const struct ipms_canfd_priv *priv,
 255                                         enum canfd_device_reg reg,
 256                                         enum canfd_reg_bitchange set_mask)
 257 {
 258         void  *addr_down;
 259         union val {
 260                 u8 val_8[4];
 261                 u32 val_32;
 262         } val;
 263         u8 offset = 0;
 264
 265         addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
 266         offset = (priv->reg_base + reg) - addr_down;
 267         val.val_32 = ioread32(addr_down);
 268         val.val_8[offset] |= set_mask;
 269         iowrite32(val.val_32, addr_down);
 270 }
 271
 272 static void canfd_reigister_off_bit(const struct ipms_canfd_priv *priv,
 273                                         enum canfd_device_reg reg,
 274                                         enum canfd_reg_bitchange set_mask)
 275 {
 276         void  *addr_down;
 277         union val {
 278                 u8 val_8[4];
 279                 u32 val_32;
 280         } val;
 281         u8 offset = 0;
 282
 283         addr_down = (void *)ALIGN_DOWN((unsigned long)(priv->reg_base + reg), 4);
 284         offset = (priv->reg_base + reg) - addr_down;
 285         val.val_32 = ioread32(addr_down);
 286         val.val_8[offset] &= set_mask;
 287         iowrite32(val.val_32, addr_down);
 288 }
 289
 290 static int canfd_device_driver_bittime_configuration(struct net_device *ndev)
 291 {
 292         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 293         struct can_bittiming *bt = &priv->can.bittiming;
 294         struct can_bittiming *dbt = &priv->can.data_bittiming;
 295         u32 reset_test, bittiming_temp, dat_bittiming;
 296
 297         reset_test = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 298
 299         if (!(reset_test & CAN_FD_SET_RST_MASK)) {
 300                 netdev_alert(ndev, "Not in reset mode, cannot set bit timing\n");
 301                 return -EPERM;
 302         }
 303
 304         bittiming_temp = ((bt->phase_seg1 + bt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
 305                          ((bt->phase_seg2 - 1) << SEG_2_SHIFT) |
 306                          ((bt->sjw - 1) << SJW_SHIFT) |
 307                          ((bt->brp - 1) << PRESC_SHIFT);
 308
 309         /* Check the bittime parameter */
 310         if ((((int)(bt->phase_seg1 + bt->prop_seg + 1) - 2) < 0) ||
 311                 (((int)(bt->phase_seg2) - 1) < 0) ||
 312                 (((int)(bt->sjw) - 1) < 0) ||
 313                 (((int)(bt->brp) - 1) < 0))
 314                 return -EINVAL;
 315
 316         priv->write_reg(priv, CANFD_S_SEG_1_OFFSET, bittiming_temp);
 317
 318         if (priv->can_or_canfd == IPMS_CAN_TYPE_CANFD) {
 319                 dat_bittiming = ((dbt->phase_seg1 + dbt->prop_seg + 1 - 2) << SEG_1_SHIFT) |
 320                                 ((dbt->phase_seg2 - 1) << SEG_2_SHIFT) |
 321                                 ((dbt->sjw - 1) << SJW_SHIFT) |
 322                                 ((dbt->brp - 1) << PRESC_SHIFT);
 323
 324                 if ((((int)(dbt->phase_seg1 + dbt->prop_seg + 1) - 2) < 0) ||
 325                         (((int)(dbt->phase_seg2) - 1) < 0) ||
 326                         (((int)(dbt->sjw) - 1) < 0) ||
 327                         (((int)(dbt->brp) - 1) < 0))
 328                         return -EINVAL;
 329
 330                 priv->write_reg(priv, CANFD_F_SEG_1_OFFSET, dat_bittiming);
 331         }
 332
 333         canfd_reigister_off_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_OFF_RST_MASK);
 334
 335         netdev_dbg(ndev, "Slow bit rate: %08x\n", priv->read_reg(priv, CANFD_S_SEG_1_OFFSET));
 336         netdev_dbg(ndev, "Fast bit rate: %08x\n", priv->read_reg(priv, CANFD_F_SEG_1_OFFSET));
 337
 338         return 0;
 339 }
 340
 341 int canfd_get_freebuffer(struct ipms_canfd_priv *priv)
 342 {
 343         /* Get next transmit buffer */
 344         canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_TENEXT_MASK);
 345
 346         if (can_ioread8(priv->reg_base + CANFD_TCTRL_OFFSET) & CAN_FD_SET_TENEXT_MASK)
 347                 return -1;
 348
 349         return 0;
 350 }
 351
 352 static void canfd_tx_interrupt(struct net_device *ndev, u8 isr)
 353 {
 354         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 355
 356         /* wait till transmission of the PTB or STB finished */
 357         while (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
 358                 if (isr & CAN_FD_SET_TPIF_MASK)
 359                         canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TPIF_MASK);
 360
 361                 if (isr & CAN_FD_SET_TSIF_MASK)
 362                         canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_TSIF_MASK);
 363
 364                 isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
 365         }
 366         netif_wake_queue(ndev);
 367 }
 368
 369 static int can_rx(struct net_device *ndev)
 370 {
 371         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 372         struct net_device_stats *stats = &ndev->stats;
 373         struct can_frame *cf;
 374         struct sk_buff *skb;
 375         u32 can_id;
 376         u8  dlc, control, rx_status;
 377
 378         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 379
 380         if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
 381                 return 0;
 382         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 383         can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
 384         dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
 385
 386         skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
 387         if (!skb) {
 388                 stats->rx_dropped++;
 389                 return 0;
 390         }
 391         cf->can_dlc = can_cc_dlc2len(dlc);
 392
 393         /* change the CANFD id into socketcan id format */
 394         if (control & CAN_FD_SET_IDE_MASK) {
 395                 cf->can_id = can_id;
 396                 cf->can_id |= CAN_EFF_FLAG;
 397         } else {
 398                 cf->can_id = can_id;
 399                 cf->can_id &= (~CAN_EFF_FLAG);
 400         }
 401
 402         if (control & CAN_FD_SET_RTR_MASK)
 403                 cf->can_id |= CAN_RTR_FLAG;
 404
 405         if (!(control & CAN_FD_SET_RTR_MASK)) {
 406                 *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
 407                 *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
 408         }
 409
 410         canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
 411         stats->rx_bytes += can_fd_dlc2len(cf->can_dlc);
 412         stats->rx_packets++;
 413         netif_receive_skb(skb);
 414
 415         return 1;
 416 }
 417
 418 static int canfd_rx(struct net_device *ndev)
 419 {
 420         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 421         struct net_device_stats *stats = &ndev->stats;
 422         struct canfd_frame *cf;
 423         struct sk_buff *skb;
 424         u32 can_id;
 425         u8  dlc, control, rx_status;
 426         int i;
 427
 428         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 429
 430         if (!(rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK))
 431                 return 0;
 432         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 433         can_id = priv->read_reg(priv, CANFD_RUBF_ID_OFFSET);
 434         dlc = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET) & CAN_FD_SET_DLC_MASK;
 435
 436         if (control & CAN_FD_SET_EDL_MASK)
 437                 /* allocate sk_buffer for canfd frame */
 438                 skb = alloc_canfd_skb(ndev, &cf);
 439         else
 440                 /* allocate sk_buffer for can frame */
 441                 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
 442
 443         if (!skb) {
 444                 stats->rx_dropped++;
 445                 return 0;
 446         }
 447
 448         /* change the CANFD or CAN2.0 data into socketcan data format */
 449         if (control & CAN_FD_SET_EDL_MASK)
 450                 cf->len = can_fd_dlc2len(dlc);
 451         else
 452                 cf->len = can_cc_dlc2len(dlc);
 453
 454         /* change the CANFD id into socketcan id format */
 455         if (control & CAN_FD_SET_EDL_MASK) {
 456                 cf->can_id = can_id;
 457                 if (control & CAN_FD_SET_IDE_MASK)
 458                         cf->can_id |= CAN_EFF_FLAG;
 459                 else
 460                         cf->can_id &= (~CAN_EFF_FLAG);
 461         } else {
 462                 cf->can_id = can_id;
 463                 if (control & CAN_FD_SET_IDE_MASK)
 464                         cf->can_id |= CAN_EFF_FLAG;
 465                 else
 466                         cf->can_id &= (~CAN_EFF_FLAG);
 467
 468                 if (control & CAN_FD_SET_RTR_MASK)
 469                         cf->can_id |= CAN_RTR_FLAG;
 470         }
 471
 472         /* CANFD frames handed over to SKB */
 473         if (control & CAN_FD_SET_EDL_MASK) {
 474                 for (i = 0; i < cf->len; i += 4)
 475                         *((u32 *)(cf->data + i)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + i);
 476         } else {
 477                 /* skb reads the received datas, if the RTR bit not set */
 478                 if (!(control & CAN_FD_SET_RTR_MASK)) {
 479                         *((u32 *)(cf->data + 0)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET);
 480                         *((u32 *)(cf->data + 4)) = priv->read_reg(priv, CANFD_RBUF_DATA_OFFSET + 4);
 481                 }
 482         }
 483
 484         canfd_reigister_set_bit(priv, CANFD_RCTRL_OFFSET, CAN_FD_SET_RREL_MASK);
 485
 486         stats->rx_bytes += cf->len;
 487         stats->rx_packets++;
 488         netif_receive_skb(skb);
 489
 490         return 1;
 491 }
 492
 493 static int canfd_rx_poll(struct napi_struct *napi, int quota)
 494 {
 495         struct net_device *ndev = napi->dev;
 496         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 497         int work_done = 0;
 498         u8 rx_status = 0, control = 0;
 499
 500         control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 501         rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 502
 503         /* clear receive interrupt and deal with all the received frames */
 504         while ((rx_status & CAN_FD_RSTAT_NOT_EMPTY_MASK) && (work_done < quota)) {
 505                 (control & CAN_FD_SET_EDL_MASK) ? (work_done += canfd_rx(ndev)) : (work_done += can_rx(ndev));
 506
 507                 control = can_ioread8(priv->reg_base + CANFD_RBUF_CTL_OFFSET);
 508                 rx_status = can_ioread8(priv->reg_base + CANFD_RCTRL_OFFSET);
 509         }
 510         napi_complete(napi);
 511         canfd_reigister_set_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_SET_RIE_MASK);
 512         return work_done;
 513 }
 514
 515 static void canfd_rxfull_interrupt(struct net_device *ndev, u8 isr)
 516 {
 517         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 518
 519         if (isr & CAN_FD_SET_RAFIF_MASK)
 520                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RAFIF_MASK);
 521
 522         if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK))
 523                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
 524                                         (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK));
 525 }
 526
 527 static int set_canfd_xmit_mode(struct net_device *ndev)
 528 {
 529         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 530
 531         switch (priv->tx_mode) {
 532         case XMIT_FULL:
 533                 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FULLCAN_MASK);
 534                 break;
 535         case XMIT_SEP_FIFO:
 536                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
 537                 canfd_reigister_set_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_SET_FIFO_MASK);
 538                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
 539                 break;
 540         case XMIT_SEP_PRIO:
 541                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FULLCAN_MASK);
 542                 canfd_reigister_off_bit(priv, CANFD_TCTRL_OFFSET, CAN_FD_OFF_FIFO_MASK);
 543                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TBSEL_MASK);
 544                 break;
 545         case XMIT_PTB_MODE:
 546                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_TBSEL_MASK);
 547                 break;
 548         default:
 549                 break;
 550         }
 551         return 0;
 552 }
 553
 554 static netdev_tx_t canfd_driver_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 555 {
 556         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 557         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
 558         struct net_device_stats *stats = &ndev->stats;
 559         u32 ttsen, id, ctl, addr_off;
 560         int i;
 561
 562         priv->tx_mode = XMIT_PTB_MODE;
 563
 564         switch (priv->tx_mode) {
 565         case XMIT_FULL:
 566                 return NETDEV_TX_BUSY;
 567         case XMIT_PTB_MODE:
 568                 set_canfd_xmit_mode(ndev);
 569                 canfd_reigister_off_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_OFF_STBY_MASK);
 570
 571                 if (cf->can_id & CAN_EFF_FLAG) {
 572                         id = (cf->can_id & CAN_EFF_MASK);
 573                         ttsen = 0 << TTSEN_8_32_SHIFT;
 574                         id |= ttsen;
 575                 } else {
 576                         id = (cf->can_id & CAN_SFF_MASK);
 577                         ttsen = 0 << TTSEN_8_32_SHIFT;
 578                         id |= ttsen;
 579                 }
 580
 581                 ctl = can_fd_len2dlc(cf->len);
 582
 583                 /* transmit can fd frame */
 584                 if (priv->can_or_canfd == IPMS_CAN_TYPE_CANFD) {
 585                         if (can_is_canfd_skb(skb)) {
 586                                 if (cf->can_id & CAN_EFF_FLAG)
 587                                         ctl |= CAN_FD_SET_IDE_MASK;
 588                                 else
 589                                         ctl &= CAN_FD_OFF_IDE_MASK;
 590
 591                                 if (cf->flags & CANFD_BRS)
 592                                         ctl |= CAN_FD_SET_BRS_MASK;
 593
 594                                 ctl |= CAN_FD_SET_EDL_MASK;
 595
 596                                 addr_off = CANFD_TBUF_DATA_OFFSET;
 597
 598                                 for (i = 0; i < cf->len; i += 4) {
 599                                         priv->write_reg(priv, addr_off,
 600                                                         *((u32 *)(cf->data + i)));
 601                                         addr_off += 4;
 602                                 }
 603                         } else {
 604                                 ctl &= CAN_FD_OFF_EDL_MASK;
 605                                 ctl &= CAN_FD_OFF_BRS_MASK;
 606
 607                                 if (cf->can_id & CAN_EFF_FLAG)
 608                                         ctl |= CAN_FD_SET_IDE_MASK;
 609                                 else
 610                                         ctl &= CAN_FD_OFF_IDE_MASK;
 611
 612                                 if (cf->can_id & CAN_RTR_FLAG) {
 613                                         ctl |= CAN_FD_SET_RTR_MASK;
 614                                         priv->write_reg(priv,
 615                                                 CANFD_TBUF_ID_OFFSET, id);
 616                                         priv->write_reg(priv,
 617                                                 CANFD_TBUF_CTL_OFFSET, ctl);
 618                                 } else {
 619                                         ctl &= CAN_FD_OFF_RTR_MASK;
 620                                         addr_off = CANFD_TBUF_DATA_OFFSET;
 621                                         priv->write_reg(priv, addr_off,
 622                                                         *((u32 *)(cf->data + 0)));
 623                                         priv->write_reg(priv, addr_off + 4,
 624                                                         *((u32 *)(cf->data + 4)));
 625                                 }
 626                         }
 627                         priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 628                         priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 629                         addr_off = CANFD_TBUF_DATA_OFFSET;
 630                 } else {
 631                         ctl &= CAN_FD_OFF_EDL_MASK;
 632                         ctl &= CAN_FD_OFF_BRS_MASK;
 633
 634                         if (cf->can_id & CAN_EFF_FLAG)
 635                                 ctl |= CAN_FD_SET_IDE_MASK;
 636                         else
 637                                 ctl &= CAN_FD_OFF_IDE_MASK;
 638
 639                         if (cf->can_id & CAN_RTR_FLAG) {
 640                                 ctl |= CAN_FD_SET_RTR_MASK;
 641                                 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 642                                 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 643                         } else {
 644                                 ctl &= CAN_FD_OFF_RTR_MASK;
 645                                 priv->write_reg(priv, CANFD_TBUF_ID_OFFSET, id);
 646                                 priv->write_reg(priv, CANFD_TBUF_CTL_OFFSET, ctl);
 647                                 addr_off = CANFD_TBUF_DATA_OFFSET;
 648                                 priv->write_reg(priv, addr_off,
 649                                                 *((u32 *)(cf->data + 0)));
 650                                 priv->write_reg(priv, addr_off + 4,
 651                                                 *((u32 *)(cf->data + 4)));
 652                         }
 653                 }
 654                 canfd_reigister_set_bit(priv, CANFD_TCMD_OFFSET, CAN_FD_SET_TPE_MASK);
 655                 stats->tx_bytes += cf->len;
 656                 netif_stop_queue(ndev);
 657                 break;
 658         default:
 659                 break;
 660         }
 661
 662         return NETDEV_TX_OK;
 663 }
 664
 665 static int set_reset_mode(struct net_device *ndev)
 666 {
 667         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 668         u8 ret;
 669
 670         ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 671         ret |= CAN_FD_SET_RST_MASK;
 672         can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
 673
 674         return 0;
 675 }
 676
 677 static void canfd_driver_stop(struct net_device *ndev)
 678 {
 679         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 680         int ret;
 681
 682         ret = set_reset_mode(ndev);
 683         if (ret)
 684                 netdev_err(ndev, "Mode Resetting Failed!\n");
 685
 686         priv->can.state = CAN_STATE_STOPPED;
 687 }
 688
 689 static int canfd_driver_close(struct net_device *ndev)
 690 {
 691         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 692
 693         netif_stop_queue(ndev);
 694         napi_disable(&priv->napi);
 695         canfd_driver_stop(ndev);
 696
 697         free_irq(ndev->irq, ndev);
 698         close_candev(ndev);
 699
 700         pm_runtime_put(priv->dev);
 701
 702         return 0;
 703 }
 704
 705 static enum can_state get_of_chip_status(struct net_device *ndev)
 706 {
 707         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 708         u8 can_stat, eir;
 709
 710         can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 711         eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
 712
 713         if (can_stat & CAN_FD_SET_BUSOFF_MASK)
 714                 return CAN_STATE_BUS_OFF;
 715
 716         if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK))
 717                 return CAN_STATE_ERROR_PASSIVE;
 718
 719         if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK))
 720                 return CAN_STATE_ERROR_WARNING;
 721
 722         if (~(eir & CAN_FD_SET_EPASS_MASK))
 723                 return CAN_STATE_ERROR_ACTIVE;
 724
 725         return CAN_STATE_ERROR_ACTIVE;
 726 }
 727
 728 static void canfd_error_interrupt(struct net_device *ndev, u8 isr, u8 eir)
 729 {
 730         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 731         struct net_device_stats *stats = &ndev->stats;
 732         struct can_frame *cf;
 733         struct sk_buff *skb;
 734         u8 koer, recnt = 0, tecnt = 0, can_stat = 0;
 735
 736         skb = alloc_can_err_skb(ndev, &cf);
 737
 738         koer = can_ioread8(priv->reg_base + CANFD_EALCAP_OFFSET) & CAN_FD_SET_KOER_MASK;
 739         recnt = can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET);
 740         tecnt = can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET);
 741
 742         /*Read can status*/
 743         can_stat = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 744
 745         /* Bus off --->active error mode */
 746         if ((isr & CAN_FD_SET_EIF_MASK) && priv->can.state == CAN_STATE_BUS_OFF)
 747                 priv->can.state = get_of_chip_status(ndev);
 748
 749         /* State selection */
 750         if (can_stat & CAN_FD_SET_BUSOFF_MASK) {
 751                 priv->can.state = get_of_chip_status(ndev);
 752                 priv->can.can_stats.bus_off++;
 753                 canfd_reigister_set_bit(priv, CANFD_CFG_STAT_OFFSET, CAN_FD_SET_BUSOFF_MASK);
 754                 can_bus_off(ndev);
 755                 if (skb)
 756                         cf->can_id |= CAN_ERR_BUSOFF;
 757
 758         } else if ((eir & CAN_FD_SET_EPASS_MASK) && ~(can_stat & CAN_FD_SET_BUSOFF_MASK)) {
 759                 priv->can.state = get_of_chip_status(ndev);
 760                 priv->can.can_stats.error_passive++;
 761                 if (skb) {
 762                         cf->can_id |= CAN_ERR_CRTL;
 763                         cf->data[1] |= (recnt > 127) ? CAN_ERR_CRTL_RX_PASSIVE : 0;
 764                         cf->data[1] |= (tecnt > 127) ? CAN_ERR_CRTL_TX_PASSIVE : 0;
 765                         cf->data[6] = tecnt;
 766                         cf->data[7] = recnt;
 767                 }
 768         } else if (eir & CAN_FD_SET_EWARN_MASK && ~(eir & CAN_FD_SET_EPASS_MASK)) {
 769                 priv->can.state = get_of_chip_status(ndev);
 770                 priv->can.can_stats.error_warning++;
 771                 if (skb) {
 772                         cf->can_id |= CAN_ERR_CRTL;
 773                         cf->data[1] |= (recnt > 95) ? CAN_ERR_CRTL_RX_WARNING : 0;
 774                         cf->data[1] |= (tecnt > 95) ? CAN_ERR_CRTL_TX_WARNING : 0;
 775                         cf->data[6] = tecnt;
 776                         cf->data[7] = recnt;
 777                 }
 778         }
 779
 780         /* Check for in protocol defined error interrupt */
 781         if (eir & CAN_FD_SET_BEIF_MASK) {
 782                 if (skb)
 783                         cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 784
 785                 /* bit error interrupt */
 786                 if (koer == CAN_FD_SET_BIT_ERROR_MASK) {
 787                         stats->tx_errors++;
 788                         if (skb) {
 789                                 cf->can_id |= CAN_ERR_PROT;
 790                                 cf->data[2] = CAN_ERR_PROT_BIT;
 791                         }
 792                 }
 793                 /* format error interrupt */
 794                 if (koer == CAN_FD_SET_FORM_ERROR_MASK) {
 795                         stats->rx_errors++;
 796                         if (skb) {
 797                                 cf->can_id |= CAN_ERR_PROT;
 798                                 cf->data[2] = CAN_ERR_PROT_FORM;
 799                         }
 800                 }
 801                 /* stuffing error interrupt */
 802                 if (koer == CAN_FD_SET_STUFF_ERROR_MASK) {
 803                         stats->rx_errors++;
 804                         if (skb) {
 805                                 cf->can_id |= CAN_ERR_PROT;
 806                                 cf->data[3] = CAN_ERR_PROT_STUFF;
 807                         }
 808                 }
 809                 /* ack error interrupt */
 810                 if (koer == CAN_FD_SET_ACK_ERROR_MASK) {
 811                         stats->tx_errors++;
 812                         if (skb) {
 813                                 cf->can_id |= CAN_ERR_PROT;
 814                                 cf->data[2] = CAN_ERR_PROT_LOC_ACK;
 815                         }
 816                 }
 817                 /* crc error interrupt */
 818                 if (koer == CAN_FD_SET_CRC_ERROR_MASK) {
 819                         stats->rx_errors++;
 820                         if (skb) {
 821                                 cf->can_id |= CAN_ERR_PROT;
 822                                 cf->data[2] = CAN_ERR_PROT_LOC_CRC_SEQ;
 823                         }
 824                 }
 825                 priv->can.can_stats.bus_error++;
 826         }
 827         if (skb) {
 828                 stats->rx_packets++;
 829                 stats->rx_bytes += cf->can_dlc;
 830                 netif_rx(skb);
 831         }
 832
 833         netdev_dbg(ndev, "Recnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_RECNT_OFFSET));
 834         netdev_dbg(ndev, "Tecnt is 0x%02x", can_ioread8(priv->reg_base + CANFD_TECNT_OFFSET));
 835 }
 836
 837 static irqreturn_t canfd_interrupt(int irq, void *dev_id)
 838 {
 839         struct net_device *ndev = (struct net_device *)dev_id;
 840         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 841         u8 isr, eir;
 842         u8 isr_handled = 0, eir_handled = 0;
 843
 844         /* read the value of interrupt status register */
 845         isr = can_ioread8(priv->reg_base + CANFD_RTIF_OFFSET);
 846
 847         /* read the value of error interrupt register */
 848         eir = can_ioread8(priv->reg_base + CANFD_ERRINT_OFFSET);
 849
 850         /* Check for Tx interrupt and Processing it */
 851         if (isr & (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK)) {
 852                 canfd_tx_interrupt(ndev, isr);
 853                 isr_handled |= (CAN_FD_SET_TPIF_MASK | CAN_FD_SET_TSIF_MASK);
 854         }
 855         if (isr & (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK)) {
 856                 canfd_rxfull_interrupt(ndev, isr);
 857                 isr_handled |= (CAN_FD_SET_RAFIF_MASK | CAN_FD_SET_RFIF_MASK);
 858         }
 859         /* Check Rx interrupt and Processing the receive interrupt routine */
 860         if (isr & CAN_FD_SET_RIF_MASK) {
 861                 canfd_reigister_off_bit(priv, CANFD_RTIE_OFFSET, CAN_FD_OFF_RIE_MASK);
 862                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET, CAN_FD_SET_RIF_MASK);
 863
 864                 napi_schedule(&priv->napi);
 865                 isr_handled |= CAN_FD_SET_RIF_MASK;
 866         }
 867         if ((isr & CAN_FD_SET_EIF_MASK) | (eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK))) {
 868                 /* reset EPIF and BEIF. Reset EIF */
 869                 canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET,
 870                                         eir & (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK));
 871                 canfd_reigister_set_bit(priv, CANFD_RTIF_OFFSET,
 872                                         isr & CAN_FD_SET_EIF_MASK);
 873
 874                 canfd_error_interrupt(ndev, isr, eir);
 875
 876                 isr_handled |= CAN_FD_SET_EIF_MASK;
 877                 eir_handled |= (CAN_FD_SET_EPIF_MASK | CAN_FD_SET_BEIF_MASK);
 878         }
 879         if ((isr_handled == 0) && (eir_handled == 0)) {
 880                 netdev_err(ndev, "Unhandled interrupt!\n");
 881                 return IRQ_NONE;
 882         }
 883
 884         return IRQ_HANDLED;
 885 }
 886
 887 static int canfd_chip_start(struct net_device *ndev)
 888 {
 889         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 890         int err;
 891         u8 ret;
 892
 893         err = set_reset_mode(ndev);
 894         if (err) {
 895                 netdev_err(ndev, "Mode Resetting Failed!\n");
 896                 return err;
 897         }
 898
 899         err = canfd_device_driver_bittime_configuration(ndev);
 900         if (err) {
 901                 netdev_err(ndev, "Bittime Setting Failed!\n");
 902                 return err;
 903         }
 904
 905         /* Set Almost Full Warning Limit */
 906         canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_AFWL_MASK);
 907
 908         /* Programmable Error Warning Limit = (EWL+1)*8. Set EWL=11->Error Warning=96 */
 909         canfd_reigister_set_bit(priv, CANFD_LIMIT_OFFSET, CAN_FD_SET_EWL_MASK);
 910
 911         /* Interrupts enable */
 912         can_iowrite8(CAN_FD_INTR_ALL_MASK, priv->reg_base + CANFD_RTIE_OFFSET);
 913
 914         /* Error Interrupts enable(Error Passive and Bus Error) */
 915         canfd_reigister_set_bit(priv, CANFD_ERRINT_OFFSET, CAN_FD_SET_EPIE_MASK);
 916
 917         ret = can_ioread8(priv->reg_base + CANFD_CFG_STAT_OFFSET);
 918
 919         /* Check whether it is loopback mode or normal mode */
 920         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
 921                 ret |= CAN_FD_LBMIMOD_MASK;
 922         } else {
 923                 ret &= ~CAN_FD_LBMEMOD_MASK;
 924                 ret &= ~CAN_FD_LBMIMOD_MASK;
 925         }
 926
 927         can_iowrite8(ret, priv->reg_base + CANFD_CFG_STAT_OFFSET);
 928
 929         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 930
 931         return 0;
 932 }
 933
 934 static int  canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
 935 {
 936         int ret;
 937
 938         switch (mode) {
 939         case CAN_MODE_START:
 940                 ret = canfd_chip_start(ndev);
 941                 if (ret) {
 942                         netdev_err(ndev, "Could Not Start CAN device !!\n");
 943                         return ret;
 944                 }
 945                 netif_wake_queue(ndev);
 946                 break;
 947         default:
 948                 ret = -EOPNOTSUPP;
 949                 break;
 950         }
 951
 952         return ret;
 953 }
 954
 955 static int canfd_driver_open(struct net_device *ndev)
 956 {
 957         struct ipms_canfd_priv *priv = netdev_priv(ndev);
 958         int ret;
 959
 960         ret = pm_runtime_get_sync(priv->dev);
 961         if (ret < 0) {
 962                 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
 963                            __func__, ret);
 964                 goto err;
 965         }
 966
 967         /* Set chip into reset mode */
 968         ret = set_reset_mode(ndev);
 969         if (ret) {
 970                 netdev_err(ndev, "Mode Resetting Failed!\n");
 971                 return ret;
 972         }
 973
 974         /* Common open */
 975         ret = open_candev(ndev);
 976         if (ret)
 977                 return ret;
 978
 979         /* Register interrupt handler */
 980         ret = request_irq(ndev->irq, canfd_interrupt, IRQF_SHARED, ndev->name, ndev);
 981         if (ret) {
 982                 netdev_err(ndev, "Request_irq err: %d\n", ret);
 983                 goto exit_irq;
 984         }
 985
 986         ret = canfd_chip_start(ndev);
 987         if (ret) {
 988                 netdev_err(ndev, "Could Not Start CAN device !\n");
 989                 goto exit_can_start;
 990         }
 991
 992         napi_enable(&priv->napi);
 993         netif_start_queue(ndev);
 994
 995         return 0;
 996
 997 exit_can_start:
 998         free_irq(ndev->irq, ndev);
 999 err:
1000         pm_runtime_put(priv->dev);
1001 exit_irq:
1002         close_candev(ndev);
1003         return ret;
1004 }
1005
1006 static int canfd_control_parse_dt(struct ipms_canfd_priv *priv)
1007 {
1008         struct of_phandle_args args;
1009         u32 syscon_mask, syscon_shift;
1010         u32 can_or_canfd;
1011         u32 syscon_offset, regval;
1012         int ret;
1013
1014         ret = of_parse_phandle_with_fixed_args(priv->dev->of_node,
1015                                                 "starfive,sys-syscon", 3, 0, &args);
1016         if (ret) {
1017                 dev_err(priv->dev, "Failed to parse starfive,sys-syscon\n");
1018                 return -EINVAL;
1019         }
1020
1021         priv->reg_syscon = syscon_node_to_regmap(args.np);
1022         of_node_put(args.np);
1023         if (IS_ERR(priv->reg_syscon))
1024                 return PTR_ERR(priv->reg_syscon);
1025
1026         syscon_offset = args.args[0];
1027         syscon_shift  = args.args[1];
1028         syscon_mask   = args.args[2];
1029
1030         ret = device_property_read_u32(priv->dev, "syscon,can_or_canfd", &can_or_canfd);
1031         if (ret)
1032                 goto exit_parse;
1033
1034         priv->can_or_canfd = can_or_canfd;
1035
1036         /* enable can2.0/canfd function */
1037         regval = can_or_canfd << syscon_shift;
1038         ret = regmap_update_bits(priv->reg_syscon, syscon_offset, syscon_mask, regval);
1039         if (ret)
1040                 return ret;
1041         return 0;
1042 exit_parse:
1043         return ret;
1044 }
1045
1046 static const struct net_device_ops canfd_netdev_ops = {
1047         .ndo_open = canfd_driver_open,
1048         .ndo_stop = canfd_driver_close,
1049         .ndo_start_xmit = canfd_driver_start_xmit,
1050         .ndo_change_mtu = can_change_mtu,
1051 };
1052
1053 static int canfd_driver_probe(struct platform_device *pdev)
1054 {
1055         struct net_device *ndev;
1056         struct ipms_canfd_priv *priv;
1057         void __iomem *addr;
1058         int ret;
1059         u32 frq;
1060
1061         addr = devm_platform_ioremap_resource(pdev, 0);
1062         if (IS_ERR(addr)) {
1063                 ret = PTR_ERR(addr);
1064                 goto exit;
1065         }
1066
1067         ndev = alloc_candev(sizeof(struct ipms_canfd_priv), 1);
1068         if (!ndev) {
1069                 ret = -ENOMEM;
1070                 goto exit;
1071         }
1072
1073         priv = netdev_priv(ndev);
1074         priv->dev = &pdev->dev;
1075
1076         ret = canfd_control_parse_dt(priv);
1077         if (ret)
1078                 goto free_exit;
1079
1080         priv->nr_clks = devm_clk_bulk_get_all(priv->dev, &priv->clks);
1081         if (priv->nr_clks < 0) {
1082                 dev_err(priv->dev, "Failed to get can clocks\n");
1083                 ret = -ENODEV;
1084                 goto free_exit;
1085         }
1086
1087         ret = clk_bulk_prepare_enable(priv->nr_clks, priv->clks);
1088         if (ret) {
1089                 dev_err(priv->dev, "Failed to enable clocks\n");
1090                 goto free_exit;
1091         }
1092
1093         priv->resets = devm_reset_control_array_get_exclusive(priv->dev);
1094         if (IS_ERR(priv->resets)) {
1095                 ret = PTR_ERR(priv->resets);
1096                 dev_err(priv->dev, "Failed to get can resets");
1097                 goto clk_exit;
1098         }
1099
1100         ret = reset_control_deassert(priv->resets);
1101         if (ret)
1102                 goto clk_exit;
1103         priv->can.bittiming_const = &canfd_bittiming_const;
1104         priv->can.data_bittiming_const = &canfd_data_bittiming_const;
1105         priv->can.do_set_mode = canfd_do_set_mode;
1106
1107         /* in user space the execution mode can be chosen */
1108         if (priv->can_or_canfd == IPMS_CAN_TYPE_CANFD)
1109                 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_FD;
1110         else
1111                 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK;
1112         priv->reg_base = addr;
1113         priv->write_reg = canfd_write_reg_le;
1114         priv->read_reg = canfd_read_reg_le;
1115
1116         pm_runtime_enable(&pdev->dev);
1117
1118         priv->can_clk = devm_clk_get(&pdev->dev, "core_clk");
1119         if (IS_ERR(priv->can_clk)) {
1120                 dev_err(&pdev->dev, "Device clock not found.\n");
1121                 ret = PTR_ERR(priv->can_clk);
1122                 goto reset_exit;
1123         }
1124
1125         device_property_read_u32(priv->dev, "frequency", &frq);
1126         clk_set_rate(priv->can_clk, frq);
1127
1128         priv->can.clock.freq = clk_get_rate(priv->can_clk);
1129         ndev->irq = platform_get_irq(pdev, 0);
1130
1131         /* we support local echo */
1132         ndev->flags |= IFF_ECHO;
1133         ndev->netdev_ops = &canfd_netdev_ops;
1134
1135         platform_set_drvdata(pdev, ndev);
1136         SET_NETDEV_DEV(ndev, &pdev->dev);
1137
1138         netif_napi_add(ndev, &priv->napi, canfd_rx_poll, 16);
1139         ret = register_candev(ndev);
1140         if (ret) {
1141                 dev_err(&pdev->dev, "Fail to register failed (err=%d)\n", ret);
1142                 goto reset_exit;
1143         }
1144
1145         dev_dbg(&pdev->dev, "Driver registered: regs=%p, irp=%d, clock=%d\n",
1146                 priv->reg_base, ndev->irq, priv->can.clock.freq);
1147
1148         return 0;
1149
1150 reset_exit:
1151         reset_control_assert(priv->resets);
1152 clk_exit:
1153         clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1154 free_exit:
1155         free_candev(ndev);
1156 exit:
1157         return ret;
1158 }
1159
1160 static int canfd_driver_remove(struct platform_device *pdev)
1161 {
1162         struct net_device *ndev = platform_get_drvdata(pdev);
1163         struct ipms_canfd_priv *priv = netdev_priv(ndev);
1164
1165         reset_control_assert(priv->resets);
1166         clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1167         pm_runtime_disable(&pdev->dev);
1168
1169         unregister_candev(ndev);
1170         netif_napi_del(&priv->napi);
1171         free_candev(ndev);
1172
1173         return 0;
1174 }
1175
1176 #ifdef CONFIG_PM_SLEEP
1177 static int __maybe_unused canfd_suspend(struct device *dev)
1178 {
1179         struct net_device *ndev = dev_get_drvdata(dev);
1180
1181         if (netif_running(ndev)) {
1182                 netif_stop_queue(ndev);
1183                 netif_device_detach(ndev);
1184                 canfd_driver_stop(ndev);
1185         }
1186
1187         return pm_runtime_force_suspend(dev);
1188 }
1189
1190 static int __maybe_unused canfd_resume(struct device *dev)
1191 {
1192         struct net_device *ndev = dev_get_drvdata(dev);
1193         int ret;
1194
1195         ret = pm_runtime_force_resume(dev);
1196         if (ret) {
1197                 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
1198                 return ret;
1199         }
1200
1201         if (netif_running(ndev)) {
1202                 ret = canfd_chip_start(ndev);
1203                 if (ret) {
1204                         dev_err(dev, "canfd_chip_start failed on resume\n");
1205                         return ret;
1206                 }
1207
1208                 netif_device_attach(ndev);
1209                 netif_start_queue(ndev);
1210         }
1211
1212         return 0;
1213 }
1214 #endif
1215
1216 #ifdef CONFIG_PM
1217 static int canfd_runtime_suspend(struct device *dev)
1218 {
1219         struct ipms_canfd_priv *priv = dev_get_drvdata(dev);
1220
1221         reset_control_assert(priv->resets);
1222         clk_bulk_disable_unprepare(priv->nr_clks, priv->clks);
1223
1224         return 0;
1225 }
1226
1227 static int canfd_runtime_resume(struct device *dev)
1228 {
1229         struct ipms_canfd_priv *priv = dev_get_drvdata(dev);
1230         int ret;
1231
1232         ret = clk_bulk_prepare_enable(priv->nr_clks, priv->clks);
1233         if (ret) {
1234                 dev_err(dev, "Failed to  prepare_enable clk\n");
1235                 return ret;
1236         }
1237
1238         ret = reset_control_deassert(priv->resets);
1239         if (ret) {
1240                 dev_err(dev, "Failed to deassert reset\n");
1241                 return ret;
1242         }
1243
1244         return 0;
1245 }
1246 #endif
1247
1248 static const struct dev_pm_ops canfd_pm_ops = {
1249         SET_SYSTEM_SLEEP_PM_OPS(canfd_suspend, canfd_resume)
1250         SET_RUNTIME_PM_OPS(canfd_runtime_suspend,
1251                            canfd_runtime_resume, NULL)
1252 };
1253
1254 static const struct of_device_id canfd_of_match[] = {
1255         { .compatible = "ipms,can" },
1256         { }
1257 };
1258 MODULE_DEVICE_TABLE(of, canfd_of_match);
1259
1260 static struct platform_driver can_driver = {
1261         .probe          = canfd_driver_probe,
1262         .remove         = canfd_driver_remove,
1263         .driver = {
1264                 .name  = DRIVER_NAME,
1265                 .pm    = &canfd_pm_ops,
1266                 .of_match_table = canfd_of_match,
1267         },
1268 };
1269
1270 module_platform_driver(can_driver);
1271 MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
1272 MODULE_LICENSE("GPL v2");
1273 MODULE_DESCRIPTION("ipms can controller driver");