drivers/net/can/flexcan/flexcan-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <dt-bindings/firmware/imx/rsrc.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/can.h>
  15 #include <linux/can/dev.h>
  16 #include <linux/can/error.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/firmware/imx/sci.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/module.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/can/platform/flexcan.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/regmap.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include "flexcan.h"
  35
  36 #define DRV_NAME                        "flexcan"
  37
  38 /* 8 for RX fifo and 2 error handling */
  39 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  40
  41 /* FLEXCAN module configuration register (CANMCR) bits */
  42 #define FLEXCAN_MCR_MDIS                BIT(31)
  43 #define FLEXCAN_MCR_FRZ                 BIT(30)
  44 #define FLEXCAN_MCR_FEN                 BIT(29)
  45 #define FLEXCAN_MCR_HALT                BIT(28)
  46 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  47 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  48 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  49 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  50 #define FLEXCAN_MCR_SUPV                BIT(23)
  51 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  52 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  53 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  54 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  55 #define FLEXCAN_MCR_DOZE                BIT(18)
  56 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  57 #define FLEXCAN_MCR_IRMQ                BIT(16)
  58 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  59 #define FLEXCAN_MCR_AEN                 BIT(12)
  60 #define FLEXCAN_MCR_FDEN                BIT(11)
  61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  62 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  63 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  64 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  65 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  66 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  67
  68 /* FLEXCAN control register (CANCTRL) bits */
  69 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  70 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  71 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  72 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  73 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  74 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  75 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  76 #define FLEXCAN_CTRL_LPB                BIT(12)
  77 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  78 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  79 #define FLEXCAN_CTRL_SMP                BIT(7)
  80 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  81 #define FLEXCAN_CTRL_TSYN               BIT(5)
  82 #define FLEXCAN_CTRL_LBUF               BIT(4)
  83 #define FLEXCAN_CTRL_LOM                BIT(3)
  84 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  85 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  86 #define FLEXCAN_CTRL_ERR_STATE \
  87         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  88          FLEXCAN_CTRL_BOFF_MSK)
  89 #define FLEXCAN_CTRL_ERR_ALL \
  90         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  91
  92 /* FLEXCAN control register 2 (CTRL2) bits */
  93 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  94 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  95 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  96 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  97 #define FLEXCAN_CTRL2_MRP               BIT(18)
  98 #define FLEXCAN_CTRL2_RRS               BIT(17)
  99 #define FLEXCAN_CTRL2_EACEN             BIT(16)
 100 #define FLEXCAN_CTRL2_ISOCANFDEN        BIT(12)
 101
 102 /* FLEXCAN memory error control register (MECR) bits */
 103 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
 104 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
 105 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
 106 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 107 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 108 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 109 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 110 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 111 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 112 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 113
 114 /* FLEXCAN error and status register (ESR) bits */
 115 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 116 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 117 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 118 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 119 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 120 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 121 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 122 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 123 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 124 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 125 #define FLEXCAN_ESR_IDLE                BIT(7)
 126 #define FLEXCAN_ESR_TXRX                BIT(6)
 127 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 128 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 131 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 132 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 133 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 134 #define FLEXCAN_ESR_ERR_BUS \
 135         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 136          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 137          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 138 #define FLEXCAN_ESR_ERR_STATE \
 139         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 140 #define FLEXCAN_ESR_ERR_ALL \
 141         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 142 #define FLEXCAN_ESR_ALL_INT \
 143         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 144          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 145
 146 /* FLEXCAN Bit Timing register (CBT) bits */
 147 #define FLEXCAN_CBT_BTF                 BIT(31)
 148 #define FLEXCAN_CBT_EPRESDIV_MASK       GENMASK(30, 21)
 149 #define FLEXCAN_CBT_ERJW_MASK           GENMASK(20, 16)
 150 #define FLEXCAN_CBT_EPROPSEG_MASK       GENMASK(15, 10)
 151 #define FLEXCAN_CBT_EPSEG1_MASK         GENMASK(9, 5)
 152 #define FLEXCAN_CBT_EPSEG2_MASK         GENMASK(4, 0)
 153
 154 /* FLEXCAN FD control register (FDCTRL) bits */
 155 #define FLEXCAN_FDCTRL_FDRATE           BIT(31)
 156 #define FLEXCAN_FDCTRL_MBDSR1           GENMASK(20, 19)
 157 #define FLEXCAN_FDCTRL_MBDSR0           GENMASK(17, 16)
 158 #define FLEXCAN_FDCTRL_MBDSR_8          0x0
 159 #define FLEXCAN_FDCTRL_MBDSR_12         0x1
 160 #define FLEXCAN_FDCTRL_MBDSR_32         0x2
 161 #define FLEXCAN_FDCTRL_MBDSR_64         0x3
 162 #define FLEXCAN_FDCTRL_TDCEN            BIT(15)
 163 #define FLEXCAN_FDCTRL_TDCFAIL          BIT(14)
 164 #define FLEXCAN_FDCTRL_TDCOFF           GENMASK(12, 8)
 165 #define FLEXCAN_FDCTRL_TDCVAL           GENMASK(5, 0)
 166
 167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
 168 #define FLEXCAN_FDCBT_FPRESDIV_MASK     GENMASK(29, 20)
 169 #define FLEXCAN_FDCBT_FRJW_MASK         GENMASK(18, 16)
 170 #define FLEXCAN_FDCBT_FPROPSEG_MASK     GENMASK(14, 10)
 171 #define FLEXCAN_FDCBT_FPSEG1_MASK       GENMASK(7, 5)
 172 #define FLEXCAN_FDCBT_FPSEG2_MASK       GENMASK(2, 0)
 173
 174 /* FLEXCAN interrupt flag register (IFLAG) bits */
 175 /* Errata ERR005829 step7: Reserve first valid MB */
 176 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO  8
 177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX       0
 178 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST  (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
 179 #define FLEXCAN_IFLAG_MB(x)             BIT_ULL(x)
 180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 181 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 183
 184 /* FLEXCAN message buffers */
 185 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 187 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 188 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 189 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 190 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 191 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 192
 193 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 194 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 195 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 196 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 197
 198 #define FLEXCAN_MB_CNT_EDL              BIT(31)
 199 #define FLEXCAN_MB_CNT_BRS              BIT(30)
 200 #define FLEXCAN_MB_CNT_ESI              BIT(29)
 201 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 202 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 203 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 204 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 205 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 206
 207 #define FLEXCAN_TIMEOUT_US              (250)
 208
 209 /* Structure of the message buffer */
 210 struct flexcan_mb {
 211         u32 can_ctrl;
 212         u32 can_id;
 213         u32 data[];
 214 };
 215
 216 /* Structure of the hardware registers */
 217 struct flexcan_regs {
 218         u32 mcr;                /* 0x00 */
 219         u32 ctrl;               /* 0x04 - Not affected by Soft Reset */
 220         u32 timer;              /* 0x08 */
 221         u32 tcr;                /* 0x0c */
 222         u32 rxgmask;            /* 0x10 - Not affected by Soft Reset */
 223         u32 rx14mask;           /* 0x14 - Not affected by Soft Reset */
 224         u32 rx15mask;           /* 0x18 - Not affected by Soft Reset */
 225         u32 ecr;                /* 0x1c */
 226         u32 esr;                /* 0x20 */
 227         u32 imask2;             /* 0x24 */
 228         u32 imask1;             /* 0x28 */
 229         u32 iflag2;             /* 0x2c */
 230         u32 iflag1;             /* 0x30 */
 231         union {                 /* 0x34 */
 232                 u32 gfwr_mx28;  /* MX28, MX53 */
 233                 u32 ctrl2;      /* MX6, VF610 - Not affected by Soft Reset */
 234         };
 235         u32 esr2;               /* 0x38 */
 236         u32 imeur;              /* 0x3c */
 237         u32 lrfr;               /* 0x40 */
 238         u32 crcr;               /* 0x44 */
 239         u32 rxfgmask;           /* 0x48 */
 240         u32 rxfir;              /* 0x4c - Not affected by Soft Reset */
 241         u32 cbt;                /* 0x50 - Not affected by Soft Reset */
 242         u32 _reserved2;         /* 0x54 */
 243         u32 dbg1;               /* 0x58 */
 244         u32 dbg2;               /* 0x5c */
 245         u32 _reserved3[8];      /* 0x60 */
 246         struct_group(init,
 247                 u8 mb[2][512];          /* 0x80 - Not affected by Soft Reset */
 248                 /* FIFO-mode:
 249                  *                      MB
 250                  * 0x080...0x08f        0       RX message buffer
 251                  * 0x090...0x0df        1-5     reserved
 252                  * 0x0e0...0x0ff        6-7     8 entry ID table
 253                  *                              (mx25, mx28, mx35, mx53)
 254                  * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 255                  *                              size conf'ed via ctrl2::RFFN
 256                  *                              (mx6, vf610)
 257                  */
 258                 u32 _reserved4[256];    /* 0x480 */
 259                 u32 rximr[64];          /* 0x880 - Not affected by Soft Reset */
 260                 u32 _reserved5[24];     /* 0x980 */
 261                 u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 262                 u32 _reserved6[39];     /* 0x9e4 */
 263                 u32 _rxfir[6];          /* 0xa80 */
 264                 u32 _reserved8[2];      /* 0xa98 */
 265                 u32 _rxmgmask;          /* 0xaa0 */
 266                 u32 _rxfgmask;          /* 0xaa4 */
 267                 u32 _rx14mask;          /* 0xaa8 */
 268                 u32 _rx15mask;          /* 0xaac */
 269                 u32 tx_smb[4];          /* 0xab0 */
 270                 u32 rx_smb0[4];         /* 0xac0 */
 271                 u32 rx_smb1[4];         /* 0xad0 */
 272         );
 273         u32 mecr;               /* 0xae0 */
 274         u32 erriar;             /* 0xae4 */
 275         u32 erridpr;            /* 0xae8 */
 276         u32 errippr;            /* 0xaec */
 277         u32 rerrar;             /* 0xaf0 */
 278         u32 rerrdr;             /* 0xaf4 */
 279         u32 rerrsynr;           /* 0xaf8 */
 280         u32 errsr;              /* 0xafc */
 281         u32 _reserved7[64];     /* 0xb00 */
 282         u32 fdctrl;             /* 0xc00 - Not affected by Soft Reset */
 283         u32 fdcbt;              /* 0xc04 - Not affected by Soft Reset */
 284         u32 fdcrc;              /* 0xc08 */
 285         u32 _reserved9[199];    /* 0xc0c */
 286         struct_group(init_fd,
 287                 u32 tx_smb_fd[18];      /* 0xf28 */
 288                 u32 rx_smb0_fd[18];     /* 0xf70 */
 289                 u32 rx_smb1_fd[18];     /* 0xfb8 */
 290         );
 291 };
 292
 293 static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
 294
 295 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
 296         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 297                 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
 298                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 299                 FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 300 };
 301
 302 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 303         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 304                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 305                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
 306                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 307                 FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 308 };
 309
 310 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 311         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 312                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 314                 FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 315 };
 316
 317 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 318         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 319                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 320                 FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
 321 };
 322
 323 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 324         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 325                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 326                 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 327                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 328                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 329 };
 330
 331 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
 332         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 333                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 334                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
 335                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 336                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 337 };
 338
 339 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
 340         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 341                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 342                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 343                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
 344                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 345                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 346 };
 347
 348 static struct flexcan_devtype_data fsl_imx93_devtype_data = {
 349         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 350                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 351                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_AUTO_STOP_MODE |
 352                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
 353                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 354                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 355 };
 356
 357 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 358         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 359                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 360                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
 361                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 362                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 363 };
 364
 365 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 366         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 367                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 368                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 369                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 370 };
 371
 372 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 373         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 374                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 375                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
 376                 FLEXCAN_QUIRK_SUPPORT_ECC |
 377                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
 378                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 379 };
 380
 381 static const struct can_bittiming_const flexcan_bittiming_const = {
 382         .name = DRV_NAME,
 383         .tseg1_min = 4,
 384         .tseg1_max = 16,
 385         .tseg2_min = 2,
 386         .tseg2_max = 8,
 387         .sjw_max = 4,
 388         .brp_min = 1,
 389         .brp_max = 256,
 390         .brp_inc = 1,
 391 };
 392
 393 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
 394         .name = DRV_NAME,
 395         .tseg1_min = 2,
 396         .tseg1_max = 96,
 397         .tseg2_min = 2,
 398         .tseg2_max = 32,
 399         .sjw_max = 16,
 400         .brp_min = 1,
 401         .brp_max = 1024,
 402         .brp_inc = 1,
 403 };
 404
 405 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
 406         .name = DRV_NAME,
 407         .tseg1_min = 2,
 408         .tseg1_max = 39,
 409         .tseg2_min = 2,
 410         .tseg2_max = 8,
 411         .sjw_max = 4,
 412         .brp_min = 1,
 413         .brp_max = 1024,
 414         .brp_inc = 1,
 415 };
 416
 417 /* FlexCAN module is essentially modelled as a little-endian IP in most
 418  * SoCs, i.e the registers as well as the message buffer areas are
 419  * implemented in a little-endian fashion.
 420  *
 421  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 422  * module in a big-endian fashion (i.e the registers as well as the
 423  * message buffer areas are implemented in a big-endian way).
 424  *
 425  * In addition, the FlexCAN module can be found on SoCs having ARM or
 426  * PPC cores. So, we need to abstract off the register read/write
 427  * functions, ensuring that these cater to all the combinations of module
 428  * endianness and underlying CPU endianness.
 429  */
 430 static inline u32 flexcan_read_be(void __iomem *addr)
 431 {
 432         return ioread32be(addr);
 433 }
 434
 435 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 436 {
 437         iowrite32be(val, addr);
 438 }
 439
 440 static inline u32 flexcan_read_le(void __iomem *addr)
 441 {
 442         return ioread32(addr);
 443 }
 444
 445 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 446 {
 447         iowrite32(val, addr);
 448 }
 449
 450 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 451                                                  u8 mb_index)
 452 {
 453         u8 bank_size;
 454         bool bank;
 455
 456         if (WARN_ON(mb_index >= priv->mb_count))
 457                 return NULL;
 458
 459         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 460
 461         bank = mb_index >= bank_size;
 462         if (bank)
 463                 mb_index -= bank_size;
 464
 465         return (struct flexcan_mb __iomem *)
 466                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 467 }
 468
 469 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 470 {
 471         struct flexcan_regs __iomem *regs = priv->regs;
 472         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 473
 474         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 475                 udelay(10);
 476
 477         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 478                 return -ETIMEDOUT;
 479
 480         return 0;
 481 }
 482
 483 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 484 {
 485         struct flexcan_regs __iomem *regs = priv->regs;
 486         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 487
 488         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 489                 udelay(10);
 490
 491         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 492                 return -ETIMEDOUT;
 493
 494         return 0;
 495 }
 496
 497 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 498 {
 499         struct flexcan_regs __iomem *regs = priv->regs;
 500         u32 reg_mcr;
 501
 502         reg_mcr = priv->read(&regs->mcr);
 503
 504         if (enable)
 505                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 506         else
 507                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 508
 509         priv->write(reg_mcr, &regs->mcr);
 510 }
 511
 512 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
 513 {
 514         u8 idx = priv->scu_idx;
 515         u32 rsrc_id, val;
 516
 517         rsrc_id = IMX_SC_R_CAN(idx);
 518
 519         if (enabled)
 520                 val = 1;
 521         else
 522                 val = 0;
 523
 524         /* stop mode request via scu firmware */
 525         return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
 526                                        IMX_SC_C_IPG_STOP, val);
 527 }
 528
 529 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 530 {
 531         struct flexcan_regs __iomem *regs = priv->regs;
 532         u32 reg_mcr;
 533         int ret;
 534
 535         reg_mcr = priv->read(&regs->mcr);
 536         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 537         priv->write(reg_mcr, &regs->mcr);
 538
 539         /* enable stop request */
 540         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 541                 ret = flexcan_stop_mode_enable_scfw(priv, true);
 542                 if (ret < 0)
 543                         return ret;
 544         } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
 545                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 546                                    1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 547         } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_AUTO_STOP_MODE) {
 548                 /* For the auto stop mode, software do nothing, hardware will cover
 549                  * all the operation automatically after system go into low power mode.
 550                  */
 551                 return 0;
 552         }
 553
 554         return flexcan_low_power_enter_ack(priv);
 555 }
 556
 557 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 558 {
 559         struct flexcan_regs __iomem *regs = priv->regs;
 560         u32 reg_mcr;
 561         int ret;
 562
 563         /* remove stop request */
 564         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 565                 ret = flexcan_stop_mode_enable_scfw(priv, false);
 566                 if (ret < 0)
 567                         return ret;
 568         } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
 569                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 570                                    1 << priv->stm.req_bit, 0);
 571         }
 572
 573         reg_mcr = priv->read(&regs->mcr);
 574         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 575         priv->write(reg_mcr, &regs->mcr);
 576
 577         /* For the auto stop mode, hardware will exist stop mode
 578          * automatically after system go out of low power mode.
 579          */
 580         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_AUTO_STOP_MODE)
 581                 return 0;
 582
 583         return flexcan_low_power_exit_ack(priv);
 584 }
 585
 586 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 587 {
 588         struct flexcan_regs __iomem *regs = priv->regs;
 589         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 590
 591         priv->write(reg_ctrl, &regs->ctrl);
 592 }
 593
 594 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 595 {
 596         struct flexcan_regs __iomem *regs = priv->regs;
 597         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 598
 599         priv->write(reg_ctrl, &regs->ctrl);
 600 }
 601
 602 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 603 {
 604         int err = 0;
 605
 606         if (priv->clk_ipg) {
 607                 err = clk_prepare_enable(priv->clk_ipg);
 608                 if (err)
 609                         return err;
 610         }
 611
 612         if (priv->clk_per) {
 613                 err = clk_prepare_enable(priv->clk_per);
 614                 if (err)
 615                         clk_disable_unprepare(priv->clk_ipg);
 616         }
 617
 618         return err;
 619 }
 620
 621 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 622 {
 623         clk_disable_unprepare(priv->clk_per);
 624         clk_disable_unprepare(priv->clk_ipg);
 625 }
 626
 627 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 628 {
 629         if (!priv->reg_xceiver)
 630                 return 0;
 631
 632         return regulator_enable(priv->reg_xceiver);
 633 }
 634
 635 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 636 {
 637         if (!priv->reg_xceiver)
 638                 return 0;
 639
 640         return regulator_disable(priv->reg_xceiver);
 641 }
 642
 643 static int flexcan_chip_enable(struct flexcan_priv *priv)
 644 {
 645         struct flexcan_regs __iomem *regs = priv->regs;
 646         u32 reg;
 647
 648         reg = priv->read(&regs->mcr);
 649         reg &= ~FLEXCAN_MCR_MDIS;
 650         priv->write(reg, &regs->mcr);
 651
 652         return flexcan_low_power_exit_ack(priv);
 653 }
 654
 655 static int flexcan_chip_disable(struct flexcan_priv *priv)
 656 {
 657         struct flexcan_regs __iomem *regs = priv->regs;
 658         u32 reg;
 659
 660         reg = priv->read(&regs->mcr);
 661         reg |= FLEXCAN_MCR_MDIS;
 662         priv->write(reg, &regs->mcr);
 663
 664         return flexcan_low_power_enter_ack(priv);
 665 }
 666
 667 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 668 {
 669         struct flexcan_regs __iomem *regs = priv->regs;
 670         unsigned int timeout;
 671         u32 bitrate = priv->can.bittiming.bitrate;
 672         u32 reg;
 673
 674         if (bitrate)
 675                 timeout = 1000 * 1000 * 10 / bitrate;
 676         else
 677                 timeout = FLEXCAN_TIMEOUT_US / 10;
 678
 679         reg = priv->read(&regs->mcr);
 680         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
 681         priv->write(reg, &regs->mcr);
 682
 683         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 684                 udelay(100);
 685
 686         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 687                 return -ETIMEDOUT;
 688
 689         return 0;
 690 }
 691
 692 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 693 {
 694         struct flexcan_regs __iomem *regs = priv->regs;
 695         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 696         u32 reg;
 697
 698         reg = priv->read(&regs->mcr);
 699         reg &= ~FLEXCAN_MCR_HALT;
 700         priv->write(reg, &regs->mcr);
 701
 702         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 703                 udelay(10);
 704
 705         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 706                 return -ETIMEDOUT;
 707
 708         return 0;
 709 }
 710
 711 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 712 {
 713         struct flexcan_regs __iomem *regs = priv->regs;
 714         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 715
 716         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 717         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 718                 udelay(10);
 719
 720         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 721                 return -ETIMEDOUT;
 722
 723         return 0;
 724 }
 725
 726 static int __flexcan_get_berr_counter(const struct net_device *dev,
 727                                       struct can_berr_counter *bec)
 728 {
 729         const struct flexcan_priv *priv = netdev_priv(dev);
 730         struct flexcan_regs __iomem *regs = priv->regs;
 731         u32 reg = priv->read(&regs->ecr);
 732
 733         bec->txerr = (reg >> 0) & 0xff;
 734         bec->rxerr = (reg >> 8) & 0xff;
 735
 736         return 0;
 737 }
 738
 739 static int flexcan_get_berr_counter(const struct net_device *dev,
 740                                     struct can_berr_counter *bec)
 741 {
 742         const struct flexcan_priv *priv = netdev_priv(dev);
 743         int err;
 744
 745         err = pm_runtime_resume_and_get(priv->dev);
 746         if (err < 0)
 747                 return err;
 748
 749         err = __flexcan_get_berr_counter(dev, bec);
 750
 751         pm_runtime_put(priv->dev);
 752
 753         return err;
 754 }
 755
 756 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 757 {
 758         const struct flexcan_priv *priv = netdev_priv(dev);
 759         struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
 760         u32 can_id;
 761         u32 data;
 762         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
 763         int i;
 764
 765         if (can_dev_dropped_skb(dev, skb))
 766                 return NETDEV_TX_OK;
 767
 768         netif_stop_queue(dev);
 769
 770         if (cfd->can_id & CAN_EFF_FLAG) {
 771                 can_id = cfd->can_id & CAN_EFF_MASK;
 772                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 773         } else {
 774                 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
 775         }
 776
 777         if (cfd->can_id & CAN_RTR_FLAG)
 778                 ctrl |= FLEXCAN_MB_CNT_RTR;
 779
 780         if (can_is_canfd_skb(skb)) {
 781                 ctrl |= FLEXCAN_MB_CNT_EDL;
 782
 783                 if (cfd->flags & CANFD_BRS)
 784                         ctrl |= FLEXCAN_MB_CNT_BRS;
 785         }
 786
 787         for (i = 0; i < cfd->len; i += sizeof(u32)) {
 788                 data = be32_to_cpup((__be32 *)&cfd->data[i]);
 789                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 790         }
 791
 792         can_put_echo_skb(skb, dev, 0, 0);
 793
 794         priv->write(can_id, &priv->tx_mb->can_id);
 795         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 796
 797         /* Errata ERR005829 step8:
 798          * Write twice INACTIVE(0x8) code to first MB.
 799          */
 800         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 801                     &priv->tx_mb_reserved->can_ctrl);
 802         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 803                     &priv->tx_mb_reserved->can_ctrl);
 804
 805         return NETDEV_TX_OK;
 806 }
 807
 808 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 809 {
 810         struct flexcan_priv *priv = netdev_priv(dev);
 811         struct flexcan_regs __iomem *regs = priv->regs;
 812         struct sk_buff *skb;
 813         struct can_frame *cf;
 814         bool rx_errors = false, tx_errors = false;
 815         u32 timestamp;
 816         int err;
 817
 818         timestamp = priv->read(&regs->timer) << 16;
 819
 820         skb = alloc_can_err_skb(dev, &cf);
 821         if (unlikely(!skb))
 822                 return;
 823
 824         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 825
 826         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 827                 netdev_dbg(dev, "BIT1_ERR irq\n");
 828                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 829                 tx_errors = true;
 830         }
 831         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 832                 netdev_dbg(dev, "BIT0_ERR irq\n");
 833                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 834                 tx_errors = true;
 835         }
 836         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 837                 netdev_dbg(dev, "ACK_ERR irq\n");
 838                 cf->can_id |= CAN_ERR_ACK;
 839                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 840                 tx_errors = true;
 841         }
 842         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 843                 netdev_dbg(dev, "CRC_ERR irq\n");
 844                 cf->data[2] |= CAN_ERR_PROT_BIT;
 845                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 846                 rx_errors = true;
 847         }
 848         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 849                 netdev_dbg(dev, "FRM_ERR irq\n");
 850                 cf->data[2] |= CAN_ERR_PROT_FORM;
 851                 rx_errors = true;
 852         }
 853         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 854                 netdev_dbg(dev, "STF_ERR irq\n");
 855                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 856                 rx_errors = true;
 857         }
 858
 859         priv->can.can_stats.bus_error++;
 860         if (rx_errors)
 861                 dev->stats.rx_errors++;
 862         if (tx_errors)
 863                 dev->stats.tx_errors++;
 864
 865         err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
 866         if (err)
 867                 dev->stats.rx_fifo_errors++;
 868 }
 869
 870 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 871 {
 872         struct flexcan_priv *priv = netdev_priv(dev);
 873         struct flexcan_regs __iomem *regs = priv->regs;
 874         struct sk_buff *skb;
 875         struct can_frame *cf;
 876         enum can_state new_state, rx_state, tx_state;
 877         int flt;
 878         struct can_berr_counter bec;
 879         u32 timestamp;
 880         int err;
 881
 882         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 883         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 884                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 885                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 886                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 887                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 888                 new_state = max(tx_state, rx_state);
 889         } else {
 890                 __flexcan_get_berr_counter(dev, &bec);
 891                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 892                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 893                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 894                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 895         }
 896
 897         /* state hasn't changed */
 898         if (likely(new_state == priv->can.state))
 899                 return;
 900
 901         timestamp = priv->read(&regs->timer) << 16;
 902
 903         skb = alloc_can_err_skb(dev, &cf);
 904         if (unlikely(!skb))
 905                 return;
 906
 907         can_change_state(dev, cf, tx_state, rx_state);
 908
 909         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 910                 can_bus_off(dev);
 911
 912         err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
 913         if (err)
 914                 dev->stats.rx_fifo_errors++;
 915 }
 916
 917 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 918 {
 919         u64 reg = 0;
 920
 921         if (upper_32_bits(mask))
 922                 reg = (u64)priv->read(addr - 4) << 32;
 923         if (lower_32_bits(mask))
 924                 reg |= priv->read(addr);
 925
 926         return reg & mask;
 927 }
 928
 929 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
 930 {
 931         if (upper_32_bits(val))
 932                 priv->write(upper_32_bits(val), addr - 4);
 933         if (lower_32_bits(val))
 934                 priv->write(lower_32_bits(val), addr);
 935 }
 936
 937 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 938 {
 939         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
 940 }
 941
 942 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
 943 {
 944         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
 945 }
 946
 947 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 948 {
 949         return container_of(offload, struct flexcan_priv, offload);
 950 }
 951
 952 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
 953                                             unsigned int n, u32 *timestamp,
 954                                             bool drop)
 955 {
 956         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 957         struct flexcan_regs __iomem *regs = priv->regs;
 958         struct flexcan_mb __iomem *mb;
 959         struct sk_buff *skb;
 960         struct canfd_frame *cfd;
 961         u32 reg_ctrl, reg_id, reg_iflag1;
 962         int i;
 963
 964         mb = flexcan_get_mb(priv, n);
 965
 966         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
 967                 u32 code;
 968
 969                 do {
 970                         reg_ctrl = priv->read(&mb->can_ctrl);
 971                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 972
 973                 /* is this MB empty? */
 974                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 975                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 976                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 977                         return NULL;
 978
 979                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 980                         /* This MB was overrun, we lost data */
 981                         offload->dev->stats.rx_over_errors++;
 982                         offload->dev->stats.rx_errors++;
 983                 }
 984         } else {
 985                 reg_iflag1 = priv->read(&regs->iflag1);
 986                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 987                         return NULL;
 988
 989                 reg_ctrl = priv->read(&mb->can_ctrl);
 990         }
 991
 992         if (unlikely(drop)) {
 993                 skb = ERR_PTR(-ENOBUFS);
 994                 goto mark_as_read;
 995         }
 996
 997         if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
 998                 skb = alloc_canfd_skb(offload->dev, &cfd);
 999         else
1000                 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1001         if (unlikely(!skb)) {
1002                 skb = ERR_PTR(-ENOMEM);
1003                 goto mark_as_read;
1004         }
1005
1006         /* increase timstamp to full 32 bit */
1007         *timestamp = reg_ctrl << 16;
1008
1009         reg_id = priv->read(&mb->can_id);
1010         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1011                 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1012         else
1013                 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1014
1015         if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1016                 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1017
1018                 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1019                         cfd->flags |= CANFD_BRS;
1020         } else {
1021                 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1022
1023                 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1024                         cfd->can_id |= CAN_RTR_FLAG;
1025         }
1026
1027         if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1028                 cfd->flags |= CANFD_ESI;
1029
1030         for (i = 0; i < cfd->len; i += sizeof(u32)) {
1031                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1032                 *(__be32 *)(cfd->data + i) = data;
1033         }
1034
1035  mark_as_read:
1036         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1037                 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1038         else
1039                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1040
1041         /* Read the Free Running Timer. It is optional but recommended
1042          * to unlock Mailbox as soon as possible and make it available
1043          * for reception.
1044          */
1045         priv->read(&regs->timer);
1046
1047         return skb;
1048 }
1049
1050 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1051 {
1052         struct net_device *dev = dev_id;
1053         struct net_device_stats *stats = &dev->stats;
1054         struct flexcan_priv *priv = netdev_priv(dev);
1055         struct flexcan_regs __iomem *regs = priv->regs;
1056         irqreturn_t handled = IRQ_NONE;
1057         u64 reg_iflag_tx;
1058         u32 reg_esr;
1059         enum can_state last_state = priv->can.state;
1060
1061         /* reception interrupt */
1062         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1063                 u64 reg_iflag_rx;
1064                 int ret;
1065
1066                 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1067                         handled = IRQ_HANDLED;
1068                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1069                                                                    reg_iflag_rx);
1070                         if (!ret)
1071                                 break;
1072                 }
1073         } else {
1074                 u32 reg_iflag1;
1075
1076                 reg_iflag1 = priv->read(&regs->iflag1);
1077                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1078                         handled = IRQ_HANDLED;
1079                         can_rx_offload_irq_offload_fifo(&priv->offload);
1080                 }
1081
1082                 /* FIFO overflow interrupt */
1083                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1084                         handled = IRQ_HANDLED;
1085                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1086                                     &regs->iflag1);
1087                         dev->stats.rx_over_errors++;
1088                         dev->stats.rx_errors++;
1089                 }
1090         }
1091
1092         reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1093
1094         /* transmission complete interrupt */
1095         if (reg_iflag_tx & priv->tx_mask) {
1096                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1097
1098                 handled = IRQ_HANDLED;
1099                 stats->tx_bytes +=
1100                         can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0,
1101                                                                     reg_ctrl << 16, NULL);
1102                 stats->tx_packets++;
1103
1104                 /* after sending a RTR frame MB is in RX mode */
1105                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1106                             &priv->tx_mb->can_ctrl);
1107                 flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1108                 netif_wake_queue(dev);
1109         }
1110
1111         reg_esr = priv->read(&regs->esr);
1112
1113         /* ACK all bus error, state change and wake IRQ sources */
1114         if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1115                 handled = IRQ_HANDLED;
1116                 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1117         }
1118
1119         /* state change interrupt or broken error state quirk fix is enabled */
1120         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1121             (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1122                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1123                 flexcan_irq_state(dev, reg_esr);
1124
1125         /* bus error IRQ - handle if bus error reporting is activated */
1126         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1127             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1128                 flexcan_irq_bus_err(dev, reg_esr);
1129
1130         /* availability of error interrupt among state transitions in case
1131          * bus error reporting is de-activated and
1132          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1133          *  +--------------------------------------------------------------+
1134          *  | +----------------------------------------------+ [stopped /  |
1135          *  | |                                              |  sleeping] -+
1136          *  +-+-> active <-> warning <-> passive -> bus off -+
1137          *        ___________^^^^^^^^^^^^_______________________________
1138          *        disabled(1)  enabled             disabled
1139          *
1140          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1141          */
1142         if ((last_state != priv->can.state) &&
1143             (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1144             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1145                 switch (priv->can.state) {
1146                 case CAN_STATE_ERROR_ACTIVE:
1147                         if (priv->devtype_data.quirks &
1148                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1149                                 flexcan_error_irq_enable(priv);
1150                         else
1151                                 flexcan_error_irq_disable(priv);
1152                         break;
1153
1154                 case CAN_STATE_ERROR_WARNING:
1155                         flexcan_error_irq_enable(priv);
1156                         break;
1157
1158                 case CAN_STATE_ERROR_PASSIVE:
1159                 case CAN_STATE_BUS_OFF:
1160                         flexcan_error_irq_disable(priv);
1161                         break;
1162
1163                 default:
1164                         break;
1165                 }
1166         }
1167
1168         if (handled)
1169                 can_rx_offload_irq_finish(&priv->offload);
1170
1171         return handled;
1172 }
1173
1174 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1175 {
1176         const struct flexcan_priv *priv = netdev_priv(dev);
1177         const struct can_bittiming *bt = &priv->can.bittiming;
1178         struct flexcan_regs __iomem *regs = priv->regs;
1179         u32 reg;
1180
1181         reg = priv->read(&regs->ctrl);
1182         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1183                  FLEXCAN_CTRL_RJW(0x3) |
1184                  FLEXCAN_CTRL_PSEG1(0x7) |
1185                  FLEXCAN_CTRL_PSEG2(0x7) |
1186                  FLEXCAN_CTRL_PROPSEG(0x7));
1187
1188         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1189                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1190                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1191                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1192                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1193
1194         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1195         priv->write(reg, &regs->ctrl);
1196
1197         /* print chip status */
1198         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1199                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1200 }
1201
1202 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1203 {
1204         struct flexcan_priv *priv = netdev_priv(dev);
1205         struct can_bittiming *bt = &priv->can.bittiming;
1206         struct can_bittiming *dbt = &priv->can.data_bittiming;
1207         struct flexcan_regs __iomem *regs = priv->regs;
1208         u32 reg_cbt, reg_fdctrl;
1209
1210         /* CBT */
1211         /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1212          * long. The can_calc_bittiming() tries to divide the tseg1
1213          * equally between phase_seg1 and prop_seg, which may not fit
1214          * in CBT register. Therefore, if phase_seg1 is more than
1215          * possible value, increase prop_seg and decrease phase_seg1.
1216          */
1217         if (bt->phase_seg1 > 0x20) {
1218                 bt->prop_seg += (bt->phase_seg1 - 0x20);
1219                 bt->phase_seg1 = 0x20;
1220         }
1221
1222         reg_cbt = FLEXCAN_CBT_BTF |
1223                 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1224                 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1225                 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1226                 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1227                 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1228
1229         netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1230         priv->write(reg_cbt, &regs->cbt);
1231
1232         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1233                 u32 reg_fdcbt, reg_ctrl2;
1234
1235                 if (bt->brp != dbt->brp)
1236                         netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1237                                     dbt->brp, bt->brp);
1238
1239                 /* FDCBT */
1240                 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1241                  * 5 bit long. The can_calc_bittiming tries to divide
1242                  * the tseg1 equally between phase_seg1 and prop_seg,
1243                  * which may not fit in FDCBT register. Therefore, if
1244                  * phase_seg1 is more than possible value, increase
1245                  * prop_seg and decrease phase_seg1
1246                  */
1247                 if (dbt->phase_seg1 > 0x8) {
1248                         dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1249                         dbt->phase_seg1 = 0x8;
1250                 }
1251
1252                 reg_fdcbt = priv->read(&regs->fdcbt);
1253                 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1254                                FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1255                                FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1256                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1257                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1258
1259                 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1260                         FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1261                         FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1262                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1263                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1264
1265                 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1266                 priv->write(reg_fdcbt, &regs->fdcbt);
1267
1268                 /* CTRL2 */
1269                 reg_ctrl2 = priv->read(&regs->ctrl2);
1270                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1271                 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1272                         reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1273
1274                 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1275                 priv->write(reg_ctrl2, &regs->ctrl2);
1276         }
1277
1278         /* FDCTRL */
1279         reg_fdctrl = priv->read(&regs->fdctrl);
1280         reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1281                         FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1282
1283         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1284                 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1285
1286                 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1287                         /* TDC must be disabled for Loop Back mode */
1288                         reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1289                 } else {
1290                         reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1291                                 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1292                                            ((dbt->phase_seg1 - 1) +
1293                                             dbt->prop_seg + 2) *
1294                                            ((dbt->brp - 1 ) + 1));
1295                 }
1296         }
1297
1298         netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1299         priv->write(reg_fdctrl, &regs->fdctrl);
1300
1301         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1302                    __func__,
1303                    priv->read(&regs->mcr), priv->read(&regs->ctrl),
1304                    priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1305                    priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1306 }
1307
1308 static void flexcan_set_bittiming(struct net_device *dev)
1309 {
1310         const struct flexcan_priv *priv = netdev_priv(dev);
1311         struct flexcan_regs __iomem *regs = priv->regs;
1312         u32 reg;
1313
1314         reg = priv->read(&regs->ctrl);
1315         reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1316                  FLEXCAN_CTRL_LOM);
1317
1318         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1319                 reg |= FLEXCAN_CTRL_LPB;
1320         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1321                 reg |= FLEXCAN_CTRL_LOM;
1322         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1323                 reg |= FLEXCAN_CTRL_SMP;
1324
1325         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1326         priv->write(reg, &regs->ctrl);
1327
1328         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1329                 return flexcan_set_bittiming_cbt(dev);
1330         else
1331                 return flexcan_set_bittiming_ctrl(dev);
1332 }
1333
1334 static void flexcan_ram_init(struct net_device *dev)
1335 {
1336         struct flexcan_priv *priv = netdev_priv(dev);
1337         struct flexcan_regs __iomem *regs = priv->regs;
1338         u32 reg_ctrl2;
1339
1340         /* 11.8.3.13 Detection and correction of memory errors:
1341          * CTRL2[WRMFRZ] grants write access to all memory positions
1342          * that require initialization, ranging from 0x080 to 0xADF
1343          * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1344          * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1345          * need to be initialized as well. MCR[RFEN] must not be set
1346          * during memory initialization.
1347          */
1348         reg_ctrl2 = priv->read(&regs->ctrl2);
1349         reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1350         priv->write(reg_ctrl2, &regs->ctrl2);
1351
1352         memset_io(&regs->init, 0, sizeof(regs->init));
1353
1354         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1355                 memset_io(&regs->init_fd, 0, sizeof(regs->init_fd));
1356
1357         reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1358         priv->write(reg_ctrl2, &regs->ctrl2);
1359 }
1360
1361 static int flexcan_rx_offload_setup(struct net_device *dev)
1362 {
1363         struct flexcan_priv *priv = netdev_priv(dev);
1364         int err;
1365
1366         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1367                 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1368         else
1369                 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1370
1371         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1372                 priv->mb_count = 16;
1373         else
1374                 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1375                                  (sizeof(priv->regs->mb[1]) / priv->mb_size);
1376
1377         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1378                 priv->tx_mb_reserved =
1379                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1380         else
1381                 priv->tx_mb_reserved =
1382                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1383         priv->tx_mb_idx = priv->mb_count - 1;
1384         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1385         priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1386
1387         priv->offload.mailbox_read = flexcan_mailbox_read;
1388
1389         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1390                 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1391                 priv->offload.mb_last = priv->mb_count - 2;
1392
1393                 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1394                                             priv->offload.mb_first);
1395                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1396         } else {
1397                 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1398                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1399                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1400                                               FLEXCAN_NAPI_WEIGHT);
1401         }
1402
1403         return err;
1404 }
1405
1406 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1407 {
1408         const struct flexcan_priv *priv = netdev_priv(dev);
1409         struct flexcan_regs __iomem *regs = priv->regs;
1410         u64 reg_imask;
1411
1412         disable_irq(dev->irq);
1413         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1414         reg_imask = priv->rx_mask | priv->tx_mask;
1415         priv->write(upper_32_bits(reg_imask), &regs->imask2);
1416         priv->write(lower_32_bits(reg_imask), &regs->imask1);
1417         enable_irq(dev->irq);
1418 }
1419
1420 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1421 {
1422         const struct flexcan_priv *priv = netdev_priv(dev);
1423         struct flexcan_regs __iomem *regs = priv->regs;
1424
1425         priv->write(0, &regs->imask2);
1426         priv->write(0, &regs->imask1);
1427         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1428                     &regs->ctrl);
1429 }
1430
1431 /* flexcan_chip_start
1432  *
1433  * this functions is entered with clocks enabled
1434  *
1435  */
1436 static int flexcan_chip_start(struct net_device *dev)
1437 {
1438         struct flexcan_priv *priv = netdev_priv(dev);
1439         struct flexcan_regs __iomem *regs = priv->regs;
1440         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1441         int err, i;
1442         struct flexcan_mb __iomem *mb;
1443
1444         /* enable module */
1445         err = flexcan_chip_enable(priv);
1446         if (err)
1447                 return err;
1448
1449         /* soft reset */
1450         err = flexcan_chip_softreset(priv);
1451         if (err)
1452                 goto out_chip_disable;
1453
1454         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1455                 flexcan_ram_init(dev);
1456
1457         flexcan_set_bittiming(dev);
1458
1459         /* set freeze, halt */
1460         err = flexcan_chip_freeze(priv);
1461         if (err)
1462                 goto out_chip_disable;
1463
1464         /* MCR
1465          *
1466          * only supervisor access
1467          * enable warning int
1468          * enable individual RX masking
1469          * choose format C
1470          * set max mailbox number
1471          */
1472         reg_mcr = priv->read(&regs->mcr);
1473         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1474         reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1475                 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1476
1477         /* MCR
1478          *
1479          * FIFO:
1480          * - disable for mailbox mode
1481          * - enable for FIFO mode
1482          */
1483         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1484                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1485         else
1486                 reg_mcr |= FLEXCAN_MCR_FEN;
1487
1488         /* MCR
1489          *
1490          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1491          *       asserted because this will impede the self reception
1492          *       of a transmitted message. This is not documented in
1493          *       earlier versions of flexcan block guide.
1494          *
1495          * Self Reception:
1496          * - enable Self Reception for loopback mode
1497          *   (by clearing "Self Reception Disable" bit)
1498          * - disable for normal operation
1499          */
1500         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1501                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1502         else
1503                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1504
1505         /* MCR - CAN-FD */
1506         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1507                 reg_mcr |= FLEXCAN_MCR_FDEN;
1508         else
1509                 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1510
1511         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1512         priv->write(reg_mcr, &regs->mcr);
1513
1514         /* CTRL
1515          *
1516          * disable timer sync feature
1517          *
1518          * disable auto busoff recovery
1519          * transmit lowest buffer first
1520          *
1521          * enable tx and rx warning interrupt
1522          * enable bus off interrupt
1523          * (== FLEXCAN_CTRL_ERR_STATE)
1524          */
1525         reg_ctrl = priv->read(&regs->ctrl);
1526         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1527         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1528                 FLEXCAN_CTRL_ERR_STATE;
1529
1530         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1531          * on most Flexcan cores, too. Otherwise we don't get
1532          * any error warning or passive interrupts.
1533          */
1534         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1535             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1536                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1537         else
1538                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1539
1540         /* save for later use */
1541         priv->reg_ctrl_default = reg_ctrl;
1542         /* leave interrupts disabled for now */
1543         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1544         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1545         priv->write(reg_ctrl, &regs->ctrl);
1546
1547         if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1548                 reg_ctrl2 = priv->read(&regs->ctrl2);
1549                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1550                 priv->write(reg_ctrl2, &regs->ctrl2);
1551         }
1552
1553         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1554                 u32 reg_fdctrl;
1555
1556                 reg_fdctrl = priv->read(&regs->fdctrl);
1557                 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1558                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1559
1560                 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1561                         reg_fdctrl |=
1562                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1563                                            FLEXCAN_FDCTRL_MBDSR_64) |
1564                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1565                                            FLEXCAN_FDCTRL_MBDSR_64);
1566                 } else {
1567                         reg_fdctrl |=
1568                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1569                                            FLEXCAN_FDCTRL_MBDSR_8) |
1570                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1571                                            FLEXCAN_FDCTRL_MBDSR_8);
1572                 }
1573
1574                 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1575                            __func__, reg_fdctrl);
1576                 priv->write(reg_fdctrl, &regs->fdctrl);
1577         }
1578
1579         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1580                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1581                         mb = flexcan_get_mb(priv, i);
1582                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1583                                     &mb->can_ctrl);
1584                 }
1585         } else {
1586                 /* clear and invalidate unused mailboxes first */
1587                 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1588                         mb = flexcan_get_mb(priv, i);
1589                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1590                                     &mb->can_ctrl);
1591                 }
1592         }
1593
1594         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1595         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1596                     &priv->tx_mb_reserved->can_ctrl);
1597
1598         /* mark TX mailbox as INACTIVE */
1599         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1600                     &priv->tx_mb->can_ctrl);
1601
1602         /* acceptance mask/acceptance code (accept everything) */
1603         priv->write(0x0, &regs->rxgmask);
1604         priv->write(0x0, &regs->rx14mask);
1605         priv->write(0x0, &regs->rx15mask);
1606
1607         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1608                 priv->write(0x0, &regs->rxfgmask);
1609
1610         /* clear acceptance filters */
1611         for (i = 0; i < priv->mb_count; i++)
1612                 priv->write(0, &regs->rximr[i]);
1613
1614         /* On Vybrid, disable non-correctable errors interrupt and
1615          * freeze mode. It still can correct the correctable errors
1616          * when HW supports ECC.
1617          *
1618          * This also works around errata e5295 which generates false
1619          * positive memory errors and put the device in freeze mode.
1620          */
1621         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1622                 /* Follow the protocol as described in "Detection
1623                  * and Correction of Memory Errors" to write to
1624                  * MECR register (step 1 - 5)
1625                  *
1626                  * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1627                  * 2. set CTRL2[ECRWRE]
1628                  */
1629                 reg_ctrl2 = priv->read(&regs->ctrl2);
1630                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1631                 priv->write(reg_ctrl2, &regs->ctrl2);
1632
1633                 /* 3. clear MECR[ECRWRDIS] */
1634                 reg_mecr = priv->read(&regs->mecr);
1635                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1636                 priv->write(reg_mecr, &regs->mecr);
1637
1638                 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1639                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1640                               FLEXCAN_MECR_FANCEI_MSK);
1641                 priv->write(reg_mecr, &regs->mecr);
1642
1643                 /* 5. after configuration done, lock MECR by either
1644                  * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1645                  */
1646                 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1647                 priv->write(reg_mecr, &regs->mecr);
1648
1649                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1650                 priv->write(reg_ctrl2, &regs->ctrl2);
1651         }
1652
1653         /* synchronize with the can bus */
1654         err = flexcan_chip_unfreeze(priv);
1655         if (err)
1656                 goto out_chip_disable;
1657
1658         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1659
1660         /* print chip status */
1661         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1662                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1663
1664         return 0;
1665
1666  out_chip_disable:
1667         flexcan_chip_disable(priv);
1668         return err;
1669 }
1670
1671 /* __flexcan_chip_stop
1672  *
1673  * this function is entered with clocks enabled
1674  */
1675 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1676 {
1677         struct flexcan_priv *priv = netdev_priv(dev);
1678         int err;
1679
1680         /* freeze + disable module */
1681         err = flexcan_chip_freeze(priv);
1682         if (err && !disable_on_error)
1683                 return err;
1684         err = flexcan_chip_disable(priv);
1685         if (err && !disable_on_error)
1686                 goto out_chip_unfreeze;
1687
1688         priv->can.state = CAN_STATE_STOPPED;
1689
1690         return 0;
1691
1692  out_chip_unfreeze:
1693         flexcan_chip_unfreeze(priv);
1694
1695         return err;
1696 }
1697
1698 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1699 {
1700         return __flexcan_chip_stop(dev, true);
1701 }
1702
1703 static inline int flexcan_chip_stop(struct net_device *dev)
1704 {
1705         return __flexcan_chip_stop(dev, false);
1706 }
1707
1708 static int flexcan_open(struct net_device *dev)
1709 {
1710         struct flexcan_priv *priv = netdev_priv(dev);
1711         int err;
1712
1713         if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1714             (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1715                 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1716                 return -EINVAL;
1717         }
1718
1719         err = pm_runtime_resume_and_get(priv->dev);
1720         if (err < 0)
1721                 return err;
1722
1723         err = open_candev(dev);
1724         if (err)
1725                 goto out_runtime_put;
1726
1727         err = flexcan_transceiver_enable(priv);
1728         if (err)
1729                 goto out_close;
1730
1731         err = flexcan_rx_offload_setup(dev);
1732         if (err)
1733                 goto out_transceiver_disable;
1734
1735         err = flexcan_chip_start(dev);
1736         if (err)
1737                 goto out_can_rx_offload_del;
1738
1739         can_rx_offload_enable(&priv->offload);
1740
1741         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1742         if (err)
1743                 goto out_can_rx_offload_disable;
1744
1745         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1746                 err = request_irq(priv->irq_boff,
1747                                   flexcan_irq, IRQF_SHARED, dev->name, dev);
1748                 if (err)
1749                         goto out_free_irq;
1750
1751                 err = request_irq(priv->irq_err,
1752                                   flexcan_irq, IRQF_SHARED, dev->name, dev);
1753                 if (err)
1754                         goto out_free_irq_boff;
1755         }
1756
1757         flexcan_chip_interrupts_enable(dev);
1758
1759         netif_start_queue(dev);
1760
1761         return 0;
1762
1763  out_free_irq_boff:
1764         free_irq(priv->irq_boff, dev);
1765  out_free_irq:
1766         free_irq(dev->irq, dev);
1767  out_can_rx_offload_disable:
1768         can_rx_offload_disable(&priv->offload);
1769         flexcan_chip_stop(dev);
1770  out_can_rx_offload_del:
1771         can_rx_offload_del(&priv->offload);
1772  out_transceiver_disable:
1773         flexcan_transceiver_disable(priv);
1774  out_close:
1775         close_candev(dev);
1776  out_runtime_put:
1777         pm_runtime_put(priv->dev);
1778
1779         return err;
1780 }
1781
1782 static int flexcan_close(struct net_device *dev)
1783 {
1784         struct flexcan_priv *priv = netdev_priv(dev);
1785
1786         netif_stop_queue(dev);
1787         flexcan_chip_interrupts_disable(dev);
1788
1789         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1790                 free_irq(priv->irq_err, dev);
1791                 free_irq(priv->irq_boff, dev);
1792         }
1793
1794         free_irq(dev->irq, dev);
1795         can_rx_offload_disable(&priv->offload);
1796         flexcan_chip_stop_disable_on_error(dev);
1797
1798         can_rx_offload_del(&priv->offload);
1799         flexcan_transceiver_disable(priv);
1800         close_candev(dev);
1801
1802         pm_runtime_put(priv->dev);
1803
1804         return 0;
1805 }
1806
1807 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1808 {
1809         int err;
1810
1811         switch (mode) {
1812         case CAN_MODE_START:
1813                 err = flexcan_chip_start(dev);
1814                 if (err)
1815                         return err;
1816
1817                 flexcan_chip_interrupts_enable(dev);
1818
1819                 netif_wake_queue(dev);
1820                 break;
1821
1822         default:
1823                 return -EOPNOTSUPP;
1824         }
1825
1826         return 0;
1827 }
1828
1829 static const struct net_device_ops flexcan_netdev_ops = {
1830         .ndo_open       = flexcan_open,
1831         .ndo_stop       = flexcan_close,
1832         .ndo_start_xmit = flexcan_start_xmit,
1833         .ndo_change_mtu = can_change_mtu,
1834 };
1835
1836 static int register_flexcandev(struct net_device *dev)
1837 {
1838         struct flexcan_priv *priv = netdev_priv(dev);
1839         struct flexcan_regs __iomem *regs = priv->regs;
1840         u32 reg, err;
1841
1842         err = flexcan_clks_enable(priv);
1843         if (err)
1844                 return err;
1845
1846         /* select "bus clock", chip must be disabled */
1847         err = flexcan_chip_disable(priv);
1848         if (err)
1849                 goto out_clks_disable;
1850
1851         reg = priv->read(&regs->ctrl);
1852         if (priv->clk_src)
1853                 reg |= FLEXCAN_CTRL_CLK_SRC;
1854         else
1855                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1856         priv->write(reg, &regs->ctrl);
1857
1858         err = flexcan_chip_enable(priv);
1859         if (err)
1860                 goto out_chip_disable;
1861
1862         /* set freeze, halt */
1863         err = flexcan_chip_freeze(priv);
1864         if (err)
1865                 goto out_chip_disable;
1866
1867         /* activate FIFO, restrict register access */
1868         reg = priv->read(&regs->mcr);
1869         reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1870         priv->write(reg, &regs->mcr);
1871
1872         /* Currently we only support newer versions of this core
1873          * featuring a RX hardware FIFO (although this driver doesn't
1874          * make use of it on some cores). Older cores, found on some
1875          * Coldfire derivates are not tested.
1876          */
1877         reg = priv->read(&regs->mcr);
1878         if (!(reg & FLEXCAN_MCR_FEN)) {
1879                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1880                 err = -ENODEV;
1881                 goto out_chip_disable;
1882         }
1883
1884         err = register_candev(dev);
1885         if (err)
1886                 goto out_chip_disable;
1887
1888         /* Disable core and let pm_runtime_put() disable the clocks.
1889          * If CONFIG_PM is not enabled, the clocks will stay powered.
1890          */
1891         flexcan_chip_disable(priv);
1892         pm_runtime_put(priv->dev);
1893
1894         return 0;
1895
1896  out_chip_disable:
1897         flexcan_chip_disable(priv);
1898  out_clks_disable:
1899         flexcan_clks_disable(priv);
1900         return err;
1901 }
1902
1903 static void unregister_flexcandev(struct net_device *dev)
1904 {
1905         unregister_candev(dev);
1906 }
1907
1908 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1909 {
1910         struct net_device *dev = platform_get_drvdata(pdev);
1911         struct device_node *np = pdev->dev.of_node;
1912         struct device_node *gpr_np;
1913         struct flexcan_priv *priv;
1914         phandle phandle;
1915         u32 out_val[3];
1916         int ret;
1917
1918         if (!np)
1919                 return -EINVAL;
1920
1921         /* stop mode property format is:
1922          * <&gpr req_gpr req_bit>.
1923          */
1924         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1925                                          ARRAY_SIZE(out_val));
1926         if (ret) {
1927                 dev_dbg(&pdev->dev, "no stop-mode property\n");
1928                 return ret;
1929         }
1930         phandle = *out_val;
1931
1932         gpr_np = of_find_node_by_phandle(phandle);
1933         if (!gpr_np) {
1934                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1935                 return -ENODEV;
1936         }
1937
1938         priv = netdev_priv(dev);
1939         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1940         if (IS_ERR(priv->stm.gpr)) {
1941                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1942                 ret = PTR_ERR(priv->stm.gpr);
1943                 goto out_put_node;
1944         }
1945
1946         priv->stm.req_gpr = out_val[1];
1947         priv->stm.req_bit = out_val[2];
1948
1949         dev_dbg(&pdev->dev,
1950                 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1951                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1952
1953         return 0;
1954
1955 out_put_node:
1956         of_node_put(gpr_np);
1957         return ret;
1958 }
1959
1960 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1961 {
1962         struct net_device *dev = platform_get_drvdata(pdev);
1963         struct flexcan_priv *priv;
1964         u8 scu_idx;
1965         int ret;
1966
1967         ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1968         if (ret < 0) {
1969                 dev_dbg(&pdev->dev, "failed to get scu index\n");
1970                 return ret;
1971         }
1972
1973         priv = netdev_priv(dev);
1974         priv->scu_idx = scu_idx;
1975
1976         /* this function could be deferred probe, return -EPROBE_DEFER */
1977         return imx_scu_get_handle(&priv->sc_ipc_handle);
1978 }
1979
1980 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1981  *
1982  * Return: = 0 setup stop mode successfully or doesn't support this feature
1983  *         < 0 fail to setup stop mode (could be deferred probe)
1984  */
1985 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1986 {
1987         struct net_device *dev = platform_get_drvdata(pdev);
1988         struct flexcan_priv *priv;
1989         int ret;
1990
1991         priv = netdev_priv(dev);
1992
1993         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1994                 ret = flexcan_setup_stop_mode_scfw(pdev);
1995         else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1996                 ret = flexcan_setup_stop_mode_gpr(pdev);
1997         else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_AUTO_STOP_MODE)
1998                 ret = 0;
1999         else
2000                 /* return 0 directly if doesn't support stop mode feature */
2001                 return 0;
2002
2003         if (ret)
2004                 return ret;
2005
2006         device_set_wakeup_capable(&pdev->dev, true);
2007
2008         if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2009                 device_set_wakeup_enable(&pdev->dev, true);
2010
2011         return 0;
2012 }
2013
2014 static const struct of_device_id flexcan_of_match[] = {
2015         { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2016         { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2017         { .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, },
2018         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2019         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2020         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2021         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2022         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2023         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2024         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2025         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2026         { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2027         { /* sentinel */ },
2028 };
2029 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2030
2031 static const struct platform_device_id flexcan_id_table[] = {
2032         {
2033                 .name = "flexcan-mcf5441x",
2034                 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2035         }, {
2036                 /* sentinel */
2037         },
2038 };
2039 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2040
2041 static int flexcan_probe(struct platform_device *pdev)
2042 {
2043         const struct of_device_id *of_id;
2044         const struct flexcan_devtype_data *devtype_data;
2045         struct net_device *dev;
2046         struct flexcan_priv *priv;
2047         struct regulator *reg_xceiver;
2048         struct clk *clk_ipg = NULL, *clk_per = NULL;
2049         struct flexcan_regs __iomem *regs;
2050         struct flexcan_platform_data *pdata;
2051         int err, irq;
2052         u8 clk_src = 1;
2053         u32 clock_freq = 0;
2054
2055         reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2056         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2057                 return -EPROBE_DEFER;
2058         else if (PTR_ERR(reg_xceiver) == -ENODEV)
2059                 reg_xceiver = NULL;
2060         else if (IS_ERR(reg_xceiver))
2061                 return PTR_ERR(reg_xceiver);
2062
2063         if (pdev->dev.of_node) {
2064                 of_property_read_u32(pdev->dev.of_node,
2065                                      "clock-frequency", &clock_freq);
2066                 of_property_read_u8(pdev->dev.of_node,
2067                                     "fsl,clk-source", &clk_src);
2068         } else {
2069                 pdata = dev_get_platdata(&pdev->dev);
2070                 if (pdata) {
2071                         clock_freq = pdata->clock_frequency;
2072                         clk_src = pdata->clk_src;
2073                 }
2074         }
2075
2076         if (!clock_freq) {
2077                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2078                 if (IS_ERR(clk_ipg)) {
2079                         dev_err(&pdev->dev, "no ipg clock defined\n");
2080                         return PTR_ERR(clk_ipg);
2081                 }
2082
2083                 clk_per = devm_clk_get(&pdev->dev, "per");
2084                 if (IS_ERR(clk_per)) {
2085                         dev_err(&pdev->dev, "no per clock defined\n");
2086                         return PTR_ERR(clk_per);
2087                 }
2088                 clock_freq = clk_get_rate(clk_per);
2089         }
2090
2091         irq = platform_get_irq(pdev, 0);
2092         if (irq < 0)
2093                 return irq;
2094
2095         regs = devm_platform_ioremap_resource(pdev, 0);
2096         if (IS_ERR(regs))
2097                 return PTR_ERR(regs);
2098
2099         of_id = of_match_device(flexcan_of_match, &pdev->dev);
2100         if (of_id)
2101                 devtype_data = of_id->data;
2102         else if (platform_get_device_id(pdev)->driver_data)
2103                 devtype_data = (struct flexcan_devtype_data *)
2104                         platform_get_device_id(pdev)->driver_data;
2105         else
2106                 return -ENODEV;
2107
2108         if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2109             !((devtype_data->quirks &
2110                (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2111                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2112                 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR |
2113                 FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) ==
2114               (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2115                FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2116                FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) {
2117                 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2118                 return -EINVAL;
2119         }
2120
2121         if ((devtype_data->quirks &
2122              (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2123               FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) ==
2124             FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) {
2125                 dev_err(&pdev->dev,
2126                         "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2127                         devtype_data->quirks);
2128                 return -EINVAL;
2129         }
2130
2131         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2132         if (!dev)
2133                 return -ENOMEM;
2134
2135         platform_set_drvdata(pdev, dev);
2136         SET_NETDEV_DEV(dev, &pdev->dev);
2137
2138         dev->netdev_ops = &flexcan_netdev_ops;
2139         dev->ethtool_ops = &flexcan_ethtool_ops;
2140         dev->irq = irq;
2141         dev->flags |= IFF_ECHO;
2142
2143         priv = netdev_priv(dev);
2144         priv->devtype_data = *devtype_data;
2145
2146         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2147             priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2148                 priv->read = flexcan_read_be;
2149                 priv->write = flexcan_write_be;
2150         } else {
2151                 priv->read = flexcan_read_le;
2152                 priv->write = flexcan_write_le;
2153         }
2154
2155         priv->dev = &pdev->dev;
2156         priv->can.clock.freq = clock_freq;
2157         priv->can.do_set_mode = flexcan_set_mode;
2158         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2159         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2160                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2161                 CAN_CTRLMODE_BERR_REPORTING;
2162         priv->regs = regs;
2163         priv->clk_ipg = clk_ipg;
2164         priv->clk_per = clk_per;
2165         priv->clk_src = clk_src;
2166         priv->reg_xceiver = reg_xceiver;
2167
2168         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2169                 priv->irq_boff = platform_get_irq(pdev, 1);
2170                 if (priv->irq_boff < 0) {
2171                         err = priv->irq_boff;
2172                         goto failed_platform_get_irq;
2173                 }
2174                 priv->irq_err = platform_get_irq(pdev, 2);
2175                 if (priv->irq_err < 0) {
2176                         err = priv->irq_err;
2177                         goto failed_platform_get_irq;
2178                 }
2179         }
2180
2181         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2182                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2183                         CAN_CTRLMODE_FD_NON_ISO;
2184                 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2185                 priv->can.data_bittiming_const =
2186                         &flexcan_fd_data_bittiming_const;
2187         } else {
2188                 priv->can.bittiming_const = &flexcan_bittiming_const;
2189         }
2190
2191         pm_runtime_get_noresume(&pdev->dev);
2192         pm_runtime_set_active(&pdev->dev);
2193         pm_runtime_enable(&pdev->dev);
2194
2195         err = register_flexcandev(dev);
2196         if (err) {
2197                 dev_err(&pdev->dev, "registering netdev failed\n");
2198                 goto failed_register;
2199         }
2200
2201         err = flexcan_setup_stop_mode(pdev);
2202         if (err < 0) {
2203                 dev_err_probe(&pdev->dev, err, "setup stop mode failed\n");
2204                 goto failed_setup_stop_mode;
2205         }
2206
2207         of_can_transceiver(dev);
2208
2209         return 0;
2210
2211  failed_setup_stop_mode:
2212         unregister_flexcandev(dev);
2213  failed_register:
2214         pm_runtime_put_noidle(&pdev->dev);
2215         pm_runtime_disable(&pdev->dev);
2216  failed_platform_get_irq:
2217         free_candev(dev);
2218         return err;
2219 }
2220
2221 static void flexcan_remove(struct platform_device *pdev)
2222 {
2223         struct net_device *dev = platform_get_drvdata(pdev);
2224
2225         device_set_wakeup_enable(&pdev->dev, false);
2226         device_set_wakeup_capable(&pdev->dev, false);
2227         unregister_flexcandev(dev);
2228         pm_runtime_disable(&pdev->dev);
2229         free_candev(dev);
2230 }
2231
2232 static int __maybe_unused flexcan_suspend(struct device *device)
2233 {
2234         struct net_device *dev = dev_get_drvdata(device);
2235         struct flexcan_priv *priv = netdev_priv(dev);
2236         int err;
2237
2238         if (netif_running(dev)) {
2239                 /* if wakeup is enabled, enter stop mode
2240                  * else enter disabled mode.
2241                  */
2242                 if (device_may_wakeup(device)) {
2243                         enable_irq_wake(dev->irq);
2244                         err = flexcan_enter_stop_mode(priv);
2245                         if (err)
2246                                 return err;
2247                 } else {
2248                         err = flexcan_chip_stop(dev);
2249                         if (err)
2250                                 return err;
2251
2252                         flexcan_chip_interrupts_disable(dev);
2253
2254                         err = pinctrl_pm_select_sleep_state(device);
2255                         if (err)
2256                                 return err;
2257                 }
2258                 netif_stop_queue(dev);
2259                 netif_device_detach(dev);
2260         }
2261         priv->can.state = CAN_STATE_SLEEPING;
2262
2263         return 0;
2264 }
2265
2266 static int __maybe_unused flexcan_resume(struct device *device)
2267 {
2268         struct net_device *dev = dev_get_drvdata(device);
2269         struct flexcan_priv *priv = netdev_priv(dev);
2270         int err;
2271
2272         priv->can.state = CAN_STATE_ERROR_ACTIVE;
2273         if (netif_running(dev)) {
2274                 netif_device_attach(dev);
2275                 netif_start_queue(dev);
2276                 if (device_may_wakeup(device)) {
2277                         disable_irq_wake(dev->irq);
2278                         err = flexcan_exit_stop_mode(priv);
2279                         if (err)
2280                                 return err;
2281                 } else {
2282                         err = pinctrl_pm_select_default_state(device);
2283                         if (err)
2284                                 return err;
2285
2286                         err = flexcan_chip_start(dev);
2287                         if (err)
2288                                 return err;
2289
2290                         flexcan_chip_interrupts_enable(dev);
2291                 }
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2298 {
2299         struct net_device *dev = dev_get_drvdata(device);
2300         struct flexcan_priv *priv = netdev_priv(dev);
2301
2302         flexcan_clks_disable(priv);
2303
2304         return 0;
2305 }
2306
2307 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2308 {
2309         struct net_device *dev = dev_get_drvdata(device);
2310         struct flexcan_priv *priv = netdev_priv(dev);
2311
2312         return flexcan_clks_enable(priv);
2313 }
2314
2315 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2316 {
2317         struct net_device *dev = dev_get_drvdata(device);
2318         struct flexcan_priv *priv = netdev_priv(dev);
2319
2320         if (netif_running(dev)) {
2321                 int err;
2322
2323                 if (device_may_wakeup(device)) {
2324                         flexcan_enable_wakeup_irq(priv, true);
2325                         /* For auto stop mode, need to keep the clock on before
2326                          * system go into low power mode. After system go into
2327                          * low power mode, hardware will config the flexcan into
2328                          * stop mode, and gate off the clock automatically.
2329                          */
2330                         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_AUTO_STOP_MODE)
2331                                 return 0;
2332                 }
2333
2334                 err = pm_runtime_force_suspend(device);
2335                 if (err)
2336                         return err;
2337         }
2338
2339         return 0;
2340 }
2341
2342 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2343 {
2344         struct net_device *dev = dev_get_drvdata(device);
2345         struct flexcan_priv *priv = netdev_priv(dev);
2346
2347         if (netif_running(dev)) {
2348                 int err;
2349
2350                 /* For the wakeup in auto stop mode, no need to gate on the
2351                  * clock here, hardware will do this automatically.
2352                  */
2353                 if (!(device_may_wakeup(device) &&
2354                       priv->devtype_data.quirks & FLEXCAN_QUIRK_AUTO_STOP_MODE)) {
2355                         err = pm_runtime_force_resume(device);
2356                         if (err)
2357                                 return err;
2358                 }
2359
2360                 if (device_may_wakeup(device))
2361                         flexcan_enable_wakeup_irq(priv, false);
2362         }
2363
2364         return 0;
2365 }
2366
2367 static const struct dev_pm_ops flexcan_pm_ops = {
2368         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2369         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2370         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2371 };
2372
2373 static struct platform_driver flexcan_driver = {
2374         .driver = {
2375                 .name = DRV_NAME,
2376                 .pm = &flexcan_pm_ops,
2377                 .of_match_table = flexcan_of_match,
2378         },
2379         .probe = flexcan_probe,
2380         .remove_new = flexcan_remove,
2381         .id_table = flexcan_id_table,
2382 };
2383
2384 module_platform_driver(flexcan_driver);
2385
2386 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2387               "Marc Kleine-Budde <kernel@pengutronix.de>");
2388 MODULE_LICENSE("GPL v2");
2389 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");