1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
51 #include <linux/stringify.h>
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
123 static struct workqueue_struct *bnx2x_wq;
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
129 enum bnx2x_board_type {
137 /* indexed by board_type, above */
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
148 #ifndef PCI_DEVICE_ID_NX2_57712
149 #define PCI_DEVICE_ID_NX2_57712 0x1662
151 #ifndef PCI_DEVICE_ID_NX2_57712E
152 #define PCI_DEVICE_ID_NX2_57712E 0x1663
155 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
156 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
157 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
158 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
159 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
160 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
164 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
166 /****************************************************************************
167 * General service functions
168 ****************************************************************************/
170 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
171 u32 addr, dma_addr_t mapping)
173 REG_WR(bp, addr, U64_LO(mapping));
174 REG_WR(bp, addr + 4, U64_HI(mapping));
177 static inline void __storm_memset_fill(struct bnx2x *bp,
178 u32 addr, size_t size, u32 val)
181 for (i = 0; i < size/4; i++)
182 REG_WR(bp, addr + (i * 4), val);
185 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
186 u8 port, u16 stat_id)
188 size_t size = sizeof(struct ustorm_per_client_stats);
190 u32 addr = BAR_USTRORM_INTMEM +
191 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
193 __storm_memset_fill(bp, addr, size, 0);
196 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
197 u8 port, u16 stat_id)
199 size_t size = sizeof(struct tstorm_per_client_stats);
201 u32 addr = BAR_TSTRORM_INTMEM +
202 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
204 __storm_memset_fill(bp, addr, size, 0);
207 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
208 u8 port, u16 stat_id)
210 size_t size = sizeof(struct xstorm_per_client_stats);
212 u32 addr = BAR_XSTRORM_INTMEM +
213 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
215 __storm_memset_fill(bp, addr, size, 0);
219 static inline void storm_memset_spq_addr(struct bnx2x *bp,
220 dma_addr_t mapping, u16 abs_fid)
222 u32 addr = XSEM_REG_FAST_MEMORY +
223 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
225 __storm_memset_dma_mapping(bp, addr, mapping);
228 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
230 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
233 static inline void storm_memset_func_cfg(struct bnx2x *bp,
234 struct tstorm_eth_function_common_config *tcfg,
237 size_t size = sizeof(struct tstorm_eth_function_common_config);
239 u32 addr = BAR_TSTRORM_INTMEM +
240 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
242 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
245 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
246 struct stats_indication_flags *flags,
249 size_t size = sizeof(struct stats_indication_flags);
251 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
253 __storm_memset_struct(bp, addr, size, (u32 *)flags);
256 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
257 struct stats_indication_flags *flags,
260 size_t size = sizeof(struct stats_indication_flags);
262 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
264 __storm_memset_struct(bp, addr, size, (u32 *)flags);
267 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
268 struct stats_indication_flags *flags,
271 size_t size = sizeof(struct stats_indication_flags);
273 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
275 __storm_memset_struct(bp, addr, size, (u32 *)flags);
278 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
279 struct stats_indication_flags *flags,
282 size_t size = sizeof(struct stats_indication_flags);
284 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
286 __storm_memset_struct(bp, addr, size, (u32 *)flags);
289 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
290 dma_addr_t mapping, u16 abs_fid)
292 u32 addr = BAR_XSTRORM_INTMEM +
293 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
295 __storm_memset_dma_mapping(bp, addr, mapping);
298 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
299 dma_addr_t mapping, u16 abs_fid)
301 u32 addr = BAR_TSTRORM_INTMEM +
302 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
304 __storm_memset_dma_mapping(bp, addr, mapping);
307 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
310 u32 addr = BAR_USTRORM_INTMEM +
311 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
313 __storm_memset_dma_mapping(bp, addr, mapping);
316 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
317 dma_addr_t mapping, u16 abs_fid)
319 u32 addr = BAR_CSTRORM_INTMEM +
320 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
322 __storm_memset_dma_mapping(bp, addr, mapping);
325 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
338 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
341 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
343 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
345 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
347 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
351 static inline void storm_memset_eq_data(struct bnx2x *bp,
352 struct event_ring_data *eq_data,
355 size_t size = sizeof(struct event_ring_data);
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
359 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
362 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
366 REG_WR16(bp, addr, eq_prod);
369 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
370 u16 fw_sb_id, u8 sb_index,
374 int index_offset = CHIP_IS_E2(bp) ?
375 offsetof(struct hc_status_block_data_e2, index_data) :
376 offsetof(struct hc_status_block_data_e1x, index_data);
377 u32 addr = BAR_CSTRORM_INTMEM +
378 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
380 sizeof(struct hc_index_data)*sb_index +
381 offsetof(struct hc_index_data, timeout);
382 REG_WR8(bp, addr, ticks);
383 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
384 port, fw_sb_id, sb_index, ticks);
386 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
387 u16 fw_sb_id, u8 sb_index,
390 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
391 int index_offset = CHIP_IS_E2(bp) ?
392 offsetof(struct hc_status_block_data_e2, index_data) :
393 offsetof(struct hc_status_block_data_e1x, index_data);
394 u32 addr = BAR_CSTRORM_INTMEM +
395 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
397 sizeof(struct hc_index_data)*sb_index +
398 offsetof(struct hc_index_data, flags);
399 u16 flags = REG_RD16(bp, addr);
401 flags &= ~HC_INDEX_DATA_HC_ENABLED;
402 flags |= enable_flag;
403 REG_WR16(bp, addr, flags);
404 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
405 port, fw_sb_id, sb_index, disable);
409 * locking is done by mcp
411 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
414 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
415 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
416 PCICFG_VENDOR_ID_OFFSET);
419 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
423 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
424 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
425 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
426 PCICFG_VENDOR_ID_OFFSET);
431 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
432 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
433 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
434 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
435 #define DMAE_DP_DST_NONE "dst_addr [none]"
437 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
440 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
442 switch (dmae->opcode & DMAE_COMMAND_DST) {
443 case DMAE_CMD_DST_PCI:
444 if (src_type == DMAE_CMD_SRC_PCI)
445 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
447 "comp_addr [%x:%08x], comp_val 0x%08x\n",
448 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
449 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
450 dmae->comp_addr_hi, dmae->comp_addr_lo,
453 DP(msglvl, "DMAE: opcode 0x%08x\n"
454 "src [%08x], len [%d*4], dst [%x:%08x]\n"
455 "comp_addr [%x:%08x], comp_val 0x%08x\n",
456 dmae->opcode, dmae->src_addr_lo >> 2,
457 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
458 dmae->comp_addr_hi, dmae->comp_addr_lo,
461 case DMAE_CMD_DST_GRC:
462 if (src_type == DMAE_CMD_SRC_PCI)
463 DP(msglvl, "DMAE: opcode 0x%08x\n"
464 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
465 "comp_addr [%x:%08x], comp_val 0x%08x\n",
466 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
467 dmae->len, dmae->dst_addr_lo >> 2,
468 dmae->comp_addr_hi, dmae->comp_addr_lo,
471 DP(msglvl, "DMAE: opcode 0x%08x\n"
472 "src [%08x], len [%d*4], dst [%08x]\n"
473 "comp_addr [%x:%08x], comp_val 0x%08x\n",
474 dmae->opcode, dmae->src_addr_lo >> 2,
475 dmae->len, dmae->dst_addr_lo >> 2,
476 dmae->comp_addr_hi, dmae->comp_addr_lo,
480 if (src_type == DMAE_CMD_SRC_PCI)
481 DP(msglvl, "DMAE: opcode 0x%08x\n"
482 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
484 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
485 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
486 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
489 DP(msglvl, "DMAE: opcode 0x%08x\n"
490 DP_LEVEL "src_addr [%08x] len [%d * 4] "
492 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
493 dmae->opcode, dmae->src_addr_lo >> 2,
494 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
501 const u32 dmae_reg_go_c[] = {
502 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
503 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
504 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
505 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
508 /* copy command into DMAE command memory and set DMAE command go */
509 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
514 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
515 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
516 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
518 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
519 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
521 REG_WR(bp, dmae_reg_go_c[idx], 1);
524 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
526 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
530 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
532 return opcode & ~DMAE_CMD_SRC_RESET;
535 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
536 bool with_comp, u8 comp_type)
540 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
541 (dst_type << DMAE_COMMAND_DST_SHIFT));
543 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
545 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
546 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
547 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
548 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
556 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
560 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
561 struct dmae_command *dmae,
562 u8 src_type, u8 dst_type)
564 memset(dmae, 0, sizeof(struct dmae_command));
567 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
568 true, DMAE_COMP_PCI);
570 /* fill in the completion parameters */
571 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
572 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
573 dmae->comp_val = DMAE_COMP_VAL;
576 /* issue a dmae command over the init-channel and wailt for completion */
577 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
578 struct dmae_command *dmae)
580 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
581 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
584 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
585 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
586 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
588 /* lock the dmae channel */
589 mutex_lock(&bp->dmae_mutex);
591 /* reset completion */
594 /* post the command on the channel used for initializations */
595 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
597 /* wait for completion */
599 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
600 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
603 BNX2X_ERR("DMAE timeout!\n");
610 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
611 BNX2X_ERR("DMAE PCI error!\n");
615 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
616 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
617 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
620 mutex_unlock(&bp->dmae_mutex);
624 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
627 struct dmae_command dmae;
629 if (!bp->dmae_ready) {
630 u32 *data = bnx2x_sp(bp, wb_data[0]);
632 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
633 " using indirect\n", dst_addr, len32);
634 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
641 /* fill in addresses and len */
642 dmae.src_addr_lo = U64_LO(dma_addr);
643 dmae.src_addr_hi = U64_HI(dma_addr);
644 dmae.dst_addr_lo = dst_addr >> 2;
645 dmae.dst_addr_hi = 0;
648 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
650 /* issue the command and wait for completion */
651 bnx2x_issue_dmae_with_comp(bp, &dmae);
654 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
656 struct dmae_command dmae;
658 if (!bp->dmae_ready) {
659 u32 *data = bnx2x_sp(bp, wb_data[0]);
662 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
663 " using indirect\n", src_addr, len32);
664 for (i = 0; i < len32; i++)
665 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
669 /* set opcode and fixed command fields */
670 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
672 /* fill in addresses and len */
673 dmae.src_addr_lo = src_addr >> 2;
674 dmae.src_addr_hi = 0;
675 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
676 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
679 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
681 /* issue the command and wait for completion */
682 bnx2x_issue_dmae_with_comp(bp, &dmae);
685 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
688 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
691 while (len > dmae_wr_max) {
692 bnx2x_write_dmae(bp, phys_addr + offset,
693 addr + offset, dmae_wr_max);
694 offset += dmae_wr_max * 4;
698 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
701 /* used only for slowpath so not inlined */
702 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
706 wb_write[0] = val_hi;
707 wb_write[1] = val_lo;
708 REG_WR_DMAE(bp, reg, wb_write, 2);
712 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
716 REG_RD_DMAE(bp, reg, wb_data, 2);
718 return HILO_U64(wb_data[0], wb_data[1]);
722 static int bnx2x_mc_assert(struct bnx2x *bp)
726 u32 row0, row1, row2, row3;
729 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
730 XSTORM_ASSERT_LIST_INDEX_OFFSET);
732 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
737 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
738 XSTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
740 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
742 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
744 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
748 " 0x%08x 0x%08x 0x%08x\n",
749 i, row3, row2, row1, row0);
757 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
758 TSTORM_ASSERT_LIST_INDEX_OFFSET);
760 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
762 /* print the asserts */
763 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
765 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
766 TSTORM_ASSERT_LIST_OFFSET(i));
767 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
768 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
769 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
770 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
771 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
772 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
775 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
776 " 0x%08x 0x%08x 0x%08x\n",
777 i, row3, row2, row1, row0);
785 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
786 CSTORM_ASSERT_LIST_INDEX_OFFSET);
788 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
790 /* print the asserts */
791 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
793 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_ASSERT_LIST_OFFSET(i));
795 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
796 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
797 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
799 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
803 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
804 " 0x%08x 0x%08x 0x%08x\n",
805 i, row3, row2, row1, row0);
813 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
814 USTORM_ASSERT_LIST_INDEX_OFFSET);
816 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
818 /* print the asserts */
819 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
821 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
822 USTORM_ASSERT_LIST_OFFSET(i));
823 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
824 USTORM_ASSERT_LIST_OFFSET(i) + 4);
825 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
826 USTORM_ASSERT_LIST_OFFSET(i) + 8);
827 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
828 USTORM_ASSERT_LIST_OFFSET(i) + 12);
830 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
831 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
832 " 0x%08x 0x%08x 0x%08x\n",
833 i, row3, row2, row1, row0);
843 static void bnx2x_fw_dump(struct bnx2x *bp)
849 u32 trace_shmem_base;
851 BNX2X_ERR("NO MCP - can not dump\n");
855 if (BP_PATH(bp) == 0)
856 trace_shmem_base = bp->common.shmem_base;
858 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
859 addr = trace_shmem_base - 0x0800 + 4;
860 mark = REG_RD(bp, addr);
861 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
862 + ((mark + 0x3) & ~0x3) - 0x08000000;
863 pr_err("begin fw dump (mark 0x%x)\n", mark);
866 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
867 for (word = 0; word < 8; word++)
868 data[word] = htonl(REG_RD(bp, offset + 4*word));
870 pr_cont("%s", (char *)data);
872 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
873 for (word = 0; word < 8; word++)
874 data[word] = htonl(REG_RD(bp, offset + 4*word));
876 pr_cont("%s", (char *)data);
878 pr_err("end of fw dump\n");
881 void bnx2x_panic_dump(struct bnx2x *bp)
885 struct hc_sp_status_block_data sp_sb_data;
886 int func = BP_FUNC(bp);
887 #ifdef BNX2X_STOP_ON_ERROR
888 u16 start = 0, end = 0;
891 bp->stats_state = STATS_STATE_DISABLED;
892 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
894 BNX2X_ERR("begin crash dump -----------------\n");
898 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
899 " spq_prod_idx(0x%x)\n",
900 bp->def_idx, bp->def_att_idx,
901 bp->attn_state, bp->spq_prod_idx);
902 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
903 bp->def_status_blk->atten_status_block.attn_bits,
904 bp->def_status_blk->atten_status_block.attn_bits_ack,
905 bp->def_status_blk->atten_status_block.status_block_id,
906 bp->def_status_blk->atten_status_block.attn_bits_index);
908 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
910 bp->def_status_blk->sp_sb.index_values[i],
911 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
913 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
914 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
918 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
919 "pf_id(0x%x) vnic_id(0x%x) "
920 "vf_id(0x%x) vf_valid (0x%x)\n",
921 sp_sb_data.igu_sb_id,
922 sp_sb_data.igu_seg_id,
923 sp_sb_data.p_func.pf_id,
924 sp_sb_data.p_func.vnic_id,
925 sp_sb_data.p_func.vf_id,
926 sp_sb_data.p_func.vf_valid);
929 for_each_eth_queue(bp, i) {
930 struct bnx2x_fastpath *fp = &bp->fp[i];
932 struct hc_status_block_data_e2 sb_data_e2;
933 struct hc_status_block_data_e1x sb_data_e1x;
934 struct hc_status_block_sm *hc_sm_p =
936 sb_data_e2.common.state_machine :
937 sb_data_e1x.common.state_machine;
938 struct hc_index_data *hc_index_p =
940 sb_data_e2.index_data :
941 sb_data_e1x.index_data;
946 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
947 " rx_comp_prod(0x%x)"
948 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
949 i, fp->rx_bd_prod, fp->rx_bd_cons,
951 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
952 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
953 " fp_hc_idx(0x%x)\n",
954 fp->rx_sge_prod, fp->last_max_sge,
955 le16_to_cpu(fp->fp_hc_idx));
958 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
959 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
960 " *tx_cons_sb(0x%x)\n",
961 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
962 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
964 loop = CHIP_IS_E2(bp) ?
965 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
973 BNX2X_ERR(" run indexes (");
974 for (j = 0; j < HC_SB_MAX_SM; j++)
976 fp->sb_running_index[j],
977 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
979 BNX2X_ERR(" indexes (");
980 for (j = 0; j < loop; j++)
982 fp->sb_index_values[j],
983 (j == loop - 1) ? ")" : " ");
985 data_size = CHIP_IS_E2(bp) ?
986 sizeof(struct hc_status_block_data_e2) :
987 sizeof(struct hc_status_block_data_e1x);
988 data_size /= sizeof(u32);
989 sb_data_p = CHIP_IS_E2(bp) ?
992 /* copy sb data in here */
993 for (j = 0; j < data_size; j++)
994 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
995 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
998 if (CHIP_IS_E2(bp)) {
999 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1000 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1001 sb_data_e2.common.p_func.pf_id,
1002 sb_data_e2.common.p_func.vf_id,
1003 sb_data_e2.common.p_func.vf_valid,
1004 sb_data_e2.common.p_func.vnic_id,
1005 sb_data_e2.common.same_igu_sb_1b);
1007 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1008 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1009 sb_data_e1x.common.p_func.pf_id,
1010 sb_data_e1x.common.p_func.vf_id,
1011 sb_data_e1x.common.p_func.vf_valid,
1012 sb_data_e1x.common.p_func.vnic_id,
1013 sb_data_e1x.common.same_igu_sb_1b);
1017 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018 pr_cont("SM[%d] __flags (0x%x) "
1019 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1020 "time_to_expire (0x%x) "
1021 "timer_value(0x%x)\n", j,
1023 hc_sm_p[j].igu_sb_id,
1024 hc_sm_p[j].igu_seg_id,
1025 hc_sm_p[j].time_to_expire,
1026 hc_sm_p[j].timer_value);
1030 for (j = 0; j < loop; j++) {
1031 pr_cont("INDEX[%d] flags (0x%x) "
1032 "timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1038 #ifdef BNX2X_STOP_ON_ERROR
1041 for_each_rx_queue(bp, i) {
1042 struct bnx2x_fastpath *fp = &bp->fp[i];
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046 for (j = start; j != end; j = RX_BD(j + 1)) {
1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1075 for_each_tx_queue(bp, i) {
1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1078 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080 for (j = start; j != end; j = TX_BD(j + 1)) {
1081 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1083 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084 i, j, sw_bd->skb, sw_bd->first_bd);
1087 start = TX_BD(fp->tx_bd_cons - 10);
1088 end = TX_BD(fp->tx_bd_cons + 254);
1089 for (j = start; j != end; j = TX_BD(j + 1)) {
1090 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1092 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1098 bnx2x_mc_assert(bp);
1099 BNX2X_ERR("end crash dump -----------------\n");
1102 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1104 int port = BP_PORT(bp);
1105 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106 u32 val = REG_RD(bp, addr);
1107 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1108 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1111 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112 HC_CONFIG_0_REG_INT_LINE_EN_0);
1113 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1116 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1121 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1122 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1123 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1126 if (!CHIP_IS_E1(bp)) {
1127 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1130 REG_WR(bp, addr, val);
1132 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1137 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1139 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1140 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1142 REG_WR(bp, addr, val);
1144 * Ensure that HC_CONFIG is written before leading/trailing edge config
1149 if (!CHIP_IS_E1(bp)) {
1150 /* init leading/trailing edge */
1152 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1154 /* enable nig and gpio3 attention */
1159 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1163 /* Make sure that interrupts are indeed enabled from here on */
1167 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1170 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1173 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1176 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177 IGU_PF_CONF_SINGLE_ISR_EN);
1178 val |= (IGU_PF_CONF_FUNC_EN |
1179 IGU_PF_CONF_MSI_MSIX_EN |
1180 IGU_PF_CONF_ATTN_BIT_EN);
1182 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_MSI_MSIX_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1188 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189 val |= (IGU_PF_CONF_FUNC_EN |
1190 IGU_PF_CONF_INT_LINE_EN |
1191 IGU_PF_CONF_ATTN_BIT_EN |
1192 IGU_PF_CONF_SINGLE_ISR_EN);
1195 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1196 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1198 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1202 /* init leading/trailing edge */
1204 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1206 /* enable nig and gpio3 attention */
1211 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1214 /* Make sure that interrupts are indeed enabled from here on */
1218 void bnx2x_int_enable(struct bnx2x *bp)
1220 if (bp->common.int_block == INT_BLOCK_HC)
1221 bnx2x_hc_int_enable(bp);
1223 bnx2x_igu_int_enable(bp);
1226 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1228 int port = BP_PORT(bp);
1229 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230 u32 val = REG_RD(bp, addr);
1233 * in E1 we must use only PCI configuration space to disable
1234 * MSI/MSIX capablility
1235 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1237 if (CHIP_IS_E1(bp)) {
1238 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239 * Use mask register to prevent from HC sending interrupts
1240 * after we exit the function
1242 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1244 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1253 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1256 /* flush all outstanding writes */
1259 REG_WR(bp, addr, val);
1260 if (REG_RD(bp, addr) != val)
1261 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1264 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1266 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1268 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269 IGU_PF_CONF_INT_LINE_EN |
1270 IGU_PF_CONF_ATTN_BIT_EN);
1272 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1274 /* flush all outstanding writes */
1277 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1282 static void bnx2x_int_disable(struct bnx2x *bp)
1284 if (bp->common.int_block == INT_BLOCK_HC)
1285 bnx2x_hc_int_disable(bp);
1287 bnx2x_igu_int_disable(bp);
1290 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1292 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1295 /* disable interrupt handling */
1296 atomic_inc(&bp->intr_sem);
1297 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1300 /* prevent the HW from sending interrupts */
1301 bnx2x_int_disable(bp);
1303 /* make sure all ISRs are done */
1305 synchronize_irq(bp->msix_table[0].vector);
1310 for_each_eth_queue(bp, i)
1311 synchronize_irq(bp->msix_table[i + offset].vector);
1313 synchronize_irq(bp->pdev->irq);
1315 /* make sure sp_task is not running */
1316 cancel_delayed_work(&bp->sp_task);
1317 flush_workqueue(bnx2x_wq);
1323 * General service functions
1326 /* Return true if succeeded to acquire the lock */
1327 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1330 u32 resource_bit = (1 << resource);
1331 int func = BP_FUNC(bp);
1332 u32 hw_lock_control_reg;
1334 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1336 /* Validating that the resource is within range */
1337 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1339 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1345 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1347 hw_lock_control_reg =
1348 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1350 /* Try to acquire the lock */
1351 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352 lock_status = REG_RD(bp, hw_lock_control_reg);
1353 if (lock_status & resource_bit)
1356 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1361 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1364 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1365 union eth_rx_cqe *rr_cqe)
1367 struct bnx2x *bp = fp->bp;
1368 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1372 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1373 fp->index, cid, command, bp->state,
1374 rr_cqe->ramrod_cqe.ramrod_type);
1376 switch (command | fp->state) {
1377 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379 fp->state = BNX2X_FP_STATE_OPEN;
1382 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1384 fp->state = BNX2X_FP_STATE_HALTED;
1387 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389 fp->state = BNX2X_FP_STATE_TERMINATED;
1393 BNX2X_ERR("unexpected MC reply (%d) "
1394 "fp[%d] state is %x\n",
1395 command, fp->index, fp->state);
1399 smp_mb__before_atomic_inc();
1400 atomic_inc(&bp->spq_left);
1401 /* push the change in fp->state and towards the memory */
1407 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1409 struct bnx2x *bp = netdev_priv(dev_instance);
1410 u16 status = bnx2x_ack_int(bp);
1414 /* Return here if interrupt is shared and it's not for us */
1415 if (unlikely(status == 0)) {
1416 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1419 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1421 /* Return here if interrupt is disabled */
1422 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1427 #ifdef BNX2X_STOP_ON_ERROR
1428 if (unlikely(bp->panic))
1432 for_each_eth_queue(bp, i) {
1433 struct bnx2x_fastpath *fp = &bp->fp[i];
1435 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1436 if (status & mask) {
1437 /* Handle Rx and Tx according to SB id */
1438 prefetch(fp->rx_cons_sb);
1439 prefetch(fp->tx_cons_sb);
1440 prefetch(&fp->sb_running_index[SM_RX_ID]);
1441 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1448 if (status & (mask | 0x1)) {
1449 struct cnic_ops *c_ops = NULL;
1452 c_ops = rcu_dereference(bp->cnic_ops);
1454 c_ops->cnic_handler(bp->cnic_data, NULL);
1461 if (unlikely(status & 0x1)) {
1462 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1469 if (unlikely(status))
1470 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1476 /* end of fast path */
1482 * General service functions
1485 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1488 u32 resource_bit = (1 << resource);
1489 int func = BP_FUNC(bp);
1490 u32 hw_lock_control_reg;
1493 /* Validating that the resource is within range */
1494 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1496 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1502 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1504 hw_lock_control_reg =
1505 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1508 /* Validating that the resource is not already taken */
1509 lock_status = REG_RD(bp, hw_lock_control_reg);
1510 if (lock_status & resource_bit) {
1511 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1512 lock_status, resource_bit);
1516 /* Try for 5 second every 5ms */
1517 for (cnt = 0; cnt < 1000; cnt++) {
1518 /* Try to acquire the lock */
1519 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520 lock_status = REG_RD(bp, hw_lock_control_reg);
1521 if (lock_status & resource_bit)
1526 DP(NETIF_MSG_HW, "Timeout\n");
1530 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1533 u32 resource_bit = (1 << resource);
1534 int func = BP_FUNC(bp);
1535 u32 hw_lock_control_reg;
1537 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1539 /* Validating that the resource is within range */
1540 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1542 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1548 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1550 hw_lock_control_reg =
1551 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1554 /* Validating that the resource is currently taken */
1555 lock_status = REG_RD(bp, hw_lock_control_reg);
1556 if (!(lock_status & resource_bit)) {
1557 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1558 lock_status, resource_bit);
1562 REG_WR(bp, hw_lock_control_reg, resource_bit);
1567 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1569 /* The GPIO should be swapped if swap register is set and active */
1570 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572 int gpio_shift = gpio_num +
1573 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574 u32 gpio_mask = (1 << gpio_shift);
1578 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1583 /* read GPIO value */
1584 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1586 /* get the requested pin value */
1587 if ((gpio_reg & gpio_mask) == gpio_mask)
1592 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1597 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1599 /* The GPIO should be swapped if swap register is set and active */
1600 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1601 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1602 int gpio_shift = gpio_num +
1603 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604 u32 gpio_mask = (1 << gpio_shift);
1607 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1612 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1613 /* read GPIO and mask except the float bits */
1614 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1617 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619 gpio_num, gpio_shift);
1620 /* clear FLOAT and set CLR */
1621 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1625 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627 gpio_num, gpio_shift);
1628 /* clear FLOAT and set SET */
1629 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1633 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1634 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635 gpio_num, gpio_shift);
1637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1644 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1645 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1650 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1652 /* The GPIO should be swapped if swap register is set and active */
1653 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655 int gpio_shift = gpio_num +
1656 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657 u32 gpio_mask = (1 << gpio_shift);
1660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1665 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1667 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1670 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672 "output low\n", gpio_num, gpio_shift);
1673 /* clear SET and set CLR */
1674 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1678 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680 "output high\n", gpio_num, gpio_shift);
1681 /* clear CLR and set SET */
1682 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1690 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1696 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1698 u32 spio_mask = (1 << spio_num);
1701 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702 (spio_num > MISC_REGISTERS_SPIO_7)) {
1703 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1707 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1708 /* read SPIO and mask except the float bits */
1709 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1712 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714 /* clear FLOAT and set CLR */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1719 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721 /* clear FLOAT and set SET */
1722 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1726 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1729 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1736 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1737 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1742 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1744 u32 sel_phy_idx = 0;
1745 if (bp->link_vars.link_up) {
1746 sel_phy_idx = EXT_PHY1;
1747 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750 sel_phy_idx = EXT_PHY2;
1753 switch (bnx2x_phy_selection(&bp->link_params)) {
1754 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757 sel_phy_idx = EXT_PHY1;
1759 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761 sel_phy_idx = EXT_PHY2;
1766 * The selected actived PHY is always after swapping (in case PHY
1767 * swapping is enabled). So when swapping is enabled, we need to reverse
1771 if (bp->link_params.multi_phy_config &
1772 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773 if (sel_phy_idx == EXT_PHY1)
1774 sel_phy_idx = EXT_PHY2;
1775 else if (sel_phy_idx == EXT_PHY2)
1776 sel_phy_idx = EXT_PHY1;
1778 return LINK_CONFIG_IDX(sel_phy_idx);
1781 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1783 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1784 switch (bp->link_vars.ieee_fc &
1785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1786 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1787 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1791 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1792 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1796 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1797 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1801 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1807 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1809 if (!BP_NOMCP(bp)) {
1811 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1813 /* Initialize link parameters structure variables */
1814 /* It is recommended to turn off RX FC for jumbo frames
1815 for better performance */
1816 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1817 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1819 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1821 bnx2x_acquire_phy_lock(bp);
1823 if (load_mode == LOAD_DIAG) {
1824 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1825 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1828 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1830 bnx2x_release_phy_lock(bp);
1832 bnx2x_calc_fc_adv(bp);
1834 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1836 bnx2x_link_report(bp);
1838 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1841 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1845 void bnx2x_link_set(struct bnx2x *bp)
1847 if (!BP_NOMCP(bp)) {
1848 bnx2x_acquire_phy_lock(bp);
1849 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1850 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1851 bnx2x_release_phy_lock(bp);
1853 bnx2x_calc_fc_adv(bp);
1855 BNX2X_ERR("Bootcode is missing - can not set link\n");
1858 static void bnx2x__link_reset(struct bnx2x *bp)
1860 if (!BP_NOMCP(bp)) {
1861 bnx2x_acquire_phy_lock(bp);
1862 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1863 bnx2x_release_phy_lock(bp);
1865 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1868 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1872 if (!BP_NOMCP(bp)) {
1873 bnx2x_acquire_phy_lock(bp);
1874 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1876 bnx2x_release_phy_lock(bp);
1878 BNX2X_ERR("Bootcode is missing - can not test link\n");
1883 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1885 u32 r_param = bp->link_vars.line_speed / 8;
1886 u32 fair_periodic_timeout_usec;
1889 memset(&(bp->cmng.rs_vars), 0,
1890 sizeof(struct rate_shaping_vars_per_port));
1891 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1893 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1896 /* this is the threshold below which no timer arming will occur
1897 1.25 coefficient is for the threshold to be a little bigger
1898 than the real time, to compensate for timer in-accuracy */
1899 bp->cmng.rs_vars.rs_threshold =
1900 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1902 /* resolution of fairness timer */
1903 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1907 /* this is the threshold below which we won't arm the timer anymore */
1908 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1910 /* we multiply by 1e3/8 to get bytes/msec.
1911 We don't want the credits to pass a credit
1912 of the t_fair*FAIR_MEM (algorithm resolution) */
1913 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914 /* since each tick is 4 usec */
1915 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1918 /* Calculates the sum of vn_min_rates.
1919 It's needed for further normalizing of the min_rates.
1921 sum of vn_min_rates.
1923 0 - if all the min_rates are 0.
1924 In the later case fainess algorithm should be deactivated.
1925 If not all min_rates are zero then those that are zeroes will be set to 1.
1927 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1932 bp->vn_weight_sum = 0;
1933 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1934 u32 vn_cfg = bp->mf_config[vn];
1935 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1938 /* Skip hidden vns */
1939 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1942 /* If min rate is zero - set it to 1 */
1944 vn_min_rate = DEF_MIN_RATE;
1948 bp->vn_weight_sum += vn_min_rate;
1951 /* ... only if all min rates are zeros - disable fairness */
1953 bp->cmng.flags.cmng_enables &=
1954 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956 " fairness will be disabled\n");
1958 bp->cmng.flags.cmng_enables |=
1959 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1962 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1964 struct rate_shaping_vars_per_vn m_rs_vn;
1965 struct fairness_vars_per_vn m_fair_vn;
1966 u32 vn_cfg = bp->mf_config[vn];
1967 int func = 2*vn + BP_PORT(bp);
1968 u16 vn_min_rate, vn_max_rate;
1971 /* If function is hidden - set min and max to zeroes */
1972 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1977 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1979 /* If min rate is zero - set it to 1 */
1980 if (bp->vn_weight_sum && (vn_min_rate == 0))
1981 vn_min_rate = DEF_MIN_RATE;
1982 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1987 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1988 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1990 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1993 /* global vn counter - maximal Mbps for this vn */
1994 m_rs_vn.vn_counter.rate = vn_max_rate;
1996 /* quota - number of bytes transmitted in this period */
1997 m_rs_vn.vn_counter.quota =
1998 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2000 if (bp->vn_weight_sum) {
2001 /* credit for each period of the fairness algorithm:
2002 number of bytes in T_FAIR (the vn share the port rate).
2003 vn_weight_sum should not be larger than 10000, thus
2004 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2006 m_fair_vn.vn_credit_delta =
2007 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008 (8 * bp->vn_weight_sum))),
2009 (bp->cmng.fair_vars.fair_threshold * 2));
2010 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2011 m_fair_vn.vn_credit_delta);
2014 /* Store it to internal memory */
2015 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018 ((u32 *)(&m_rs_vn))[i]);
2020 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023 ((u32 *)(&m_fair_vn))[i]);
2026 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2028 if (CHIP_REV_IS_SLOW(bp))
2029 return CMNG_FNS_NONE;
2031 return CMNG_FNS_MINMAX;
2033 return CMNG_FNS_NONE;
2036 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2038 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2041 return; /* what should be the default bvalue in this case */
2043 /* For 2 port configuration the absolute function number formula
2045 * abs_func = 2 * vn + BP_PORT + BP_PATH
2047 * and there are 4 functions per port
2049 * For 4 port configuration it is
2050 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2052 * and there are 2 functions per port
2054 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2055 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2057 if (func >= E1H_FUNC_MAX)
2061 MF_CFG_RD(bp, func_mf_config[func].config);
2065 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2068 if (cmng_type == CMNG_FNS_MINMAX) {
2071 /* clear cmng_enables */
2072 bp->cmng.flags.cmng_enables = 0;
2074 /* read mf conf from shmem */
2076 bnx2x_read_mf_cfg(bp);
2078 /* Init rate shaping and fairness contexts */
2079 bnx2x_init_port_minmax(bp);
2081 /* vn_weight_sum and enable fairness if not 0 */
2082 bnx2x_calc_vn_weight_sum(bp);
2084 /* calculate and set min-max rate for each vn */
2085 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086 bnx2x_init_vn_minmax(bp, vn);
2088 /* always enable rate shaping and fairness */
2089 bp->cmng.flags.cmng_enables |=
2090 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091 if (!bp->vn_weight_sum)
2092 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093 " fairness will be disabled\n");
2097 /* rate shaping and fairness are disabled */
2099 "rate shaping and fairness are disabled\n");
2102 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2104 int port = BP_PORT(bp);
2108 /* Set the attention towards other drivers on the same port */
2109 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110 if (vn == BP_E1HVN(bp))
2113 func = ((vn << 1) | port);
2114 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2119 /* This function is called upon link interrupt */
2120 static void bnx2x_link_attn(struct bnx2x *bp)
2122 u32 prev_link_status = bp->link_vars.link_status;
2123 /* Make sure that we are synced with the current statistics */
2124 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2126 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2128 if (bp->link_vars.link_up) {
2130 /* dropless flow control */
2131 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2132 int port = BP_PORT(bp);
2133 u32 pause_enabled = 0;
2135 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2138 REG_WR(bp, BAR_USTRORM_INTMEM +
2139 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2143 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144 struct host_port_stats *pstats;
2146 pstats = bnx2x_sp(bp, port_stats);
2147 /* reset old bmac stats */
2148 memset(&(pstats->mac_stx[0]), 0,
2149 sizeof(struct mac_stx));
2151 if (bp->state == BNX2X_STATE_OPEN)
2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2155 /* indicate link status only if link status actually changed */
2156 if (prev_link_status != bp->link_vars.link_status)
2157 bnx2x_link_report(bp);
2160 bnx2x_link_sync_notify(bp);
2162 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2165 if (cmng_fns != CMNG_FNS_NONE) {
2166 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2169 /* rate shaping and fairness are disabled */
2171 "single function mode without fairness\n");
2175 void bnx2x__link_status_update(struct bnx2x *bp)
2177 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
2180 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2182 if (bp->link_vars.link_up)
2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2185 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2187 /* the link status update could be the result of a DCC event
2188 hence re-read the shmem mf configuration */
2189 bnx2x_read_mf_cfg(bp);
2191 /* indicate link status */
2192 bnx2x_link_report(bp);
2195 static void bnx2x_pmf_update(struct bnx2x *bp)
2197 int port = BP_PORT(bp);
2201 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2203 /* enable nig attention */
2204 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2205 if (bp->common.int_block == INT_BLOCK_HC) {
2206 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208 } else if (CHIP_IS_E2(bp)) {
2209 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2213 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2221 * General service functions
2224 /* send the MCP a request, block until there is a reply */
2225 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2227 int mb_idx = BP_FW_MB_IDX(bp);
2228 u32 seq = ++bp->fw_seq;
2231 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2233 mutex_lock(&bp->fw_mb_mutex);
2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2237 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2240 /* let the FW do it's magic ... */
2243 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2245 /* Give the FW up to 5 second (500*10ms) */
2246 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2248 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249 cnt*delay, rc, seq);
2251 /* is this a reply to our command? */
2252 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253 rc &= FW_MSG_CODE_MASK;
2256 BNX2X_ERR("FW failed to respond!\n");
2260 mutex_unlock(&bp->fw_mb_mutex);
2265 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2268 if (IS_FCOE_FP(fp) && IS_MF(bp))
2274 /* must be called under rtnl_lock */
2275 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2277 u32 mask = (1 << cl_id);
2279 /* initial seeting is BNX2X_ACCEPT_NONE */
2280 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282 u8 unmatched_unicast = 0;
2284 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285 unmatched_unicast = 1;
2287 if (filters & BNX2X_PROMISCUOUS_MODE) {
2288 /* promiscious - accept all, drop none */
2289 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2293 * SI mode defines to accept in promiscuos mode
2294 * only unmatched packets
2296 unmatched_unicast = 1;
2300 if (filters & BNX2X_ACCEPT_UNICAST) {
2301 /* accept matched ucast */
2304 if (filters & BNX2X_ACCEPT_MULTICAST) {
2305 /* accept matched mcast */
2308 /* since mcast addresses won't arrive with ovlan,
2309 * fw needs to accept all of them in
2310 * switch-independent mode */
2313 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2314 /* accept all mcast */
2318 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2319 /* accept all mcast */
2323 if (filters & BNX2X_ACCEPT_BROADCAST) {
2324 /* accept (all) bcast */
2329 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2330 bp->mac_filters.ucast_drop_all | mask :
2331 bp->mac_filters.ucast_drop_all & ~mask;
2333 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2334 bp->mac_filters.mcast_drop_all | mask :
2335 bp->mac_filters.mcast_drop_all & ~mask;
2337 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2338 bp->mac_filters.bcast_drop_all | mask :
2339 bp->mac_filters.bcast_drop_all & ~mask;
2341 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2342 bp->mac_filters.ucast_accept_all | mask :
2343 bp->mac_filters.ucast_accept_all & ~mask;
2345 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2346 bp->mac_filters.mcast_accept_all | mask :
2347 bp->mac_filters.mcast_accept_all & ~mask;
2349 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2350 bp->mac_filters.bcast_accept_all | mask :
2351 bp->mac_filters.bcast_accept_all & ~mask;
2353 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2354 bp->mac_filters.unmatched_unicast | mask :
2355 bp->mac_filters.unmatched_unicast & ~mask;
2358 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2360 struct tstorm_eth_function_common_config tcfg = {0};
2364 if (p->func_flgs & FUNC_FLG_TPA)
2365 tcfg.config_flags |=
2366 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2369 rss_flgs = (p->rss->mode <<
2370 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2372 if (p->rss->cap & RSS_IPV4_CAP)
2373 rss_flgs |= RSS_IPV4_CAP_MASK;
2374 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2375 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2376 if (p->rss->cap & RSS_IPV6_CAP)
2377 rss_flgs |= RSS_IPV6_CAP_MASK;
2378 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2379 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2381 tcfg.config_flags |= rss_flgs;
2382 tcfg.rss_result_mask = p->rss->result_mask;
2384 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2386 /* Enable the function in the FW */
2387 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2388 storm_memset_func_en(bp, p->func_id, 1);
2391 if (p->func_flgs & FUNC_FLG_STATS) {
2392 struct stats_indication_flags stats_flags = {0};
2393 stats_flags.collect_eth = 1;
2395 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2396 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2398 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2399 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2401 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2402 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2404 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2405 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2409 if (p->func_flgs & FUNC_FLG_SPQ) {
2410 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2411 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2412 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2416 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2417 struct bnx2x_fastpath *fp)
2421 /* calculate queue flags */
2422 flags |= QUEUE_FLG_CACHE_ALIGN;
2423 flags |= QUEUE_FLG_HC;
2424 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2426 flags |= QUEUE_FLG_VLAN;
2427 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2429 if (!fp->disable_tpa)
2430 flags |= QUEUE_FLG_TPA;
2432 flags = stat_counter_valid(bp, fp) ?
2433 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2438 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2439 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2440 struct bnx2x_rxq_init_params *rxq_init)
2444 u16 tpa_agg_size = 0;
2446 /* calculate queue flags */
2447 u16 flags = bnx2x_get_cl_flags(bp, fp);
2449 if (!fp->disable_tpa) {
2450 pause->sge_th_hi = 250;
2451 pause->sge_th_lo = 150;
2452 tpa_agg_size = min_t(u32,
2453 (min_t(u32, 8, MAX_SKB_FRAGS) *
2454 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2455 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2457 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2458 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2459 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2463 /* pause - not for e1 */
2464 if (!CHIP_IS_E1(bp)) {
2465 pause->bd_th_hi = 350;
2466 pause->bd_th_lo = 250;
2467 pause->rcq_th_hi = 350;
2468 pause->rcq_th_lo = 250;
2469 pause->sge_th_hi = 0;
2470 pause->sge_th_lo = 0;
2475 rxq_init->flags = flags;
2476 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2477 rxq_init->dscr_map = fp->rx_desc_mapping;
2478 rxq_init->sge_map = fp->rx_sge_mapping;
2479 rxq_init->rcq_map = fp->rx_comp_mapping;
2480 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2481 rxq_init->mtu = bp->dev->mtu;
2482 rxq_init->buf_sz = bp->rx_buf_size;
2483 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484 rxq_init->cl_id = fp->cl_id;
2485 rxq_init->spcl_id = fp->cl_id;
2486 rxq_init->stat_id = fp->cl_id;
2487 rxq_init->tpa_agg_sz = tpa_agg_size;
2488 rxq_init->sge_buf_sz = sge_sz;
2489 rxq_init->max_sges_pkt = max_sge;
2490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491 rxq_init->fw_sb_id = fp->fw_sb_id;
2494 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2496 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2498 rxq_init->cid = HW_CID(bp, fp->cid);
2500 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2503 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2506 u16 flags = bnx2x_get_cl_flags(bp, fp);
2508 txq_init->flags = flags;
2509 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510 txq_init->dscr_map = fp->tx_desc_mapping;
2511 txq_init->stat_id = fp->cl_id;
2512 txq_init->cid = HW_CID(bp, fp->cid);
2513 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515 txq_init->fw_sb_id = fp->fw_sb_id;
2517 if (IS_FCOE_FP(fp)) {
2518 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2522 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2525 static void bnx2x_pf_init(struct bnx2x *bp)
2527 struct bnx2x_func_init_params func_init = {0};
2528 struct bnx2x_rss_params rss = {0};
2529 struct event_ring_data eq_data = { {0} };
2532 /* pf specific setups */
2533 if (!CHIP_IS_E1(bp))
2534 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2536 if (CHIP_IS_E2(bp)) {
2537 /* reset IGU PF statistics: MSIX + ATTN */
2539 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541 (CHIP_MODE_IS_4_PORT(bp) ?
2542 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547 (CHIP_MODE_IS_4_PORT(bp) ?
2548 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2551 /* function setup flags */
2552 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2554 if (CHIP_IS_E1x(bp))
2555 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2557 flags |= FUNC_FLG_TPA;
2559 /* function setup */
2562 * Although RSS is meaningless when there is a single HW queue we
2563 * still need it enabled in order to have HW Rx hash generated.
2565 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567 rss.mode = bp->multi_mode;
2568 rss.result_mask = MULTI_MASK;
2569 func_init.rss = &rss;
2571 func_init.func_flgs = flags;
2572 func_init.pf_id = BP_FUNC(bp);
2573 func_init.func_id = BP_FUNC(bp);
2574 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575 func_init.spq_map = bp->spq_mapping;
2576 func_init.spq_prod = bp->spq_prod_idx;
2578 bnx2x_func_init(bp, &func_init);
2580 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2583 Congestion management values depend on the link rate
2584 There is no active link so initial link rate is set to 10 Gbps.
2585 When the link comes up The congestion management values are
2586 re-calculated according to the actual link rate.
2588 bp->link_vars.line_speed = SPEED_10000;
2589 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2591 /* Only the PMF sets the HW */
2593 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2595 /* no rx until link is up */
2596 bp->rx_mode = BNX2X_RX_MODE_NONE;
2597 bnx2x_set_storm_rx_mode(bp);
2599 /* init Event Queue */
2600 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602 eq_data.producer = bp->eq_prod;
2603 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604 eq_data.sb_id = DEF_SB_ID;
2605 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2609 static void bnx2x_e1h_disable(struct bnx2x *bp)
2611 int port = BP_PORT(bp);
2613 netif_tx_disable(bp->dev);
2615 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2617 netif_carrier_off(bp->dev);
2620 static void bnx2x_e1h_enable(struct bnx2x *bp)
2622 int port = BP_PORT(bp);
2624 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2626 /* Tx queue should be only reenabled */
2627 netif_tx_wake_all_queues(bp->dev);
2630 * Should not call netif_carrier_on since it will be called if the link
2631 * is up when checking for link state
2635 /* called due to MCP event (on pmf):
2636 * reread new bandwidth configuration
2638 * notify others function about the change
2640 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2642 if (bp->link_vars.link_up) {
2643 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2644 bnx2x_link_sync_notify(bp);
2646 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2649 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2651 bnx2x_config_mf_bw(bp);
2652 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2655 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2657 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2659 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2662 * This is the only place besides the function initialization
2663 * where the bp->flags can change so it is done without any
2666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2667 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2668 bp->flags |= MF_FUNC_DIS;
2670 bnx2x_e1h_disable(bp);
2672 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2673 bp->flags &= ~MF_FUNC_DIS;
2675 bnx2x_e1h_enable(bp);
2677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2680 bnx2x_config_mf_bw(bp);
2681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2684 /* Report results to MCP */
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2691 /* must be called under the spq lock */
2692 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2694 struct eth_spe *next_spe = bp->spq_prod_bd;
2696 if (bp->spq_prod_bd == bp->spq_last_bd) {
2697 bp->spq_prod_bd = bp->spq;
2698 bp->spq_prod_idx = 0;
2699 DP(NETIF_MSG_TIMER, "end of spq\n");
2707 /* must be called under the spq lock */
2708 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2710 int func = BP_FUNC(bp);
2712 /* Make sure that BD data is updated before writing the producer */
2715 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2720 /* the slow path queue is odd since completions arrive on the fastpath ring */
2721 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2722 u32 data_hi, u32 data_lo, int common)
2724 struct eth_spe *spe;
2727 #ifdef BNX2X_STOP_ON_ERROR
2728 if (unlikely(bp->panic))
2732 spin_lock_bh(&bp->spq_lock);
2734 if (!atomic_read(&bp->spq_left)) {
2735 BNX2X_ERR("BUG! SPQ ring full!\n");
2736 spin_unlock_bh(&bp->spq_lock);
2741 spe = bnx2x_sp_get_next(bp);
2743 /* CID needs port number to be encoded int it */
2744 spe->hdr.conn_and_cmd_data =
2745 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2750 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2751 * TRAFFIC_STOP, TRAFFIC_START
2753 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2754 & SPE_HDR_CONN_TYPE;
2756 /* ETH ramrods: SETUP, HALT */
2757 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2758 & SPE_HDR_CONN_TYPE;
2760 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2761 SPE_HDR_FUNCTION_ID);
2763 spe->hdr.type = cpu_to_le16(type);
2765 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2766 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2768 /* stats ramrod has it's own slot on the spq */
2769 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2770 /* It's ok if the actual decrement is issued towards the memory
2771 * somewhere between the spin_lock and spin_unlock. Thus no
2772 * more explict memory barrier is needed.
2774 atomic_dec(&bp->spq_left);
2776 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2777 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2778 "type(0x%x) left %x\n",
2779 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2780 (u32)(U64_LO(bp->spq_mapping) +
2781 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2782 HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
2784 bnx2x_sp_prod_update(bp);
2785 spin_unlock_bh(&bp->spq_lock);
2789 /* acquire split MCP access lock register */
2790 static int bnx2x_acquire_alr(struct bnx2x *bp)
2796 for (j = 0; j < 1000; j++) {
2798 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2799 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2800 if (val & (1L << 31))
2805 if (!(val & (1L << 31))) {
2806 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2813 /* release split MCP access lock register */
2814 static void bnx2x_release_alr(struct bnx2x *bp)
2816 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2819 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2820 #define BNX2X_DEF_SB_IDX 0x0002
2822 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2824 struct host_sp_status_block *def_sb = bp->def_status_blk;
2827 barrier(); /* status block is written to by the chip */
2828 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2829 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2830 rc |= BNX2X_DEF_SB_ATT_IDX;
2833 if (bp->def_idx != def_sb->sp_sb.running_index) {
2834 bp->def_idx = def_sb->sp_sb.running_index;
2835 rc |= BNX2X_DEF_SB_IDX;
2838 /* Do not reorder: indecies reading should complete before handling */
2844 * slow path service functions
2847 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2849 int port = BP_PORT(bp);
2850 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2851 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2852 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2853 NIG_REG_MASK_INTERRUPT_PORT0;
2858 if (bp->attn_state & asserted)
2859 BNX2X_ERR("IGU ERROR\n");
2861 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2862 aeu_mask = REG_RD(bp, aeu_addr);
2864 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2865 aeu_mask, asserted);
2866 aeu_mask &= ~(asserted & 0x3ff);
2867 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2869 REG_WR(bp, aeu_addr, aeu_mask);
2870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2872 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2873 bp->attn_state |= asserted;
2874 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2876 if (asserted & ATTN_HARD_WIRED_MASK) {
2877 if (asserted & ATTN_NIG_FOR_FUNC) {
2879 bnx2x_acquire_phy_lock(bp);
2881 /* save nig interrupt mask */
2882 nig_mask = REG_RD(bp, nig_int_mask_addr);
2883 REG_WR(bp, nig_int_mask_addr, 0);
2885 bnx2x_link_attn(bp);
2887 /* handle unicore attn? */
2889 if (asserted & ATTN_SW_TIMER_4_FUNC)
2890 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2892 if (asserted & GPIO_2_FUNC)
2893 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2895 if (asserted & GPIO_3_FUNC)
2896 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2898 if (asserted & GPIO_4_FUNC)
2899 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2902 if (asserted & ATTN_GENERAL_ATTN_1) {
2903 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2904 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2906 if (asserted & ATTN_GENERAL_ATTN_2) {
2907 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2908 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2910 if (asserted & ATTN_GENERAL_ATTN_3) {
2911 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2912 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2915 if (asserted & ATTN_GENERAL_ATTN_4) {
2916 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2917 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2919 if (asserted & ATTN_GENERAL_ATTN_5) {
2920 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2921 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2923 if (asserted & ATTN_GENERAL_ATTN_6) {
2924 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2925 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2929 } /* if hardwired */
2931 if (bp->common.int_block == INT_BLOCK_HC)
2932 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2933 COMMAND_REG_ATTN_BITS_SET);
2935 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2937 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2938 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2939 REG_WR(bp, reg_addr, asserted);
2941 /* now set back the mask */
2942 if (asserted & ATTN_NIG_FOR_FUNC) {
2943 REG_WR(bp, nig_int_mask_addr, nig_mask);
2944 bnx2x_release_phy_lock(bp);
2948 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2950 int port = BP_PORT(bp);
2952 /* mark the failure */
2955 dev_info.port_hw_config[port].external_phy_config);
2957 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2958 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2959 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2962 /* log the failure */
2963 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2964 " the driver to shutdown the card to prevent permanent"
2965 " damage. Please contact OEM Support for assistance\n");
2968 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2970 int port = BP_PORT(bp);
2974 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2977 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2979 val = REG_RD(bp, reg_offset);
2980 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2981 REG_WR(bp, reg_offset, val);
2983 BNX2X_ERR("SPIO5 hw attention\n");
2985 /* Fan failure attention */
2986 bnx2x_hw_reset_phy(&bp->link_params);
2987 bnx2x_fan_failure(bp);
2990 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2991 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2992 bnx2x_acquire_phy_lock(bp);
2993 bnx2x_handle_module_detect_int(&bp->link_params);
2994 bnx2x_release_phy_lock(bp);
2997 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2999 val = REG_RD(bp, reg_offset);
3000 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3001 REG_WR(bp, reg_offset, val);
3003 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3004 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3009 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3013 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3015 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3016 BNX2X_ERR("DB hw attention 0x%x\n", val);
3017 /* DORQ discard attention */
3019 BNX2X_ERR("FATAL error from DORQ\n");
3022 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3024 int port = BP_PORT(bp);
3027 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3028 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3030 val = REG_RD(bp, reg_offset);
3031 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3032 REG_WR(bp, reg_offset, val);
3034 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3035 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3040 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3044 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3046 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3047 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3048 /* CFC error attention */
3050 BNX2X_ERR("FATAL error from CFC\n");
3053 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3055 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3056 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3057 /* RQ_USDMDP_FIFO_OVERFLOW */
3059 BNX2X_ERR("FATAL error from PXP\n");
3060 if (CHIP_IS_E2(bp)) {
3061 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3062 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3066 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3068 int port = BP_PORT(bp);
3071 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3072 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3074 val = REG_RD(bp, reg_offset);
3075 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3076 REG_WR(bp, reg_offset, val);
3078 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3079 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3084 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3088 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3090 if (attn & BNX2X_PMF_LINK_ASSERT) {
3091 int func = BP_FUNC(bp);
3093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3094 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3095 func_mf_config[BP_ABS_FUNC(bp)].config);
3097 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3098 if (val & DRV_STATUS_DCC_EVENT_MASK)
3100 (val & DRV_STATUS_DCC_EVENT_MASK));
3102 if (val & DRV_STATUS_SET_MF_BW)
3103 bnx2x_set_mf_bw(bp);
3105 bnx2x__link_status_update(bp);
3106 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3107 bnx2x_pmf_update(bp);
3110 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3111 bp->dcbx_enabled > 0)
3112 /* start dcbx state machine */
3113 bnx2x_dcbx_set_params(bp,
3114 BNX2X_DCBX_STATE_NEG_RECEIVED);
3115 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3117 BNX2X_ERR("MC assert!\n");
3118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3121 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3124 } else if (attn & BNX2X_MCP_ASSERT) {
3126 BNX2X_ERR("MCP assert!\n");
3127 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3131 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3134 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3135 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3136 if (attn & BNX2X_GRC_TIMEOUT) {
3137 val = CHIP_IS_E1(bp) ? 0 :
3138 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3139 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3141 if (attn & BNX2X_GRC_RSV) {
3142 val = CHIP_IS_E1(bp) ? 0 :
3143 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3144 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3146 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3150 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3151 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3152 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3153 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3154 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3155 #define CHIP_PARITY_SUPPORTED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
3158 * should be run under rtnl lock
3160 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3162 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3163 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3164 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3170 * should be run under rtnl lock
3172 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3174 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3176 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3182 * should be run under rtnl lock
3184 bool bnx2x_reset_is_done(struct bnx2x *bp)
3186 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3187 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3188 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3192 * should be run under rtnl lock
3194 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3196 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3198 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3200 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3201 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3207 * should be run under rtnl lock
3209 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3211 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3213 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3215 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3216 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3224 * should be run under rtnl lock
3226 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3228 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3231 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3233 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3234 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3237 static inline void _print_next_block(int idx, const char *blk)
3244 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3248 for (i = 0; sig; i++) {
3249 cur_bit = ((u32)0x1 << i);
3250 if (sig & cur_bit) {
3252 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3253 _print_next_block(par_num++, "BRB");
3255 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3256 _print_next_block(par_num++, "PARSER");
3258 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3259 _print_next_block(par_num++, "TSDM");
3261 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3262 _print_next_block(par_num++, "SEARCHER");
3264 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3265 _print_next_block(par_num++, "TSEMI");
3277 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3281 for (i = 0; sig; i++) {
3282 cur_bit = ((u32)0x1 << i);
3283 if (sig & cur_bit) {
3285 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3286 _print_next_block(par_num++, "PBCLIENT");
3288 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3289 _print_next_block(par_num++, "QM");
3291 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3292 _print_next_block(par_num++, "XSDM");
3294 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3295 _print_next_block(par_num++, "XSEMI");
3297 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3298 _print_next_block(par_num++, "DOORBELLQ");
3300 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3301 _print_next_block(par_num++, "VAUX PCI CORE");
3303 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3304 _print_next_block(par_num++, "DEBUG");
3306 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3307 _print_next_block(par_num++, "USDM");
3309 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3310 _print_next_block(par_num++, "USEMI");
3312 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3313 _print_next_block(par_num++, "UPB");
3315 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3316 _print_next_block(par_num++, "CSDM");
3328 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3332 for (i = 0; sig; i++) {
3333 cur_bit = ((u32)0x1 << i);
3334 if (sig & cur_bit) {
3336 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3337 _print_next_block(par_num++, "CSEMI");
3339 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3340 _print_next_block(par_num++, "PXP");
3342 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3343 _print_next_block(par_num++,
3344 "PXPPCICLOCKCLIENT");
3346 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3347 _print_next_block(par_num++, "CFC");
3349 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3350 _print_next_block(par_num++, "CDU");
3352 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3353 _print_next_block(par_num++, "IGU");
3355 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3356 _print_next_block(par_num++, "MISC");
3368 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3372 for (i = 0; sig; i++) {
3373 cur_bit = ((u32)0x1 << i);
3374 if (sig & cur_bit) {
3376 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3377 _print_next_block(par_num++, "MCP ROM");
3379 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3380 _print_next_block(par_num++, "MCP UMP RX");
3382 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3383 _print_next_block(par_num++, "MCP UMP TX");
3385 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3386 _print_next_block(par_num++, "MCP SCPAD");
3398 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3401 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3402 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3404 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3405 "[0]:0x%08x [1]:0x%08x "
3406 "[2]:0x%08x [3]:0x%08x\n",
3407 sig0 & HW_PRTY_ASSERT_SET_0,
3408 sig1 & HW_PRTY_ASSERT_SET_1,
3409 sig2 & HW_PRTY_ASSERT_SET_2,
3410 sig3 & HW_PRTY_ASSERT_SET_3);
3411 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3413 par_num = bnx2x_print_blocks_with_parity0(
3414 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3415 par_num = bnx2x_print_blocks_with_parity1(
3416 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3417 par_num = bnx2x_print_blocks_with_parity2(
3418 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3419 par_num = bnx2x_print_blocks_with_parity3(
3420 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3427 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3429 struct attn_route attn;
3430 int port = BP_PORT(bp);
3432 attn.sig[0] = REG_RD(bp,
3433 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3435 attn.sig[1] = REG_RD(bp,
3436 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3438 attn.sig[2] = REG_RD(bp,
3439 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3441 attn.sig[3] = REG_RD(bp,
3442 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3445 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3450 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3453 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3455 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3456 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3457 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3458 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3460 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3461 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3462 "INCORRECT_RCV_BEHAVIOR\n");
3463 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3464 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3465 "WAS_ERROR_ATTN\n");
3466 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3467 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3468 "VF_LENGTH_VIOLATION_ATTN\n");
3470 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3471 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3472 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3474 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "TCPL_ERROR_ATTN\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "TCPL_IN_TWO_RCBS_ATTN\n");
3483 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3484 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3485 "CSSNOOP_FIFO_OVERFLOW\n");
3487 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3488 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3489 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3490 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3491 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3492 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3493 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3494 "_ATC_TCPL_TO_NOT_PEND\n");
3495 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3496 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3497 "ATC_GPA_MULTIPLE_HITS\n");
3498 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3499 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3500 "ATC_RCPL_TO_EMPTY_CNT\n");
3501 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3502 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3503 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3504 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3505 "ATC_IREQ_LESS_THAN_STU\n");
3508 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3509 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3510 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3511 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3512 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3517 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3519 struct attn_route attn, *group_mask;
3520 int port = BP_PORT(bp);
3526 /* need to take HW lock because MCP or other port might also
3527 try to handle this event */
3528 bnx2x_acquire_alr(bp);
3530 if (bnx2x_chk_parity_attn(bp)) {
3531 bp->recovery_state = BNX2X_RECOVERY_INIT;
3532 bnx2x_set_reset_in_progress(bp);
3533 schedule_delayed_work(&bp->reset_task, 0);
3534 /* Disable HW interrupts */
3535 bnx2x_int_disable(bp);
3536 bnx2x_release_alr(bp);
3537 /* In case of parity errors don't handle attentions so that
3538 * other function would "see" parity errors.
3543 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3544 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3545 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3546 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3549 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3553 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3554 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3556 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3557 if (deasserted & (1 << index)) {
3558 group_mask = &bp->attn_group[index];
3560 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3563 group_mask->sig[0], group_mask->sig[1],
3564 group_mask->sig[2], group_mask->sig[3],
3565 group_mask->sig[4]);
3567 bnx2x_attn_int_deasserted4(bp,
3568 attn.sig[4] & group_mask->sig[4]);
3569 bnx2x_attn_int_deasserted3(bp,
3570 attn.sig[3] & group_mask->sig[3]);
3571 bnx2x_attn_int_deasserted1(bp,
3572 attn.sig[1] & group_mask->sig[1]);
3573 bnx2x_attn_int_deasserted2(bp,
3574 attn.sig[2] & group_mask->sig[2]);
3575 bnx2x_attn_int_deasserted0(bp,
3576 attn.sig[0] & group_mask->sig[0]);
3580 bnx2x_release_alr(bp);
3582 if (bp->common.int_block == INT_BLOCK_HC)
3583 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3584 COMMAND_REG_ATTN_BITS_CLR);
3586 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3589 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3590 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3591 REG_WR(bp, reg_addr, val);
3593 if (~bp->attn_state & deasserted)
3594 BNX2X_ERR("IGU ERROR\n");
3596 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3597 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3599 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3600 aeu_mask = REG_RD(bp, reg_addr);
3602 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3603 aeu_mask, deasserted);
3604 aeu_mask |= (deasserted & 0x3ff);
3605 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3607 REG_WR(bp, reg_addr, aeu_mask);
3608 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3610 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3611 bp->attn_state &= ~deasserted;
3612 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3615 static void bnx2x_attn_int(struct bnx2x *bp)
3617 /* read local copy of bits */
3618 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3620 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3622 u32 attn_state = bp->attn_state;
3624 /* look for changed bits */
3625 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3626 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3629 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3630 attn_bits, attn_ack, asserted, deasserted);
3632 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3633 BNX2X_ERR("BAD attention state\n");
3635 /* handle bits that were raised */
3637 bnx2x_attn_int_asserted(bp, asserted);
3640 bnx2x_attn_int_deasserted(bp, deasserted);
3643 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3645 /* No memory barriers */
3646 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3647 mmiowb(); /* keep prod updates ordered */
3651 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3652 union event_ring_elem *elem)
3654 if (!bp->cnic_eth_dev.starting_cid ||
3655 cid < bp->cnic_eth_dev.starting_cid)
3658 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3660 if (unlikely(elem->message.data.cfc_del_event.error)) {
3661 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3663 bnx2x_panic_dump(bp);
3665 bnx2x_cnic_cfc_comp(bp, cid);
3670 static void bnx2x_eq_int(struct bnx2x *bp)
3672 u16 hw_cons, sw_cons, sw_prod;
3673 union event_ring_elem *elem;
3678 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3680 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3681 * when we get the the next-page we nned to adjust so the loop
3682 * condition below will be met. The next element is the size of a
3683 * regular element and hence incrementing by 1
3685 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3688 /* This function may never run in parralel with itself for a
3689 * specific bp, thus there is no need in "paired" read memory
3692 sw_cons = bp->eq_cons;
3693 sw_prod = bp->eq_prod;
3695 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
3696 hw_cons, sw_cons, atomic_read(&bp->spq_left));
3698 for (; sw_cons != hw_cons;
3699 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3702 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3704 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3705 opcode = elem->message.opcode;
3708 /* handle eq element */
3710 case EVENT_RING_OPCODE_STAT_QUERY:
3711 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3712 /* nothing to do with stats comp */
3715 case EVENT_RING_OPCODE_CFC_DEL:
3716 /* handle according to cid range */
3718 * we may want to verify here that the bp state is
3721 DP(NETIF_MSG_IFDOWN,
3722 "got delete ramrod for MULTI[%d]\n", cid);
3724 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3726 if (cid == BNX2X_FCOE_ETH_CID)
3727 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3730 bnx2x_fp(bp, cid, state) =
3731 BNX2X_FP_STATE_CLOSED;
3735 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3736 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3737 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3739 case EVENT_RING_OPCODE_START_TRAFFIC:
3740 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3741 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3745 switch (opcode | bp->state) {
3746 case (EVENT_RING_OPCODE_FUNCTION_START |
3747 BNX2X_STATE_OPENING_WAIT4_PORT):
3748 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3749 bp->state = BNX2X_STATE_FUNC_STARTED;
3752 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3753 BNX2X_STATE_CLOSING_WAIT4_HALT):
3754 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3755 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3758 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3759 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3760 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3761 bp->set_mac_pending = 0;
3764 case (EVENT_RING_OPCODE_SET_MAC |
3765 BNX2X_STATE_CLOSING_WAIT4_HALT):
3766 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3767 bp->set_mac_pending = 0;
3770 /* unknown event log error and continue */
3771 BNX2X_ERR("Unknown EQ event %d\n",
3772 elem->message.opcode);
3778 smp_mb__before_atomic_inc();
3779 atomic_add(spqe_cnt, &bp->spq_left);
3781 bp->eq_cons = sw_cons;
3782 bp->eq_prod = sw_prod;
3783 /* Make sure that above mem writes were issued towards the memory */
3786 /* update producer */
3787 bnx2x_update_eq_prod(bp, bp->eq_prod);
3790 static void bnx2x_sp_task(struct work_struct *work)
3792 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3795 /* Return here if interrupt is disabled */
3796 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3797 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3801 status = bnx2x_update_dsb_idx(bp);
3802 /* if (status == 0) */
3803 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3805 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3808 if (status & BNX2X_DEF_SB_ATT_IDX) {
3810 status &= ~BNX2X_DEF_SB_ATT_IDX;
3813 /* SP events: STAT_QUERY and others */
3814 if (status & BNX2X_DEF_SB_IDX) {
3816 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3818 if ((!NO_FCOE(bp)) &&
3819 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3820 napi_schedule(&bnx2x_fcoe(bp, napi));
3822 /* Handle EQ completions */
3825 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3826 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3828 status &= ~BNX2X_DEF_SB_IDX;
3831 if (unlikely(status))
3832 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3835 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3836 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3839 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3841 struct net_device *dev = dev_instance;
3842 struct bnx2x *bp = netdev_priv(dev);
3844 /* Return here if interrupt is disabled */
3845 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3846 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3850 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3851 IGU_INT_DISABLE, 0);
3853 #ifdef BNX2X_STOP_ON_ERROR
3854 if (unlikely(bp->panic))
3860 struct cnic_ops *c_ops;
3863 c_ops = rcu_dereference(bp->cnic_ops);
3865 c_ops->cnic_handler(bp->cnic_data, NULL);
3869 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3874 /* end of slow path */
3876 static void bnx2x_timer(unsigned long data)
3878 struct bnx2x *bp = (struct bnx2x *) data;
3880 if (!netif_running(bp->dev))
3883 if (atomic_read(&bp->intr_sem) != 0)
3887 struct bnx2x_fastpath *fp = &bp->fp[0];
3891 rc = bnx2x_rx_int(fp, 1000);
3894 if (!BP_NOMCP(bp)) {
3895 int mb_idx = BP_FW_MB_IDX(bp);
3899 ++bp->fw_drv_pulse_wr_seq;
3900 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3901 /* TBD - add SYSTEM_TIME */
3902 drv_pulse = bp->fw_drv_pulse_wr_seq;
3903 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3905 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3906 MCP_PULSE_SEQ_MASK);
3907 /* The delta between driver pulse and mcp response
3908 * should be 1 (before mcp response) or 0 (after mcp response)
3910 if ((drv_pulse != mcp_pulse) &&
3911 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3912 /* someone lost a heartbeat... */
3913 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3914 drv_pulse, mcp_pulse);
3918 if (bp->state == BNX2X_STATE_OPEN)
3919 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3922 mod_timer(&bp->timer, jiffies + bp->current_interval);
3925 /* end of Statistics */
3930 * nic init service functions
3933 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3936 if (!(len%4) && !(addr%4))
3937 for (i = 0; i < len; i += 4)
3938 REG_WR(bp, addr + i, fill);
3940 for (i = 0; i < len; i++)
3941 REG_WR8(bp, addr + i, fill);
3945 /* helper: writes FP SP data to FW - data_size in dwords */
3946 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3952 for (index = 0; index < data_size; index++)
3953 REG_WR(bp, BAR_CSTRORM_INTMEM +
3954 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3956 *(sb_data_p + index));
3959 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3963 struct hc_status_block_data_e2 sb_data_e2;
3964 struct hc_status_block_data_e1x sb_data_e1x;
3966 /* disable the function first */
3967 if (CHIP_IS_E2(bp)) {
3968 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3969 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3970 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3971 sb_data_e2.common.p_func.vf_valid = false;
3972 sb_data_p = (u32 *)&sb_data_e2;
3973 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3975 memset(&sb_data_e1x, 0,
3976 sizeof(struct hc_status_block_data_e1x));
3977 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3978 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3979 sb_data_e1x.common.p_func.vf_valid = false;
3980 sb_data_p = (u32 *)&sb_data_e1x;
3981 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3983 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
3985 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3986 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3987 CSTORM_STATUS_BLOCK_SIZE);
3988 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3989 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3990 CSTORM_SYNC_BLOCK_SIZE);
3993 /* helper: writes SP SB data to FW */
3994 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3995 struct hc_sp_status_block_data *sp_sb_data)
3997 int func = BP_FUNC(bp);
3999 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4000 REG_WR(bp, BAR_CSTRORM_INTMEM +
4001 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4003 *((u32 *)sp_sb_data + i));
4006 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4008 int func = BP_FUNC(bp);
4009 struct hc_sp_status_block_data sp_sb_data;
4010 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4012 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4013 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4014 sp_sb_data.p_func.vf_valid = false;
4016 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4018 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4019 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4020 CSTORM_SP_STATUS_BLOCK_SIZE);
4021 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4022 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4023 CSTORM_SP_SYNC_BLOCK_SIZE);
4029 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4030 int igu_sb_id, int igu_seg_id)
4032 hc_sm->igu_sb_id = igu_sb_id;
4033 hc_sm->igu_seg_id = igu_seg_id;
4034 hc_sm->timer_value = 0xFF;
4035 hc_sm->time_to_expire = 0xFFFFFFFF;
4038 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4039 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4043 struct hc_status_block_data_e2 sb_data_e2;
4044 struct hc_status_block_data_e1x sb_data_e1x;
4045 struct hc_status_block_sm *hc_sm_p;
4046 struct hc_index_data *hc_index_p;
4050 if (CHIP_INT_MODE_IS_BC(bp))
4051 igu_seg_id = HC_SEG_ACCESS_NORM;
4053 igu_seg_id = IGU_SEG_ACCESS_NORM;
4055 bnx2x_zero_fp_sb(bp, fw_sb_id);
4057 if (CHIP_IS_E2(bp)) {
4058 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4059 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4060 sb_data_e2.common.p_func.vf_id = vfid;
4061 sb_data_e2.common.p_func.vf_valid = vf_valid;
4062 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4063 sb_data_e2.common.same_igu_sb_1b = true;
4064 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4065 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4066 hc_sm_p = sb_data_e2.common.state_machine;
4067 hc_index_p = sb_data_e2.index_data;
4068 sb_data_p = (u32 *)&sb_data_e2;
4069 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4071 memset(&sb_data_e1x, 0,
4072 sizeof(struct hc_status_block_data_e1x));
4073 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4074 sb_data_e1x.common.p_func.vf_id = 0xff;
4075 sb_data_e1x.common.p_func.vf_valid = false;
4076 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4077 sb_data_e1x.common.same_igu_sb_1b = true;
4078 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4079 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4080 hc_sm_p = sb_data_e1x.common.state_machine;
4081 hc_index_p = sb_data_e1x.index_data;
4082 sb_data_p = (u32 *)&sb_data_e1x;
4083 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4086 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4087 igu_sb_id, igu_seg_id);
4088 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4089 igu_sb_id, igu_seg_id);
4091 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4093 /* write indecies to HW */
4094 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4097 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4098 u8 sb_index, u8 disable, u16 usec)
4100 int port = BP_PORT(bp);
4101 u8 ticks = usec / BNX2X_BTR;
4103 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4105 disable = disable ? 1 : (usec ? 0 : 1);
4106 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4109 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4110 u16 tx_usec, u16 rx_usec)
4112 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4114 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4118 static void bnx2x_init_def_sb(struct bnx2x *bp)
4120 struct host_sp_status_block *def_sb = bp->def_status_blk;
4121 dma_addr_t mapping = bp->def_status_blk_mapping;
4122 int igu_sp_sb_index;
4124 int port = BP_PORT(bp);
4125 int func = BP_FUNC(bp);
4129 struct hc_sp_status_block_data sp_sb_data;
4130 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4132 if (CHIP_INT_MODE_IS_BC(bp)) {
4133 igu_sp_sb_index = DEF_SB_IGU_ID;
4134 igu_seg_id = HC_SEG_ACCESS_DEF;
4136 igu_sp_sb_index = bp->igu_dsb_id;
4137 igu_seg_id = IGU_SEG_ACCESS_DEF;
4141 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4142 atten_status_block);
4143 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4147 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4149 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4151 /* take care of sig[0]..sig[4] */
4152 for (sindex = 0; sindex < 4; sindex++)
4153 bp->attn_group[index].sig[sindex] =
4154 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4158 * enable5 is separate from the rest of the registers,
4159 * and therefore the address skip is 4
4160 * and not 16 between the different groups
4162 bp->attn_group[index].sig[4] = REG_RD(bp,
4163 reg_offset + 0x10 + 0x4*index);
4165 bp->attn_group[index].sig[4] = 0;
4168 if (bp->common.int_block == INT_BLOCK_HC) {
4169 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4170 HC_REG_ATTN_MSG0_ADDR_L);
4172 REG_WR(bp, reg_offset, U64_LO(section));
4173 REG_WR(bp, reg_offset + 4, U64_HI(section));
4174 } else if (CHIP_IS_E2(bp)) {
4175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4176 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4179 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4182 bnx2x_zero_sp_sb(bp);
4184 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4185 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4186 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4187 sp_sb_data.igu_seg_id = igu_seg_id;
4188 sp_sb_data.p_func.pf_id = func;
4189 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4190 sp_sb_data.p_func.vf_id = 0xff;
4192 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4194 bp->stats_pending = 0;
4195 bp->set_mac_pending = 0;
4197 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4200 void bnx2x_update_coalesce(struct bnx2x *bp)
4204 for_each_eth_queue(bp, i)
4205 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4206 bp->rx_ticks, bp->tx_ticks);
4209 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4211 spin_lock_init(&bp->spq_lock);
4212 atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
4214 bp->spq_prod_idx = 0;
4215 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4216 bp->spq_prod_bd = bp->spq;
4217 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4220 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4223 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4224 union event_ring_elem *elem =
4225 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4227 elem->next_page.addr.hi =
4228 cpu_to_le32(U64_HI(bp->eq_mapping +
4229 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4230 elem->next_page.addr.lo =
4231 cpu_to_le32(U64_LO(bp->eq_mapping +
4232 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4235 bp->eq_prod = NUM_EQ_DESC;
4236 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4239 static void bnx2x_init_ind_table(struct bnx2x *bp)
4241 int func = BP_FUNC(bp);
4244 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4248 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
4249 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4250 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4251 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4252 bp->fp->cl_id + (i % (bp->num_queues -
4253 NONE_ETH_CONTEXT_USE)));
4256 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4258 int mode = bp->rx_mode;
4259 int port = BP_PORT(bp);
4261 u32 def_q_filters = 0;
4263 /* All but management unicast packets should pass to the host as well */
4265 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4266 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4267 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4268 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4271 case BNX2X_RX_MODE_NONE: /* no Rx */
4272 def_q_filters = BNX2X_ACCEPT_NONE;
4275 cl_id = bnx2x_fcoe(bp, cl_id);
4276 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4281 case BNX2X_RX_MODE_NORMAL:
4282 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4283 BNX2X_ACCEPT_MULTICAST;
4285 cl_id = bnx2x_fcoe(bp, cl_id);
4286 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4287 BNX2X_ACCEPT_MULTICAST);
4291 case BNX2X_RX_MODE_ALLMULTI:
4292 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4293 BNX2X_ACCEPT_ALL_MULTICAST;
4295 cl_id = bnx2x_fcoe(bp, cl_id);
4296 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4297 BNX2X_ACCEPT_MULTICAST);
4301 case BNX2X_RX_MODE_PROMISC:
4302 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4304 cl_id = bnx2x_fcoe(bp, cl_id);
4305 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4306 BNX2X_ACCEPT_MULTICAST);
4308 /* pass management unicast packets as well */
4309 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4313 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4317 cl_id = BP_L_ID(bp);
4318 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4321 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4322 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4324 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4325 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4326 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4327 "unmatched_ucast 0x%x\n", mode,
4328 bp->mac_filters.ucast_drop_all,
4329 bp->mac_filters.mcast_drop_all,
4330 bp->mac_filters.bcast_drop_all,
4331 bp->mac_filters.ucast_accept_all,
4332 bp->mac_filters.mcast_accept_all,
4333 bp->mac_filters.bcast_accept_all,
4334 bp->mac_filters.unmatched_unicast
4337 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4340 static void bnx2x_init_internal_common(struct bnx2x *bp)
4344 if (!CHIP_IS_E1(bp)) {
4346 /* xstorm needs to know whether to add ovlan to packets or not,
4347 * in switch-independent we'll write 0 to here... */
4348 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4350 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4352 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4354 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4360 * In switch independent mode, the TSTORM needs to accept
4361 * packets that failed classification, since approximate match
4362 * mac addresses aren't written to NIG LLH
4364 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4365 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4367 /* Zero this manually as its initialization is
4368 currently missing in the initTool */
4369 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4370 REG_WR(bp, BAR_USTRORM_INTMEM +
4371 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4372 if (CHIP_IS_E2(bp)) {
4373 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4374 CHIP_INT_MODE_IS_BC(bp) ?
4375 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4379 static void bnx2x_init_internal_port(struct bnx2x *bp)
4382 bnx2x_dcb_init_intmem_pfc(bp);
4385 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4387 switch (load_code) {
4388 case FW_MSG_CODE_DRV_LOAD_COMMON:
4389 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4390 bnx2x_init_internal_common(bp);
4393 case FW_MSG_CODE_DRV_LOAD_PORT:
4394 bnx2x_init_internal_port(bp);
4397 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4398 /* internal memory per function is
4399 initialized inside bnx2x_pf_init */
4403 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4408 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4410 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4412 fp->state = BNX2X_FP_STATE_CLOSED;
4414 fp->index = fp->cid = fp_idx;
4415 fp->cl_id = BP_L_ID(bp) + fp_idx;
4416 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4417 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4418 /* qZone id equals to FW (per path) client id */
4419 fp->cl_qzone_id = fp->cl_id +
4420 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4421 ETH_MAX_RX_CLIENTS_E1H);
4423 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4424 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4425 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4426 /* Setup SB indicies */
4427 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4428 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4430 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4431 "cl_id %d fw_sb %d igu_sb %d\n",
4432 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4434 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4435 fp->fw_sb_id, fp->igu_sb_id);
4437 bnx2x_update_fpsb_idx(fp);
4440 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4444 for_each_eth_queue(bp, i)
4445 bnx2x_init_fp_sb(bp, i);
4448 bnx2x_init_fcoe_fp(bp);
4450 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4451 BNX2X_VF_ID_INVALID, false,
4452 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4456 /* ensure status block indices were read */
4459 bnx2x_init_def_sb(bp);
4460 bnx2x_update_dsb_idx(bp);
4461 bnx2x_init_rx_rings(bp);
4462 bnx2x_init_tx_rings(bp);
4463 bnx2x_init_sp_ring(bp);
4464 bnx2x_init_eq_ring(bp);
4465 bnx2x_init_internal(bp, load_code);
4467 bnx2x_init_ind_table(bp);
4468 bnx2x_stats_init(bp);
4470 /* At this point, we are ready for interrupts */
4471 atomic_set(&bp->intr_sem, 0);
4473 /* flush all before enabling interrupts */
4477 bnx2x_int_enable(bp);
4479 /* Check for SPIO5 */
4480 bnx2x_attn_int_deasserted0(bp,
4481 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4482 AEU_INPUTS_ATTN_BITS_SPIO5);
4485 /* end of nic init */
4488 * gzip service functions
4491 static int bnx2x_gunzip_init(struct bnx2x *bp)
4493 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4494 &bp->gunzip_mapping, GFP_KERNEL);
4495 if (bp->gunzip_buf == NULL)
4498 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4499 if (bp->strm == NULL)
4502 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4504 if (bp->strm->workspace == NULL)
4514 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4515 bp->gunzip_mapping);
4516 bp->gunzip_buf = NULL;
4519 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4520 " un-compression\n");
4524 static void bnx2x_gunzip_end(struct bnx2x *bp)
4526 kfree(bp->strm->workspace);
4530 if (bp->gunzip_buf) {
4531 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4532 bp->gunzip_mapping);
4533 bp->gunzip_buf = NULL;
4537 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4541 /* check gzip header */
4542 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4543 BNX2X_ERR("Bad gzip header\n");
4551 if (zbuf[3] & FNAME)
4552 while ((zbuf[n++] != 0) && (n < len));
4554 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4555 bp->strm->avail_in = len - n;
4556 bp->strm->next_out = bp->gunzip_buf;
4557 bp->strm->avail_out = FW_BUF_SIZE;
4559 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4563 rc = zlib_inflate(bp->strm, Z_FINISH);
4564 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4565 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4568 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4569 if (bp->gunzip_outlen & 0x3)
4570 netdev_err(bp->dev, "Firmware decompression error:"
4571 " gunzip_outlen (%d) not aligned\n",
4573 bp->gunzip_outlen >>= 2;
4575 zlib_inflateEnd(bp->strm);
4577 if (rc == Z_STREAM_END)
4583 /* nic load/unload */
4586 * General service functions
4589 /* send a NIG loopback debug packet */
4590 static void bnx2x_lb_pckt(struct bnx2x *bp)
4594 /* Ethernet source and destination addresses */
4595 wb_write[0] = 0x55555555;
4596 wb_write[1] = 0x55555555;
4597 wb_write[2] = 0x20; /* SOP */
4598 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4600 /* NON-IP protocol */
4601 wb_write[0] = 0x09000000;
4602 wb_write[1] = 0x55555555;
4603 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4604 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4607 /* some of the internal memories
4608 * are not directly readable from the driver
4609 * to test them we send debug packets
4611 static int bnx2x_int_mem_test(struct bnx2x *bp)
4617 if (CHIP_REV_IS_FPGA(bp))
4619 else if (CHIP_REV_IS_EMUL(bp))
4624 /* Disable inputs of parser neighbor blocks */
4625 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4626 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4627 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4628 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4630 /* Write 0 to parser credits for CFC search request */
4631 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4633 /* send Ethernet packet */
4636 /* TODO do i reset NIG statistic? */
4637 /* Wait until NIG register shows 1 packet of size 0x10 */
4638 count = 1000 * factor;
4641 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4642 val = *bnx2x_sp(bp, wb_data[0]);
4650 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4654 /* Wait until PRS register shows 1 packet */
4655 count = 1000 * factor;
4657 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4665 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4669 /* Reset and init BRB, PRS */
4670 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4672 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4674 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4675 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4677 DP(NETIF_MSG_HW, "part2\n");
4679 /* Disable inputs of parser neighbor blocks */
4680 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4681 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4682 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4683 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4685 /* Write 0 to parser credits for CFC search request */
4686 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4688 /* send 10 Ethernet packets */
4689 for (i = 0; i < 10; i++)
4692 /* Wait until NIG register shows 10 + 1
4693 packets of size 11*0x10 = 0xb0 */
4694 count = 1000 * factor;
4697 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4698 val = *bnx2x_sp(bp, wb_data[0]);
4706 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4710 /* Wait until PRS register shows 2 packets */
4711 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4713 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4715 /* Write 1 to parser credits for CFC search request */
4716 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4718 /* Wait until PRS register shows 3 packets */
4719 msleep(10 * factor);
4720 /* Wait until NIG register shows 1 packet of size 0x10 */
4721 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4723 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4725 /* clear NIG EOP FIFO */
4726 for (i = 0; i < 11; i++)
4727 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4728 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4730 BNX2X_ERR("clear of NIG failed\n");
4734 /* Reset and init BRB, PRS, NIG */
4735 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4737 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4739 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4740 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4743 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4746 /* Enable inputs of parser neighbor blocks */
4747 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4748 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4749 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4750 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4752 DP(NETIF_MSG_HW, "done\n");
4757 static void enable_blocks_attention(struct bnx2x *bp)
4759 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4761 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4763 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4764 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4765 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4767 * mask read length error interrupts in brb for parser
4768 * (parsing unit and 'checksum and crc' unit)
4769 * these errors are legal (PU reads fixed length and CAC can cause
4770 * read length error on truncated packets)
4772 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4773 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4774 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4775 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4776 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4777 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4778 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4779 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4780 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4781 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4782 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4783 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4784 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4785 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4786 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4787 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4788 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4789 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4790 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4792 if (CHIP_REV_IS_FPGA(bp))
4793 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4794 else if (CHIP_IS_E2(bp))
4795 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4796 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4797 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4798 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4799 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4800 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4802 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4803 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4804 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4805 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4806 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4807 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4808 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4809 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4810 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4811 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
4814 static const struct {
4817 } bnx2x_parity_mask[] = {
4818 {PXP_REG_PXP_PRTY_MASK, 0x3ffffff},
4819 {PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
4820 {PXP2_REG_PXP2_PRTY_MASK_1, 0x7f},
4821 {HC_REG_HC_PRTY_MASK, 0x7},
4822 {MISC_REG_MISC_PRTY_MASK, 0x1},
4823 {QM_REG_QM_PRTY_MASK, 0x0},
4824 {DORQ_REG_DORQ_PRTY_MASK, 0x0},
4825 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
4826 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
4827 {SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
4828 {CDU_REG_CDU_PRTY_MASK, 0x0},
4829 {CFC_REG_CFC_PRTY_MASK, 0x0},
4830 {DBG_REG_DBG_PRTY_MASK, 0x0},
4831 {DMAE_REG_DMAE_PRTY_MASK, 0x0},
4832 {BRB1_REG_BRB1_PRTY_MASK, 0x0},
4833 {PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
4834 {TSDM_REG_TSDM_PRTY_MASK, 0x18}, /* bit 3,4 */
4835 {CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
4836 {USDM_REG_USDM_PRTY_MASK, 0x38}, /* bit 3,4,5 */
4837 {XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
4838 {TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
4839 {TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
4840 {USEM_REG_USEM_PRTY_MASK_0, 0x0},
4841 {USEM_REG_USEM_PRTY_MASK_1, 0x0},
4842 {CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
4843 {CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
4844 {XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
4845 {XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
4848 static void enable_blocks_parity(struct bnx2x *bp)
4852 for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
4853 REG_WR(bp, bnx2x_parity_mask[i].addr,
4854 bnx2x_parity_mask[i].mask);
4858 static void bnx2x_reset_common(struct bnx2x *bp)
4861 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4863 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4866 static void bnx2x_init_pxp(struct bnx2x *bp)
4869 int r_order, w_order;
4871 pci_read_config_word(bp->pdev,
4872 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4873 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4874 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4876 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4878 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4882 bnx2x_init_pxp_arb(bp, r_order, w_order);
4885 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4895 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4896 SHARED_HW_CFG_FAN_FAILURE_MASK;
4898 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4902 * The fan failure mechanism is usually related to the PHY type since
4903 * the power consumption of the board is affected by the PHY. Currently,
4904 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4906 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4907 for (port = PORT_0; port < PORT_MAX; port++) {
4909 bnx2x_fan_failure_det_req(
4911 bp->common.shmem_base,
4912 bp->common.shmem2_base,
4916 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4918 if (is_required == 0)
4921 /* Fan failure is indicated by SPIO 5 */
4922 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4923 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4925 /* set to active low mode */
4926 val = REG_RD(bp, MISC_REG_SPIO_INT);
4927 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4928 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4929 REG_WR(bp, MISC_REG_SPIO_INT, val);
4931 /* enable interrupt to signal the IGU */
4932 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4933 val |= (1 << MISC_REGISTERS_SPIO_5);
4934 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4937 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4943 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4946 switch (BP_ABS_FUNC(bp)) {
4948 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4951 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4954 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4957 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4960 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4963 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4966 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4969 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4975 REG_WR(bp, offset, pretend_func_num);
4977 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4980 static void bnx2x_pf_disable(struct bnx2x *bp)
4982 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4983 val &= ~IGU_PF_CONF_FUNC_EN;
4985 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4986 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4987 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4990 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4994 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4996 bnx2x_reset_common(bp);
4997 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4998 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5000 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
5001 if (!CHIP_IS_E1(bp))
5002 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
5004 if (CHIP_IS_E2(bp)) {
5008 * 4-port mode or 2-port mode we need to turn of master-enable
5009 * for everyone, after that, turn it back on for self.
5010 * so, we disregard multi-function or not, and always disable
5011 * for all functions on the given path, this means 0,2,4,6 for
5012 * path 0 and 1,3,5,7 for path 1
5014 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5015 if (fid == BP_ABS_FUNC(bp)) {
5017 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5022 bnx2x_pretend_func(bp, fid);
5023 /* clear pf enable */
5024 bnx2x_pf_disable(bp);
5025 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5029 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5030 if (CHIP_IS_E1(bp)) {
5031 /* enable HW interrupt from PXP on USDM overflow
5032 bit 16 on INT_MASK_0 */
5033 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5036 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5040 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5041 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5042 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5043 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5044 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5045 /* make sure this value is 0 */
5046 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5048 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5049 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5050 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5051 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5052 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5055 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5057 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5058 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5060 /* let the HW do it's magic ... */
5062 /* finish PXP init */
5063 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5065 BNX2X_ERR("PXP2 CFG failed\n");
5068 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5070 BNX2X_ERR("PXP2 RD_INIT failed\n");
5074 /* Timers bug workaround E2 only. We need to set the entire ILT to
5075 * have entries with value "0" and valid bit on.
5076 * This needs to be done by the first PF that is loaded in a path
5077 * (i.e. common phase)
5079 if (CHIP_IS_E2(bp)) {
5080 struct ilt_client_info ilt_cli;
5081 struct bnx2x_ilt ilt;
5082 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5083 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5085 /* initalize dummy TM client */
5087 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5088 ilt_cli.client_num = ILT_CLIENT_TM;
5090 /* Step 1: set zeroes to all ilt page entries with valid bit on
5091 * Step 2: set the timers first/last ilt entry to point
5092 * to the entire range to prevent ILT range error for 3rd/4th
5093 * vnic (this code assumes existance of the vnic)
5095 * both steps performed by call to bnx2x_ilt_client_init_op()
5096 * with dummy TM client
5098 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5099 * and his brother are split registers
5101 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5102 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5103 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5105 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5106 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5107 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5111 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5112 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5114 if (CHIP_IS_E2(bp)) {
5115 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5116 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5117 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5119 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5121 /* let the HW do it's magic ... */
5124 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5125 } while (factor-- && (val != 1));
5128 BNX2X_ERR("ATC_INIT failed\n");
5133 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5135 /* clean the DMAE memory */
5137 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5139 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5140 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5141 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5142 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5144 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5145 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5146 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5147 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5149 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5151 if (CHIP_MODE_IS_4_PORT(bp))
5152 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5154 /* QM queues pointers table */
5155 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5157 /* soft reset pulse */
5158 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5159 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5162 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5165 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5166 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5168 if (!CHIP_REV_IS_SLOW(bp)) {
5169 /* enable hw interrupt from doorbell Q */
5170 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5173 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5174 if (CHIP_MODE_IS_4_PORT(bp)) {
5175 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5176 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5179 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5180 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5183 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5185 if (!CHIP_IS_E1(bp))
5186 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5188 if (CHIP_IS_E2(bp)) {
5189 /* Bit-map indicating which L2 hdrs may appear after the
5190 basic Ethernet header */
5191 int has_ovlan = IS_MF_SD(bp);
5192 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5193 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5196 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5197 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5198 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5199 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5201 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5202 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5203 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5204 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5206 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5207 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5208 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5209 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5211 if (CHIP_MODE_IS_4_PORT(bp))
5212 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5215 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5217 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5220 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5221 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5222 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5224 if (CHIP_IS_E2(bp)) {
5225 int has_ovlan = IS_MF_SD(bp);
5226 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5227 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5230 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5231 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5232 REG_WR(bp, i, random32());
5234 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5241 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5242 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5243 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5244 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5245 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5247 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5249 if (sizeof(union cdu_context) != 1024)
5250 /* we currently assume that a context is 1024 bytes */
5251 dev_alert(&bp->pdev->dev, "please adjust the size "
5252 "of cdu_context(%ld)\n",
5253 (long)sizeof(union cdu_context));
5255 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5256 val = (4 << 24) + (0 << 12) + 1024;
5257 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5259 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5260 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5261 /* enable context validation interrupt from CFC */
5262 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5264 /* set the thresholds to prevent CFC/CDU race */
5265 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5267 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5269 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5270 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5272 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5273 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5275 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5276 /* Reset PCIE errors for debug */
5277 REG_WR(bp, 0x2814, 0xffffffff);
5278 REG_WR(bp, 0x3820, 0xffffffff);
5280 if (CHIP_IS_E2(bp)) {
5281 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5282 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5283 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5284 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5285 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5286 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5287 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5288 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5289 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5290 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5291 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5294 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5295 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5296 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5297 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5299 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5300 if (!CHIP_IS_E1(bp)) {
5301 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5302 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5304 if (CHIP_IS_E2(bp)) {
5305 /* Bit-map indicating which L2 hdrs may appear after the
5306 basic Ethernet header */
5307 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5310 if (CHIP_REV_IS_SLOW(bp))
5313 /* finish CFC init */
5314 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5316 BNX2X_ERR("CFC LL_INIT failed\n");
5319 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5321 BNX2X_ERR("CFC AC_INIT failed\n");
5324 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5326 BNX2X_ERR("CFC CAM_INIT failed\n");
5329 REG_WR(bp, CFC_REG_DEBUG0, 0);
5331 if (CHIP_IS_E1(bp)) {
5332 /* read NIG statistic
5333 to see if this is our first up since powerup */
5334 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5335 val = *bnx2x_sp(bp, wb_data[0]);
5337 /* do internal memory self test */
5338 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5339 BNX2X_ERR("internal mem self test failed\n");
5344 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5345 bp->common.shmem_base,
5346 bp->common.shmem2_base);
5348 bnx2x_setup_fan_failure_detection(bp);
5350 /* clear PXP2 attentions */
5351 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5353 enable_blocks_attention(bp);
5354 if (CHIP_PARITY_SUPPORTED(bp))
5355 enable_blocks_parity(bp);
5357 if (!BP_NOMCP(bp)) {
5358 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5359 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5361 u32 shmem_base[2], shmem2_base[2];
5362 shmem_base[0] = bp->common.shmem_base;
5363 shmem2_base[0] = bp->common.shmem2_base;
5364 if (CHIP_IS_E2(bp)) {
5366 SHMEM2_RD(bp, other_shmem_base_addr);
5368 SHMEM2_RD(bp, other_shmem2_base_addr);
5370 bnx2x_acquire_phy_lock(bp);
5371 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5372 bp->common.chip_id);
5373 bnx2x_release_phy_lock(bp);
5376 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5381 static int bnx2x_init_hw_port(struct bnx2x *bp)
5383 int port = BP_PORT(bp);
5384 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5388 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5390 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5392 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5393 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5395 /* Timers bug workaround: disables the pf_master bit in pglue at
5396 * common phase, we need to enable it here before any dmae access are
5397 * attempted. Therefore we manually added the enable-master to the
5398 * port phase (it also happens in the function phase)
5401 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5403 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5404 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5405 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5406 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5408 /* QM cid (connection) count */
5409 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5412 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5413 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5414 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5417 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5419 if (CHIP_MODE_IS_4_PORT(bp))
5420 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5422 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5423 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5424 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5425 /* no pause for emulation and FPGA */
5430 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5431 else if (bp->dev->mtu > 4096) {
5432 if (bp->flags & ONE_PORT_FLAG)
5436 /* (24*1024 + val*4)/256 */
5437 low = 96 + (val/64) +
5438 ((val % 64) ? 1 : 0);
5441 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5442 high = low + 56; /* 14*1024/256 */
5444 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5445 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5448 if (CHIP_MODE_IS_4_PORT(bp)) {
5449 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5450 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5451 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5452 BRB1_REG_MAC_GUARANTIED_0), 40);
5455 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5457 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5458 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5459 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5460 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5462 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5463 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5464 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5465 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5466 if (CHIP_MODE_IS_4_PORT(bp))
5467 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5469 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5470 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5472 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5474 if (!CHIP_IS_E2(bp)) {
5475 /* configure PBF to work without PAUSE mtu 9000 */
5476 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5478 /* update threshold */
5479 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5480 /* update init credit */
5481 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5484 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5486 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5490 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5492 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5493 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5495 if (CHIP_IS_E1(bp)) {
5496 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5497 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5499 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5501 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5503 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5504 /* init aeu_mask_attn_func_0/1:
5505 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5506 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5507 * bits 4-7 are used for "per vn group attention" */
5508 val = IS_MF(bp) ? 0xF7 : 0x7;
5509 /* Enable DCBX attention for all but E1 */
5510 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5511 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5513 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5514 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5515 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5516 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5517 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5519 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5521 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5523 if (!CHIP_IS_E1(bp)) {
5524 /* 0x2 disable mf_ov, 0x1 enable */
5525 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5526 (IS_MF_SD(bp) ? 0x1 : 0x2));
5528 if (CHIP_IS_E2(bp)) {
5530 switch (bp->mf_mode) {
5531 case MULTI_FUNCTION_SD:
5534 case MULTI_FUNCTION_SI:
5539 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5540 NIG_REG_LLH0_CLS_TYPE), val);
5543 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5544 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5545 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5549 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5550 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5551 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5552 bp->common.shmem_base,
5553 bp->common.shmem2_base);
5554 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5555 bp->common.shmem2_base, port)) {
5556 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5557 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5558 val = REG_RD(bp, reg_addr);
5559 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5560 REG_WR(bp, reg_addr, val);
5562 bnx2x__link_reset(bp);
5567 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5572 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5574 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5576 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5579 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5581 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5584 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5586 u32 i, base = FUNC_ILT_BASE(func);
5587 for (i = base; i < base + ILT_PER_FUNC; i++)
5588 bnx2x_ilt_wr(bp, i, 0);
5591 static int bnx2x_init_hw_func(struct bnx2x *bp)
5593 int port = BP_PORT(bp);
5594 int func = BP_FUNC(bp);
5595 struct bnx2x_ilt *ilt = BP_ILT(bp);
5598 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5599 int i, main_mem_width;
5601 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5603 /* set MSI reconfigure capability */
5604 if (bp->common.int_block == INT_BLOCK_HC) {
5605 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5606 val = REG_RD(bp, addr);
5607 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5608 REG_WR(bp, addr, val);
5612 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5614 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5615 ilt->lines[cdu_ilt_start + i].page =
5616 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5617 ilt->lines[cdu_ilt_start + i].page_mapping =
5618 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5619 /* cdu ilt pages are allocated manually so there's no need to
5622 bnx2x_ilt_init_op(bp, INITOP_SET);
5625 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5627 /* T1 hash bits value determines the T1 number of entries */
5628 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5633 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5634 #endif /* BCM_CNIC */
5636 if (CHIP_IS_E2(bp)) {
5637 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5639 /* Turn on a single ISR mode in IGU if driver is going to use
5642 if (!(bp->flags & USING_MSIX_FLAG))
5643 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5645 * Timers workaround bug: function init part.
5646 * Need to wait 20msec after initializing ILT,
5647 * needed to make sure there are no requests in
5648 * one of the PXP internal queues with "old" ILT addresses
5652 * Master enable - Due to WB DMAE writes performed before this
5653 * register is re-initialized as part of the regular function
5656 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5657 /* Enable the function in IGU */
5658 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5663 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5666 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5668 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5669 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5670 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5671 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5672 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5673 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5674 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5675 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5676 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5678 if (CHIP_IS_E2(bp)) {
5679 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5681 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5685 if (CHIP_MODE_IS_4_PORT(bp))
5686 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5689 REG_WR(bp, QM_REG_PF_EN, 1);
5691 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5693 if (CHIP_MODE_IS_4_PORT(bp))
5694 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5696 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5697 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5698 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5699 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5700 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5701 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5702 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5703 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5704 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5705 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5706 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5708 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5710 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5712 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5715 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5718 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5719 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5722 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5724 /* HC init per function */
5725 if (bp->common.int_block == INT_BLOCK_HC) {
5726 if (CHIP_IS_E1H(bp)) {
5727 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5729 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5730 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5732 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5735 int num_segs, sb_idx, prod_offset;
5737 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5739 if (CHIP_IS_E2(bp)) {
5740 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5741 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5744 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5746 if (CHIP_IS_E2(bp)) {
5750 * E2 mode: address 0-135 match to the mapping memory;
5751 * 136 - PF0 default prod; 137 - PF1 default prod;
5752 * 138 - PF2 default prod; 139 - PF3 default prod;
5753 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5754 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5757 * E1.5 mode - In backward compatible mode;
5758 * for non default SB; each even line in the memory
5759 * holds the U producer and each odd line hold
5760 * the C producer. The first 128 producers are for
5761 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5762 * producers are for the DSB for each PF.
5763 * Each PF has five segments: (the order inside each
5764 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5765 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5766 * 144-147 attn prods;
5768 /* non-default-status-blocks */
5769 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5770 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5771 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5772 prod_offset = (bp->igu_base_sb + sb_idx) *
5775 for (i = 0; i < num_segs; i++) {
5776 addr = IGU_REG_PROD_CONS_MEMORY +
5777 (prod_offset + i) * 4;
5778 REG_WR(bp, addr, 0);
5780 /* send consumer update with value 0 */
5781 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5782 USTORM_ID, 0, IGU_INT_NOP, 1);
5783 bnx2x_igu_clear_sb(bp,
5784 bp->igu_base_sb + sb_idx);
5787 /* default-status-blocks */
5788 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5789 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5791 if (CHIP_MODE_IS_4_PORT(bp))
5792 dsb_idx = BP_FUNC(bp);
5794 dsb_idx = BP_E1HVN(bp);
5796 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5797 IGU_BC_BASE_DSB_PROD + dsb_idx :
5798 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5800 for (i = 0; i < (num_segs * E1HVN_MAX);
5802 addr = IGU_REG_PROD_CONS_MEMORY +
5803 (prod_offset + i)*4;
5804 REG_WR(bp, addr, 0);
5806 /* send consumer update with 0 */
5807 if (CHIP_INT_MODE_IS_BC(bp)) {
5808 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5809 USTORM_ID, 0, IGU_INT_NOP, 1);
5810 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5811 CSTORM_ID, 0, IGU_INT_NOP, 1);
5812 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5813 XSTORM_ID, 0, IGU_INT_NOP, 1);
5814 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5815 TSTORM_ID, 0, IGU_INT_NOP, 1);
5816 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5817 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5819 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5820 USTORM_ID, 0, IGU_INT_NOP, 1);
5821 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5822 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5824 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5826 /* !!! these should become driver const once
5827 rf-tool supports split-68 const */
5828 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5829 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5830 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5831 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5832 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5833 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5837 /* Reset PCIE errors for debug */
5838 REG_WR(bp, 0x2114, 0xffffffff);
5839 REG_WR(bp, 0x2120, 0xffffffff);
5841 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5842 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5843 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5844 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5845 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5846 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5848 if (CHIP_IS_E1x(bp)) {
5849 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5850 main_mem_base = HC_REG_MAIN_MEMORY +
5851 BP_PORT(bp) * (main_mem_size * 4);
5852 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5855 val = REG_RD(bp, main_mem_prty_clr);
5857 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5859 "function init (0x%x)!\n", val);
5861 /* Clear "false" parity errors in MSI-X table */
5862 for (i = main_mem_base;
5863 i < main_mem_base + main_mem_size * 4;
5864 i += main_mem_width) {
5865 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5866 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5867 i, main_mem_width / 4);
5869 /* Clear HC parity attention */
5870 REG_RD(bp, main_mem_prty_clr);
5873 bnx2x_phy_probe(&bp->link_params);
5878 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5882 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5883 BP_ABS_FUNC(bp), load_code);
5886 mutex_init(&bp->dmae_mutex);
5887 rc = bnx2x_gunzip_init(bp);
5891 switch (load_code) {
5892 case FW_MSG_CODE_DRV_LOAD_COMMON:
5893 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5894 rc = bnx2x_init_hw_common(bp, load_code);
5899 case FW_MSG_CODE_DRV_LOAD_PORT:
5900 rc = bnx2x_init_hw_port(bp);
5905 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5906 rc = bnx2x_init_hw_func(bp);
5912 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5916 if (!BP_NOMCP(bp)) {
5917 int mb_idx = BP_FW_MB_IDX(bp);
5919 bp->fw_drv_pulse_wr_seq =
5920 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5921 DRV_PULSE_SEQ_MASK);
5922 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5926 bnx2x_gunzip_end(bp);
5931 void bnx2x_free_mem(struct bnx2x *bp)
5934 #define BNX2X_PCI_FREE(x, y, size) \
5937 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
5943 #define BNX2X_FREE(x) \
5955 for_each_queue(bp, i) {
5957 /* FCoE client uses default status block */
5958 if (IS_FCOE_IDX(i)) {
5959 union host_hc_status_block *sb =
5960 &bnx2x_fp(bp, i, status_blk);
5961 memset(sb, 0, sizeof(union host_hc_status_block));
5962 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5967 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5968 bnx2x_fp(bp, i, status_blk_mapping),
5969 sizeof(struct host_hc_status_block_e2));
5971 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5972 bnx2x_fp(bp, i, status_blk_mapping),
5973 sizeof(struct host_hc_status_block_e1x));
5979 for_each_rx_queue(bp, i) {
5981 /* fastpath rx rings: rx_buf rx_desc rx_comp */
5982 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5983 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5984 bnx2x_fp(bp, i, rx_desc_mapping),
5985 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5987 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5988 bnx2x_fp(bp, i, rx_comp_mapping),
5989 sizeof(struct eth_fast_path_rx_cqe) *
5993 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5994 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5995 bnx2x_fp(bp, i, rx_sge_mapping),
5996 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5999 for_each_tx_queue(bp, i) {
6001 /* fastpath tx rings: tx_buf tx_desc */
6002 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
6003 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
6004 bnx2x_fp(bp, i, tx_desc_mapping),
6005 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6007 /* end of fastpath */
6009 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6010 sizeof(struct host_sp_status_block));
6012 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6013 sizeof(struct bnx2x_slowpath));
6015 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6018 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6020 BNX2X_FREE(bp->ilt->lines);
6024 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6025 sizeof(struct host_hc_status_block_e2));
6027 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6028 sizeof(struct host_hc_status_block_e1x));
6030 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6033 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6035 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6036 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6038 #undef BNX2X_PCI_FREE
6042 static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
6044 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
6045 if (CHIP_IS_E2(bp)) {
6046 bnx2x_fp(bp, index, sb_index_values) =
6047 (__le16 *)status_blk.e2_sb->sb.index_values;
6048 bnx2x_fp(bp, index, sb_running_index) =
6049 (__le16 *)status_blk.e2_sb->sb.running_index;
6051 bnx2x_fp(bp, index, sb_index_values) =
6052 (__le16 *)status_blk.e1x_sb->sb.index_values;
6053 bnx2x_fp(bp, index, sb_running_index) =
6054 (__le16 *)status_blk.e1x_sb->sb.running_index;
6058 int bnx2x_alloc_mem(struct bnx2x *bp)
6060 #define BNX2X_PCI_ALLOC(x, y, size) \
6062 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
6064 goto alloc_mem_err; \
6065 memset(x, 0, size); \
6068 #define BNX2X_ALLOC(x, size) \
6070 x = kzalloc(size, GFP_KERNEL); \
6072 goto alloc_mem_err; \
6079 for_each_queue(bp, i) {
6080 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
6081 bnx2x_fp(bp, i, bp) = bp;
6084 if (!IS_FCOE_IDX(i)) {
6087 BNX2X_PCI_ALLOC(sb->e2_sb,
6088 &bnx2x_fp(bp, i, status_blk_mapping),
6089 sizeof(struct host_hc_status_block_e2));
6091 BNX2X_PCI_ALLOC(sb->e1x_sb,
6092 &bnx2x_fp(bp, i, status_blk_mapping),
6093 sizeof(struct host_hc_status_block_e1x));
6097 set_sb_shortcuts(bp, i);
6100 for_each_queue(bp, i) {
6102 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6103 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6104 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6105 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6106 &bnx2x_fp(bp, i, rx_desc_mapping),
6107 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6109 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6110 &bnx2x_fp(bp, i, rx_comp_mapping),
6111 sizeof(struct eth_fast_path_rx_cqe) *
6115 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6116 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6117 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6118 &bnx2x_fp(bp, i, rx_sge_mapping),
6119 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6122 for_each_queue(bp, i) {
6124 /* fastpath tx rings: tx_buf tx_desc */
6125 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6126 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6127 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6128 &bnx2x_fp(bp, i, tx_desc_mapping),
6129 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6131 /* end of fastpath */
6135 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6136 sizeof(struct host_hc_status_block_e2));
6138 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6139 sizeof(struct host_hc_status_block_e1x));
6141 /* allocate searcher T2 table */
6142 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6146 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6147 sizeof(struct host_sp_status_block));
6149 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6150 sizeof(struct bnx2x_slowpath));
6152 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6154 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6157 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6159 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6162 /* Slow path ring */
6163 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6166 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6167 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6174 #undef BNX2X_PCI_ALLOC
6179 * Init service functions
6181 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6182 int *state_p, int flags);
6184 int bnx2x_func_start(struct bnx2x *bp)
6186 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6188 /* Wait for completion */
6189 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6190 WAIT_RAMROD_COMMON);
6193 static int bnx2x_func_stop(struct bnx2x *bp)
6195 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6197 /* Wait for completion */
6198 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6199 0, &(bp->state), WAIT_RAMROD_COMMON);
6203 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
6205 * @param bp driver descriptor
6206 * @param set set or clear an entry (1 or 0)
6207 * @param mac pointer to a buffer containing a MAC
6208 * @param cl_bit_vec bit vector of clients to register a MAC for
6209 * @param cam_offset offset in a CAM to use
6210 * @param is_bcast is the set MAC a broadcast address (for E1 only)
6212 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6213 u32 cl_bit_vec, u8 cam_offset,
6216 struct mac_configuration_cmd *config =
6217 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6218 int ramrod_flags = WAIT_RAMROD_COMMON;
6220 bp->set_mac_pending = 1;
6223 config->hdr.length = 1;
6224 config->hdr.offset = cam_offset;
6225 config->hdr.client_id = 0xff;
6226 config->hdr.reserved1 = 0;
6229 config->config_table[0].msb_mac_addr =
6230 swab16(*(u16 *)&mac[0]);
6231 config->config_table[0].middle_mac_addr =
6232 swab16(*(u16 *)&mac[2]);
6233 config->config_table[0].lsb_mac_addr =
6234 swab16(*(u16 *)&mac[4]);
6235 config->config_table[0].clients_bit_vector =
6236 cpu_to_le32(cl_bit_vec);
6237 config->config_table[0].vlan_id = 0;
6238 config->config_table[0].pf_id = BP_FUNC(bp);
6240 SET_FLAG(config->config_table[0].flags,
6241 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6242 T_ETH_MAC_COMMAND_SET);
6244 SET_FLAG(config->config_table[0].flags,
6245 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6246 T_ETH_MAC_COMMAND_INVALIDATE);
6249 SET_FLAG(config->config_table[0].flags,
6250 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6252 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6253 (set ? "setting" : "clearing"),
6254 config->config_table[0].msb_mac_addr,
6255 config->config_table[0].middle_mac_addr,
6256 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6258 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6259 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6260 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6262 /* Wait for a completion */
6263 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6266 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6267 int *state_p, int flags)
6269 /* can take a while if any port is running */
6271 u8 poll = flags & WAIT_RAMROD_POLL;
6272 u8 common = flags & WAIT_RAMROD_COMMON;
6274 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6275 poll ? "polling" : "waiting", state, idx);
6283 bnx2x_rx_int(bp->fp, 10);
6284 /* if index is different from 0
6285 * the reply for some commands will
6286 * be on the non default queue
6289 bnx2x_rx_int(&bp->fp[idx], 10);
6293 mb(); /* state is changed by bnx2x_sp_event() */
6294 if (*state_p == state) {
6295 #ifdef BNX2X_STOP_ON_ERROR
6296 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6308 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6309 poll ? "polling" : "waiting", state, idx);
6310 #ifdef BNX2X_STOP_ON_ERROR
6317 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6319 if (CHIP_IS_E1H(bp))
6320 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6321 else if (CHIP_MODE_IS_4_PORT(bp))
6322 return BP_FUNC(bp) * 32 + rel_offset;
6324 return BP_VN(bp) * 32 + rel_offset;
6328 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6329 * relevant. In addition, current implementation is tuned for a
6332 * When multiple unicast ETH MACs PF configuration in switch
6333 * independent mode is required (NetQ, multiple netdev MACs,
6334 * etc.), consider better utilisation of 16 per function MAC
6335 * entries in the LLH memory.
6338 LLH_CAM_ISCSI_ETH_LINE = 0,
6340 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6343 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6345 unsigned char *dev_addr,
6349 u32 mem_offset, ena_offset, mem_index;
6352 * 0..7 - goes to MEM
6353 * 8..15 - goes to MEM2
6356 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6359 /* calculate memory start offset according to the mapping
6360 * and index in the memory */
6361 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6362 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6363 NIG_REG_LLH0_FUNC_MEM;
6364 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6365 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6368 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6369 NIG_REG_P0_LLH_FUNC_MEM2;
6370 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6371 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6372 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6376 /* LLH_FUNC_MEM is a u64 WB register */
6377 mem_offset += 8*mem_index;
6379 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6380 (dev_addr[4] << 8) | dev_addr[5]);
6381 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6383 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6386 /* enable/disable the entry */
6387 REG_WR(bp, ena_offset + 4*mem_index, set);
6391 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6393 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6394 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6396 /* networking MAC */
6397 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6398 (1 << bp->fp->cl_id), cam_offset , 0);
6400 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6402 if (CHIP_IS_E1(bp)) {
6404 static const u8 bcast[ETH_ALEN] = {
6405 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6407 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6410 static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6413 struct net_device *dev = bp->dev;
6414 struct netdev_hw_addr *ha;
6415 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6416 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6418 netdev_for_each_mc_addr(ha, dev) {
6420 config_cmd->config_table[i].msb_mac_addr =
6421 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6422 config_cmd->config_table[i].middle_mac_addr =
6423 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6424 config_cmd->config_table[i].lsb_mac_addr =
6425 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6427 config_cmd->config_table[i].vlan_id = 0;
6428 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6429 config_cmd->config_table[i].clients_bit_vector =
6430 cpu_to_le32(1 << BP_L_ID(bp));
6432 SET_FLAG(config_cmd->config_table[i].flags,
6433 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6434 T_ETH_MAC_COMMAND_SET);
6437 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6438 config_cmd->config_table[i].msb_mac_addr,
6439 config_cmd->config_table[i].middle_mac_addr,
6440 config_cmd->config_table[i].lsb_mac_addr);
6443 old = config_cmd->hdr.length;
6445 for (; i < old; i++) {
6446 if (CAM_IS_INVALID(config_cmd->
6448 /* already invalidated */
6452 SET_FLAG(config_cmd->config_table[i].flags,
6453 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6454 T_ETH_MAC_COMMAND_INVALIDATE);
6458 config_cmd->hdr.length = i;
6459 config_cmd->hdr.offset = offset;
6460 config_cmd->hdr.client_id = 0xff;
6461 config_cmd->hdr.reserved1 = 0;
6463 bp->set_mac_pending = 1;
6466 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6467 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6469 static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
6472 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6473 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6474 int ramrod_flags = WAIT_RAMROD_COMMON;
6476 bp->set_mac_pending = 1;
6479 for (i = 0; i < config_cmd->hdr.length; i++)
6480 SET_FLAG(config_cmd->config_table[i].flags,
6481 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6482 T_ETH_MAC_COMMAND_INVALIDATE);
6484 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6485 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6487 /* Wait for a completion */
6488 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6495 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6496 * MAC(s). This function will wait until the ramdord completion
6499 * @param bp driver handle
6500 * @param set set or clear the CAM entry
6502 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6504 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6506 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6507 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6508 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6509 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6510 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6512 /* Send a SET_MAC ramrod */
6513 bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
6516 bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6522 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6523 * ETH MAC(s). This function will wait until the ramdord
6524 * completion returns.
6526 * @param bp driver handle
6527 * @param set set or clear the CAM entry
6529 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6531 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6533 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6535 * CAM allocation for E1H
6536 * eth unicasts: by func number
6537 * iscsi: by func number
6538 * fip unicast: by func number
6539 * fip multicast: by func number
6541 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6542 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6547 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6549 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6552 * CAM allocation for E1H
6553 * eth unicasts: by func number
6554 * iscsi: by func number
6555 * fip unicast: by func number
6556 * fip multicast: by func number
6558 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6559 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6565 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6566 struct bnx2x_client_init_params *params,
6568 struct client_init_ramrod_data *data)
6570 /* Clear the buffer */
6571 memset(data, 0, sizeof(*data));
6574 data->general.client_id = params->rxq_params.cl_id;
6575 data->general.statistics_counter_id = params->rxq_params.stat_id;
6576 data->general.statistics_en_flg =
6577 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6578 data->general.is_fcoe_flg =
6579 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6580 data->general.activate_flg = activate;
6581 data->general.sp_client_id = params->rxq_params.spcl_id;
6584 data->rx.tpa_en_flg =
6585 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6586 data->rx.vmqueue_mode_en_flg = 0;
6587 data->rx.cache_line_alignment_log_size =
6588 params->rxq_params.cache_line_log;
6589 data->rx.enable_dynamic_hc =
6590 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6591 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6592 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6593 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6595 /* We don't set drop flags */
6596 data->rx.drop_ip_cs_err_flg = 0;
6597 data->rx.drop_tcp_cs_err_flg = 0;
6598 data->rx.drop_ttl0_flg = 0;
6599 data->rx.drop_udp_cs_err_flg = 0;
6601 data->rx.inner_vlan_removal_enable_flg =
6602 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6603 data->rx.outer_vlan_removal_enable_flg =
6604 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6605 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6606 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6607 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6608 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6609 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6610 data->rx.bd_page_base.lo =
6611 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6612 data->rx.bd_page_base.hi =
6613 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6614 data->rx.sge_page_base.lo =
6615 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6616 data->rx.sge_page_base.hi =
6617 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6618 data->rx.cqe_page_base.lo =
6619 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6620 data->rx.cqe_page_base.hi =
6621 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6622 data->rx.is_leading_rss =
6623 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6624 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6627 data->tx.enforce_security_flg = 0; /* VF specific */
6628 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6629 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6630 data->tx.mtu = 0; /* VF specific */
6631 data->tx.tx_bd_page_base.lo =
6632 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6633 data->tx.tx_bd_page_base.hi =
6634 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6636 /* flow control data */
6637 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6638 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6639 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6640 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6641 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6642 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6643 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6645 data->fc.safc_group_num = params->txq_params.cos;
6646 data->fc.safc_group_en_flg =
6647 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6648 data->fc.traffic_type =
6649 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6650 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6653 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6655 /* ustorm cxt validation */
6656 cxt->ustorm_ag_context.cdu_usage =
6657 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6658 ETH_CONNECTION_TYPE);
6659 /* xcontext validation */
6660 cxt->xstorm_ag_context.cdu_reserved =
6661 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6662 ETH_CONNECTION_TYPE);
6665 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6666 struct bnx2x_client_init_params *params,
6668 struct client_init_ramrod_data *data,
6669 dma_addr_t data_mapping)
6672 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6673 int ramrod_flags = 0, rc;
6675 /* HC and context validation values */
6676 hc_usec = params->txq_params.hc_rate ?
6677 1000000 / params->txq_params.hc_rate : 0;
6678 bnx2x_update_coalesce_sb_index(bp,
6679 params->txq_params.fw_sb_id,
6680 params->txq_params.sb_cq_index,
6681 !(params->txq_params.flags & QUEUE_FLG_HC),
6684 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6686 hc_usec = params->rxq_params.hc_rate ?
6687 1000000 / params->rxq_params.hc_rate : 0;
6688 bnx2x_update_coalesce_sb_index(bp,
6689 params->rxq_params.fw_sb_id,
6690 params->rxq_params.sb_cq_index,
6691 !(params->rxq_params.flags & QUEUE_FLG_HC),
6694 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6695 params->rxq_params.cid);
6698 if (params->txq_params.flags & QUEUE_FLG_STATS)
6699 storm_memset_xstats_zero(bp, BP_PORT(bp),
6700 params->txq_params.stat_id);
6702 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6703 storm_memset_ustats_zero(bp, BP_PORT(bp),
6704 params->rxq_params.stat_id);
6705 storm_memset_tstats_zero(bp, BP_PORT(bp),
6706 params->rxq_params.stat_id);
6709 /* Fill the ramrod data */
6710 bnx2x_fill_cl_init_data(bp, params, activate, data);
6714 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6715 * barrier except from mmiowb() is needed to impose a
6716 * proper ordering of memory operations.
6721 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6722 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6724 /* Wait for completion */
6725 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6726 params->ramrod_params.index,
6727 params->ramrod_params.pstate,
6733 * Configure interrupt mode according to current configuration.
6734 * In case of MSI-X it will also try to enable MSI-X.
6740 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6744 switch (bp->int_mode) {
6746 bnx2x_enable_msi(bp);
6747 /* falling through... */
6749 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6750 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6753 /* Set number of queues according to bp->multi_mode value */
6754 bnx2x_set_num_queues(bp);
6756 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6759 /* if we can't use MSI-X we only need one fp,
6760 * so try to enable MSI-X with the requested number of fp's
6761 * and fallback to MSI or legacy INTx with one fp
6763 rc = bnx2x_enable_msix(bp);
6765 /* failed to enable MSI-X */
6768 "Multi requested but failed to "
6769 "enable MSI-X (%d), "
6770 "set number of queues to %d\n",
6772 1 + NONE_ETH_CONTEXT_USE);
6773 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6775 if (!(bp->flags & DISABLE_MSI_FLAG))
6776 bnx2x_enable_msi(bp);
6785 /* must be called prioir to any HW initializations */
6786 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6788 return L2_ILT_LINES(bp);
6791 void bnx2x_ilt_set_info(struct bnx2x *bp)
6793 struct ilt_client_info *ilt_client;
6794 struct bnx2x_ilt *ilt = BP_ILT(bp);
6797 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6798 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6801 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6802 ilt_client->client_num = ILT_CLIENT_CDU;
6803 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6804 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6805 ilt_client->start = line;
6806 line += L2_ILT_LINES(bp);
6808 line += CNIC_ILT_LINES;
6810 ilt_client->end = line - 1;
6812 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6813 "flags 0x%x, hw psz %d\n",
6816 ilt_client->page_size,
6818 ilog2(ilt_client->page_size >> 12));
6821 if (QM_INIT(bp->qm_cid_count)) {
6822 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6823 ilt_client->client_num = ILT_CLIENT_QM;
6824 ilt_client->page_size = QM_ILT_PAGE_SZ;
6825 ilt_client->flags = 0;
6826 ilt_client->start = line;
6828 /* 4 bytes for each cid */
6829 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6832 ilt_client->end = line - 1;
6834 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6835 "flags 0x%x, hw psz %d\n",
6838 ilt_client->page_size,
6840 ilog2(ilt_client->page_size >> 12));
6844 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6846 ilt_client->client_num = ILT_CLIENT_SRC;
6847 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6848 ilt_client->flags = 0;
6849 ilt_client->start = line;
6850 line += SRC_ILT_LINES;
6851 ilt_client->end = line - 1;
6853 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6854 "flags 0x%x, hw psz %d\n",
6857 ilt_client->page_size,
6859 ilog2(ilt_client->page_size >> 12));
6862 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6866 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6868 ilt_client->client_num = ILT_CLIENT_TM;
6869 ilt_client->page_size = TM_ILT_PAGE_SZ;
6870 ilt_client->flags = 0;
6871 ilt_client->start = line;
6872 line += TM_ILT_LINES;
6873 ilt_client->end = line - 1;
6875 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6876 "flags 0x%x, hw psz %d\n",
6879 ilt_client->page_size,
6881 ilog2(ilt_client->page_size >> 12));
6884 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6888 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6891 struct bnx2x_client_init_params params = { {0} };
6894 /* reset IGU state skip FCoE L2 queue */
6895 if (!IS_FCOE_FP(fp))
6896 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6899 params.ramrod_params.pstate = &fp->state;
6900 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6901 params.ramrod_params.index = fp->index;
6902 params.ramrod_params.cid = fp->cid;
6906 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6911 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6913 bnx2x_pf_rx_cl_prep(bp, fp, ¶ms.pause, ¶ms.rxq_params);
6915 bnx2x_pf_tx_cl_prep(bp, fp, ¶ms.txq_params);
6917 rc = bnx2x_setup_fw_client(bp, ¶ms, 1,
6918 bnx2x_sp(bp, client_init_data),
6919 bnx2x_sp_mapping(bp, client_init_data));
6923 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6924 struct bnx2x_client_ramrod_params *p)
6928 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6930 /* halt the connection */
6931 *p->pstate = BNX2X_FP_STATE_HALTING;
6932 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6935 /* Wait for completion */
6936 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6937 p->pstate, poll_flag);
6938 if (rc) /* timeout */
6941 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6942 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6944 /* Wait for completion */
6945 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6946 p->pstate, poll_flag);
6947 if (rc) /* timeout */
6951 /* delete cfc entry */
6952 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6954 /* Wait for completion */
6955 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6956 p->pstate, WAIT_RAMROD_COMMON);
6960 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6962 struct bnx2x_client_ramrod_params client_stop = {0};
6963 struct bnx2x_fastpath *fp = &bp->fp[index];
6965 client_stop.index = index;
6966 client_stop.cid = fp->cid;
6967 client_stop.cl_id = fp->cl_id;
6968 client_stop.pstate = &(fp->state);
6969 client_stop.poll = 0;
6971 return bnx2x_stop_fw_client(bp, &client_stop);
6975 static void bnx2x_reset_func(struct bnx2x *bp)
6977 int port = BP_PORT(bp);
6978 int func = BP_FUNC(bp);
6980 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6982 offsetof(struct hc_status_block_data_e2, common) :
6983 offsetof(struct hc_status_block_data_e1x, common));
6984 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6985 int pfid_offset = offsetof(struct pci_entity, pf_id);
6987 /* Disable the function in the FW */
6988 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6989 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6990 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6991 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6994 for_each_eth_queue(bp, i) {
6995 struct bnx2x_fastpath *fp = &bp->fp[i];
6997 BAR_CSTRORM_INTMEM +
6998 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6999 + pfunc_offset_fp + pfid_offset,
7000 HC_FUNCTION_DISABLED);
7005 BAR_CSTRORM_INTMEM +
7006 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
7007 pfunc_offset_sp + pfid_offset,
7008 HC_FUNCTION_DISABLED);
7011 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7012 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7016 if (bp->common.int_block == INT_BLOCK_HC) {
7017 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7018 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7020 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7021 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7025 /* Disable Timer scan */
7026 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7028 * Wait for at least 10ms and up to 2 second for the timers scan to
7031 for (i = 0; i < 200; i++) {
7033 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7038 bnx2x_clear_func_ilt(bp, func);
7040 /* Timers workaround bug for E2: if this is vnic-3,
7041 * we need to set the entire ilt range for this timers.
7043 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
7044 struct ilt_client_info ilt_cli;
7045 /* use dummy TM client */
7046 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7048 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7049 ilt_cli.client_num = ILT_CLIENT_TM;
7051 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7054 /* this assumes that reset_port() called before reset_func()*/
7056 bnx2x_pf_disable(bp);
7061 static void bnx2x_reset_port(struct bnx2x *bp)
7063 int port = BP_PORT(bp);
7066 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7068 /* Do not rcv packets to BRB */
7069 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7070 /* Do not direct rcv packets that are not for MCP to the BRB */
7071 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7072 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7075 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7078 /* Check for BRB port occupancy */
7079 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7081 DP(NETIF_MSG_IFDOWN,
7082 "BRB1 is not empty %d blocks are occupied\n", val);
7084 /* TODO: Close Doorbell port? */
7087 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7089 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
7090 BP_ABS_FUNC(bp), reset_code);
7092 switch (reset_code) {
7093 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7094 bnx2x_reset_port(bp);
7095 bnx2x_reset_func(bp);
7096 bnx2x_reset_common(bp);
7099 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7100 bnx2x_reset_port(bp);
7101 bnx2x_reset_func(bp);
7104 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7105 bnx2x_reset_func(bp);
7109 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7115 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7117 if (bp->flags & FCOE_MACS_SET) {
7119 bnx2x_set_fip_eth_mac_addr(bp, 0);
7121 bnx2x_set_all_enode_macs(bp, 0);
7123 bp->flags &= ~FCOE_MACS_SET;
7128 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7130 int port = BP_PORT(bp);
7134 /* Wait until tx fastpath tasks complete */
7135 for_each_tx_queue(bp, i) {
7136 struct bnx2x_fastpath *fp = &bp->fp[i];
7139 while (bnx2x_has_tx_work_unload(fp)) {
7142 BNX2X_ERR("timeout waiting for queue[%d]\n",
7144 #ifdef BNX2X_STOP_ON_ERROR
7155 /* Give HW time to discard old tx messages */
7158 if (CHIP_IS_E1(bp)) {
7159 /* invalidate mc list,
7160 * wait and poll (interrupts are off)
7162 bnx2x_invlidate_e1_mc_list(bp);
7163 bnx2x_set_eth_mac(bp, 0);
7166 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7168 bnx2x_set_eth_mac(bp, 0);
7170 for (i = 0; i < MC_HASH_SIZE; i++)
7171 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7175 bnx2x_del_fcoe_eth_macs(bp);
7178 if (unload_mode == UNLOAD_NORMAL)
7179 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7181 else if (bp->flags & NO_WOL_FLAG)
7182 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7185 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7186 u8 *mac_addr = bp->dev->dev_addr;
7188 /* The mac address is written to entries 1-4 to
7189 preserve entry 0 which is used by the PMF */
7190 u8 entry = (BP_E1HVN(bp) + 1)*8;
7192 val = (mac_addr[0] << 8) | mac_addr[1];
7193 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7195 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7196 (mac_addr[4] << 8) | mac_addr[5];
7197 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7199 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7202 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7204 /* Close multi and leading connections
7205 Completions for ramrods are collected in a synchronous way */
7206 for_each_queue(bp, i)
7208 if (bnx2x_stop_client(bp, i))
7209 #ifdef BNX2X_STOP_ON_ERROR
7215 rc = bnx2x_func_stop(bp);
7217 BNX2X_ERR("Function stop failed!\n");
7218 #ifdef BNX2X_STOP_ON_ERROR
7224 #ifndef BNX2X_STOP_ON_ERROR
7228 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7230 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7231 "%d, %d, %d\n", BP_PATH(bp),
7232 load_count[BP_PATH(bp)][0],
7233 load_count[BP_PATH(bp)][1],
7234 load_count[BP_PATH(bp)][2]);
7235 load_count[BP_PATH(bp)][0]--;
7236 load_count[BP_PATH(bp)][1 + port]--;
7237 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7238 "%d, %d, %d\n", BP_PATH(bp),
7239 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7240 load_count[BP_PATH(bp)][2]);
7241 if (load_count[BP_PATH(bp)][0] == 0)
7242 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7243 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7244 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7246 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7249 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7250 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7251 bnx2x__link_reset(bp);
7253 /* Disable HW interrupts, NAPI */
7254 bnx2x_netif_stop(bp, 1);
7259 /* Reset the chip */
7260 bnx2x_reset_chip(bp, reset_code);
7262 /* Report UNLOAD_DONE to MCP */
7264 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7268 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7272 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7274 if (CHIP_IS_E1(bp)) {
7275 int port = BP_PORT(bp);
7276 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7277 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7279 val = REG_RD(bp, addr);
7281 REG_WR(bp, addr, val);
7282 } else if (CHIP_IS_E1H(bp)) {
7283 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7284 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7285 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7286 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7290 /* Close gates #2, #3 and #4: */
7291 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7295 /* Gates #2 and #4a are closed/opened for "not E1" only */
7296 if (!CHIP_IS_E1(bp)) {
7298 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7299 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7300 close ? (val | 0x1) : (val & (~(u32)1)));
7302 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7303 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7304 close ? (val | 0x1) : (val & (~(u32)1)));
7308 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7309 val = REG_RD(bp, addr);
7310 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7312 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7313 close ? "closing" : "opening");
7317 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7319 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7321 /* Do some magic... */
7322 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7323 *magic_val = val & SHARED_MF_CLP_MAGIC;
7324 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7327 /* Restore the value of the `magic' bit.
7329 * @param pdev Device handle.
7330 * @param magic_val Old value of the `magic' bit.
7332 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7334 /* Restore the `magic' bit value... */
7335 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7336 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7337 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7341 * Prepares for MCP reset: takes care of CLP configurations.
7344 * @param magic_val Old value of 'magic' bit.
7346 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7349 u32 validity_offset;
7351 DP(NETIF_MSG_HW, "Starting\n");
7353 /* Set `magic' bit in order to save MF config */
7354 if (!CHIP_IS_E1(bp))
7355 bnx2x_clp_reset_prep(bp, magic_val);
7357 /* Get shmem offset */
7358 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7359 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7361 /* Clear validity map flags */
7363 REG_WR(bp, shmem + validity_offset, 0);
7366 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7367 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7369 /* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7370 * depending on the HW type.
7374 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7376 /* special handling for emulation and FPGA,
7377 wait 10 times longer */
7378 if (CHIP_REV_IS_SLOW(bp))
7379 msleep(MCP_ONE_TIMEOUT*10);
7381 msleep(MCP_ONE_TIMEOUT);
7384 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7386 u32 shmem, cnt, validity_offset, val;
7391 /* Get shmem offset */
7392 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7394 BNX2X_ERR("Shmem 0 return failure\n");
7399 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7401 /* Wait for MCP to come up */
7402 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7403 /* TBD: its best to check validity map of last port.
7404 * currently checks on port 0.
7406 val = REG_RD(bp, shmem + validity_offset);
7407 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7408 shmem + validity_offset, val);
7410 /* check that shared memory is valid. */
7411 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7412 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7415 bnx2x_mcp_wait_one(bp);
7418 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7420 /* Check that shared memory is valid. This indicates that MCP is up. */
7421 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7422 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7423 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7429 /* Restore the `magic' bit value */
7430 if (!CHIP_IS_E1(bp))
7431 bnx2x_clp_reset_done(bp, magic_val);
7436 static void bnx2x_pxp_prep(struct bnx2x *bp)
7438 if (!CHIP_IS_E1(bp)) {
7439 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7440 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7441 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7447 * Reset the whole chip except for:
7449 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7452 * - MISC (including AEU)
7456 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7458 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7461 MISC_REGISTERS_RESET_REG_1_RST_HC |
7462 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7463 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7466 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7467 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7468 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7469 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7470 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7471 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7472 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7473 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7475 reset_mask1 = 0xffffffff;
7478 reset_mask2 = 0xffff;
7480 reset_mask2 = 0x1ffff;
7482 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7483 reset_mask1 & (~not_reset_mask1));
7484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7485 reset_mask2 & (~not_reset_mask2));
7490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7491 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7495 static int bnx2x_process_kill(struct bnx2x *bp)
7499 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7502 /* Empty the Tetris buffer, wait for 1s */
7504 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7505 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7506 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7507 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7508 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7509 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7510 ((port_is_idle_0 & 0x1) == 0x1) &&
7511 ((port_is_idle_1 & 0x1) == 0x1) &&
7512 (pgl_exp_rom2 == 0xffffffff))
7515 } while (cnt-- > 0);
7518 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7520 " outstanding read requests after 1s!\n");
7521 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7522 " port_is_idle_0=0x%08x,"
7523 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7524 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7531 /* Close gates #2, #3 and #4 */
7532 bnx2x_set_234_gates(bp, true);
7534 /* TBD: Indicate that "process kill" is in progress to MCP */
7536 /* Clear "unprepared" bit */
7537 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7540 /* Make sure all is written to the chip before the reset */
7543 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7544 * PSWHST, GRC and PSWRD Tetris buffer.
7548 /* Prepare to chip reset: */
7550 bnx2x_reset_mcp_prep(bp, &val);
7556 /* reset the chip */
7557 bnx2x_process_kill_chip_reset(bp);
7560 /* Recover after reset: */
7562 if (bnx2x_reset_mcp_comp(bp, val))
7568 /* Open the gates #2, #3 and #4 */
7569 bnx2x_set_234_gates(bp, false);
7571 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7572 * reset state, re-enable attentions. */
7577 static int bnx2x_leader_reset(struct bnx2x *bp)
7580 /* Try to recover after the failure */
7581 if (bnx2x_process_kill(bp)) {
7582 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7585 goto exit_leader_reset;
7588 /* Clear "reset is in progress" bit and update the driver state */
7589 bnx2x_set_reset_done(bp);
7590 bp->recovery_state = BNX2X_RECOVERY_DONE;
7594 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7599 /* Assumption: runs under rtnl lock. This together with the fact
7600 * that it's called only from bnx2x_reset_task() ensure that it
7601 * will never be called when netif_running(bp->dev) is false.
7603 static void bnx2x_parity_recover(struct bnx2x *bp)
7605 DP(NETIF_MSG_HW, "Handling parity\n");
7607 switch (bp->recovery_state) {
7608 case BNX2X_RECOVERY_INIT:
7609 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7610 /* Try to get a LEADER_LOCK HW lock */
7611 if (bnx2x_trylock_hw_lock(bp,
7612 HW_LOCK_RESOURCE_RESERVED_08))
7615 /* Stop the driver */
7616 /* If interface has been removed - break */
7617 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7620 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7621 /* Ensure "is_leader" and "recovery_state"
7622 * update values are seen on other CPUs
7627 case BNX2X_RECOVERY_WAIT:
7628 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7629 if (bp->is_leader) {
7630 u32 load_counter = bnx2x_get_load_cnt(bp);
7632 /* Wait until all other functions get
7635 schedule_delayed_work(&bp->reset_task,
7639 /* If all other functions got down -
7640 * try to bring the chip back to
7641 * normal. In any case it's an exit
7642 * point for a leader.
7644 if (bnx2x_leader_reset(bp) ||
7645 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7646 printk(KERN_ERR"%s: Recovery "
7647 "has failed. Power cycle is "
7648 "needed.\n", bp->dev->name);
7649 /* Disconnect this device */
7650 netif_device_detach(bp->dev);
7651 /* Block ifup for all function
7652 * of this ASIC until
7653 * "process kill" or power
7656 bnx2x_set_reset_in_progress(bp);
7657 /* Shut down the power */
7658 bnx2x_set_power_state(bp,
7665 } else { /* non-leader */
7666 if (!bnx2x_reset_is_done(bp)) {
7667 /* Try to get a LEADER_LOCK HW lock as
7668 * long as a former leader may have
7669 * been unloaded by the user or
7670 * released a leadership by another
7673 if (bnx2x_trylock_hw_lock(bp,
7674 HW_LOCK_RESOURCE_RESERVED_08)) {
7675 /* I'm a leader now! Restart a
7682 schedule_delayed_work(&bp->reset_task,
7686 } else { /* A leader has completed
7687 * the "process kill". It's an exit
7688 * point for a non-leader.
7690 bnx2x_nic_load(bp, LOAD_NORMAL);
7691 bp->recovery_state =
7692 BNX2X_RECOVERY_DONE;
7703 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7704 * scheduled on a general queue in order to prevent a dead lock.
7706 static void bnx2x_reset_task(struct work_struct *work)
7708 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7710 #ifdef BNX2X_STOP_ON_ERROR
7711 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7712 " so reset not done to allow debug dump,\n"
7713 KERN_ERR " you will need to reboot when done\n");
7719 if (!netif_running(bp->dev))
7720 goto reset_task_exit;
7722 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7723 bnx2x_parity_recover(bp);
7725 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7726 bnx2x_nic_load(bp, LOAD_NORMAL);
7733 /* end of nic load/unload */
7736 * Init service functions
7739 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7741 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7742 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7743 return base + (BP_ABS_FUNC(bp)) * stride;
7746 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7748 u32 reg = bnx2x_get_pretend_reg(bp);
7750 /* Flush all outstanding writes */
7753 /* Pretend to be function 0 */
7755 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7757 /* From now we are in the "like-E1" mode */
7758 bnx2x_int_disable(bp);
7760 /* Flush all outstanding writes */
7763 /* Restore the original function */
7764 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7768 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7771 bnx2x_int_disable(bp);
7773 bnx2x_undi_int_disable_e1h(bp);
7776 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7780 /* Check if there is any driver already loaded */
7781 val = REG_RD(bp, MISC_REG_UNPREPARED);
7783 /* Check if it is the UNDI driver
7784 * UNDI driver initializes CID offset for normal bell to 0x7
7786 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7787 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7789 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7790 /* save our pf_num */
7791 int orig_pf_num = bp->pf_num;
7795 /* clear the UNDI indication */
7796 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7798 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7800 /* try unload UNDI on port 0 */
7803 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7804 DRV_MSG_SEQ_NUMBER_MASK);
7805 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7807 /* if UNDI is loaded on the other port */
7808 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7810 /* send "DONE" for previous unload */
7811 bnx2x_fw_command(bp,
7812 DRV_MSG_CODE_UNLOAD_DONE, 0);
7814 /* unload UNDI on port 1 */
7817 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7818 DRV_MSG_SEQ_NUMBER_MASK);
7819 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7821 bnx2x_fw_command(bp, reset_code, 0);
7824 /* now it's safe to release the lock */
7825 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7827 bnx2x_undi_int_disable(bp);
7829 /* close input traffic and wait for it */
7830 /* Do not rcv packets to BRB */
7832 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7833 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7834 /* Do not direct rcv packets that are not for MCP to
7837 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7838 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7841 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7842 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7845 /* save NIG port swap info */
7846 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7847 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7850 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7853 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7855 /* take the NIG out of reset and restore swap values */
7857 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7858 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7859 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7860 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7862 /* send unload done to the MCP */
7863 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7865 /* restore our func and fw_seq */
7866 bp->pf_num = orig_pf_num;
7868 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7869 DRV_MSG_SEQ_NUMBER_MASK);
7871 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7875 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7877 u32 val, val2, val3, val4, id;
7880 /* Get the chip revision id and number. */
7881 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7882 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7883 id = ((val & 0xffff) << 16);
7884 val = REG_RD(bp, MISC_REG_CHIP_REV);
7885 id |= ((val & 0xf) << 12);
7886 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7887 id |= ((val & 0xff) << 4);
7888 val = REG_RD(bp, MISC_REG_BOND_ID);
7890 bp->common.chip_id = id;
7892 /* Set doorbell size */
7893 bp->db_size = (1 << BNX2X_DB_SHIFT);
7895 if (CHIP_IS_E2(bp)) {
7896 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7898 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7900 val = (val >> 1) & 1;
7901 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7903 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7906 if (CHIP_MODE_IS_4_PORT(bp))
7907 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7909 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7911 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7912 bp->pfid = bp->pf_num; /* 0..7 */
7916 * set base FW non-default (fast path) status block id, this value is
7917 * used to initialize the fw_sb_id saved on the fp/queue structure to
7918 * determine the id used by the FW.
7920 if (CHIP_IS_E1x(bp))
7921 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7923 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7925 bp->link_params.chip_id = bp->common.chip_id;
7926 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7928 val = (REG_RD(bp, 0x2874) & 0x55);
7929 if ((bp->common.chip_id & 0x1) ||
7930 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7931 bp->flags |= ONE_PORT_FLAG;
7932 BNX2X_DEV_INFO("single port device\n");
7935 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7936 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7937 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7938 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7939 bp->common.flash_size, bp->common.flash_size);
7941 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7942 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7943 MISC_REG_GENERIC_CR_1 :
7944 MISC_REG_GENERIC_CR_0));
7945 bp->link_params.shmem_base = bp->common.shmem_base;
7946 bp->link_params.shmem2_base = bp->common.shmem2_base;
7947 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7948 bp->common.shmem_base, bp->common.shmem2_base);
7950 if (!bp->common.shmem_base) {
7951 BNX2X_DEV_INFO("MCP not active\n");
7952 bp->flags |= NO_MCP_FLAG;
7956 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7957 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7958 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7959 BNX2X_ERR("BAD MCP validity signature\n");
7961 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7962 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7964 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7965 SHARED_HW_CFG_LED_MODE_MASK) >>
7966 SHARED_HW_CFG_LED_MODE_SHIFT);
7968 bp->link_params.feature_config_flags = 0;
7969 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7970 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7971 bp->link_params.feature_config_flags |=
7972 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7974 bp->link_params.feature_config_flags &=
7975 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7977 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7978 bp->common.bc_ver = val;
7979 BNX2X_DEV_INFO("bc_ver %X\n", val);
7980 if (val < BNX2X_BC_VER) {
7981 /* for now only warn
7982 * later we might need to enforce this */
7983 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7984 "please upgrade BC\n", BNX2X_BC_VER, val);
7986 bp->link_params.feature_config_flags |=
7987 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7988 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7990 bp->link_params.feature_config_flags |=
7991 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7992 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7994 if (BP_E1HVN(bp) == 0) {
7995 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7996 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7998 /* no WOL capability for E1HVN != 0 */
7999 bp->flags |= NO_WOL_FLAG;
8001 BNX2X_DEV_INFO("%sWoL capable\n",
8002 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8004 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8005 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8006 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8007 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8009 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8010 val, val2, val3, val4);
8013 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8014 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8016 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8018 int pfid = BP_FUNC(bp);
8019 int vn = BP_E1HVN(bp);
8024 bp->igu_base_sb = 0xff;
8026 if (CHIP_INT_MODE_IS_BC(bp)) {
8027 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8028 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8030 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8033 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8034 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8039 /* IGU in normal mode - read CAM */
8040 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8042 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8043 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8046 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8047 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8049 if (IGU_VEC(val) == 0)
8050 /* default status block */
8051 bp->igu_dsb_id = igu_sb_id;
8053 if (bp->igu_base_sb == 0xff)
8054 bp->igu_base_sb = igu_sb_id;
8059 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8060 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8061 if (bp->igu_sb_cnt == 0)
8062 BNX2X_ERR("CAM configuration error\n");
8065 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8068 int cfg_size = 0, idx, port = BP_PORT(bp);
8070 /* Aggregation of supported attributes of all external phys */
8071 bp->port.supported[0] = 0;
8072 bp->port.supported[1] = 0;
8073 switch (bp->link_params.num_phys) {
8075 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8079 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8083 if (bp->link_params.multi_phy_config &
8084 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8085 bp->port.supported[1] =
8086 bp->link_params.phy[EXT_PHY1].supported;
8087 bp->port.supported[0] =
8088 bp->link_params.phy[EXT_PHY2].supported;
8090 bp->port.supported[0] =
8091 bp->link_params.phy[EXT_PHY1].supported;
8092 bp->port.supported[1] =
8093 bp->link_params.phy[EXT_PHY2].supported;
8099 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8100 BNX2X_ERR("NVRAM config error. BAD phy config."
8101 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8103 dev_info.port_hw_config[port].external_phy_config),
8105 dev_info.port_hw_config[port].external_phy_config2));
8109 switch (switch_cfg) {
8111 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8113 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8116 case SWITCH_CFG_10G:
8117 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8119 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8123 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8124 bp->port.link_config[0]);
8127 /* mask what we support according to speed_cap_mask per configuration */
8128 for (idx = 0; idx < cfg_size; idx++) {
8129 if (!(bp->link_params.speed_cap_mask[idx] &
8130 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8131 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8133 if (!(bp->link_params.speed_cap_mask[idx] &
8134 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8135 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8137 if (!(bp->link_params.speed_cap_mask[idx] &
8138 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8139 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8141 if (!(bp->link_params.speed_cap_mask[idx] &
8142 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8143 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8145 if (!(bp->link_params.speed_cap_mask[idx] &
8146 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8147 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8148 SUPPORTED_1000baseT_Full);
8150 if (!(bp->link_params.speed_cap_mask[idx] &
8151 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8152 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8154 if (!(bp->link_params.speed_cap_mask[idx] &
8155 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8156 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8160 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8161 bp->port.supported[1]);
8164 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8166 u32 link_config, idx, cfg_size = 0;
8167 bp->port.advertising[0] = 0;
8168 bp->port.advertising[1] = 0;
8169 switch (bp->link_params.num_phys) {
8178 for (idx = 0; idx < cfg_size; idx++) {
8179 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8180 link_config = bp->port.link_config[idx];
8181 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8182 case PORT_FEATURE_LINK_SPEED_AUTO:
8183 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8184 bp->link_params.req_line_speed[idx] =
8186 bp->port.advertising[idx] |=
8187 bp->port.supported[idx];
8189 /* force 10G, no AN */
8190 bp->link_params.req_line_speed[idx] =
8192 bp->port.advertising[idx] |=
8193 (ADVERTISED_10000baseT_Full |
8199 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8200 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8201 bp->link_params.req_line_speed[idx] =
8203 bp->port.advertising[idx] |=
8204 (ADVERTISED_10baseT_Full |
8207 BNX2X_ERROR("NVRAM config error. "
8208 "Invalid link_config 0x%x"
8209 " speed_cap_mask 0x%x\n",
8211 bp->link_params.speed_cap_mask[idx]);
8216 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8217 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8218 bp->link_params.req_line_speed[idx] =
8220 bp->link_params.req_duplex[idx] =
8222 bp->port.advertising[idx] |=
8223 (ADVERTISED_10baseT_Half |
8226 BNX2X_ERROR("NVRAM config error. "
8227 "Invalid link_config 0x%x"
8228 " speed_cap_mask 0x%x\n",
8230 bp->link_params.speed_cap_mask[idx]);
8235 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8236 if (bp->port.supported[idx] &
8237 SUPPORTED_100baseT_Full) {
8238 bp->link_params.req_line_speed[idx] =
8240 bp->port.advertising[idx] |=
8241 (ADVERTISED_100baseT_Full |
8244 BNX2X_ERROR("NVRAM config error. "
8245 "Invalid link_config 0x%x"
8246 " speed_cap_mask 0x%x\n",
8248 bp->link_params.speed_cap_mask[idx]);
8253 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8254 if (bp->port.supported[idx] &
8255 SUPPORTED_100baseT_Half) {
8256 bp->link_params.req_line_speed[idx] =
8258 bp->link_params.req_duplex[idx] =
8260 bp->port.advertising[idx] |=
8261 (ADVERTISED_100baseT_Half |
8264 BNX2X_ERROR("NVRAM config error. "
8265 "Invalid link_config 0x%x"
8266 " speed_cap_mask 0x%x\n",
8268 bp->link_params.speed_cap_mask[idx]);
8273 case PORT_FEATURE_LINK_SPEED_1G:
8274 if (bp->port.supported[idx] &
8275 SUPPORTED_1000baseT_Full) {
8276 bp->link_params.req_line_speed[idx] =
8278 bp->port.advertising[idx] |=
8279 (ADVERTISED_1000baseT_Full |
8282 BNX2X_ERROR("NVRAM config error. "
8283 "Invalid link_config 0x%x"
8284 " speed_cap_mask 0x%x\n",
8286 bp->link_params.speed_cap_mask[idx]);
8291 case PORT_FEATURE_LINK_SPEED_2_5G:
8292 if (bp->port.supported[idx] &
8293 SUPPORTED_2500baseX_Full) {
8294 bp->link_params.req_line_speed[idx] =
8296 bp->port.advertising[idx] |=
8297 (ADVERTISED_2500baseX_Full |
8300 BNX2X_ERROR("NVRAM config error. "
8301 "Invalid link_config 0x%x"
8302 " speed_cap_mask 0x%x\n",
8304 bp->link_params.speed_cap_mask[idx]);
8309 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8310 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8311 case PORT_FEATURE_LINK_SPEED_10G_KR:
8312 if (bp->port.supported[idx] &
8313 SUPPORTED_10000baseT_Full) {
8314 bp->link_params.req_line_speed[idx] =
8316 bp->port.advertising[idx] |=
8317 (ADVERTISED_10000baseT_Full |
8320 BNX2X_ERROR("NVRAM config error. "
8321 "Invalid link_config 0x%x"
8322 " speed_cap_mask 0x%x\n",
8324 bp->link_params.speed_cap_mask[idx]);
8330 BNX2X_ERROR("NVRAM config error. "
8331 "BAD link speed link_config 0x%x\n",
8333 bp->link_params.req_line_speed[idx] =
8335 bp->port.advertising[idx] =
8336 bp->port.supported[idx];
8340 bp->link_params.req_flow_ctrl[idx] = (link_config &
8341 PORT_FEATURE_FLOW_CONTROL_MASK);
8342 if ((bp->link_params.req_flow_ctrl[idx] ==
8343 BNX2X_FLOW_CTRL_AUTO) &&
8344 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8345 bp->link_params.req_flow_ctrl[idx] =
8346 BNX2X_FLOW_CTRL_NONE;
8349 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8350 " 0x%x advertising 0x%x\n",
8351 bp->link_params.req_line_speed[idx],
8352 bp->link_params.req_duplex[idx],
8353 bp->link_params.req_flow_ctrl[idx],
8354 bp->port.advertising[idx]);
8358 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8360 mac_hi = cpu_to_be16(mac_hi);
8361 mac_lo = cpu_to_be32(mac_lo);
8362 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8363 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8366 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8368 int port = BP_PORT(bp);
8370 u32 ext_phy_type, ext_phy_config;
8372 bp->link_params.bp = bp;
8373 bp->link_params.port = port;
8375 bp->link_params.lane_config =
8376 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8378 bp->link_params.speed_cap_mask[0] =
8380 dev_info.port_hw_config[port].speed_capability_mask);
8381 bp->link_params.speed_cap_mask[1] =
8383 dev_info.port_hw_config[port].speed_capability_mask2);
8384 bp->port.link_config[0] =
8385 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8387 bp->port.link_config[1] =
8388 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8390 bp->link_params.multi_phy_config =
8391 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8392 /* If the device is capable of WoL, set the default state according
8395 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8396 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8397 (config & PORT_FEATURE_WOL_ENABLED));
8399 BNX2X_DEV_INFO("lane_config 0x%08x "
8400 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8401 bp->link_params.lane_config,
8402 bp->link_params.speed_cap_mask[0],
8403 bp->port.link_config[0]);
8405 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8406 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8407 bnx2x_phy_probe(&bp->link_params);
8408 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8410 bnx2x_link_settings_requested(bp);
8413 * If connected directly, work with the internal PHY, otherwise, work
8414 * with the external PHY
8418 dev_info.port_hw_config[port].external_phy_config);
8419 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8420 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8421 bp->mdio.prtad = bp->port.phy_addr;
8423 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8424 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8426 XGXS_EXT_PHY_ADDR(ext_phy_config);
8429 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8432 int func = BP_ABS_FUNC(bp);
8433 int port = BP_PORT(bp);
8436 BNX2X_ERROR("warning: random MAC workaround active\n");
8437 random_ether_addr(bp->dev->dev_addr);
8438 } else if (IS_MF(bp)) {
8439 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8440 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8441 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8442 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8443 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8446 /* iSCSI NPAR MAC */
8448 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8449 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8450 val2 = MF_CFG_RD(bp, func_ext_config[func].
8451 iscsi_mac_addr_upper);
8452 val = MF_CFG_RD(bp, func_ext_config[func].
8453 iscsi_mac_addr_lower);
8454 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8459 /* in SF read MACs from port configuration */
8460 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8461 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8462 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8465 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8467 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8469 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8473 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8474 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8477 /* Inform the upper layers about FCoE MAC */
8478 if (!CHIP_IS_E1x(bp)) {
8480 memcpy(bp->fip_mac, bp->dev->dev_addr,
8481 sizeof(bp->fip_mac));
8483 memcpy(bp->fip_mac, bp->iscsi_mac,
8484 sizeof(bp->fip_mac));
8489 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8491 int /*abs*/func = BP_ABS_FUNC(bp);
8496 bnx2x_get_common_hwinfo(bp);
8498 if (CHIP_IS_E1x(bp)) {
8499 bp->common.int_block = INT_BLOCK_HC;
8501 bp->igu_dsb_id = DEF_SB_IGU_ID;
8502 bp->igu_base_sb = 0;
8503 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8504 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8506 bp->common.int_block = INT_BLOCK_IGU;
8507 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8508 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8509 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8510 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8512 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8514 bnx2x_get_igu_cam_info(bp);
8517 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8518 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8521 * Initialize MF configuration
8529 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8531 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8532 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8533 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8534 if (SHMEM2_HAS(bp, mf_cfg_addr))
8535 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8537 bp->common.mf_cfg_base = bp->common.shmem_base +
8538 offsetof(struct shmem_region, func_mb) +
8539 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8541 * get mf configuration:
8542 * 1. existance of MF configuration
8543 * 2. MAC address must be legal (check only upper bytes)
8544 * for Switch-Independent mode;
8545 * OVLAN must be legal for Switch-Dependent mode
8546 * 3. SF_MODE configures specific MF mode
8548 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8549 /* get mf configuration */
8551 dev_info.shared_feature_config.config);
8552 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8555 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8556 val = MF_CFG_RD(bp, func_mf_config[func].
8558 /* check for legal mac (upper bytes)*/
8559 if (val != 0xffff) {
8560 bp->mf_mode = MULTI_FUNCTION_SI;
8561 bp->mf_config[vn] = MF_CFG_RD(bp,
8562 func_mf_config[func].config);
8564 DP(NETIF_MSG_PROBE, "illegal MAC "
8565 "address for SI\n");
8567 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8568 /* get OV configuration */
8570 func_mf_config[FUNC_0].e1hov_tag);
8571 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8573 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8574 bp->mf_mode = MULTI_FUNCTION_SD;
8575 bp->mf_config[vn] = MF_CFG_RD(bp,
8576 func_mf_config[func].config);
8578 DP(NETIF_MSG_PROBE, "illegal OV for "
8582 /* Unknown configuration: reset mf_config */
8583 bp->mf_config[vn] = 0;
8584 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8589 BNX2X_DEV_INFO("%s function mode\n",
8590 IS_MF(bp) ? "multi" : "single");
8592 switch (bp->mf_mode) {
8593 case MULTI_FUNCTION_SD:
8594 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8595 FUNC_MF_CFG_E1HOV_TAG_MASK;
8596 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8598 BNX2X_DEV_INFO("MF OV for func %d is %d"
8599 " (0x%04x)\n", func,
8600 bp->mf_ov, bp->mf_ov);
8602 BNX2X_ERR("No valid MF OV for func %d,"
8603 " aborting\n", func);
8607 case MULTI_FUNCTION_SI:
8608 BNX2X_DEV_INFO("func %d is in MF "
8609 "switch-independent mode\n", func);
8613 BNX2X_ERR("VN %d in single function mode,"
8622 /* adjust igu_sb_cnt to MF for E1x */
8623 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8624 bp->igu_sb_cnt /= E1HVN_MAX;
8627 * adjust E2 sb count: to be removed when FW will support
8628 * more then 16 L2 clients
8630 #define MAX_L2_CLIENTS 16
8632 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8633 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8635 if (!BP_NOMCP(bp)) {
8636 bnx2x_get_port_hwinfo(bp);
8639 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8640 DRV_MSG_SEQ_NUMBER_MASK);
8641 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8644 /* Get MAC addresses */
8645 bnx2x_get_mac_hwinfo(bp);
8650 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8652 int cnt, i, block_end, rodi;
8653 char vpd_data[BNX2X_VPD_LEN+1];
8654 char str_id_reg[VENDOR_ID_LEN+1];
8655 char str_id_cap[VENDOR_ID_LEN+1];
8658 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8659 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8661 if (cnt < BNX2X_VPD_LEN)
8664 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8665 PCI_VPD_LRDT_RO_DATA);
8670 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8671 pci_vpd_lrdt_size(&vpd_data[i]);
8673 i += PCI_VPD_LRDT_TAG_SIZE;
8675 if (block_end > BNX2X_VPD_LEN)
8678 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8679 PCI_VPD_RO_KEYWORD_MFR_ID);
8683 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8685 if (len != VENDOR_ID_LEN)
8688 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8690 /* vendor specific info */
8691 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8692 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8693 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8694 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8696 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8697 PCI_VPD_RO_KEYWORD_VENDOR0);
8699 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8701 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8703 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8704 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8705 bp->fw_ver[len] = ' ';
8714 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8720 /* Disable interrupt handling until HW is initialized */
8721 atomic_set(&bp->intr_sem, 1);
8722 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8724 mutex_init(&bp->port.phy_mutex);
8725 mutex_init(&bp->fw_mb_mutex);
8726 spin_lock_init(&bp->stats_lock);
8728 mutex_init(&bp->cnic_mutex);
8731 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8732 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8734 rc = bnx2x_get_hwinfo(bp);
8737 rc = bnx2x_alloc_mem_bp(bp);
8739 bnx2x_read_fwinfo(bp);
8743 /* need to reset chip if undi was active */
8745 bnx2x_undi_unload(bp);
8747 if (CHIP_REV_IS_FPGA(bp))
8748 dev_err(&bp->pdev->dev, "FPGA detected\n");
8750 if (BP_NOMCP(bp) && (func == 0))
8751 dev_err(&bp->pdev->dev, "MCP disabled, "
8752 "must load devices in order!\n");
8754 /* Set multi queue mode */
8755 if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
8756 ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
8757 dev_err(&bp->pdev->dev, "Multi disabled since int_mode "
8758 "requested is not MSI-X\n");
8759 multi_mode = ETH_RSS_MODE_DISABLED;
8761 bp->multi_mode = multi_mode;
8762 bp->int_mode = int_mode;
8764 bp->dev->features |= NETIF_F_GRO;
8768 bp->flags &= ~TPA_ENABLE_FLAG;
8769 bp->dev->features &= ~NETIF_F_LRO;
8771 bp->flags |= TPA_ENABLE_FLAG;
8772 bp->dev->features |= NETIF_F_LRO;
8774 bp->disable_tpa = disable_tpa;
8777 bp->dropless_fc = 0;
8779 bp->dropless_fc = dropless_fc;
8783 bp->tx_ring_size = MAX_TX_AVAIL;
8787 /* make sure that the numbers are in the right granularity */
8788 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8789 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8791 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8792 bp->current_interval = (poll ? poll : timer_interval);
8794 init_timer(&bp->timer);
8795 bp->timer.expires = jiffies + bp->current_interval;
8796 bp->timer.data = (unsigned long) bp;
8797 bp->timer.function = bnx2x_timer;
8799 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8800 bnx2x_dcbx_init_params(bp);
8806 /****************************************************************************
8807 * General service functions
8808 ****************************************************************************/
8810 /* called with rtnl_lock */
8811 static int bnx2x_open(struct net_device *dev)
8813 struct bnx2x *bp = netdev_priv(dev);
8815 netif_carrier_off(dev);
8817 bnx2x_set_power_state(bp, PCI_D0);
8819 if (!bnx2x_reset_is_done(bp)) {
8821 /* Reset MCP mail box sequence if there is on going
8826 /* If it's the first function to load and reset done
8827 * is still not cleared it may mean that. We don't
8828 * check the attention state here because it may have
8829 * already been cleared by a "common" reset but we
8830 * shell proceed with "process kill" anyway.
8832 if ((bnx2x_get_load_cnt(bp) == 0) &&
8833 bnx2x_trylock_hw_lock(bp,
8834 HW_LOCK_RESOURCE_RESERVED_08) &&
8835 (!bnx2x_leader_reset(bp))) {
8836 DP(NETIF_MSG_HW, "Recovered in open\n");
8840 bnx2x_set_power_state(bp, PCI_D3hot);
8842 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8843 " completed yet. Try again later. If u still see this"
8844 " message after a few retries then power cycle is"
8845 " required.\n", bp->dev->name);
8851 bp->recovery_state = BNX2X_RECOVERY_DONE;
8853 return bnx2x_nic_load(bp, LOAD_OPEN);
8856 /* called with rtnl_lock */
8857 static int bnx2x_close(struct net_device *dev)
8859 struct bnx2x *bp = netdev_priv(dev);
8861 /* Unload the driver, release IRQs */
8862 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8863 bnx2x_set_power_state(bp, PCI_D3hot);
8868 /* called with netif_tx_lock from dev_mcast.c */
8869 void bnx2x_set_rx_mode(struct net_device *dev)
8871 struct bnx2x *bp = netdev_priv(dev);
8872 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8873 int port = BP_PORT(bp);
8875 if (bp->state != BNX2X_STATE_OPEN) {
8876 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8880 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8882 if (dev->flags & IFF_PROMISC)
8883 rx_mode = BNX2X_RX_MODE_PROMISC;
8884 else if ((dev->flags & IFF_ALLMULTI) ||
8885 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8887 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8888 else { /* some multicasts */
8889 if (CHIP_IS_E1(bp)) {
8891 * set mc list, do not wait as wait implies sleep
8892 * and set_rx_mode can be invoked from non-sleepable
8895 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8896 BNX2X_MAX_EMUL_MULTI*(1 + port) :
8897 BNX2X_MAX_MULTICAST*(1 + port));
8899 bnx2x_set_e1_mc_list(bp, offset);
8901 /* Accept one or more multicasts */
8902 struct netdev_hw_addr *ha;
8903 u32 mc_filter[MC_HASH_SIZE];
8904 u32 crc, bit, regidx;
8907 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8909 netdev_for_each_mc_addr(ha, dev) {
8910 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
8913 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8915 bit = (crc >> 24) & 0xff;
8918 mc_filter[regidx] |= (1 << bit);
8921 for (i = 0; i < MC_HASH_SIZE; i++)
8922 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8927 bp->rx_mode = rx_mode;
8928 bnx2x_set_storm_rx_mode(bp);
8931 /* called with rtnl_lock */
8932 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8933 int devad, u16 addr)
8935 struct bnx2x *bp = netdev_priv(netdev);
8939 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8940 prtad, devad, addr);
8942 /* The HW expects different devad if CL22 is used */
8943 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8945 bnx2x_acquire_phy_lock(bp);
8946 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
8947 bnx2x_release_phy_lock(bp);
8948 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
8955 /* called with rtnl_lock */
8956 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8957 u16 addr, u16 value)
8959 struct bnx2x *bp = netdev_priv(netdev);
8962 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8963 " value 0x%x\n", prtad, devad, addr, value);
8965 /* The HW expects different devad if CL22 is used */
8966 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8968 bnx2x_acquire_phy_lock(bp);
8969 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
8970 bnx2x_release_phy_lock(bp);
8974 /* called with rtnl_lock */
8975 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8977 struct bnx2x *bp = netdev_priv(dev);
8978 struct mii_ioctl_data *mdio = if_mii(ifr);
8980 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
8981 mdio->phy_id, mdio->reg_num, mdio->val_in);
8983 if (!netif_running(dev))
8986 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
8989 #ifdef CONFIG_NET_POLL_CONTROLLER
8990 static void poll_bnx2x(struct net_device *dev)
8992 struct bnx2x *bp = netdev_priv(dev);
8994 disable_irq(bp->pdev->irq);
8995 bnx2x_interrupt(bp->pdev->irq, dev);
8996 enable_irq(bp->pdev->irq);
9000 static const struct net_device_ops bnx2x_netdev_ops = {
9001 .ndo_open = bnx2x_open,
9002 .ndo_stop = bnx2x_close,
9003 .ndo_start_xmit = bnx2x_start_xmit,
9004 .ndo_select_queue = bnx2x_select_queue,
9005 .ndo_set_multicast_list = bnx2x_set_rx_mode,
9006 .ndo_set_mac_address = bnx2x_change_mac_addr,
9007 .ndo_validate_addr = eth_validate_addr,
9008 .ndo_do_ioctl = bnx2x_ioctl,
9009 .ndo_change_mtu = bnx2x_change_mtu,
9010 .ndo_tx_timeout = bnx2x_tx_timeout,
9011 #ifdef CONFIG_NET_POLL_CONTROLLER
9012 .ndo_poll_controller = poll_bnx2x,
9016 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9017 struct net_device *dev)
9022 SET_NETDEV_DEV(dev, &pdev->dev);
9023 bp = netdev_priv(dev);
9028 bp->pf_num = PCI_FUNC(pdev->devfn);
9030 rc = pci_enable_device(pdev);
9032 dev_err(&bp->pdev->dev,
9033 "Cannot enable PCI device, aborting\n");
9037 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9038 dev_err(&bp->pdev->dev,
9039 "Cannot find PCI device base address, aborting\n");
9041 goto err_out_disable;
9044 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9045 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9046 " base address, aborting\n");
9048 goto err_out_disable;
9051 if (atomic_read(&pdev->enable_cnt) == 1) {
9052 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9054 dev_err(&bp->pdev->dev,
9055 "Cannot obtain PCI resources, aborting\n");
9056 goto err_out_disable;
9059 pci_set_master(pdev);
9060 pci_save_state(pdev);
9063 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9064 if (bp->pm_cap == 0) {
9065 dev_err(&bp->pdev->dev,
9066 "Cannot find power management capability, aborting\n");
9068 goto err_out_release;
9071 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9072 if (bp->pcie_cap == 0) {
9073 dev_err(&bp->pdev->dev,
9074 "Cannot find PCI Express capability, aborting\n");
9076 goto err_out_release;
9079 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9080 bp->flags |= USING_DAC_FLAG;
9081 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9082 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9083 " failed, aborting\n");
9085 goto err_out_release;
9088 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9089 dev_err(&bp->pdev->dev,
9090 "System does not support DMA, aborting\n");
9092 goto err_out_release;
9095 dev->mem_start = pci_resource_start(pdev, 0);
9096 dev->base_addr = dev->mem_start;
9097 dev->mem_end = pci_resource_end(pdev, 0);
9099 dev->irq = pdev->irq;
9101 bp->regview = pci_ioremap_bar(pdev, 0);
9103 dev_err(&bp->pdev->dev,
9104 "Cannot map register space, aborting\n");
9106 goto err_out_release;
9109 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9110 min_t(u64, BNX2X_DB_SIZE(bp),
9111 pci_resource_len(pdev, 2)));
9112 if (!bp->doorbells) {
9113 dev_err(&bp->pdev->dev,
9114 "Cannot map doorbell space, aborting\n");
9119 bnx2x_set_power_state(bp, PCI_D0);
9121 /* clean indirect addresses */
9122 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9123 PCICFG_VENDOR_ID_OFFSET);
9124 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9125 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9126 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9127 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9129 /* Reset the load counter */
9130 bnx2x_clear_load_cnt(bp);
9132 dev->watchdog_timeo = TX_TIMEOUT;
9134 dev->netdev_ops = &bnx2x_netdev_ops;
9135 bnx2x_set_ethtool_ops(dev);
9136 dev->features |= NETIF_F_SG;
9137 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9138 if (bp->flags & USING_DAC_FLAG)
9139 dev->features |= NETIF_F_HIGHDMA;
9140 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9141 dev->features |= NETIF_F_TSO6;
9142 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9144 dev->vlan_features |= NETIF_F_SG;
9145 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9146 if (bp->flags & USING_DAC_FLAG)
9147 dev->vlan_features |= NETIF_F_HIGHDMA;
9148 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9149 dev->vlan_features |= NETIF_F_TSO6;
9152 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9155 /* get_port_hwinfo() will set prtad and mmds properly */
9156 bp->mdio.prtad = MDIO_PRTAD_NONE;
9158 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9160 bp->mdio.mdio_read = bnx2x_mdio_read;
9161 bp->mdio.mdio_write = bnx2x_mdio_write;
9167 iounmap(bp->regview);
9170 if (bp->doorbells) {
9171 iounmap(bp->doorbells);
9172 bp->doorbells = NULL;
9176 if (atomic_read(&pdev->enable_cnt) == 1)
9177 pci_release_regions(pdev);
9180 pci_disable_device(pdev);
9181 pci_set_drvdata(pdev, NULL);
9187 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9188 int *width, int *speed)
9190 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9192 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9194 /* return value of 1=2.5GHz 2=5GHz */
9195 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9198 static int bnx2x_check_firmware(struct bnx2x *bp)
9200 const struct firmware *firmware = bp->firmware;
9201 struct bnx2x_fw_file_hdr *fw_hdr;
9202 struct bnx2x_fw_file_section *sections;
9203 u32 offset, len, num_ops;
9208 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9211 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9212 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9214 /* Make sure none of the offsets and sizes make us read beyond
9215 * the end of the firmware data */
9216 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9217 offset = be32_to_cpu(sections[i].offset);
9218 len = be32_to_cpu(sections[i].len);
9219 if (offset + len > firmware->size) {
9220 dev_err(&bp->pdev->dev,
9221 "Section %d length is out of bounds\n", i);
9226 /* Likewise for the init_ops offsets */
9227 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9228 ops_offsets = (u16 *)(firmware->data + offset);
9229 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9231 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9232 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9233 dev_err(&bp->pdev->dev,
9234 "Section offset %d is out of bounds\n", i);
9239 /* Check FW version */
9240 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9241 fw_ver = firmware->data + offset;
9242 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9243 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9244 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9245 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9246 dev_err(&bp->pdev->dev,
9247 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9248 fw_ver[0], fw_ver[1], fw_ver[2],
9249 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9250 BCM_5710_FW_MINOR_VERSION,
9251 BCM_5710_FW_REVISION_VERSION,
9252 BCM_5710_FW_ENGINEERING_VERSION);
9259 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9261 const __be32 *source = (const __be32 *)_source;
9262 u32 *target = (u32 *)_target;
9265 for (i = 0; i < n/4; i++)
9266 target[i] = be32_to_cpu(source[i]);
9270 Ops array is stored in the following format:
9271 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9273 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9275 const __be32 *source = (const __be32 *)_source;
9276 struct raw_op *target = (struct raw_op *)_target;
9279 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9280 tmp = be32_to_cpu(source[j]);
9281 target[i].op = (tmp >> 24) & 0xff;
9282 target[i].offset = tmp & 0xffffff;
9283 target[i].raw_data = be32_to_cpu(source[j + 1]);
9288 * IRO array is stored in the following format:
9289 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9291 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9293 const __be32 *source = (const __be32 *)_source;
9294 struct iro *target = (struct iro *)_target;
9297 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9298 target[i].base = be32_to_cpu(source[j]);
9300 tmp = be32_to_cpu(source[j]);
9301 target[i].m1 = (tmp >> 16) & 0xffff;
9302 target[i].m2 = tmp & 0xffff;
9304 tmp = be32_to_cpu(source[j]);
9305 target[i].m3 = (tmp >> 16) & 0xffff;
9306 target[i].size = tmp & 0xffff;
9311 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9313 const __be16 *source = (const __be16 *)_source;
9314 u16 *target = (u16 *)_target;
9317 for (i = 0; i < n/2; i++)
9318 target[i] = be16_to_cpu(source[i]);
9321 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9323 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9324 bp->arr = kmalloc(len, GFP_KERNEL); \
9326 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9329 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9330 (u8 *)bp->arr, len); \
9333 int bnx2x_init_firmware(struct bnx2x *bp)
9335 const char *fw_file_name;
9336 struct bnx2x_fw_file_hdr *fw_hdr;
9340 fw_file_name = FW_FILE_NAME_E1;
9341 else if (CHIP_IS_E1H(bp))
9342 fw_file_name = FW_FILE_NAME_E1H;
9343 else if (CHIP_IS_E2(bp))
9344 fw_file_name = FW_FILE_NAME_E2;
9346 BNX2X_ERR("Unsupported chip revision\n");
9350 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9352 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9354 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9355 goto request_firmware_exit;
9358 rc = bnx2x_check_firmware(bp);
9360 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9361 goto request_firmware_exit;
9364 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9366 /* Initialize the pointers to the init arrays */
9368 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9371 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9374 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9377 /* STORMs firmware */
9378 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9379 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9380 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9381 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9382 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9383 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9384 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9385 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9386 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9387 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9388 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9389 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9390 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9391 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9392 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9393 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9395 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9400 kfree(bp->init_ops_offsets);
9401 init_offsets_alloc_err:
9402 kfree(bp->init_ops);
9404 kfree(bp->init_data);
9405 request_firmware_exit:
9406 release_firmware(bp->firmware);
9411 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9413 int cid_count = L2_FP_COUNT(l2_cid_count);
9416 cid_count += CNIC_CID_MAX;
9418 return roundup(cid_count, QM_CID_ROUND);
9421 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9422 const struct pci_device_id *ent)
9424 struct net_device *dev = NULL;
9426 int pcie_width, pcie_speed;
9429 switch (ent->driver_data) {
9433 cid_count = FP_SB_MAX_E1x;
9438 cid_count = FP_SB_MAX_E2;
9442 pr_err("Unknown board_type (%ld), aborting\n",
9447 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9449 /* dev zeroed in init_etherdev */
9450 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9452 dev_err(&pdev->dev, "Cannot allocate net device\n");
9456 bp = netdev_priv(dev);
9457 bp->msg_enable = debug;
9459 pci_set_drvdata(pdev, dev);
9461 bp->l2_cid_count = cid_count;
9463 rc = bnx2x_init_dev(pdev, dev);
9469 rc = bnx2x_init_bp(bp);
9473 /* calc qm_cid_count */
9474 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9477 /* disable FCOE L2 queue for E1x*/
9478 if (CHIP_IS_E1x(bp))
9479 bp->flags |= NO_FCOE_FLAG;
9483 /* Configure interupt mode: try to enable MSI-X/MSI if
9484 * needed, set bp->num_queues appropriately.
9486 bnx2x_set_int_mode(bp);
9488 /* Add all NAPI objects */
9489 bnx2x_add_all_napi(bp);
9491 rc = register_netdev(dev);
9493 dev_err(&pdev->dev, "Cannot register net device\n");
9499 /* Add storage MAC address */
9501 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9506 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9508 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9509 " IRQ %d, ", board_info[ent->driver_data].name,
9510 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9512 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9513 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9514 "5GHz (Gen2)" : "2.5GHz",
9515 dev->base_addr, bp->pdev->irq);
9516 pr_cont("node addr %pM\n", dev->dev_addr);
9522 iounmap(bp->regview);
9525 iounmap(bp->doorbells);
9529 if (atomic_read(&pdev->enable_cnt) == 1)
9530 pci_release_regions(pdev);
9532 pci_disable_device(pdev);
9533 pci_set_drvdata(pdev, NULL);
9538 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9540 struct net_device *dev = pci_get_drvdata(pdev);
9544 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9547 bp = netdev_priv(dev);
9550 /* Delete storage MAC address */
9553 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9558 unregister_netdev(dev);
9560 /* Delete all NAPI objects */
9561 bnx2x_del_all_napi(bp);
9563 /* Disable MSI/MSI-X */
9564 bnx2x_disable_msi(bp);
9566 /* Make sure RESET task is not scheduled before continuing */
9567 cancel_delayed_work_sync(&bp->reset_task);
9570 iounmap(bp->regview);
9573 iounmap(bp->doorbells);
9575 bnx2x_free_mem_bp(bp);
9579 if (atomic_read(&pdev->enable_cnt) == 1)
9580 pci_release_regions(pdev);
9582 pci_disable_device(pdev);
9583 pci_set_drvdata(pdev, NULL);
9586 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9590 bp->state = BNX2X_STATE_ERROR;
9592 bp->rx_mode = BNX2X_RX_MODE_NONE;
9594 bnx2x_netif_stop(bp, 0);
9595 netif_carrier_off(bp->dev);
9597 del_timer_sync(&bp->timer);
9598 bp->stats_state = STATS_STATE_DISABLED;
9599 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9604 /* Free SKBs, SGEs, TPA pool and driver internals */
9605 bnx2x_free_skbs(bp);
9607 for_each_rx_queue(bp, i)
9608 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9612 bp->state = BNX2X_STATE_CLOSED;
9617 static void bnx2x_eeh_recover(struct bnx2x *bp)
9621 mutex_init(&bp->port.phy_mutex);
9623 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9624 bp->link_params.shmem_base = bp->common.shmem_base;
9625 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9627 if (!bp->common.shmem_base ||
9628 (bp->common.shmem_base < 0xA0000) ||
9629 (bp->common.shmem_base >= 0xC0000)) {
9630 BNX2X_DEV_INFO("MCP not active\n");
9631 bp->flags |= NO_MCP_FLAG;
9635 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9636 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9637 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9638 BNX2X_ERR("BAD MCP validity signature\n");
9640 if (!BP_NOMCP(bp)) {
9642 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9643 DRV_MSG_SEQ_NUMBER_MASK);
9644 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9649 * bnx2x_io_error_detected - called when PCI error is detected
9650 * @pdev: Pointer to PCI device
9651 * @state: The current pci connection state
9653 * This function is called after a PCI bus error affecting
9654 * this device has been detected.
9656 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9657 pci_channel_state_t state)
9659 struct net_device *dev = pci_get_drvdata(pdev);
9660 struct bnx2x *bp = netdev_priv(dev);
9664 netif_device_detach(dev);
9666 if (state == pci_channel_io_perm_failure) {
9668 return PCI_ERS_RESULT_DISCONNECT;
9671 if (netif_running(dev))
9672 bnx2x_eeh_nic_unload(bp);
9674 pci_disable_device(pdev);
9678 /* Request a slot reset */
9679 return PCI_ERS_RESULT_NEED_RESET;
9683 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9684 * @pdev: Pointer to PCI device
9686 * Restart the card from scratch, as if from a cold-boot.
9688 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9690 struct net_device *dev = pci_get_drvdata(pdev);
9691 struct bnx2x *bp = netdev_priv(dev);
9695 if (pci_enable_device(pdev)) {
9697 "Cannot re-enable PCI device after reset\n");
9699 return PCI_ERS_RESULT_DISCONNECT;
9702 pci_set_master(pdev);
9703 pci_restore_state(pdev);
9705 if (netif_running(dev))
9706 bnx2x_set_power_state(bp, PCI_D0);
9710 return PCI_ERS_RESULT_RECOVERED;
9714 * bnx2x_io_resume - called when traffic can start flowing again
9715 * @pdev: Pointer to PCI device
9717 * This callback is called when the error recovery driver tells us that
9718 * its OK to resume normal operation.
9720 static void bnx2x_io_resume(struct pci_dev *pdev)
9722 struct net_device *dev = pci_get_drvdata(pdev);
9723 struct bnx2x *bp = netdev_priv(dev);
9725 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9726 printk(KERN_ERR "Handling parity error recovery. "
9727 "Try again later\n");
9733 bnx2x_eeh_recover(bp);
9735 if (netif_running(dev))
9736 bnx2x_nic_load(bp, LOAD_NORMAL);
9738 netif_device_attach(dev);
9743 static struct pci_error_handlers bnx2x_err_handler = {
9744 .error_detected = bnx2x_io_error_detected,
9745 .slot_reset = bnx2x_io_slot_reset,
9746 .resume = bnx2x_io_resume,
9749 static struct pci_driver bnx2x_pci_driver = {
9750 .name = DRV_MODULE_NAME,
9751 .id_table = bnx2x_pci_tbl,
9752 .probe = bnx2x_init_one,
9753 .remove = __devexit_p(bnx2x_remove_one),
9754 .suspend = bnx2x_suspend,
9755 .resume = bnx2x_resume,
9756 .err_handler = &bnx2x_err_handler,
9759 static int __init bnx2x_init(void)
9763 pr_info("%s", version);
9765 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9766 if (bnx2x_wq == NULL) {
9767 pr_err("Cannot create workqueue\n");
9771 ret = pci_register_driver(&bnx2x_pci_driver);
9773 pr_err("Cannot register driver\n");
9774 destroy_workqueue(bnx2x_wq);
9779 static void __exit bnx2x_cleanup(void)
9781 pci_unregister_driver(&bnx2x_pci_driver);
9783 destroy_workqueue(bnx2x_wq);
9786 module_init(bnx2x_init);
9787 module_exit(bnx2x_cleanup);
9791 /* count denotes the number of new completions we have seen */
9792 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9794 struct eth_spe *spe;
9796 #ifdef BNX2X_STOP_ON_ERROR
9797 if (unlikely(bp->panic))
9801 spin_lock_bh(&bp->spq_lock);
9802 BUG_ON(bp->cnic_spq_pending < count);
9803 bp->cnic_spq_pending -= count;
9806 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9807 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9808 & SPE_HDR_CONN_TYPE) >>
9809 SPE_HDR_CONN_TYPE_SHIFT;
9811 /* Set validation for iSCSI L2 client before sending SETUP
9814 if (type == ETH_CONNECTION_TYPE) {
9815 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9816 hdr.conn_and_cmd_data) >>
9817 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9819 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9820 bnx2x_set_ctx_validation(&bp->context.
9821 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9822 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9825 /* There may be not more than 8 L2 and COMMON SPEs and not more
9826 * than 8 L5 SPEs in the air.
9828 if ((type == NONE_CONNECTION_TYPE) ||
9829 (type == ETH_CONNECTION_TYPE)) {
9830 if (!atomic_read(&bp->spq_left))
9833 atomic_dec(&bp->spq_left);
9834 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9835 (type == FCOE_CONNECTION_TYPE)) {
9836 if (bp->cnic_spq_pending >=
9837 bp->cnic_eth_dev.max_kwqe_pending)
9840 bp->cnic_spq_pending++;
9842 BNX2X_ERR("Unknown SPE type: %d\n", type);
9847 spe = bnx2x_sp_get_next(bp);
9848 *spe = *bp->cnic_kwq_cons;
9850 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9851 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9853 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9854 bp->cnic_kwq_cons = bp->cnic_kwq;
9856 bp->cnic_kwq_cons++;
9858 bnx2x_sp_prod_update(bp);
9859 spin_unlock_bh(&bp->spq_lock);
9862 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9863 struct kwqe_16 *kwqes[], u32 count)
9865 struct bnx2x *bp = netdev_priv(dev);
9868 #ifdef BNX2X_STOP_ON_ERROR
9869 if (unlikely(bp->panic))
9873 spin_lock_bh(&bp->spq_lock);
9875 for (i = 0; i < count; i++) {
9876 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9878 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9881 *bp->cnic_kwq_prod = *spe;
9883 bp->cnic_kwq_pending++;
9885 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9886 spe->hdr.conn_and_cmd_data, spe->hdr.type,
9887 spe->data.update_data_addr.hi,
9888 spe->data.update_data_addr.lo,
9889 bp->cnic_kwq_pending);
9891 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9892 bp->cnic_kwq_prod = bp->cnic_kwq;
9894 bp->cnic_kwq_prod++;
9897 spin_unlock_bh(&bp->spq_lock);
9899 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9900 bnx2x_cnic_sp_post(bp, 0);
9905 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9907 struct cnic_ops *c_ops;
9910 mutex_lock(&bp->cnic_mutex);
9911 c_ops = bp->cnic_ops;
9913 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9914 mutex_unlock(&bp->cnic_mutex);
9919 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9921 struct cnic_ops *c_ops;
9925 c_ops = rcu_dereference(bp->cnic_ops);
9927 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9934 * for commands that have no data
9936 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
9938 struct cnic_ctl_info ctl = {0};
9942 return bnx2x_cnic_ctl_send(bp, &ctl);
9945 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9947 struct cnic_ctl_info ctl;
9949 /* first we tell CNIC and only then we count this as a completion */
9950 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9951 ctl.data.comp.cid = cid;
9953 bnx2x_cnic_ctl_send_bh(bp, &ctl);
9954 bnx2x_cnic_sp_post(bp, 0);
9957 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9959 struct bnx2x *bp = netdev_priv(dev);
9963 case DRV_CTL_CTXTBL_WR_CMD: {
9964 u32 index = ctl->data.io.offset;
9965 dma_addr_t addr = ctl->data.io.dma_addr;
9967 bnx2x_ilt_wr(bp, index, addr);
9971 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
9972 int count = ctl->data.credit.credit_count;
9974 bnx2x_cnic_sp_post(bp, count);
9978 /* rtnl_lock is held. */
9979 case DRV_CTL_START_L2_CMD: {
9980 u32 cli = ctl->data.ring.client_id;
9982 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
9983 bnx2x_del_fcoe_eth_macs(bp);
9985 /* Set iSCSI MAC address */
9986 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
9991 /* Start accepting on iSCSI L2 ring. Accept all multicasts
9992 * because it's the only way for UIO Client to accept
9993 * multicasts (in non-promiscuous mode only one Client per
9994 * function will receive multicast packets (leading in our
9997 bnx2x_rxq_set_mac_filters(bp, cli,
9998 BNX2X_ACCEPT_UNICAST |
9999 BNX2X_ACCEPT_BROADCAST |
10000 BNX2X_ACCEPT_ALL_MULTICAST);
10001 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10006 /* rtnl_lock is held. */
10007 case DRV_CTL_STOP_L2_CMD: {
10008 u32 cli = ctl->data.ring.client_id;
10010 /* Stop accepting on iSCSI L2 ring */
10011 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10012 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10017 /* Unset iSCSI L2 MAC */
10018 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10021 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10022 int count = ctl->data.credit.credit_count;
10024 smp_mb__before_atomic_inc();
10025 atomic_add(count, &bp->spq_left);
10026 smp_mb__after_atomic_inc();
10031 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10038 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10040 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10042 if (bp->flags & USING_MSIX_FLAG) {
10043 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10044 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10045 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10047 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10048 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10050 if (CHIP_IS_E2(bp))
10051 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10053 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10055 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10056 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10057 cp->irq_arr[1].status_blk = bp->def_status_blk;
10058 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10059 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10064 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10067 struct bnx2x *bp = netdev_priv(dev);
10068 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10073 if (atomic_read(&bp->intr_sem) != 0)
10076 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10080 bp->cnic_kwq_cons = bp->cnic_kwq;
10081 bp->cnic_kwq_prod = bp->cnic_kwq;
10082 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10084 bp->cnic_spq_pending = 0;
10085 bp->cnic_kwq_pending = 0;
10087 bp->cnic_data = data;
10090 cp->drv_state = CNIC_DRV_STATE_REGD;
10091 cp->iro_arr = bp->iro_arr;
10093 bnx2x_setup_cnic_irq_info(bp);
10095 rcu_assign_pointer(bp->cnic_ops, ops);
10100 static int bnx2x_unregister_cnic(struct net_device *dev)
10102 struct bnx2x *bp = netdev_priv(dev);
10103 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10105 mutex_lock(&bp->cnic_mutex);
10107 rcu_assign_pointer(bp->cnic_ops, NULL);
10108 mutex_unlock(&bp->cnic_mutex);
10110 kfree(bp->cnic_kwq);
10111 bp->cnic_kwq = NULL;
10116 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10118 struct bnx2x *bp = netdev_priv(dev);
10119 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10121 cp->drv_owner = THIS_MODULE;
10122 cp->chip_id = CHIP_ID(bp);
10123 cp->pdev = bp->pdev;
10124 cp->io_base = bp->regview;
10125 cp->io_base2 = bp->doorbells;
10126 cp->max_kwqe_pending = 8;
10127 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10128 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10129 bnx2x_cid_ilt_lines(bp);
10130 cp->ctx_tbl_len = CNIC_ILT_LINES;
10131 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10132 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10133 cp->drv_ctl = bnx2x_drv_ctl;
10134 cp->drv_register_cnic = bnx2x_register_cnic;
10135 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10136 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10137 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10138 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10139 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10141 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10142 "starting cid %d\n",
10144 cp->ctx_tbl_offset,
10149 EXPORT_SYMBOL(bnx2x_cnic_probe);
10151 #endif /* BCM_CNIC */