2 * Driver for Blackfin On-Chip MAC device
4 * Copyright (c) 2005-2008 Analog Device, Inc.
6 * Licensed under the GPL-2 or later.
16 #include <linux/mii.h>
18 #include <asm/blackfin.h>
19 #include <asm/clock.h>
20 #include <asm/portmux.h>
21 #include <asm/mach-common/bits/dma.h>
22 #include <asm/mach-common/bits/emac.h>
23 #include <asm/mach-common/bits/pll.h>
27 #ifndef CONFIG_PHY_ADDR
28 # define CONFIG_PHY_ADDR 1
30 #ifndef CONFIG_PHY_CLOCK_FREQ
31 # define CONFIG_PHY_CLOCK_FREQ 2500000
38 #define RXBUF_BASE_ADDR 0xFF900000
39 #define TXBUF_BASE_ADDR 0xFF800000
42 #define TOUT_LOOP 1000000
44 static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
45 static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
46 static u16 txIdx; /* index of the current RX buffer */
47 static u16 rxIdx; /* index of the current TX buffer */
49 /* DMAx_CONFIG values at DMA Restart */
52 ADI_DMA_CONFIG_REG reg;
55 .b_DMA_EN = 1, /* enabled */
56 .b_WNR = 0, /* read from memory */
57 .b_WDSIZE = 2, /* wordsize is 32 bits */
61 .b_DI_EN = 0, /* no interrupt */
62 .b_NDSIZE = 5, /* 5 half words is desc size */
63 .b_FLOW = 7 /* large desc flow */
67 static int bfin_miiphy_wait(void)
69 /* poll the STABUSY bit */
70 while (bfin_read_EMAC_STAADD() & STABUSY)
75 static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
77 if (bfin_miiphy_wait())
79 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
80 if (bfin_miiphy_wait())
82 *val = bfin_read_EMAC_STADAT();
86 static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
88 if (bfin_miiphy_wait())
90 bfin_write_EMAC_STADAT(val);
91 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
95 int bfin_EMAC_initialize(bd_t *bis)
97 struct eth_device *dev;
98 dev = malloc(sizeof(*dev));
102 memset(dev, 0, sizeof(*dev));
103 strcpy(dev->name, "bfin_mac");
107 dev->init = bfin_EMAC_init;
108 dev->halt = bfin_EMAC_halt;
109 dev->send = bfin_EMAC_send;
110 dev->recv = bfin_EMAC_recv;
111 dev->write_hwaddr = bfin_EMAC_setup_addr;
115 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
116 miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
122 static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
128 printf("Ethernet: bad packet size: %d\n", length);
132 if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
133 printf("Ethernet: tx DMA error\n");
137 for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
139 puts("Ethernet: tx time out\n");
143 txbuf[txIdx]->FrmData->NoBytes = length;
144 memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
145 txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
146 bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
147 bfin_write_DMA2_CONFIG(txdmacfg.data);
148 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
150 for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
152 puts("Ethernet: tx error\n");
156 result = txbuf[txIdx]->StatusWord;
157 txbuf[txIdx]->StatusWord = 0;
158 if ((txIdx + 1) >= TX_BUF_CNT)
163 debug("BFIN EMAC send: length = %d\n", length);
167 static int bfin_EMAC_recv(struct eth_device *dev)
172 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
176 if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
177 printf("Ethernet: rx dma overrun\n");
180 if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
181 printf("Ethernet: rx error\n");
184 length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
186 printf("Ethernet: bad frame\n");
190 debug("%s: len = %d\n", __func__, length - 4);
192 net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
193 net_process_received_packet(net_rx_packets[rxIdx], length - 4);
194 bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
195 rxbuf[rxIdx]->StatusWord = 0x00000000;
196 if ((rxIdx + 1) >= PKTBUFSRX)
205 /**************************************************************
207 * Ethernet Initialization Routine
209 *************************************************************/
211 /* MDC = SCLK / MDC_freq / 2 - 1 */
212 #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
214 #ifndef CONFIG_BFIN_MAC_PINS
216 # define CONFIG_BFIN_MAC_PINS P_RMII0
218 # define CONFIG_BFIN_MAC_PINS P_MII0
222 static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
224 const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
228 /* Enable PHY output */
229 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
231 /* Set all the pins to peripheral mode */
232 peripheral_request_list(pins, "bfin_mac");
234 /* Odd word alignment for Receive Frame DMA word */
235 /* Configure checksum support and rcve frame word alignment */
236 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
238 /* turn on auto-negotiation and wait for link to come up */
239 bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
243 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
245 if (phydat & BMSR_LSTATUS)
248 printf("%s: link down, check cable\n", dev->name);
254 /* see what kind of link we have */
255 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
257 if (phydat & LPA_DUPLEX)
262 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
263 bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
264 bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
266 /* Initialize the TX DMA channel registers */
267 bfin_write_DMA2_X_COUNT(0);
268 bfin_write_DMA2_X_MODIFY(4);
269 bfin_write_DMA2_Y_COUNT(0);
270 bfin_write_DMA2_Y_MODIFY(0);
272 /* Initialize the RX DMA channel registers */
273 bfin_write_DMA1_X_COUNT(0);
274 bfin_write_DMA1_X_MODIFY(4);
275 bfin_write_DMA1_Y_COUNT(0);
276 bfin_write_DMA1_Y_MODIFY(0);
281 static int bfin_EMAC_setup_addr(struct eth_device *dev)
283 bfin_write_EMAC_ADDRLO(
285 dev->enetaddr[1] << 8 |
286 dev->enetaddr[2] << 16 |
287 dev->enetaddr[3] << 24
289 bfin_write_EMAC_ADDRHI(
291 dev->enetaddr[5] << 8
296 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
301 debug("Eth_init: ......\n");
306 /* Initialize System Register */
307 if (bfin_miiphy_init(dev, &dat) < 0)
310 /* Initialize EMAC address */
311 bfin_EMAC_setup_addr(dev);
313 /* Initialize TX and RX buffer */
314 for (i = 0; i < PKTBUFSRX; i++) {
315 rxbuf[i] = SetupRxBuffer(i);
317 rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
318 if (i == (PKTBUFSRX - 1))
319 rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
322 for (i = 0; i < TX_BUF_CNT; i++) {
323 txbuf[i] = SetupTxBuffer(i);
325 txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
326 if (i == (TX_BUF_CNT - 1))
327 txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
332 bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
333 bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
338 /* We enable only RX here */
339 /* ASTP : Enable Automatic Pad Stripping
340 PR : Promiscuous Mode for test
341 PSF : Receive frames with total length less than 64 bytes.
342 FDMODE : Full Duplex Mode
343 LB : Internal Loopback for test
344 RE : Receiver Enable */
346 opmode = ASTP | FDMODE | PSF;
353 /* Turn on the EMAC */
354 bfin_write_EMAC_OPMODE(opmode);
358 static void bfin_EMAC_halt(struct eth_device *dev)
360 debug("Eth_halt: ......\n");
361 /* Turn off the EMAC */
362 bfin_write_EMAC_OPMODE(0);
363 /* Turn off the EMAC RX DMA */
364 bfin_write_DMA1_CONFIG(0);
365 bfin_write_DMA2_CONFIG(0);
368 ADI_ETHER_BUFFER *SetupRxBuffer(int no)
370 ADI_ETHER_FRAME_BUFFER *frmbuf;
371 ADI_ETHER_BUFFER *buf;
372 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
373 int total_size = nobytes_buffer + RECV_BUFSIZE;
375 buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
376 frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
378 memset(buf, 0x00, nobytes_buffer);
379 buf->FrmData = frmbuf;
380 memset(frmbuf, 0xfe, RECV_BUFSIZE);
382 /* set up first desc to point to receive frame buffer */
383 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
384 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
385 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
386 buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
387 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
388 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
389 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
391 /* set up second desc to point to status word */
392 buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
393 buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
394 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
395 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
396 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
397 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
398 buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
399 buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
404 ADI_ETHER_BUFFER *SetupTxBuffer(int no)
406 ADI_ETHER_FRAME_BUFFER *frmbuf;
407 ADI_ETHER_BUFFER *buf;
408 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
409 int total_size = nobytes_buffer + RECV_BUFSIZE;
411 buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
412 frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
414 memset(buf, 0x00, nobytes_buffer);
415 buf->FrmData = frmbuf;
416 memset(frmbuf, 0x00, RECV_BUFSIZE);
418 /* set up first desc to point to receive frame buffer */
419 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
420 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
421 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
422 buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
423 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
424 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
425 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
427 /* set up second desc to point to status word */
428 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
429 buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
430 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
431 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
432 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
433 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
434 buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
435 buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
440 #if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
441 int ether_post_test(int flags)
448 printf("\n--------");
449 bfin_EMAC_init(NULL, NULL);
450 /* construct the package */
451 addr = bfin_read_EMAC_ADDRLO();
452 buf[0] = buf[6] = addr;
453 buf[1] = buf[7] = addr >> 8;
454 buf[2] = buf[8] = addr >> 16;
455 buf[3] = buf[9] = addr >> 24;
456 addr = bfin_read_EMAC_ADDRHI();
457 buf[4] = buf[10] = addr;
458 buf[5] = buf[11] = addr >> 8;
459 buf[12] = 0x08; /* Type: ARP */
461 buf[14] = 0x00; /* Hardware type: Ethernet */
463 buf[16] = 0x08; /* Protocal type: IP */
465 buf[18] = 0x06; /* Hardware size */
466 buf[19] = 0x04; /* Protocol size */
467 buf[20] = 0x00; /* Opcode: request */
470 for (i = 0; i < 42; i++)
472 printf("--------Send 64 bytes......\n");
473 bfin_EMAC_send(NULL, buf, 64);
474 for (i = 0; i < 100; i++) {
476 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
482 printf("--------EMAC can't receive any data\n");
486 length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
487 for (i = 0; i < length; i++) {
488 if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
489 printf("--------EMAC receive error data!\n");
494 printf("--------receive %d bytes, matched\n", length);
495 bfin_EMAC_halt(NULL);