2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
38 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
39 /* MPU semphore POST stage values */
40 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
41 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
42 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
43 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
45 /********* Memory BAR register ************/
46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
48 * Disable" may still globally block interrupts in addition to individual
49 * interrupt masks; a mechanism for the device driver to block all interrupts
50 * atomically without having to arbitrate for the PCI Interrupt Disable bit
53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
55 /********* Power managment (WOL) **********/
56 #define PCICFG_PM_CONTROL_OFFSET 0x44
57 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
59 /********* ISR0 Register offset **********/
60 #define CEV_ISR0_OFFSET 0xC18
61 #define CEV_ISR_SIZE 4
63 /********* Event Q door bell *************/
64 #define DB_EQ_OFFSET DB_CQ_OFFSET
65 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
66 /* Clear the interrupt for this eq */
67 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
69 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
70 /* Number of event entries processed */
71 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
73 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
75 /********* Compl Q door bell *************/
76 #define DB_CQ_OFFSET 0x120
77 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
78 /* Number of event entries processed */
79 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
81 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
83 /********** TX ULP door bell *************/
84 #define DB_TXULP1_OFFSET 0x60
85 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
86 /* Number of tx entries posted */
87 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
88 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
90 /********** RQ(erx) door bell ************/
91 #define DB_RQ_OFFSET 0x100
92 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
93 /* Number of rx frags posted */
94 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
96 /********** MCC door bell ************/
97 #define DB_MCCQ_OFFSET 0x140
98 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
99 /* Number of entries posted */
100 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
102 /* Flashrom related descriptors */
103 #define IMAGE_TYPE_FIRMWARE 160
104 #define IMAGE_TYPE_BOOTCODE 224
105 #define IMAGE_TYPE_OPTIONROM 32
107 #define NUM_FLASHDIR_ENTRIES 32
109 #define IMG_TYPE_ISCSI_ACTIVE 0
110 #define IMG_TYPE_REDBOOT 1
111 #define IMG_TYPE_BIOS 2
112 #define IMG_TYPE_PXE_BIOS 3
113 #define IMG_TYPE_FCOE_BIOS 8
114 #define IMG_TYPE_ISCSI_BACKUP 9
115 #define IMG_TYPE_FCOE_FW_ACTIVE 10
116 #define IMG_TYPE_FCOE_FW_BACKUP 11
117 #define IMG_TYPE_NCSI_BITFILE 13
118 #define IMG_TYPE_NCSI_8051 14
120 #define FLASHROM_OPER_FLASH 1
121 #define FLASHROM_OPER_SAVE 2
122 #define FLASHROM_OPER_REPORT 4
124 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */
125 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */
126 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
127 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */
128 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */
129 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
131 #define FLASH_NCSI_MAGIC (0x16032009)
132 #define FLASH_NCSI_DISABLED (0)
133 #define FLASH_NCSI_ENABLED (1)
135 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
137 /* Offsets for components on Flash. */
138 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
139 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
140 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
141 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
142 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
143 #define FLASH_PXE_BIOS_START_g2 (7864320)
144 #define FLASH_FCoE_BIOS_START_g2 (524288)
145 #define FLASH_REDBOOT_START_g2 (0)
147 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
148 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
149 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
150 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
151 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
152 #define FLASH_PXE_BIOS_START_g3 (13107200)
153 #define FLASH_FCoE_BIOS_START_g3 (13631488)
154 #define FLASH_REDBOOT_START_g3 (262144)
160 * BE descriptors: host memory data structures whose formats
161 * are hardwired in BE silicon.
163 /* Event Queue Descriptor */
164 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
165 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
166 #define EQ_ENTRY_RES_ID_SHIFT 16
172 /* TX Queue Descriptor */
173 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
175 u32 frag_pa_hi; /* dword 0 */
176 u32 frag_pa_lo; /* dword 1 */
177 u32 rsvd0; /* dword 2 */
178 u32 frag_len; /* dword 3: bits 0 - 15 */
181 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
182 * actual structure is defined as a byte : used to calculate
183 * offset/shift/mask of each field */
184 struct amap_eth_hdr_wrb {
185 u8 rsvd0[32]; /* dword 0 */
186 u8 rsvd1[32]; /* dword 1 */
187 u8 complete; /* dword 2 */
201 u8 len[16]; /* dword 3 */
205 struct be_eth_hdr_wrb {
209 /* TX Compl Queue Descriptor */
211 /* Pseudo amap definition for eth_tx_compl in which each bit of the
212 * actual structure is defined as a byte: used to calculate
213 * offset/shift/mask of each field */
214 struct amap_eth_tx_compl {
215 u8 wrb_index[16]; /* dword 0 */
216 u8 ct[2]; /* dword 0 */
217 u8 port[2]; /* dword 0 */
218 u8 rsvd0[8]; /* dword 0 */
219 u8 status[4]; /* dword 0 */
220 u8 user_bytes[16]; /* dword 1 */
221 u8 nwh_bytes[8]; /* dword 1 */
222 u8 lso; /* dword 1 */
223 u8 cast_enc[2]; /* dword 1 */
224 u8 rsvd1[5]; /* dword 1 */
225 u8 rsvd2[32]; /* dword 2 */
226 u8 pkts[16]; /* dword 3 */
227 u8 ringid[11]; /* dword 3 */
228 u8 hash_val[4]; /* dword 3 */
229 u8 valid; /* dword 3 */
232 struct be_eth_tx_compl {
236 /* RX Queue Descriptor */
242 /* RX Compl Queue Descriptor */
244 /* Pseudo amap definition for eth_rx_compl in which each bit of the
245 * actual structure is defined as a byte: used to calculate
246 * offset/shift/mask of each field */
247 struct amap_eth_rx_compl {
248 u8 vlan_tag[16]; /* dword 0 */
249 u8 pktsize[14]; /* dword 0 */
250 u8 port; /* dword 0 */
251 u8 ip_opt; /* dword 0 */
252 u8 err; /* dword 1 */
253 u8 rsshp; /* dword 1 */
254 u8 ipf; /* dword 1 */
255 u8 tcpf; /* dword 1 */
256 u8 udpf; /* dword 1 */
257 u8 ipcksm; /* dword 1 */
258 u8 l4_cksm; /* dword 1 */
259 u8 ip_version; /* dword 1 */
260 u8 macdst[6]; /* dword 1 */
261 u8 vtp; /* dword 1 */
262 u8 rsvd0; /* dword 1 */
263 u8 fragndx[10]; /* dword 1 */
264 u8 ct[2]; /* dword 1 */
266 u8 numfrags[3]; /* dword 1 */
267 u8 rss_flush; /* dword 2 */
268 u8 cast_enc[2]; /* dword 2 */
269 u8 vtm; /* dword 2 */
270 u8 rss_bank; /* dword 2 */
271 u8 rsvd1[23]; /* dword 2 */
272 u8 lro_pkt; /* dword 2 */
273 u8 rsvd2[2]; /* dword 2 */
274 u8 valid; /* dword 2 */
275 u8 rsshash[32]; /* dword 3 */
278 struct be_eth_rx_compl {
282 struct controller_id {
290 unsigned long offset;
300 u8 image_version[32];
302 struct flash_file_hdr_g2 {
306 struct controller_id cont_id;
314 struct flash_file_hdr_g3 {
325 struct flash_section_hdr {
331 u32 active_entry_mask;
332 u32 valid_entry_mask;
333 u32 org_content_mask;
341 struct flash_section_entry {
353 struct flash_section_info {
355 struct flash_section_hdr fsec_hdr;
356 struct flash_section_entry fsec_entry[32];