net: bcmgenet: move PHY initialization from probe() to start()
[platform/kernel/u-boot.git] / drivers / net / bcmgenet.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com>
4  *
5  * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4)
6  * This driver is based on the Linux driver:
7  *      drivers/net/ethernet/broadcom/genet/bcmgenet.c
8  *      which is: Copyright (c) 2014-2017 Broadcom
9  *
10  * The hardware supports multiple queues (16 priority queues and one
11  * default queue), both for RX and TX. There are 256 DMA descriptors (both
12  * for TX and RX), and they live in MMIO registers. The hardware allows
13  * assigning descriptor ranges to queues, but we choose the most simple setup:
14  * All 256 descriptors are assigned to the default queue (#16).
15  * Also the Linux driver supports multiple generations of the MAC, whereas
16  * we only support v5, as used in the Raspberry Pi 4.
17  */
18
19 #include <asm/io.h>
20 #include <clk.h>
21 #include <cpu_func.h>
22 #include <dm.h>
23 #include <fdt_support.h>
24 #include <linux/err.h>
25 #include <malloc.h>
26 #include <miiphy.h>
27 #include <net.h>
28 #include <dm/of_access.h>
29 #include <dm/ofnode.h>
30 #include <linux/iopoll.h>
31 #include <linux/sizes.h>
32 #include <asm/dma-mapping.h>
33 #include <wait_bit.h>
34
35 /* Register definitions derived from Linux source */
36 #define SYS_REV_CTRL                    0x00
37
38 #define SYS_PORT_CTRL                   0x04
39 #define PORT_MODE_EXT_GPHY              3
40
41 #define GENET_SYS_OFF                   0x0000
42 #define SYS_RBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x08)
43 #define SYS_TBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x0c)
44
45 #define GENET_EXT_OFF                   0x0080
46 #define EXT_RGMII_OOB_CTRL              (GENET_EXT_OFF + 0x0c)
47 #define RGMII_LINK                      BIT(4)
48 #define OOB_DISABLE                     BIT(5)
49 #define RGMII_MODE_EN                   BIT(6)
50 #define ID_MODE_DIS                     BIT(16)
51
52 #define GENET_RBUF_OFF                  0x0300
53 #define RBUF_TBUF_SIZE_CTRL             (GENET_RBUF_OFF + 0xb4)
54 #define RBUF_CTRL                       (GENET_RBUF_OFF + 0x00)
55 #define RBUF_ALIGN_2B                   BIT(1)
56
57 #define GENET_UMAC_OFF                  0x0800
58 #define UMAC_MIB_CTRL                   (GENET_UMAC_OFF + 0x580)
59 #define UMAC_MAX_FRAME_LEN              (GENET_UMAC_OFF + 0x014)
60 #define UMAC_MAC0                       (GENET_UMAC_OFF + 0x00c)
61 #define UMAC_MAC1                       (GENET_UMAC_OFF + 0x010)
62 #define UMAC_CMD                        (GENET_UMAC_OFF + 0x008)
63 #define MDIO_CMD                        (GENET_UMAC_OFF + 0x614)
64 #define UMAC_TX_FLUSH                   (GENET_UMAC_OFF + 0x334)
65 #define MDIO_START_BUSY                 BIT(29)
66 #define MDIO_READ_FAIL                  BIT(28)
67 #define MDIO_RD                         (2 << 26)
68 #define MDIO_WR                         BIT(26)
69 #define MDIO_PMD_SHIFT                  21
70 #define MDIO_PMD_MASK                   0x1f
71 #define MDIO_REG_SHIFT                  16
72 #define MDIO_REG_MASK                   0x1f
73
74 #define CMD_TX_EN                       BIT(0)
75 #define CMD_RX_EN                       BIT(1)
76 #define UMAC_SPEED_10                   0
77 #define UMAC_SPEED_100                  1
78 #define UMAC_SPEED_1000                 2
79 #define UMAC_SPEED_2500                 3
80 #define CMD_SPEED_SHIFT                 2
81 #define CMD_SPEED_MASK                  3
82 #define CMD_SW_RESET                    BIT(13)
83 #define CMD_LCL_LOOP_EN                 BIT(15)
84 #define CMD_TX_EN                       BIT(0)
85 #define CMD_RX_EN                       BIT(1)
86
87 #define MIB_RESET_RX                    BIT(0)
88 #define MIB_RESET_RUNT                  BIT(1)
89 #define MIB_RESET_TX                    BIT(2)
90
91 /* total number of Buffer Descriptors, same for Rx/Tx */
92 #define TOTAL_DESCS                     256
93 #define RX_DESCS                        TOTAL_DESCS
94 #define TX_DESCS                        TOTAL_DESCS
95
96 #define DEFAULT_Q                       0x10
97
98 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
99  * 1536 is multiple of 256 bytes
100  */
101 #define ENET_BRCM_TAG_LEN               6
102 #define ENET_PAD                        8
103 #define ENET_MAX_MTU_SIZE               (ETH_DATA_LEN + ETH_HLEN +       \
104                                          VLAN_HLEN + ENET_BRCM_TAG_LEN + \
105                                          ETH_FCS_LEN + ENET_PAD)
106
107 /* Tx/Rx Dma Descriptor common bits */
108 #define DMA_EN                          BIT(0)
109 #define DMA_RING_BUF_EN_SHIFT           0x01
110 #define DMA_RING_BUF_EN_MASK            0xffff
111 #define DMA_BUFLENGTH_MASK              0x0fff
112 #define DMA_BUFLENGTH_SHIFT             16
113 #define DMA_RING_SIZE_SHIFT             16
114 #define DMA_OWN                         0x8000
115 #define DMA_EOP                         0x4000
116 #define DMA_SOP                         0x2000
117 #define DMA_WRAP                        0x1000
118 #define DMA_MAX_BURST_LENGTH            0x8
119 /* Tx specific DMA descriptor bits */
120 #define DMA_TX_UNDERRUN                 0x0200
121 #define DMA_TX_APPEND_CRC               0x0040
122 #define DMA_TX_OW_CRC                   0x0020
123 #define DMA_TX_DO_CSUM                  0x0010
124 #define DMA_TX_QTAG_SHIFT               7
125
126 /* DMA rings size */
127 #define DMA_RING_SIZE                   0x40
128 #define DMA_RINGS_SIZE                  (DMA_RING_SIZE * (DEFAULT_Q + 1))
129
130 /* DMA descriptor */
131 #define DMA_DESC_LENGTH_STATUS          0x00
132 #define DMA_DESC_ADDRESS_LO             0x04
133 #define DMA_DESC_ADDRESS_HI             0x08
134 #define DMA_DESC_SIZE                   12
135
136 #define GENET_RX_OFF                    0x2000
137 #define GENET_RDMA_REG_OFF                                      \
138         (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
139 #define GENET_TX_OFF                    0x4000
140 #define GENET_TDMA_REG_OFF                                      \
141         (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
142
143 #define DMA_FC_THRESH_HI                (RX_DESCS >> 4)
144 #define DMA_FC_THRESH_LO                5
145 #define DMA_FC_THRESH_VALUE             ((DMA_FC_THRESH_LO << 16) |     \
146                                           DMA_FC_THRESH_HI)
147
148 #define DMA_XOFF_THRESHOLD_SHIFT        16
149
150 #define TDMA_RING_REG_BASE                                      \
151         (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
152 #define TDMA_READ_PTR                   (TDMA_RING_REG_BASE + 0x00)
153 #define TDMA_CONS_INDEX                 (TDMA_RING_REG_BASE + 0x08)
154 #define TDMA_PROD_INDEX                 (TDMA_RING_REG_BASE + 0x0c)
155 #define DMA_RING_BUF_SIZE               0x10
156 #define DMA_START_ADDR                  0x14
157 #define DMA_END_ADDR                    0x1c
158 #define DMA_MBUF_DONE_THRESH            0x24
159 #define TDMA_FLOW_PERIOD                (TDMA_RING_REG_BASE + 0x28)
160 #define TDMA_WRITE_PTR                  (TDMA_RING_REG_BASE + 0x2c)
161
162 #define RDMA_RING_REG_BASE                                      \
163         (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
164 #define RDMA_WRITE_PTR                  (RDMA_RING_REG_BASE + 0x00)
165 #define RDMA_PROD_INDEX                 (RDMA_RING_REG_BASE + 0x08)
166 #define RDMA_CONS_INDEX                 (RDMA_RING_REG_BASE + 0x0c)
167 #define RDMA_XON_XOFF_THRESH            (RDMA_RING_REG_BASE + 0x28)
168 #define RDMA_READ_PTR                   (RDMA_RING_REG_BASE + 0x2c)
169
170 #define TDMA_REG_BASE                   (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
171 #define RDMA_REG_BASE                   (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
172 #define DMA_RING_CFG                    0x00
173 #define DMA_CTRL                        0x04
174 #define DMA_SCB_BURST_SIZE              0x0c
175
176 #define RX_BUF_LENGTH                   2048
177 #define RX_TOTAL_BUFSIZE                (RX_BUF_LENGTH * RX_DESCS)
178 #define RX_BUF_OFFSET                   2
179
180 struct bcmgenet_eth_priv {
181         char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
182         void *mac_reg;
183         void *tx_desc_base;
184         void *rx_desc_base;
185         int tx_index;
186         int rx_index;
187         int c_index;
188         int phyaddr;
189         u32 interface;
190         u32 speed;
191         struct phy_device *phydev;
192         struct mii_dev *bus;
193 };
194
195 static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv)
196 {
197         u32 reg;
198
199         reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
200         reg |= BIT(1);
201         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
202         udelay(10);
203
204         reg &= ~BIT(1);
205         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
206         udelay(10);
207
208         writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
209         udelay(10);
210
211         writel(0, priv->mac_reg + UMAC_CMD);
212
213         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
214         udelay(2);
215         writel(0, priv->mac_reg + UMAC_CMD);
216
217         /* clear tx/rx counter */
218         writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
219                priv->mac_reg + UMAC_MIB_CTRL);
220         writel(0, priv->mac_reg + UMAC_MIB_CTRL);
221
222         writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN);
223
224         /* init rx registers, enable ip header optimization */
225         reg = readl(priv->mac_reg + RBUF_CTRL);
226         reg |= RBUF_ALIGN_2B;
227         writel(reg, (priv->mac_reg + RBUF_CTRL));
228
229         writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL));
230 }
231
232 static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
233 {
234         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
235         struct eth_pdata *pdata = dev_get_platdata(dev);
236         uchar *addr = pdata->enetaddr;
237         u32 reg;
238
239         reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
240         writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
241
242         reg = addr[4] << 8 | addr[5];
243         writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
244
245         return 0;
246 }
247
248 static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv)
249 {
250         clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN);
251         clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN);
252
253         writel(1, priv->mac_reg + UMAC_TX_FLUSH);
254         udelay(10);
255         writel(0, priv->mac_reg + UMAC_TX_FLUSH);
256 }
257
258 static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv)
259 {
260         u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
261
262         writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL);
263
264         setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl);
265 }
266
267 static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length)
268 {
269         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
270         void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE;
271         u32 len_stat = length << DMA_BUFLENGTH_SHIFT;
272         ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN);
273         u32 prod_index, cons;
274         u32 tries = 100;
275
276         prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX);
277
278         /* There is actually no reason for the rounding here, but the ARMv7
279          * implementation of flush_dcache_range() checks for aligned
280          * boundaries of the flushed range.
281          * Adjust them here to pass that check and avoid misleading messages.
282          */
283         flush_dcache_range(packet_aligned,
284                            packet_aligned + roundup(length, ARCH_DMA_MINALIGN));
285
286         len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
287         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
288
289         /* Set-up packet for transmission */
290         writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO));
291         writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI));
292         writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS));
293
294         /* Increment index and start transmission */
295         if (++priv->tx_index >= TX_DESCS)
296                 priv->tx_index = 0;
297
298         prod_index++;
299
300         /* Start Transmisson */
301         writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX);
302
303         do {
304                 cons = readl(priv->mac_reg + TDMA_CONS_INDEX);
305         } while ((cons & 0xffff) < prod_index && --tries);
306         if (!tries)
307                 return -ETIMEDOUT;
308
309         return 0;
310 }
311
312 /* Check whether all cache lines affected by an invalidate are within
313  * the buffer, to make sure we don't accidentally lose unrelated dirty
314  * data stored nearby.
315  * Alignment of the buffer start address will be checked in the implementation
316  * of invalidate_dcache_range().
317  */
318 static void invalidate_dcache_check(unsigned long addr, size_t size,
319                                     size_t buffer_size)
320 {
321         size_t inval_size = roundup(size, ARCH_DMA_MINALIGN);
322
323         if (unlikely(inval_size > buffer_size))
324                 printf("WARNING: Cache invalidate area exceeds buffer size\n");
325
326         invalidate_dcache_range(addr, addr + inval_size);
327 }
328
329 static int bcmgenet_gmac_eth_recv(struct udevice *dev,
330                                   int flags, uchar **packetp)
331 {
332         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
333         void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
334         u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
335         u32 length, addr;
336
337         if (prod_index == priv->c_index)
338                 return -EAGAIN;
339
340         length = readl(desc_base + DMA_DESC_LENGTH_STATUS);
341         length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
342         addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
343
344         invalidate_dcache_check(addr, length, RX_BUF_LENGTH);
345
346         /* To cater for the IP header alignment the hardware does.
347          * This would actually not be needed if we don't program
348          * RBUF_ALIGN_2B
349          */
350         *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET;
351
352         return length - RX_BUF_OFFSET;
353 }
354
355 static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet,
356                                   int length)
357 {
358         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
359
360         /* Tell the MAC we have consumed that last receive buffer. */
361         priv->c_index = (priv->c_index + 1) & 0xFFFF;
362         writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
363
364         /* Forward our descriptor pointer, wrapping around if needed. */
365         if (++priv->rx_index >= RX_DESCS)
366                 priv->rx_index = 0;
367
368         return 0;
369 }
370
371 static void rx_descs_init(struct bcmgenet_eth_priv *priv)
372 {
373         char *rxbuffs = &priv->rxbuffer[0];
374         u32 len_stat, i;
375         void *desc_base = priv->rx_desc_base;
376
377         priv->c_index = 0;
378
379         len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
380
381         for (i = 0; i < RX_DESCS; i++) {
382                 writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
383                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO);
384                 writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
385                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI);
386                 writel(len_stat,
387                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS);
388         }
389 }
390
391 static void rx_ring_init(struct bcmgenet_eth_priv *priv)
392 {
393         writel(DMA_MAX_BURST_LENGTH,
394                priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE);
395
396         writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR);
397         writel(0x0, priv->mac_reg + RDMA_READ_PTR);
398         writel(0x0, priv->mac_reg + RDMA_WRITE_PTR);
399         writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
400                priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
401
402         writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
403         writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
404         writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
405                priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
406         writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
407         writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG);
408 }
409
410 static void tx_ring_init(struct bcmgenet_eth_priv *priv)
411 {
412         writel(DMA_MAX_BURST_LENGTH,
413                priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE);
414
415         writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR);
416         writel(0x0, priv->mac_reg + TDMA_READ_PTR);
417         writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
418         writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
419                priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
420         writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
421         writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
422         writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
423         writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
424         writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
425                priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
426
427         writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG);
428 }
429
430 static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv)
431 {
432         struct phy_device *phy_dev = priv->phydev;
433         u32 speed;
434
435         switch (phy_dev->speed) {
436         case SPEED_1000:
437                 speed = UMAC_SPEED_1000;
438                 break;
439         case SPEED_100:
440                 speed = UMAC_SPEED_100;
441                 break;
442         case SPEED_10:
443                 speed = UMAC_SPEED_10;
444                 break;
445         default:
446                 printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed);
447                 return -EINVAL;
448         }
449
450         clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
451                         RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
452
453         writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
454
455         return 0;
456 }
457
458 static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev);
459
460 static int bcmgenet_gmac_eth_start(struct udevice *dev)
461 {
462         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
463         int ret;
464
465         ret = bcmgenet_phy_init(priv, dev);
466         if (ret)
467                 return ret;
468
469         priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
470         priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
471         priv->tx_index = 0x0;
472         priv->rx_index = 0x0;
473
474         bcmgenet_umac_reset(priv);
475
476         bcmgenet_gmac_write_hwaddr(dev);
477
478         /* Disable RX/TX DMA and flush TX queues */
479         bcmgenet_disable_dma(priv);
480
481         rx_ring_init(priv);
482         rx_descs_init(priv);
483
484         tx_ring_init(priv);
485
486         /* Enable RX/TX DMA */
487         bcmgenet_enable_dma(priv);
488
489         /* read PHY properties over the wire from generic PHY set-up */
490         ret = phy_startup(priv->phydev);
491         if (ret) {
492                 printf("bcmgenet: PHY startup failed: %d\n", ret);
493                 return ret;
494         }
495
496         /* Update MAC registers based on PHY property */
497         ret = bcmgenet_adjust_link(priv);
498         if (ret) {
499                 printf("bcmgenet: adjust PHY link failed: %d\n", ret);
500                 return ret;
501         }
502
503         /* Enable Rx/Tx */
504         setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
505
506         return 0;
507 }
508
509 static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev)
510 {
511         struct phy_device *phydev;
512         int ret;
513
514         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
515         if (!phydev)
516                 return -ENODEV;
517
518         phydev->supported &= PHY_GBIT_FEATURES;
519         if (priv->speed) {
520                 ret = phy_set_supported(priv->phydev, priv->speed);
521                 if (ret)
522                         return ret;
523         }
524         phydev->advertising = phydev->supported;
525
526         phy_connect_dev(phydev, dev);
527
528         priv->phydev = phydev;
529         phy_config(priv->phydev);
530
531         return 0;
532 }
533
534 static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv)
535 {
536         setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY);
537 }
538
539 static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad,
540                                int reg, u16 value)
541 {
542         struct udevice *dev = bus->priv;
543         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
544         u32 val;
545
546         /* Prepare the read operation */
547         val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |
548                 (reg << MDIO_REG_SHIFT) | (0xffff & value);
549         writel_relaxed(val,  priv->mac_reg + MDIO_CMD);
550
551         /* Start MDIO transaction */
552         bcmgenet_mdio_start(priv);
553
554         return wait_for_bit_32(priv->mac_reg + MDIO_CMD,
555                                MDIO_START_BUSY, false, 20, true);
556 }
557
558 static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
559 {
560         struct udevice *dev = bus->priv;
561         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
562         u32 val;
563         int ret;
564
565         /* Prepare the read operation */
566         val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
567         writel_relaxed(val, priv->mac_reg + MDIO_CMD);
568
569         /* Start MDIO transaction */
570         bcmgenet_mdio_start(priv);
571
572         ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD,
573                               MDIO_START_BUSY, false, 20, true);
574         if (ret)
575                 return ret;
576
577         val = readl_relaxed(priv->mac_reg + MDIO_CMD);
578
579         return val & 0xffff;
580 }
581
582 static int bcmgenet_mdio_init(const char *name, struct udevice *priv)
583 {
584         struct mii_dev *bus = mdio_alloc();
585
586         if (!bus) {
587                 debug("Failed to allocate MDIO bus\n");
588                 return -ENOMEM;
589         }
590
591         bus->read = bcmgenet_mdio_read;
592         bus->write = bcmgenet_mdio_write;
593         snprintf(bus->name, sizeof(bus->name), name);
594         bus->priv = (void *)priv;
595
596         return mdio_register(bus);
597 }
598
599 /* We only support RGMII (as used on the RPi4). */
600 static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv)
601 {
602         phy_interface_t phy_mode = priv->interface;
603
604         switch (phy_mode) {
605         case PHY_INTERFACE_MODE_RGMII:
606         case PHY_INTERFACE_MODE_RGMII_RXID:
607                 writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL);
608                 break;
609         default:
610                 printf("unknown phy mode: %d\n", priv->interface);
611                 return -EINVAL;
612         }
613
614         return 0;
615 }
616
617 static int bcmgenet_eth_probe(struct udevice *dev)
618 {
619         struct eth_pdata *pdata = dev_get_platdata(dev);
620         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
621         ofnode mdio_node;
622         const char *name;
623         u32 reg;
624         int ret;
625         u8 major;
626
627         priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE);
628         priv->interface = pdata->phy_interface;
629         priv->speed = pdata->max_speed;
630
631         /* Read GENET HW version */
632         reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL);
633         major = (reg >> 24) & 0x0f;
634         if (major != 6) {
635                 if (major == 5)
636                         major = 4;
637                 else if (major == 0)
638                         major = 1;
639
640                 printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f);
641                 return -ENODEV;
642         }
643
644         ret = bcmgenet_interface_set(priv);
645         if (ret)
646                 return ret;
647
648         writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
649         udelay(10);
650         /* disable MAC while updating its registers */
651         writel(0, priv->mac_reg + UMAC_CMD);
652         /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
653         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
654
655         mdio_node = dev_read_first_subnode(dev);
656         name = ofnode_get_name(mdio_node);
657
658         ret = bcmgenet_mdio_init(name, dev);
659         if (ret)
660                 return ret;
661
662         priv->bus = miiphy_get_dev_by_name(name);
663
664         return 0;
665 }
666
667 static void bcmgenet_gmac_eth_stop(struct udevice *dev)
668 {
669         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
670
671         clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
672
673         bcmgenet_disable_dma(priv);
674 }
675
676 static const struct eth_ops bcmgenet_gmac_eth_ops = {
677         .start                  = bcmgenet_gmac_eth_start,
678         .write_hwaddr           = bcmgenet_gmac_write_hwaddr,
679         .send                   = bcmgenet_gmac_eth_send,
680         .recv                   = bcmgenet_gmac_eth_recv,
681         .free_pkt               = bcmgenet_gmac_free_pkt,
682         .stop                   = bcmgenet_gmac_eth_stop,
683 };
684
685 static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
686 {
687         struct eth_pdata *pdata = dev_get_platdata(dev);
688         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
689         struct ofnode_phandle_args phy_node;
690         const char *phy_mode;
691         int ret;
692
693         pdata->iobase = dev_read_addr(dev);
694
695         /* Get phy mode from DT */
696         pdata->phy_interface = -1;
697         phy_mode = dev_read_string(dev, "phy-mode");
698         if (phy_mode)
699                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
700         if (pdata->phy_interface == -1) {
701                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
702                 return -EINVAL;
703         }
704
705         ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
706                                          &phy_node);
707         if (!ret) {
708                 ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr);
709                 ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed);
710         }
711
712         return 0;
713 }
714
715 /* The BCM2711 implementation has a limited burst length compared to a generic
716  * GENETv5 version, but we go with that shorter value (8) in both cases, for
717  * the sake of simplicity.
718  */
719 static const struct udevice_id bcmgenet_eth_ids[] = {
720         {.compatible = "brcm,genet-v5"},
721         {.compatible = "brcm,bcm2711-genet-v5"},
722         {}
723 };
724
725 U_BOOT_DRIVER(eth_bcmgenet) = {
726         .name   = "eth_bcmgenet",
727         .id     = UCLASS_ETH,
728         .of_match = bcmgenet_eth_ids,
729         .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
730         .probe  = bcmgenet_eth_probe,
731         .ops    = &bcmgenet_gmac_eth_ops,
732         .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
733         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
734         .flags = DM_FLAG_ALLOC_PRIV_DMA,
735 };