1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
19 #include <dm/device_compat.h>
21 #define ETH_PORT_STR "brcm,enetsw-port"
23 #define ETH_RX_DESC PKTBUFSRX
25 #define ETH_TIMEOUT 100
27 #define ETH_MAX_PORT 8
28 #define ETH_RGMII_PORT0 4
30 /* Port traffic control */
31 #define ETH_PTCTRL_REG(x) (0x0 + (x))
32 #define ETH_PTCTRL_RXDIS_SHIFT 0
33 #define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT)
34 #define ETH_PTCTRL_TXDIS_SHIFT 1
35 #define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT)
37 /* Switch mode register */
38 #define ETH_SWMODE_REG 0xb
39 #define ETH_SWMODE_FWD_EN_SHIFT 1
40 #define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT)
42 /* IMP override Register */
43 #define ETH_IMPOV_REG 0xe
44 #define ETH_IMPOV_LINKUP_SHIFT 0
45 #define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT)
46 #define ETH_IMPOV_FDX_SHIFT 1
47 #define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT)
48 #define ETH_IMPOV_100_SHIFT 2
49 #define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT)
50 #define ETH_IMPOV_1000_SHIFT 3
51 #define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT)
52 #define ETH_IMPOV_RXFLOW_SHIFT 4
53 #define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT)
54 #define ETH_IMPOV_TXFLOW_SHIFT 5
55 #define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT)
56 #define ETH_IMPOV_FORCE_SHIFT 7
57 #define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT)
59 /* Port override Register */
60 #define ETH_PORTOV_REG(x) (0x58 + (x))
61 #define ETH_PORTOV_LINKUP_SHIFT 0
62 #define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT)
63 #define ETH_PORTOV_FDX_SHIFT 1
64 #define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT)
65 #define ETH_PORTOV_100_SHIFT 2
66 #define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT)
67 #define ETH_PORTOV_1000_SHIFT 3
68 #define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT)
69 #define ETH_PORTOV_RXFLOW_SHIFT 4
70 #define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT)
71 #define ETH_PORTOV_TXFLOW_SHIFT 5
72 #define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT)
73 #define ETH_PORTOV_ENABLE_SHIFT 6
74 #define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT)
76 /* Port RGMII control register */
77 #define ETH_RGMII_CTRL_REG(x) (0x60 + (x))
78 #define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7)
79 #define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
80 #define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4)
81 #define ETH_RGMII_CTRL_RGMII_MODE (0 << 4)
82 #define ETH_RGMII_CTRL_MII_MODE (1 << 4)
83 #define ETH_RGMII_CTRL_RVMII_MODE (2 << 4)
84 #define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0)
86 /* Port RGMII timing register */
87 #define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x))
89 /* MDIO control register */
90 #define MII_SC_REG 0xb0
91 #define MII_SC_EXT_SHIFT 16
92 #define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT)
93 #define MII_SC_REG_SHIFT 20
94 #define MII_SC_PHYID_SHIFT 25
95 #define MII_SC_RD_SHIFT 30
96 #define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT)
97 #define MII_SC_WR_SHIFT 31
98 #define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT)
100 /* MDIO data register */
101 #define MII_DAT_REG 0xb4
103 /* Global Management Configuration Register */
104 #define ETH_GMCR_REG 0x200
105 #define ETH_GMCR_RST_MIB_SHIFT 0
106 #define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT)
108 /* Jumbo control register port mask register */
109 #define ETH_JMBCTL_PORT_REG 0x4004
111 /* Jumbo control mib good frame register */
112 #define ETH_JMBCTL_MAXSIZE_REG 0x4008
115 struct bcm_enetsw_port {
121 bool force_duplex_full;
127 struct bcm6368_eth_priv {
134 struct bcm_enetsw_port used_ports[ETH_MAX_PORT];
135 int sw_port_link[ETH_MAX_PORT];
142 static inline bool bcm_enet_port_is_rgmii(int portid)
144 return portid >= ETH_RGMII_PORT0;
147 static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext,
152 writel_be(0, priv->base + MII_SC_REG);
154 val = MII_SC_RD_MASK |
155 (phy_id << MII_SC_PHYID_SHIFT) |
156 (reg << MII_SC_REG_SHIFT);
159 val |= MII_SC_EXT_MASK;
161 writel_be(val, priv->base + MII_SC_REG);
164 return readw_be(priv->base + MII_DAT_REG);
167 static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext,
168 int phy_id, int reg, u16 data)
172 writel_be(0, priv->base + MII_SC_REG);
174 val = MII_SC_WR_MASK |
175 (phy_id << MII_SC_PHYID_SHIFT) |
176 (reg << MII_SC_REG_SHIFT);
179 val |= MII_SC_EXT_MASK;
183 writel_be(val, priv->base + MII_SC_REG);
189 static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
191 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
193 return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
196 static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp)
198 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
200 return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
203 static int bcm6368_eth_send(struct udevice *dev, void *packet, int length)
205 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
207 /* pad packets smaller than ETH_ZLEN */
208 if (length < ETH_ZLEN) {
209 memset(packet + length, 0, ETH_ZLEN - length);
213 return dma_send(&priv->tx_dma, packet, length, NULL);
216 static int bcm6368_eth_adjust_link(struct udevice *dev)
218 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
221 for (i = 0; i < priv->num_ports; i++) {
222 struct bcm_enetsw_port *port;
223 int val, j, up, adv, lpa, speed, duplex, media;
224 int external_phy = bcm_enet_port_is_rgmii(i);
227 port = &priv->used_ports[i];
231 if (port->bypass_link)
234 /* dummy read to clear */
235 for (j = 0; j < 2; j++)
236 val = bcm6368_mdio_read(priv, external_phy,
237 port->phy_id, MII_BMSR);
242 up = (val & BMSR_LSTATUS) ? 1 : 0;
243 if (!(up ^ priv->sw_port_link[i]))
246 priv->sw_port_link[i] = up;
250 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
252 writeb_be(ETH_PORTOV_ENABLE_MASK,
253 priv->base + ETH_PORTOV_REG(i));
254 writeb_be(ETH_PTCTRL_RXDIS_MASK |
255 ETH_PTCTRL_TXDIS_MASK,
256 priv->base + ETH_PTCTRL_REG(i));
260 adv = bcm6368_mdio_read(priv, external_phy,
261 port->phy_id, MII_ADVERTISE);
263 lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id,
266 /* figure out media and duplex from advertise and LPA values */
267 media = mii_nway_result(lpa & adv);
268 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
270 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
275 if (val & BMSR_ESTATEN) {
276 adv = bcm6368_mdio_read(priv, external_phy,
277 port->phy_id, MII_CTRL1000);
279 lpa = bcm6368_mdio_read(priv, external_phy,
280 port->phy_id, MII_STAT1000);
282 if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
283 (lpa & (LPA_1000FULL | LPA_1000HALF))) {
285 duplex = (lpa & LPA_1000FULL);
289 pr_alert("link UP on %s, %dMbps, %s-duplex\n",
290 port->name, speed, duplex ? "full" : "half");
292 override = ETH_PORTOV_ENABLE_MASK |
293 ETH_PORTOV_LINKUP_MASK;
296 override |= ETH_PORTOV_1000_MASK;
297 else if (speed == 100)
298 override |= ETH_PORTOV_100_MASK;
300 override |= ETH_PORTOV_FDX_MASK;
302 writeb_be(override, priv->base + ETH_PORTOV_REG(i));
303 writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
309 static int bcm6368_eth_start(struct udevice *dev)
311 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
314 /* disable all ports */
315 for (i = 0; i < priv->num_ports; i++) {
316 setbits_8(priv->base + ETH_PORTOV_REG(i),
317 ETH_PORTOV_ENABLE_MASK);
318 setbits_8(priv->base + ETH_PTCTRL_REG(i),
319 ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
320 priv->sw_port_link[i] = 0;
323 /* enable external ports */
324 for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
325 u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
327 if (!priv->used_ports[i].used)
330 if (priv->rgmii_override)
331 rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
332 if (priv->rgmii_timing)
333 rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
335 setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
339 setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
341 clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
344 /* force CPU port state */
345 setbits_8(priv->base + ETH_IMPOV_REG,
346 ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
348 /* enable switch forward engine */
349 setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
351 /* prepare rx dma buffers */
352 for (i = 0; i < ETH_RX_DESC; i++) {
353 int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
359 /* enable dma rx channel */
360 dma_enable(&priv->rx_dma);
362 /* enable dma tx channel */
363 dma_enable(&priv->tx_dma);
365 /* apply override config for bypass_link ports here. */
366 for (i = 0; i < priv->num_ports; i++) {
367 struct bcm_enetsw_port *port;
370 port = &priv->used_ports[i];
374 if (!port->bypass_link)
377 override = ETH_PORTOV_ENABLE_MASK |
378 ETH_PORTOV_LINKUP_MASK;
380 switch (port->force_speed) {
382 override |= ETH_PORTOV_1000_MASK;
385 override |= ETH_PORTOV_100_MASK;
390 pr_warn("%s: invalid forced speed on port %s\n",
391 __func__, port->name);
395 if (port->force_duplex_full)
396 override |= ETH_PORTOV_FDX_MASK;
398 writeb_be(override, priv->base + ETH_PORTOV_REG(i));
399 writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
402 bcm6368_eth_adjust_link(dev);
407 static void bcm6368_eth_stop(struct udevice *dev)
409 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
412 /* disable all ports */
413 for (i = 0; i < priv->num_ports; i++) {
414 setbits_8(priv->base + ETH_PORTOV_REG(i),
415 ETH_PORTOV_ENABLE_MASK);
416 setbits_8(priv->base + ETH_PTCTRL_REG(i),
417 ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
420 /* disable external ports */
421 for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
422 if (!priv->used_ports[i].used)
425 clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
426 ETH_RGMII_CTRL_GMII_CLK_EN);
429 /* disable CPU port */
430 clrbits_8(priv->base + ETH_IMPOV_REG,
431 ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
433 /* disable switch forward engine */
434 clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
436 /* disable dma rx channel */
437 dma_disable(&priv->rx_dma);
439 /* disable dma tx channel */
440 dma_disable(&priv->tx_dma);
443 static const struct eth_ops bcm6368_eth_ops = {
444 .free_pkt = bcm6368_eth_free_pkt,
445 .recv = bcm6368_eth_recv,
446 .send = bcm6368_eth_send,
447 .start = bcm6368_eth_start,
448 .stop = bcm6368_eth_stop,
451 static const struct udevice_id bcm6368_eth_ids[] = {
452 { .compatible = "brcm,bcm6368-enet", },
456 static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id)
460 for (i = 0; i < priv->num_ports; ++i) {
461 if (!priv->used_ports[i].used)
463 if (priv->used_ports[i].phy_id == phy_id)
464 return bcm_enet_port_is_rgmii(i);
470 static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr,
473 struct bcm6368_eth_priv *priv = bus->priv;
474 bool ext = bcm6368_phy_is_external(priv, addr);
476 return bcm6368_mdio_read(priv, ext, addr, reg);
479 static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr,
482 struct bcm6368_eth_priv *priv = bus->priv;
483 bool ext = bcm6368_phy_is_external(priv, addr);
485 return bcm6368_mdio_write(priv, ext, addr, reg, data);
488 static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv)
494 pr_err("%s: failed to allocate MDIO bus\n", __func__);
498 bus->read = bcm6368_mii_mdio_read;
499 bus->write = bcm6368_mii_mdio_write;
501 snprintf(bus->name, sizeof(bus->name), "%s", name);
503 return mdio_register(bus);
506 static int bcm6368_eth_probe(struct udevice *dev)
508 struct eth_pdata *pdata = dev_get_platdata(dev);
509 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
510 int num_ports, ret, i;
513 /* get base address */
514 priv->base = dev_remap_addr(dev);
517 pdata->iobase = (phys_addr_t) priv->base;
519 /* get number of ports */
520 num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT);
521 if (!num_ports || num_ports > ETH_MAX_PORT)
524 /* get dma channels */
525 ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
529 ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
533 /* try to enable clocks */
538 ret = clk_get_by_index(dev, i, &clk);
542 ret = clk_enable(&clk);
544 pr_err("%s: error enabling clock %d\n", __func__, i);
548 ret = clk_free(&clk);
550 pr_err("%s: error freeing clock %d\n", __func__, i);
555 /* try to perform resets */
557 struct reset_ctl reset;
560 ret = reset_get_by_index(dev, i, &reset);
564 ret = reset_deassert(&reset);
566 pr_err("%s: error deasserting reset %d\n", __func__, i);
570 ret = reset_free(&reset);
572 pr_err("%s: error freeing reset %d\n", __func__, i);
578 priv->num_ports = num_ports;
579 if (dev_read_bool(dev, "brcm,rgmii-override"))
580 priv->rgmii_override = true;
581 if (dev_read_bool(dev, "brcm,rgmii-timing"))
582 priv->rgmii_timing = true;
585 dev_for_each_subnode(node, dev) {
592 comp = ofnode_read_string(node, "compatible");
593 if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR)))
596 p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT);
600 label = ofnode_read_string(node, "label");
602 debug("%s: node %s has no label\n", __func__,
603 ofnode_get_name(node));
607 phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1);
609 priv->used_ports[p].used = true;
610 priv->used_ports[p].name = label;
611 priv->used_ports[p].phy_id = phy_id;
613 if (ofnode_read_bool(node, "full-duplex"))
614 priv->used_ports[p].force_duplex_full = true;
615 if (ofnode_read_bool(node, "bypass-link"))
616 priv->used_ports[p].bypass_link = true;
617 speed = ofnode_read_u32_default(node, "speed", 0);
619 priv->used_ports[p].force_speed = speed;
623 ret = bcm6368_mdio_init(dev->name, priv);
627 /* enable jumbo on all ports */
628 writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
629 writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG);
634 U_BOOT_DRIVER(bcm6368_eth) = {
635 .name = "bcm6368_eth",
637 .of_match = bcm6368_eth_ids,
638 .ops = &bcm6368_eth_ops,
639 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
640 .priv_auto_alloc_size = sizeof(struct bcm6368_eth_priv),
641 .probe = bcm6368_eth_probe,