1 /* b44.c: Broadcom 4400 device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
6 * Distribute under GPL.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/version.h>
22 #include <linux/dma-mapping.h>
24 #include <asm/uaccess.h>
30 #define DRV_MODULE_NAME "b44"
31 #define PFX DRV_MODULE_NAME ": "
32 #define DRV_MODULE_VERSION "0.95"
33 #define DRV_MODULE_RELDATE "Aug 3, 2004"
35 #define B44_DEF_MSG_ENABLE \
45 /* length of time before we decide the hardware is borked,
46 * and dev->tx_timeout() should be called to fix the problem
48 #define B44_TX_TIMEOUT (5 * HZ)
50 /* hardware minimum and maximum for a single frame's data payload */
51 #define B44_MIN_MTU 60
52 #define B44_MAX_MTU 1500
54 #define B44_RX_RING_SIZE 512
55 #define B44_DEF_RX_RING_PENDING 200
56 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
58 #define B44_TX_RING_SIZE 512
59 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
60 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
62 #define B44_DMA_MASK 0x3fffffff
64 #define TX_RING_GAP(BP) \
65 (B44_TX_RING_SIZE - (BP)->tx_pending)
66 #define TX_BUFFS_AVAIL(BP) \
67 (((BP)->tx_cons <= (BP)->tx_prod) ? \
68 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
69 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
70 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
72 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
73 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
75 /* minimum number of free TX descriptors required to wake up TX process */
76 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
78 static char version[] __devinitdata =
79 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
83 MODULE_LICENSE("GPL");
84 MODULE_VERSION(DRV_MODULE_VERSION);
86 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
87 module_param(b44_debug, int, 0);
88 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
90 static struct pci_device_id b44_pci_tbl[] = {
91 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
93 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
95 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
97 { } /* terminate list with empty entry */
100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
102 static void b44_halt(struct b44 *);
103 static void b44_init_rings(struct b44 *);
104 static void b44_init_hw(struct b44 *);
106 static int dma_desc_align_mask;
107 static int dma_desc_sync_size;
109 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
110 #define _B44(x...) # x,
115 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
117 unsigned long offset,
118 enum dma_data_direction dir)
120 dma_sync_single_range_for_device(&pdev->dev, dma_base,
121 offset & dma_desc_align_mask,
122 dma_desc_sync_size, dir);
125 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
127 unsigned long offset,
128 enum dma_data_direction dir)
130 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
131 offset & dma_desc_align_mask,
132 dma_desc_sync_size, dir);
135 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
137 return readl(bp->regs + reg);
140 static inline void bw32(const struct b44 *bp,
141 unsigned long reg, unsigned long val)
143 writel(val, bp->regs + reg);
146 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
147 u32 bit, unsigned long timeout, const int clear)
151 for (i = 0; i < timeout; i++) {
152 u32 val = br32(bp, reg);
154 if (clear && !(val & bit))
156 if (!clear && (val & bit))
161 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
165 (clear ? "clear" : "set"));
171 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
172 * buzz words used on this company's website :-)
174 * All of these routines must be invoked with bp->lock held and
175 * interrupts disabled.
178 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
179 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
181 static u32 ssb_get_core_rev(struct b44 *bp)
183 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
186 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
188 u32 bar_orig, pci_rev, val;
190 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
191 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
192 pci_rev = ssb_get_core_rev(bp);
194 val = br32(bp, B44_SBINTVEC);
196 bw32(bp, B44_SBINTVEC, val);
198 val = br32(bp, SSB_PCI_TRANS_2);
199 val |= SSB_PCI_PREF | SSB_PCI_BURST;
200 bw32(bp, SSB_PCI_TRANS_2, val);
202 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
207 static void ssb_core_disable(struct b44 *bp)
209 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
212 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
213 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
214 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
215 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
216 SBTMSLOW_REJECT | SBTMSLOW_RESET));
217 br32(bp, B44_SBTMSLOW);
219 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
220 br32(bp, B44_SBTMSLOW);
224 static void ssb_core_reset(struct b44 *bp)
228 ssb_core_disable(bp);
229 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
230 br32(bp, B44_SBTMSLOW);
233 /* Clear SERR if set, this is a hw bug workaround. */
234 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
235 bw32(bp, B44_SBTMSHIGH, 0);
237 val = br32(bp, B44_SBIMSTATE);
238 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
239 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
241 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
242 br32(bp, B44_SBTMSLOW);
245 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
246 br32(bp, B44_SBTMSLOW);
250 static int ssb_core_unit(struct b44 *bp)
253 u32 val = br32(bp, B44_SBADMATCH0);
256 type = val & SBADMATCH0_TYPE_MASK;
259 base = val & SBADMATCH0_BS0_MASK;
263 base = val & SBADMATCH0_BS1_MASK;
268 base = val & SBADMATCH0_BS2_MASK;
275 static int ssb_is_core_up(struct b44 *bp)
277 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
281 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
285 val = ((u32) data[2]) << 24;
286 val |= ((u32) data[3]) << 16;
287 val |= ((u32) data[4]) << 8;
288 val |= ((u32) data[5]) << 0;
289 bw32(bp, B44_CAM_DATA_LO, val);
290 val = (CAM_DATA_HI_VALID |
291 (((u32) data[0]) << 8) |
292 (((u32) data[1]) << 0));
293 bw32(bp, B44_CAM_DATA_HI, val);
294 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
295 (index << CAM_CTRL_INDEX_SHIFT)));
296 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
299 static inline void __b44_disable_ints(struct b44 *bp)
301 bw32(bp, B44_IMASK, 0);
304 static void b44_disable_ints(struct b44 *bp)
306 __b44_disable_ints(bp);
308 /* Flush posted writes. */
312 static void b44_enable_ints(struct b44 *bp)
314 bw32(bp, B44_IMASK, bp->imask);
317 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
321 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
322 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
323 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
324 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
325 (reg << MDIO_DATA_RA_SHIFT) |
326 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
327 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
328 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
333 static int b44_writephy(struct b44 *bp, int reg, u32 val)
335 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
336 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
337 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
338 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
339 (reg << MDIO_DATA_RA_SHIFT) |
340 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
341 (val & MDIO_DATA_DATA)));
342 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
345 /* miilib interface */
346 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
347 * due to code existing before miilib use was added to this driver.
348 * Someone should remove this artificial driver limitation in
349 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
351 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
354 struct b44 *bp = netdev_priv(dev);
355 int rc = b44_readphy(bp, location, &val);
361 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
364 struct b44 *bp = netdev_priv(dev);
365 b44_writephy(bp, location, val);
368 static int b44_phy_reset(struct b44 *bp)
373 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
377 err = b44_readphy(bp, MII_BMCR, &val);
379 if (val & BMCR_RESET) {
380 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
389 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
393 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
394 bp->flags |= pause_flags;
396 val = br32(bp, B44_RXCONFIG);
397 if (pause_flags & B44_FLAG_RX_PAUSE)
398 val |= RXCONFIG_FLOW;
400 val &= ~RXCONFIG_FLOW;
401 bw32(bp, B44_RXCONFIG, val);
403 val = br32(bp, B44_MAC_FLOW);
404 if (pause_flags & B44_FLAG_TX_PAUSE)
405 val |= (MAC_FLOW_PAUSE_ENAB |
406 (0xc0 & MAC_FLOW_RX_HI_WATER));
408 val &= ~MAC_FLOW_PAUSE_ENAB;
409 bw32(bp, B44_MAC_FLOW, val);
412 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
414 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
417 if (local & ADVERTISE_PAUSE_CAP) {
418 if (local & ADVERTISE_PAUSE_ASYM) {
419 if (remote & LPA_PAUSE_CAP)
420 pause_enab |= (B44_FLAG_TX_PAUSE |
422 else if (remote & LPA_PAUSE_ASYM)
423 pause_enab |= B44_FLAG_RX_PAUSE;
425 if (remote & LPA_PAUSE_CAP)
426 pause_enab |= (B44_FLAG_TX_PAUSE |
429 } else if (local & ADVERTISE_PAUSE_ASYM) {
430 if ((remote & LPA_PAUSE_CAP) &&
431 (remote & LPA_PAUSE_ASYM))
432 pause_enab |= B44_FLAG_TX_PAUSE;
435 __b44_set_flow_ctrl(bp, pause_enab);
438 static int b44_setup_phy(struct b44 *bp)
443 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
445 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
446 val & MII_ALEDCTRL_ALLMSK)) != 0)
448 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
450 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
451 val | MII_TLEDCTRL_ENABLE)) != 0)
454 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
455 u32 adv = ADVERTISE_CSMA;
457 if (bp->flags & B44_FLAG_ADV_10HALF)
458 adv |= ADVERTISE_10HALF;
459 if (bp->flags & B44_FLAG_ADV_10FULL)
460 adv |= ADVERTISE_10FULL;
461 if (bp->flags & B44_FLAG_ADV_100HALF)
462 adv |= ADVERTISE_100HALF;
463 if (bp->flags & B44_FLAG_ADV_100FULL)
464 adv |= ADVERTISE_100FULL;
466 if (bp->flags & B44_FLAG_PAUSE_AUTO)
467 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
469 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
471 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
472 BMCR_ANRESTART))) != 0)
477 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
479 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
480 if (bp->flags & B44_FLAG_100_BASE_T)
481 bmcr |= BMCR_SPEED100;
482 if (bp->flags & B44_FLAG_FULL_DUPLEX)
483 bmcr |= BMCR_FULLDPLX;
484 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
487 /* Since we will not be negotiating there is no safe way
488 * to determine if the link partner supports flow control
489 * or not. So just disable it completely in this case.
491 b44_set_flow_ctrl(bp, 0, 0);
498 static void b44_stats_update(struct b44 *bp)
503 val = &bp->hw_stats.tx_good_octets;
504 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
505 *val++ += br32(bp, reg);
511 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
512 *val++ += br32(bp, reg);
516 static void b44_link_report(struct b44 *bp)
518 if (!netif_carrier_ok(bp->dev)) {
519 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
521 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
523 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
524 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
526 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
529 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
530 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
534 static void b44_check_phy(struct b44 *bp)
538 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
539 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
541 if (aux & MII_AUXCTRL_SPEED)
542 bp->flags |= B44_FLAG_100_BASE_T;
544 bp->flags &= ~B44_FLAG_100_BASE_T;
545 if (aux & MII_AUXCTRL_DUPLEX)
546 bp->flags |= B44_FLAG_FULL_DUPLEX;
548 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
550 if (!netif_carrier_ok(bp->dev) &&
551 (bmsr & BMSR_LSTATUS)) {
552 u32 val = br32(bp, B44_TX_CTRL);
553 u32 local_adv, remote_adv;
555 if (bp->flags & B44_FLAG_FULL_DUPLEX)
556 val |= TX_CTRL_DUPLEX;
558 val &= ~TX_CTRL_DUPLEX;
559 bw32(bp, B44_TX_CTRL, val);
561 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
562 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
563 !b44_readphy(bp, MII_LPA, &remote_adv))
564 b44_set_flow_ctrl(bp, local_adv, remote_adv);
567 netif_carrier_on(bp->dev);
569 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
571 netif_carrier_off(bp->dev);
575 if (bmsr & BMSR_RFAULT)
576 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
579 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
584 static void b44_timer(unsigned long __opaque)
586 struct b44 *bp = (struct b44 *) __opaque;
588 spin_lock_irq(&bp->lock);
592 b44_stats_update(bp);
594 spin_unlock_irq(&bp->lock);
596 bp->timer.expires = jiffies + HZ;
597 add_timer(&bp->timer);
600 static void b44_tx(struct b44 *bp)
604 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
605 cur /= sizeof(struct dma_desc);
607 /* XXX needs updating when NETIF_F_SG is supported */
608 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
609 struct ring_info *rp = &bp->tx_buffers[cons];
610 struct sk_buff *skb = rp->skb;
612 if (unlikely(skb == NULL))
615 pci_unmap_single(bp->pdev,
616 pci_unmap_addr(rp, mapping),
620 dev_kfree_skb_irq(skb);
624 if (netif_queue_stopped(bp->dev) &&
625 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
626 netif_wake_queue(bp->dev);
628 bw32(bp, B44_GPTIMER, 0);
631 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
632 * before the DMA address you give it. So we allocate 30 more bytes
633 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
634 * point the chip at 30 bytes past where the rx_header will go.
636 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
639 struct ring_info *src_map, *map;
640 struct rx_header *rh;
648 src_map = &bp->rx_buffers[src_idx];
649 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
650 map = &bp->rx_buffers[dest_idx];
651 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
655 mapping = pci_map_single(bp->pdev, skb->data,
659 /* Hardware bug work-around, the chip is unable to do PCI DMA
660 to/from anything above 1GB :-( */
661 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
663 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
664 dev_kfree_skb_any(skb);
665 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
668 mapping = pci_map_single(bp->pdev, skb->data,
671 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
672 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
673 dev_kfree_skb_any(skb);
679 skb_reserve(skb, bp->rx_offset);
681 rh = (struct rx_header *)
682 (skb->data - bp->rx_offset);
687 pci_unmap_addr_set(map, mapping, mapping);
692 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
693 if (dest_idx == (B44_RX_RING_SIZE - 1))
694 ctrl |= DESC_CTRL_EOT;
696 dp = &bp->rx_ring[dest_idx];
697 dp->ctrl = cpu_to_le32(ctrl);
698 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
700 if (bp->flags & B44_FLAG_RX_RING_HACK)
701 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
702 dest_idx * sizeof(dp),
705 return RX_PKT_BUF_SZ;
708 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
710 struct dma_desc *src_desc, *dest_desc;
711 struct ring_info *src_map, *dest_map;
712 struct rx_header *rh;
716 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
717 dest_desc = &bp->rx_ring[dest_idx];
718 dest_map = &bp->rx_buffers[dest_idx];
719 src_desc = &bp->rx_ring[src_idx];
720 src_map = &bp->rx_buffers[src_idx];
722 dest_map->skb = src_map->skb;
723 rh = (struct rx_header *) src_map->skb->data;
726 pci_unmap_addr_set(dest_map, mapping,
727 pci_unmap_addr(src_map, mapping));
729 if (bp->flags & B44_FLAG_RX_RING_HACK)
730 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
731 src_idx * sizeof(src_desc),
734 ctrl = src_desc->ctrl;
735 if (dest_idx == (B44_RX_RING_SIZE - 1))
736 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
738 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
740 dest_desc->ctrl = ctrl;
741 dest_desc->addr = src_desc->addr;
745 if (bp->flags & B44_FLAG_RX_RING_HACK)
746 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
747 dest_idx * sizeof(dest_desc),
750 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
755 static int b44_rx(struct b44 *bp, int budget)
761 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
762 prod /= sizeof(struct dma_desc);
765 while (cons != prod && budget > 0) {
766 struct ring_info *rp = &bp->rx_buffers[cons];
767 struct sk_buff *skb = rp->skb;
768 dma_addr_t map = pci_unmap_addr(rp, mapping);
769 struct rx_header *rh;
772 pci_dma_sync_single_for_cpu(bp->pdev, map,
775 rh = (struct rx_header *) skb->data;
776 len = cpu_to_le16(rh->len);
777 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
778 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
780 b44_recycle_rx(bp, cons, bp->rx_prod);
782 bp->stats.rx_dropped++;
792 len = cpu_to_le16(rh->len);
793 } while (len == 0 && i++ < 5);
801 if (len > RX_COPY_THRESHOLD) {
803 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
806 pci_unmap_single(bp->pdev, map,
807 skb_size, PCI_DMA_FROMDEVICE);
808 /* Leave out rx_header */
809 skb_put(skb, len+bp->rx_offset);
810 skb_pull(skb,bp->rx_offset);
812 struct sk_buff *copy_skb;
814 b44_recycle_rx(bp, cons, bp->rx_prod);
815 copy_skb = dev_alloc_skb(len + 2);
816 if (copy_skb == NULL)
817 goto drop_it_no_recycle;
819 copy_skb->dev = bp->dev;
820 skb_reserve(copy_skb, 2);
821 skb_put(copy_skb, len);
822 /* DMA sync done above, copy just the actual packet */
823 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
827 skb->ip_summed = CHECKSUM_NONE;
828 skb->protocol = eth_type_trans(skb, bp->dev);
829 netif_receive_skb(skb);
830 bp->dev->last_rx = jiffies;
834 bp->rx_prod = (bp->rx_prod + 1) &
835 (B44_RX_RING_SIZE - 1);
836 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
840 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
845 static int b44_poll(struct net_device *netdev, int *budget)
847 struct b44 *bp = netdev_priv(netdev);
850 spin_lock_irq(&bp->lock);
852 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
853 /* spin_lock(&bp->tx_lock); */
855 /* spin_unlock(&bp->tx_lock); */
857 spin_unlock_irq(&bp->lock);
860 if (bp->istat & ISTAT_RX) {
861 int orig_budget = *budget;
864 if (orig_budget > netdev->quota)
865 orig_budget = netdev->quota;
867 work_done = b44_rx(bp, orig_budget);
869 *budget -= work_done;
870 netdev->quota -= work_done;
872 if (work_done >= orig_budget)
876 if (bp->istat & ISTAT_ERRORS) {
877 spin_lock_irq(&bp->lock);
881 netif_wake_queue(bp->dev);
882 spin_unlock_irq(&bp->lock);
887 netif_rx_complete(netdev);
891 return (done ? 0 : 1);
894 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
896 struct net_device *dev = dev_id;
897 struct b44 *bp = netdev_priv(dev);
901 spin_lock(&bp->lock);
903 istat = br32(bp, B44_ISTAT);
904 imask = br32(bp, B44_IMASK);
906 /* ??? What the fuck is the purpose of the interrupt mask
907 * ??? register if we have to mask it out by hand anyways?
912 if (netif_rx_schedule_prep(dev)) {
913 /* NOTE: These writes are posted by the readback of
914 * the ISTAT register below.
917 __b44_disable_ints(bp);
918 __netif_rx_schedule(dev);
920 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
924 bw32(bp, B44_ISTAT, istat);
927 spin_unlock(&bp->lock);
928 return IRQ_RETVAL(handled);
931 static void b44_tx_timeout(struct net_device *dev)
933 struct b44 *bp = netdev_priv(dev);
935 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
938 spin_lock_irq(&bp->lock);
944 spin_unlock_irq(&bp->lock);
948 netif_wake_queue(dev);
951 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
953 struct b44 *bp = netdev_priv(dev);
954 struct sk_buff *bounce_skb;
955 int rc = NETDEV_TX_OK;
957 u32 len, entry, ctrl;
960 spin_lock_irq(&bp->lock);
962 /* This is a hard error, log it. */
963 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
964 netif_stop_queue(dev);
965 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
970 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
971 if (mapping + len > B44_DMA_MASK) {
972 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
973 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
975 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
980 mapping = pci_map_single(bp->pdev, bounce_skb->data,
981 len, PCI_DMA_TODEVICE);
982 if (mapping + len > B44_DMA_MASK) {
983 pci_unmap_single(bp->pdev, mapping,
984 len, PCI_DMA_TODEVICE);
985 dev_kfree_skb_any(bounce_skb);
989 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
990 dev_kfree_skb_any(skb);
995 bp->tx_buffers[entry].skb = skb;
996 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
998 ctrl = (len & DESC_CTRL_LEN);
999 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1000 if (entry == (B44_TX_RING_SIZE - 1))
1001 ctrl |= DESC_CTRL_EOT;
1003 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1004 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1006 if (bp->flags & B44_FLAG_TX_RING_HACK)
1007 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1008 entry * sizeof(bp->tx_ring[0]),
1011 entry = NEXT_TX(entry);
1013 bp->tx_prod = entry;
1017 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1018 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1019 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1020 if (bp->flags & B44_FLAG_REORDER_BUG)
1021 br32(bp, B44_DMATX_PTR);
1023 if (TX_BUFFS_AVAIL(bp) < 1)
1024 netif_stop_queue(dev);
1026 dev->trans_start = jiffies;
1029 spin_unlock_irq(&bp->lock);
1034 rc = NETDEV_TX_BUSY;
1038 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1040 struct b44 *bp = netdev_priv(dev);
1042 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1045 if (!netif_running(dev)) {
1046 /* We'll just catch it later when the
1053 spin_lock_irq(&bp->lock);
1058 spin_unlock_irq(&bp->lock);
1060 b44_enable_ints(bp);
1065 /* Free up pending packets in all rx/tx rings.
1067 * The chip has been shut down and the driver detached from
1068 * the networking, so no interrupts or new tx packets will
1069 * end up in the driver. bp->lock is not held and we are not
1070 * in an interrupt context and thus may sleep.
1072 static void b44_free_rings(struct b44 *bp)
1074 struct ring_info *rp;
1077 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1078 rp = &bp->rx_buffers[i];
1080 if (rp->skb == NULL)
1082 pci_unmap_single(bp->pdev,
1083 pci_unmap_addr(rp, mapping),
1085 PCI_DMA_FROMDEVICE);
1086 dev_kfree_skb_any(rp->skb);
1090 /* XXX needs changes once NETIF_F_SG is set... */
1091 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1092 rp = &bp->tx_buffers[i];
1094 if (rp->skb == NULL)
1096 pci_unmap_single(bp->pdev,
1097 pci_unmap_addr(rp, mapping),
1100 dev_kfree_skb_any(rp->skb);
1105 /* Initialize tx/rx rings for packet processing.
1107 * The chip has been shut down and the driver detached from
1108 * the networking, so no interrupts or new tx packets will
1109 * end up in the driver.
1111 static void b44_init_rings(struct b44 *bp)
1117 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1118 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1120 if (bp->flags & B44_FLAG_RX_RING_HACK)
1121 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1123 PCI_DMA_BIDIRECTIONAL);
1125 if (bp->flags & B44_FLAG_TX_RING_HACK)
1126 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1130 for (i = 0; i < bp->rx_pending; i++) {
1131 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1137 * Must not be invoked with interrupt sources disabled and
1138 * the hardware shutdown down.
1140 static void b44_free_consistent(struct b44 *bp)
1142 kfree(bp->rx_buffers);
1143 bp->rx_buffers = NULL;
1144 kfree(bp->tx_buffers);
1145 bp->tx_buffers = NULL;
1147 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1148 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1153 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1154 bp->rx_ring, bp->rx_ring_dma);
1156 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1159 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1160 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1165 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1166 bp->tx_ring, bp->tx_ring_dma);
1168 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1173 * Must not be invoked with interrupt sources disabled and
1174 * the hardware shutdown down. Can sleep.
1176 static int b44_alloc_consistent(struct b44 *bp)
1180 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1181 bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1182 if (!bp->rx_buffers)
1185 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1186 bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1187 if (!bp->tx_buffers)
1190 size = DMA_TABLE_BYTES;
1191 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1193 /* Allocation may have failed due to pci_alloc_consistent
1194 insisting on use of GFP_DMA, which is more restrictive
1195 than necessary... */
1196 struct dma_desc *rx_ring;
1197 dma_addr_t rx_ring_dma;
1199 rx_ring = kzalloc(size, GFP_KERNEL);
1203 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1207 if (rx_ring_dma + size > B44_DMA_MASK) {
1212 bp->rx_ring = rx_ring;
1213 bp->rx_ring_dma = rx_ring_dma;
1214 bp->flags |= B44_FLAG_RX_RING_HACK;
1217 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1219 /* Allocation may have failed due to pci_alloc_consistent
1220 insisting on use of GFP_DMA, which is more restrictive
1221 than necessary... */
1222 struct dma_desc *tx_ring;
1223 dma_addr_t tx_ring_dma;
1225 tx_ring = kzalloc(size, GFP_KERNEL);
1229 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1233 if (tx_ring_dma + size > B44_DMA_MASK) {
1238 bp->tx_ring = tx_ring;
1239 bp->tx_ring_dma = tx_ring_dma;
1240 bp->flags |= B44_FLAG_TX_RING_HACK;
1246 b44_free_consistent(bp);
1250 /* bp->lock is held. */
1251 static void b44_clear_stats(struct b44 *bp)
1255 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1256 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1258 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1262 /* bp->lock is held. */
1263 static void b44_chip_reset(struct b44 *bp)
1265 if (ssb_is_core_up(bp)) {
1266 bw32(bp, B44_RCV_LAZY, 0);
1267 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1268 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1269 bw32(bp, B44_DMATX_CTRL, 0);
1270 bp->tx_prod = bp->tx_cons = 0;
1271 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1272 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1275 bw32(bp, B44_DMARX_CTRL, 0);
1276 bp->rx_prod = bp->rx_cons = 0;
1278 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1285 b44_clear_stats(bp);
1287 /* Make PHY accessible. */
1288 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1289 (0x0d & MDIO_CTRL_MAXF_MASK)));
1290 br32(bp, B44_MDIO_CTRL);
1292 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1293 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1294 br32(bp, B44_ENET_CTRL);
1295 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1297 u32 val = br32(bp, B44_DEVCTRL);
1299 if (val & DEVCTRL_EPR) {
1300 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1301 br32(bp, B44_DEVCTRL);
1304 bp->flags |= B44_FLAG_INTERNAL_PHY;
1308 /* bp->lock is held. */
1309 static void b44_halt(struct b44 *bp)
1311 b44_disable_ints(bp);
1315 /* bp->lock is held. */
1316 static void __b44_set_mac_addr(struct b44 *bp)
1318 bw32(bp, B44_CAM_CTRL, 0);
1319 if (!(bp->dev->flags & IFF_PROMISC)) {
1322 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1323 val = br32(bp, B44_CAM_CTRL);
1324 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1328 static int b44_set_mac_addr(struct net_device *dev, void *p)
1330 struct b44 *bp = netdev_priv(dev);
1331 struct sockaddr *addr = p;
1333 if (netif_running(dev))
1336 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1338 spin_lock_irq(&bp->lock);
1339 __b44_set_mac_addr(bp);
1340 spin_unlock_irq(&bp->lock);
1345 /* Called at device open time to get the chip ready for
1346 * packet processing. Invoked with bp->lock held.
1348 static void __b44_set_rx_mode(struct net_device *);
1349 static void b44_init_hw(struct b44 *bp)
1357 /* Enable CRC32, set proper LED modes and power on PHY */
1358 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1359 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1361 /* This sets the MAC address too. */
1362 __b44_set_rx_mode(bp->dev);
1364 /* MTU + eth header + possible VLAN tag + struct rx_header */
1365 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1366 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1368 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1369 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1370 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1371 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1372 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1373 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1375 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1376 bp->rx_prod = bp->rx_pending;
1378 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1380 val = br32(bp, B44_ENET_CTRL);
1381 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1384 static int b44_open(struct net_device *dev)
1386 struct b44 *bp = netdev_priv(dev);
1389 err = b44_alloc_consistent(bp);
1395 bp->flags |= B44_FLAG_INIT_COMPLETE;
1397 netif_carrier_off(dev);
1400 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1401 if (unlikely(err < 0)) {
1404 b44_free_consistent(bp);
1408 init_timer(&bp->timer);
1409 bp->timer.expires = jiffies + HZ;
1410 bp->timer.data = (unsigned long) bp;
1411 bp->timer.function = b44_timer;
1412 add_timer(&bp->timer);
1414 b44_enable_ints(bp);
1420 /*static*/ void b44_dump_state(struct b44 *bp)
1422 u32 val32, val32_2, val32_3, val32_4, val32_5;
1425 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1426 printk("DEBUG: PCI status [%04x] \n", val16);
1431 #ifdef CONFIG_NET_POLL_CONTROLLER
1433 * Polling receive - used by netconsole and other diagnostic tools
1434 * to allow network i/o with interrupts disabled.
1436 static void b44_poll_controller(struct net_device *dev)
1438 disable_irq(dev->irq);
1439 b44_interrupt(dev->irq, dev, NULL);
1440 enable_irq(dev->irq);
1444 static int b44_close(struct net_device *dev)
1446 struct b44 *bp = netdev_priv(dev);
1448 netif_stop_queue(dev);
1450 del_timer_sync(&bp->timer);
1452 spin_lock_irq(&bp->lock);
1459 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1460 netif_carrier_off(bp->dev);
1462 spin_unlock_irq(&bp->lock);
1464 free_irq(dev->irq, dev);
1466 b44_free_consistent(bp);
1471 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1473 struct b44 *bp = netdev_priv(dev);
1474 struct net_device_stats *nstat = &bp->stats;
1475 struct b44_hw_stats *hwstat = &bp->hw_stats;
1477 /* Convert HW stats into netdevice stats. */
1478 nstat->rx_packets = hwstat->rx_pkts;
1479 nstat->tx_packets = hwstat->tx_pkts;
1480 nstat->rx_bytes = hwstat->rx_octets;
1481 nstat->tx_bytes = hwstat->tx_octets;
1482 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1483 hwstat->tx_oversize_pkts +
1484 hwstat->tx_underruns +
1485 hwstat->tx_excessive_cols +
1486 hwstat->tx_late_cols);
1487 nstat->multicast = hwstat->tx_multicast_pkts;
1488 nstat->collisions = hwstat->tx_total_cols;
1490 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1491 hwstat->rx_undersize);
1492 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1493 nstat->rx_frame_errors = hwstat->rx_align_errs;
1494 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1495 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1496 hwstat->rx_oversize_pkts +
1497 hwstat->rx_missed_pkts +
1498 hwstat->rx_crc_align_errs +
1499 hwstat->rx_undersize +
1500 hwstat->rx_crc_errs +
1501 hwstat->rx_align_errs +
1502 hwstat->rx_symbol_errs);
1504 nstat->tx_aborted_errors = hwstat->tx_underruns;
1506 /* Carrier lost counter seems to be broken for some devices */
1507 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1513 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1515 struct dev_mc_list *mclist;
1518 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1519 mclist = dev->mc_list;
1520 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1521 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1526 static void __b44_set_rx_mode(struct net_device *dev)
1528 struct b44 *bp = netdev_priv(dev);
1531 val = br32(bp, B44_RXCONFIG);
1532 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1533 if (dev->flags & IFF_PROMISC) {
1534 val |= RXCONFIG_PROMISC;
1535 bw32(bp, B44_RXCONFIG, val);
1537 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1540 __b44_set_mac_addr(bp);
1542 if (dev->flags & IFF_ALLMULTI)
1543 val |= RXCONFIG_ALLMULTI;
1545 i = __b44_load_mcast(bp, dev);
1547 for (; i < 64; i++) {
1548 __b44_cam_write(bp, zero, i);
1550 bw32(bp, B44_RXCONFIG, val);
1551 val = br32(bp, B44_CAM_CTRL);
1552 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1556 static void b44_set_rx_mode(struct net_device *dev)
1558 struct b44 *bp = netdev_priv(dev);
1560 spin_lock_irq(&bp->lock);
1561 __b44_set_rx_mode(dev);
1562 spin_unlock_irq(&bp->lock);
1565 static u32 b44_get_msglevel(struct net_device *dev)
1567 struct b44 *bp = netdev_priv(dev);
1568 return bp->msg_enable;
1571 static void b44_set_msglevel(struct net_device *dev, u32 value)
1573 struct b44 *bp = netdev_priv(dev);
1574 bp->msg_enable = value;
1577 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1579 struct b44 *bp = netdev_priv(dev);
1580 struct pci_dev *pci_dev = bp->pdev;
1582 strcpy (info->driver, DRV_MODULE_NAME);
1583 strcpy (info->version, DRV_MODULE_VERSION);
1584 strcpy (info->bus_info, pci_name(pci_dev));
1587 static int b44_nway_reset(struct net_device *dev)
1589 struct b44 *bp = netdev_priv(dev);
1593 spin_lock_irq(&bp->lock);
1594 b44_readphy(bp, MII_BMCR, &bmcr);
1595 b44_readphy(bp, MII_BMCR, &bmcr);
1597 if (bmcr & BMCR_ANENABLE) {
1598 b44_writephy(bp, MII_BMCR,
1599 bmcr | BMCR_ANRESTART);
1602 spin_unlock_irq(&bp->lock);
1607 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1609 struct b44 *bp = netdev_priv(dev);
1611 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1613 cmd->supported = (SUPPORTED_Autoneg);
1614 cmd->supported |= (SUPPORTED_100baseT_Half |
1615 SUPPORTED_100baseT_Full |
1616 SUPPORTED_10baseT_Half |
1617 SUPPORTED_10baseT_Full |
1620 cmd->advertising = 0;
1621 if (bp->flags & B44_FLAG_ADV_10HALF)
1622 cmd->advertising |= ADVERTISED_10baseT_Half;
1623 if (bp->flags & B44_FLAG_ADV_10FULL)
1624 cmd->advertising |= ADVERTISED_10baseT_Full;
1625 if (bp->flags & B44_FLAG_ADV_100HALF)
1626 cmd->advertising |= ADVERTISED_100baseT_Half;
1627 if (bp->flags & B44_FLAG_ADV_100FULL)
1628 cmd->advertising |= ADVERTISED_100baseT_Full;
1629 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1630 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1631 SPEED_100 : SPEED_10;
1632 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1633 DUPLEX_FULL : DUPLEX_HALF;
1635 cmd->phy_address = bp->phy_addr;
1636 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1637 XCVR_INTERNAL : XCVR_EXTERNAL;
1638 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1639 AUTONEG_DISABLE : AUTONEG_ENABLE;
1645 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1647 struct b44 *bp = netdev_priv(dev);
1649 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1652 /* We do not support gigabit. */
1653 if (cmd->autoneg == AUTONEG_ENABLE) {
1654 if (cmd->advertising &
1655 (ADVERTISED_1000baseT_Half |
1656 ADVERTISED_1000baseT_Full))
1658 } else if ((cmd->speed != SPEED_100 &&
1659 cmd->speed != SPEED_10) ||
1660 (cmd->duplex != DUPLEX_HALF &&
1661 cmd->duplex != DUPLEX_FULL)) {
1665 spin_lock_irq(&bp->lock);
1667 if (cmd->autoneg == AUTONEG_ENABLE) {
1668 bp->flags &= ~B44_FLAG_FORCE_LINK;
1669 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1670 B44_FLAG_ADV_10FULL |
1671 B44_FLAG_ADV_100HALF |
1672 B44_FLAG_ADV_100FULL);
1673 if (cmd->advertising & ADVERTISE_10HALF)
1674 bp->flags |= B44_FLAG_ADV_10HALF;
1675 if (cmd->advertising & ADVERTISE_10FULL)
1676 bp->flags |= B44_FLAG_ADV_10FULL;
1677 if (cmd->advertising & ADVERTISE_100HALF)
1678 bp->flags |= B44_FLAG_ADV_100HALF;
1679 if (cmd->advertising & ADVERTISE_100FULL)
1680 bp->flags |= B44_FLAG_ADV_100FULL;
1682 bp->flags |= B44_FLAG_FORCE_LINK;
1683 if (cmd->speed == SPEED_100)
1684 bp->flags |= B44_FLAG_100_BASE_T;
1685 if (cmd->duplex == DUPLEX_FULL)
1686 bp->flags |= B44_FLAG_FULL_DUPLEX;
1691 spin_unlock_irq(&bp->lock);
1696 static void b44_get_ringparam(struct net_device *dev,
1697 struct ethtool_ringparam *ering)
1699 struct b44 *bp = netdev_priv(dev);
1701 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1702 ering->rx_pending = bp->rx_pending;
1704 /* XXX ethtool lacks a tx_max_pending, oops... */
1707 static int b44_set_ringparam(struct net_device *dev,
1708 struct ethtool_ringparam *ering)
1710 struct b44 *bp = netdev_priv(dev);
1712 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1713 (ering->rx_mini_pending != 0) ||
1714 (ering->rx_jumbo_pending != 0) ||
1715 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1718 spin_lock_irq(&bp->lock);
1720 bp->rx_pending = ering->rx_pending;
1721 bp->tx_pending = ering->tx_pending;
1726 netif_wake_queue(bp->dev);
1727 spin_unlock_irq(&bp->lock);
1729 b44_enable_ints(bp);
1734 static void b44_get_pauseparam(struct net_device *dev,
1735 struct ethtool_pauseparam *epause)
1737 struct b44 *bp = netdev_priv(dev);
1740 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1742 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1744 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1747 static int b44_set_pauseparam(struct net_device *dev,
1748 struct ethtool_pauseparam *epause)
1750 struct b44 *bp = netdev_priv(dev);
1752 spin_lock_irq(&bp->lock);
1753 if (epause->autoneg)
1754 bp->flags |= B44_FLAG_PAUSE_AUTO;
1756 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1757 if (epause->rx_pause)
1758 bp->flags |= B44_FLAG_RX_PAUSE;
1760 bp->flags &= ~B44_FLAG_RX_PAUSE;
1761 if (epause->tx_pause)
1762 bp->flags |= B44_FLAG_TX_PAUSE;
1764 bp->flags &= ~B44_FLAG_TX_PAUSE;
1765 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1770 __b44_set_flow_ctrl(bp, bp->flags);
1772 spin_unlock_irq(&bp->lock);
1774 b44_enable_ints(bp);
1779 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1783 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1788 static int b44_get_stats_count(struct net_device *dev)
1790 return ARRAY_SIZE(b44_gstrings);
1793 static void b44_get_ethtool_stats(struct net_device *dev,
1794 struct ethtool_stats *stats, u64 *data)
1796 struct b44 *bp = netdev_priv(dev);
1797 u32 *val = &bp->hw_stats.tx_good_octets;
1800 spin_lock_irq(&bp->lock);
1802 b44_stats_update(bp);
1804 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1807 spin_unlock_irq(&bp->lock);
1810 static struct ethtool_ops b44_ethtool_ops = {
1811 .get_drvinfo = b44_get_drvinfo,
1812 .get_settings = b44_get_settings,
1813 .set_settings = b44_set_settings,
1814 .nway_reset = b44_nway_reset,
1815 .get_link = ethtool_op_get_link,
1816 .get_ringparam = b44_get_ringparam,
1817 .set_ringparam = b44_set_ringparam,
1818 .get_pauseparam = b44_get_pauseparam,
1819 .set_pauseparam = b44_set_pauseparam,
1820 .get_msglevel = b44_get_msglevel,
1821 .set_msglevel = b44_set_msglevel,
1822 .get_strings = b44_get_strings,
1823 .get_stats_count = b44_get_stats_count,
1824 .get_ethtool_stats = b44_get_ethtool_stats,
1825 .get_perm_addr = ethtool_op_get_perm_addr,
1828 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1830 struct mii_ioctl_data *data = if_mii(ifr);
1831 struct b44 *bp = netdev_priv(dev);
1834 spin_lock_irq(&bp->lock);
1835 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1836 spin_unlock_irq(&bp->lock);
1841 /* Read 128-bytes of EEPROM. */
1842 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1845 u16 *ptr = (u16 *) data;
1847 for (i = 0; i < 128; i += 2)
1848 ptr[i / 2] = readw(bp->regs + 4096 + i);
1853 static int __devinit b44_get_invariants(struct b44 *bp)
1858 err = b44_read_eeprom(bp, &eeprom[0]);
1862 bp->dev->dev_addr[0] = eeprom[79];
1863 bp->dev->dev_addr[1] = eeprom[78];
1864 bp->dev->dev_addr[2] = eeprom[81];
1865 bp->dev->dev_addr[3] = eeprom[80];
1866 bp->dev->dev_addr[4] = eeprom[83];
1867 bp->dev->dev_addr[5] = eeprom[82];
1868 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1870 bp->phy_addr = eeprom[90] & 0x1f;
1872 /* With this, plus the rx_header prepended to the data by the
1873 * hardware, we'll land the ethernet header on a 2-byte boundary.
1877 bp->imask = IMASK_DEF;
1879 bp->core_unit = ssb_core_unit(bp);
1880 bp->dma_offset = SB_PCI_DMA;
1882 /* XXX - really required?
1883 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1889 static int __devinit b44_init_one(struct pci_dev *pdev,
1890 const struct pci_device_id *ent)
1892 static int b44_version_printed = 0;
1893 unsigned long b44reg_base, b44reg_len;
1894 struct net_device *dev;
1898 if (b44_version_printed++ == 0)
1899 printk(KERN_INFO "%s", version);
1901 err = pci_enable_device(pdev);
1903 printk(KERN_ERR PFX "Cannot enable PCI device, "
1908 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1909 printk(KERN_ERR PFX "Cannot find proper PCI device "
1910 "base address, aborting.\n");
1912 goto err_out_disable_pdev;
1915 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1917 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1919 goto err_out_disable_pdev;
1922 pci_set_master(pdev);
1924 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1926 printk(KERN_ERR PFX "No usable DMA configuration, "
1928 goto err_out_free_res;
1931 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1933 printk(KERN_ERR PFX "No usable DMA configuration, "
1935 goto err_out_free_res;
1938 b44reg_base = pci_resource_start(pdev, 0);
1939 b44reg_len = pci_resource_len(pdev, 0);
1941 dev = alloc_etherdev(sizeof(*bp));
1943 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1945 goto err_out_free_res;
1948 SET_MODULE_OWNER(dev);
1949 SET_NETDEV_DEV(dev,&pdev->dev);
1951 /* No interesting netdevice features in this card... */
1954 bp = netdev_priv(dev);
1958 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1960 spin_lock_init(&bp->lock);
1962 bp->regs = ioremap(b44reg_base, b44reg_len);
1963 if (bp->regs == 0UL) {
1964 printk(KERN_ERR PFX "Cannot map device registers, "
1967 goto err_out_free_dev;
1970 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1971 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1973 dev->open = b44_open;
1974 dev->stop = b44_close;
1975 dev->hard_start_xmit = b44_start_xmit;
1976 dev->get_stats = b44_get_stats;
1977 dev->set_multicast_list = b44_set_rx_mode;
1978 dev->set_mac_address = b44_set_mac_addr;
1979 dev->do_ioctl = b44_ioctl;
1980 dev->tx_timeout = b44_tx_timeout;
1981 dev->poll = b44_poll;
1983 dev->watchdog_timeo = B44_TX_TIMEOUT;
1984 #ifdef CONFIG_NET_POLL_CONTROLLER
1985 dev->poll_controller = b44_poll_controller;
1987 dev->change_mtu = b44_change_mtu;
1988 dev->irq = pdev->irq;
1989 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1991 err = b44_get_invariants(bp);
1993 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1995 goto err_out_iounmap;
1998 bp->mii_if.dev = dev;
1999 bp->mii_if.mdio_read = b44_mii_read;
2000 bp->mii_if.mdio_write = b44_mii_write;
2001 bp->mii_if.phy_id = bp->phy_addr;
2002 bp->mii_if.phy_id_mask = 0x1f;
2003 bp->mii_if.reg_num_mask = 0x1f;
2005 /* By default, advertise all speed/duplex settings. */
2006 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2007 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2009 /* By default, auto-negotiate PAUSE. */
2010 bp->flags |= B44_FLAG_PAUSE_AUTO;
2012 err = register_netdev(dev);
2014 printk(KERN_ERR PFX "Cannot register net device, "
2016 goto err_out_iounmap;
2019 pci_set_drvdata(pdev, dev);
2021 pci_save_state(bp->pdev);
2023 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2024 for (i = 0; i < 6; i++)
2025 printk("%2.2x%c", dev->dev_addr[i],
2026 i == 5 ? '\n' : ':');
2037 pci_release_regions(pdev);
2039 err_out_disable_pdev:
2040 pci_disable_device(pdev);
2041 pci_set_drvdata(pdev, NULL);
2045 static void __devexit b44_remove_one(struct pci_dev *pdev)
2047 struct net_device *dev = pci_get_drvdata(pdev);
2048 struct b44 *bp = netdev_priv(dev);
2050 unregister_netdev(dev);
2053 pci_release_regions(pdev);
2054 pci_disable_device(pdev);
2055 pci_set_drvdata(pdev, NULL);
2058 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2060 struct net_device *dev = pci_get_drvdata(pdev);
2061 struct b44 *bp = netdev_priv(dev);
2063 if (!netif_running(dev))
2066 del_timer_sync(&bp->timer);
2068 spin_lock_irq(&bp->lock);
2071 netif_carrier_off(bp->dev);
2072 netif_device_detach(bp->dev);
2075 spin_unlock_irq(&bp->lock);
2077 free_irq(dev->irq, dev);
2078 pci_disable_device(pdev);
2082 static int b44_resume(struct pci_dev *pdev)
2084 struct net_device *dev = pci_get_drvdata(pdev);
2085 struct b44 *bp = netdev_priv(dev);
2087 pci_restore_state(pdev);
2088 pci_enable_device(pdev);
2089 pci_set_master(pdev);
2091 if (!netif_running(dev))
2094 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2095 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2097 spin_lock_irq(&bp->lock);
2101 netif_device_attach(bp->dev);
2102 spin_unlock_irq(&bp->lock);
2104 bp->timer.expires = jiffies + HZ;
2105 add_timer(&bp->timer);
2107 b44_enable_ints(bp);
2111 static struct pci_driver b44_driver = {
2112 .name = DRV_MODULE_NAME,
2113 .id_table = b44_pci_tbl,
2114 .probe = b44_init_one,
2115 .remove = __devexit_p(b44_remove_one),
2116 .suspend = b44_suspend,
2117 .resume = b44_resume,
2120 static int __init b44_init(void)
2122 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2124 /* Setup paramaters for syncing RX/TX DMA descriptors */
2125 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2126 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2128 return pci_module_init(&b44_driver);
2131 static void __exit b44_cleanup(void)
2133 pci_unregister_driver(&b44_driver);
2136 module_init(b44_init);
2137 module_exit(b44_cleanup);