2 * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
4 * This program is free software; you can distribute it and/or modify
5 * it under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 * This program is distributed in the hope it will be useful, but
8 * WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
18 * ========================================================================
19 * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
21 * The AX88180 Ethernet controller is a high performance and highly
22 * integrated local CPU bus Ethernet controller with embedded 40K bytes
23 * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
25 * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
26 * controller that supports both MII and RGMII interfaces and is
27 * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
29 * Please visit ASIX's web site (http://www.asix.com.tw) for more
32 * Module Name : ax88180.c
35 * 09/06/2006 : New release for AX88180 US2 chip.
36 * 07/07/2008 : Fix up the coding style and using inline functions
38 * ========================================================================
45 #include <linux/mii.h>
49 * ===========================================================================
50 * Local SubProgram Declaration
51 * ===========================================================================
53 static void ax88180_rx_handler (struct eth_device *dev);
54 static int ax88180_phy_initial (struct eth_device *dev);
55 static void ax88180_media_config (struct eth_device *dev);
56 static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
57 static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
58 static unsigned short ax88180_mdio_read (struct eth_device *dev,
59 unsigned long regaddr);
60 static void ax88180_mdio_write (struct eth_device *dev,
61 unsigned long regaddr, unsigned short regdata);
64 * ===========================================================================
65 * Local SubProgram Bodies
66 * ===========================================================================
68 static int ax88180_mdio_check_complete (struct eth_device *dev)
71 unsigned short tmpval;
73 /* MDIO read/write should not take more than 10 ms */
75 tmpval = INW (dev, MDIOCTRL);
76 if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
84 ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
86 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
87 unsigned long tmpval = 0;
89 OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
91 if (ax88180_mdio_check_complete (dev))
92 tmpval = INW (dev, MDIODP);
94 printf ("Failed to read PHY register!\n");
96 return (unsigned short)(tmpval & 0xFFFF);
100 ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
101 unsigned short regdata)
103 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
105 OUTW (dev, regdata, MDIODP);
107 OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
109 if (!ax88180_mdio_check_complete (dev))
110 printf ("Failed to write PHY register!\n");
113 static int ax88180_phy_reset (struct eth_device *dev)
115 unsigned short delay_cnt = 500;
117 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
119 /* Wait for the reset to complete, or time out (500 ms) */
120 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
122 if (--delay_cnt == 0) {
123 printf ("Failed to reset PHY!\n");
131 static void ax88180_mac_reset (struct eth_device *dev)
133 unsigned long tmpval;
137 unsigned short offset, value;
140 MISC, MISC_NORMAL}, {
141 RXINDICATOR, DEFAULT_RXINDICATOR}, {
142 TXCMD, DEFAULT_TXCMD}, {
143 TXBS, DEFAULT_TXBS}, {
144 TXDES0, DEFAULT_TXDES0}, {
145 TXDES1, DEFAULT_TXDES1}, {
146 TXDES2, DEFAULT_TXDES2}, {
147 TXDES3, DEFAULT_TXDES3}, {
148 TXCFG, DEFAULT_TXCFG}, {
149 MACCFG2, DEFAULT_MACCFG2}, {
150 MACCFG3, DEFAULT_MACCFG3}, {
151 TXLEN, DEFAULT_TXLEN}, {
152 RXBTHD0, DEFAULT_RXBTHD0}, {
153 RXBTHD1, DEFAULT_RXBTHD1}, {
154 RXFULTHD, DEFAULT_RXFULTHD}, {
155 DOGTHD0, DEFAULT_DOGTHD0}, {
156 DOGTHD1, DEFAULT_DOGTHD1},};
158 OUTW (dev, MISC_RESET_MAC, MISC);
159 tmpval = INW (dev, MISC);
161 for (i = 0; i < ARRAY_SIZE(program_seq); i++)
162 OUTW (dev, program_seq[i].value, program_seq[i].offset);
165 static int ax88180_poll_tx_complete (struct eth_device *dev)
167 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
168 unsigned long tmpval, txbs_txdp;
169 int TimeOutCnt = 10000;
171 txbs_txdp = 1 << priv->NextTxDesc;
173 while (TimeOutCnt--) {
175 tmpval = INW (dev, TXBS);
177 if ((tmpval & txbs_txdp) == 0)
189 static void ax88180_rx_handler (struct eth_device *dev)
191 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
192 unsigned long data_size;
193 unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
195 #if defined (CONFIG_DRIVER_AX88180_16BIT)
196 unsigned short *rxdata = (unsigned short *)net_rx_packets[0];
198 unsigned long *rxdata = (unsigned long *)net_rx_packets[0];
200 unsigned short count;
202 rxcurt_ptr = INW (dev, RXCURT);
203 rxbound_ptr = INW (dev, RXBOUND);
204 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
206 debug ("ax88180: RX original RXBOUND=0x%04x,"
207 " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
209 while (next_ptr != rxcurt_ptr) {
211 OUTW (dev, RX_START_READ, RXINDICATOR);
213 data_size = READ_RXBUF (dev) & 0xFFFF;
215 if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
217 OUTW (dev, RX_STOP_READ, RXINDICATOR);
219 ax88180_mac_reset (dev);
220 printf ("ax88180: Invalid Rx packet length!"
221 " (len=0x%04lx)\n", data_size);
223 debug ("ax88180: RX RXBOUND=0x%04x,"
224 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
228 rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
229 rxbound_ptr &= RX_PAGE_NUM_MASK;
231 /* Comput access times */
232 count = (data_size + priv->PadSize) >> priv->BusWidth;
234 for (i = 0; i < count; i++) {
235 *(rxdata + i) = READ_RXBUF (dev);
238 OUTW (dev, RX_STOP_READ, RXINDICATOR);
240 /* Pass the packet up to the protocol layers. */
241 net_process_received_packet(net_rx_packets[0], data_size);
243 OUTW (dev, rxbound_ptr, RXBOUND);
245 rxcurt_ptr = INW (dev, RXCURT);
246 rxbound_ptr = INW (dev, RXBOUND);
247 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
249 debug ("ax88180: RX updated RXBOUND=0x%04x,"
250 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
256 static int ax88180_phy_initial (struct eth_device *dev)
258 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
259 unsigned long tmp_regval;
260 unsigned short phyaddr;
262 /* Search for first avaliable PHY chipset */
263 #ifdef CONFIG_PHY_ADDR
264 phyaddr = CONFIG_PHY_ADDR;
266 for (phyaddr = 0; phyaddr < 32; ++phyaddr)
269 priv->PhyAddr = phyaddr;
270 priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
271 priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
273 switch (priv->PhyID0) {
274 case MARVELL_ALASKA_PHYSID0:
275 debug("ax88180: Found Marvell Alaska PHY family."
276 " (PHY Addr=0x%x)\n", priv->PhyAddr);
278 switch (priv->PhyID1) {
279 case MARVELL_88E1118_PHYSID1:
280 ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
281 ax88180_mdio_write(dev, M88E1118_CR,
282 M88E1118_CR_DEFAULT);
283 ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
284 ax88180_mdio_write(dev, M88E1118_LEDCTL,
285 M88E1118_LEDCTL_DEFAULT);
286 ax88180_mdio_write(dev, M88E1118_LEDMIX,
287 M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
288 ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
289 default: /* Default to 88E1111 Phy */
290 tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
291 if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
292 ax88180_mdio_write(dev, M88E1111_EXT_SCR,
296 if (ax88180_phy_reset(dev) < 0)
298 ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
302 case CICADA_CIS8201_PHYSID0:
303 debug("ax88180: Found CICADA CIS8201 PHY"
304 " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
306 ax88180_mdio_write(dev, CIS_IMR,
307 (CIS_INT_ENABLE | LINK_CHANGE_INT));
309 /* Set CIS_SMI_PRIORITY bit before force the media mode */
310 tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
311 tmp_regval &= ~CIS_SMI_PRIORITY;
312 ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
317 /* No PHY at this addr */
321 printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
322 priv->PhyID0, priv->PhyAddr);
327 printf("ax88180: Unknown PHY chipset!!\n");
331 static void ax88180_media_config (struct eth_device *dev)
333 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
334 unsigned long bmcr_val, bmsr_val;
335 unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
336 unsigned long RealMediaMode;
339 /* Waiting 2 seconds for PHY link stable */
340 for (i = 0; i < 20000; i++) {
341 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
342 if (bmsr_val & BMSR_LSTATUS) {
348 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
349 debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
351 if (bmsr_val & BMSR_LSTATUS) {
352 bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
354 if (bmcr_val & BMCR_ANENABLE) {
357 * Waiting for Auto-negotiation completion, this may
358 * take up to 5 seconds.
360 debug ("ax88180: Auto-negotiation is "
361 "enabled. Waiting for NWay completion..\n");
362 for (i = 0; i < 50000; i++) {
363 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
364 if (bmsr_val & BMSR_ANEGCOMPLETE) {
370 debug ("ax88180: Auto-negotiation is disabled.\n");
372 debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
373 (unsigned int)bmcr_val, (unsigned int)bmsr_val);
375 /* Get real media mode here */
376 switch (priv->PhyID0) {
377 case MARVELL_ALASKA_PHYSID0:
378 RealMediaMode = get_MarvellPHY_media_mode(dev);
380 case CICADA_CIS8201_PHYSID0:
381 RealMediaMode = get_CicadaPHY_media_mode(dev);
384 RealMediaMode = MEDIA_1000FULL;
388 priv->LinkState = INS_LINK_UP;
390 switch (RealMediaMode) {
392 debug ("ax88180: 1000Mbps Full-duplex mode.\n");
393 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
394 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
395 maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
396 FULLDUPLEX | DEFAULT_MACCFG1;
400 debug ("ax88180: 1000Mbps Half-duplex mode.\n");
401 rxcfg_val = DEFAULT_RXCFG;
402 maccfg0_val = DEFAULT_MACCFG0;
403 maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
407 debug ("ax88180: 100Mbps Full-duplex mode.\n");
408 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
409 maccfg0_val = SPEED100 | TXFLOW_ENABLE
411 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
415 debug ("ax88180: 100Mbps Half-duplex mode.\n");
416 rxcfg_val = DEFAULT_RXCFG;
417 maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
418 maccfg1_val = DEFAULT_MACCFG1;
422 debug ("ax88180: 10Mbps Full-duplex mode.\n");
423 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
424 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
425 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
429 debug ("ax88180: 10Mbps Half-duplex mode.\n");
430 rxcfg_val = DEFAULT_RXCFG;
431 maccfg0_val = DEFAULT_MACCFG0;
432 maccfg1_val = DEFAULT_MACCFG1;
435 debug ("ax88180: Unknow media mode.\n");
436 rxcfg_val = DEFAULT_RXCFG;
437 maccfg0_val = DEFAULT_MACCFG0;
438 maccfg1_val = DEFAULT_MACCFG1;
440 priv->LinkState = INS_LINK_DOWN;
445 rxcfg_val = DEFAULT_RXCFG;
446 maccfg0_val = DEFAULT_MACCFG0;
447 maccfg1_val = DEFAULT_MACCFG1;
449 priv->LinkState = INS_LINK_DOWN;
452 OUTW (dev, rxcfg_val, RXCFG);
453 OUTW (dev, maccfg0_val, MACCFG0);
454 OUTW (dev, maccfg1_val, MACCFG1);
459 static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
461 unsigned long m88_ssr;
462 unsigned long MediaMode;
464 m88_ssr = ax88180_mdio_read (dev, M88_SSR);
465 switch (m88_ssr & SSR_MEDIA_MASK) {
467 MediaMode = MEDIA_1000FULL;
470 MediaMode = MEDIA_1000HALF;
473 MediaMode = MEDIA_100FULL;
476 MediaMode = MEDIA_100HALF;
479 MediaMode = MEDIA_10FULL;
482 MediaMode = MEDIA_10HALF;
485 MediaMode = MEDIA_UNKNOWN;
492 static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
494 unsigned long tmp_regval;
495 unsigned long MediaMode;
497 tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
498 switch (tmp_regval & CIS_MEDIA_MASK) {
500 MediaMode = MEDIA_1000FULL;
503 MediaMode = MEDIA_1000HALF;
506 MediaMode = MEDIA_100FULL;
509 MediaMode = MEDIA_100HALF;
512 MediaMode = MEDIA_10FULL;
515 MediaMode = MEDIA_10HALF;
518 MediaMode = MEDIA_UNKNOWN;
525 static void ax88180_halt (struct eth_device *dev)
527 /* Disable AX88180 TX/RX functions */
528 OUTW (dev, WAKEMOD, CMD);
531 static int ax88180_init (struct eth_device *dev, bd_t * bd)
533 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
534 unsigned short tmp_regval;
536 ax88180_mac_reset (dev);
538 /* Disable interrupt */
539 OUTW (dev, CLEAR_IMR, IMR);
541 /* Disable AX88180 TX/RX functions */
542 OUTW (dev, WAKEMOD, CMD);
544 /* Fill the MAC address */
546 dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
547 OUTW (dev, tmp_regval, MACID0);
550 dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
551 OUTW (dev, tmp_regval, MACID1);
554 dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
555 OUTW (dev, tmp_regval, MACID2);
557 ax88180_media_config (dev);
559 OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
561 /* Initial variables here */
562 priv->FirstTxDesc = TXDP0;
563 priv->NextTxDesc = TXDP0;
565 /* Check if there is any invalid interrupt status and clear it. */
566 OUTW (dev, INW (dev, ISR), ISR);
568 /* Start AX88180 TX/RX functions */
569 OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
574 /* Get a data block via Ethernet */
575 static int ax88180_recv (struct eth_device *dev)
577 unsigned short ISR_Status;
578 unsigned short tmp_regval;
580 /* Read and check interrupt status here. */
581 ISR_Status = INW (dev, ISR);
584 /* Clear the interrupt status */
585 OUTW (dev, ISR_Status, ISR);
587 debug ("\nax88180: The interrupt status = 0x%04x\n",
590 if (ISR_Status & ISR_PHY) {
591 /* Read ISR register once to clear PHY interrupt bit */
592 tmp_regval = ax88180_mdio_read (dev, M88_ISR);
593 ax88180_media_config (dev);
596 if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
597 ax88180_rx_handler (dev);
600 /* Read and check interrupt status again */
601 ISR_Status = INW (dev, ISR);
607 /* Send a data block via Ethernet. */
608 static int ax88180_send(struct eth_device *dev, void *packet, int length)
610 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
611 unsigned short TXDES_addr;
612 unsigned short txcmd_txdp, txbs_txdp;
613 unsigned short tmp_data;
615 #if defined (CONFIG_DRIVER_AX88180_16BIT)
616 volatile unsigned short *txdata = (volatile unsigned short *)packet;
618 volatile unsigned long *txdata = (volatile unsigned long *)packet;
620 unsigned short count;
622 if (priv->LinkState != INS_LINK_UP) {
626 priv->FirstTxDesc = priv->NextTxDesc;
627 txbs_txdp = 1 << priv->FirstTxDesc;
629 debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
631 txcmd_txdp = priv->FirstTxDesc << 13;
632 TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
634 OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
636 /* Comput access times */
637 count = (length + priv->PadSize) >> priv->BusWidth;
639 for (i = 0; i < count; i++) {
640 WRITE_TXBUF (dev, *(txdata + i));
643 OUTW (dev, txcmd_txdp | length, TXCMD);
644 OUTW (dev, txbs_txdp, TXBS);
645 OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
647 priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
650 * Check the available transmit descriptor, if we had exhausted all
651 * transmit descriptor ,then we have to wait for at least one free
654 txbs_txdp = 1 << priv->NextTxDesc;
655 tmp_data = INW (dev, TXBS);
657 if (tmp_data & txbs_txdp) {
658 if (ax88180_poll_tx_complete (dev) < 0) {
659 ax88180_mac_reset (dev);
660 priv->FirstTxDesc = TXDP0;
661 priv->NextTxDesc = TXDP0;
662 printf ("ax88180: Transmit time out occurred!\n");
669 static void ax88180_read_mac_addr (struct eth_device *dev)
671 unsigned short macid0_val, macid1_val, macid2_val;
672 unsigned short tmp_regval;
675 /* Reload MAC address from EEPROM */
676 OUTW (dev, RELOAD_EEPROM, PROMCTRL);
678 /* Waiting for reload eeprom completion */
679 for (i = 0; i < 500; i++) {
680 tmp_regval = INW (dev, PROMCTRL);
681 if ((tmp_regval & RELOAD_EEPROM) == 0)
686 /* Get MAC addresses */
687 macid0_val = INW (dev, MACID0);
688 macid1_val = INW (dev, MACID1);
689 macid2_val = INW (dev, MACID2);
691 if (((macid0_val | macid1_val | macid2_val) != 0) &&
692 ((macid0_val & 0x01) == 0)) {
693 dev->enetaddr[0] = (unsigned char)macid0_val;
694 dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
695 dev->enetaddr[2] = (unsigned char)macid1_val;
696 dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
697 dev->enetaddr[4] = (unsigned char)macid2_val;
698 dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
702 /* Exported SubProgram Bodies */
703 int ax88180_initialize (bd_t * bis)
705 struct eth_device *dev;
706 struct ax88180_private *priv;
708 dev = (struct eth_device *)malloc (sizeof *dev);
713 memset (dev, 0, sizeof *dev);
715 priv = (struct ax88180_private *)malloc (sizeof (*priv));
720 memset (priv, 0, sizeof *priv);
722 strcpy(dev->name, "ax88180");
723 dev->iobase = AX88180_BASE;
725 dev->init = ax88180_init;
726 dev->halt = ax88180_halt;
727 dev->send = ax88180_send;
728 dev->recv = ax88180_recv;
730 priv->BusWidth = BUS_WIDTH_32;
732 #if defined (CONFIG_DRIVER_AX88180_16BIT)
733 OUTW (dev, (START_BASE >> 8), BASE);
734 OUTW (dev, DECODE_EN, DECODE);
736 priv->BusWidth = BUS_WIDTH_16;
740 ax88180_mac_reset (dev);
742 /* Disable interrupt */
743 OUTW (dev, CLEAR_IMR, IMR);
745 /* Disable AX88180 TX/RX functions */
746 OUTW (dev, WAKEMOD, CMD);
748 ax88180_read_mac_addr (dev);
752 return ax88180_phy_initial (dev);