2 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
3 * Jens Scharsig (esw@bus-elektronik.de)
6 * Author : Hamid Ikdoumi (Atmel)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifndef CONFIG_AT91_LEGACY
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/at91_emac.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
35 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */
36 #include <asm/arch-at91/at91rm9200.h>
37 #include <asm/arch-at91/hardware.h>
38 #include <asm/arch-at91/at91_emac.h>
39 #include <asm/arch-at91/at91_pmc.h>
40 #include <asm/arch-at91/at91_pio.h>
46 #include <linux/mii.h>
51 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
52 #error AT91 EMAC supports max 1024 RX buffers. \
53 Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
56 #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
57 #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
60 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
61 #if (AT91C_MASTER_CLOCK > 80000000)
62 #define HCLK_DIV AT91_EMAC_CFG_MCLK_64
63 #elif (AT91C_MASTER_CLOCK > 40000000)
64 #define HCLK_DIV AT91_EMAC_CFG_MCLK_32
65 #elif (AT91C_MASTER_CLOCK > 20000000)
66 #define HCLK_DIV AT91_EMAC_CFG_MCLK_16
68 #define HCLK_DIV AT91_EMAC_CFG_MCLK_8
72 #define DEBUG_AT91EMAC(...) printf(__VA_ARGS__);
74 #define DEBUG_AT91EMAC(...)
78 #define DEBUG_AT91PHY(...) printf(__VA_ARGS__);
80 #define DEBUG_AT91PHY(...)
83 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
84 #define VERBOSEP(...) printf(__VA_ARGS__);
89 #define RBF_ADDR 0xfffffffc
90 #define RBF_OWNER (1<<0)
91 #define RBF_WRAP (1<<1)
92 #define RBF_BROADCAST (1<<31)
93 #define RBF_MULTICAST (1<<30)
94 #define RBF_UNICAST (1<<29)
95 #define RBF_EXTERNAL (1<<28)
96 #define RBF_UNKOWN (1<<27)
97 #define RBF_SIZE 0x07ff
98 #define RBF_LOCAL4 (1<<26)
99 #define RBF_LOCAL3 (1<<25)
100 #define RBF_LOCAL2 (1<<24)
101 #define RBF_LOCAL1 (1<<23)
103 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
104 #define RBF_FRAMELEN 0x600
107 unsigned long addr, size;
111 rbf_t rbfdt[RBF_FRAMEMAX];
112 unsigned long rbindex;
115 void at91emac_EnableMDIO(at91_emac_t *at91mac)
117 /* Mac CTRL reg set for MDIO enable */
118 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
121 void at91emac_DisableMDIO(at91_emac_t *at91mac)
123 /* Mac CTRL reg set for MDIO disable */
124 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
127 int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
128 unsigned char reg, unsigned short *value)
130 at91emac_EnableMDIO(at91mac);
132 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
133 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
134 AT91_EMAC_MAN_PHYA(addr),
137 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
139 at91emac_DisableMDIO(at91mac);
141 DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value)
146 int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
147 unsigned char reg, unsigned short value)
149 DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)
151 at91emac_EnableMDIO(at91mac);
153 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
154 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
155 AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
159 at91emac_DisableMDIO(at91mac);
163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
165 at91_emac_t *get_emacbase_by_name(char *devname)
167 struct eth_device *netdev;
169 netdev = eth_get_dev_by_name(devname);
170 return (at91_emac_t *) netdev->iobase;
173 int at91emac_mii_read(char *devname, unsigned char addr,
174 unsigned char reg, unsigned short *value)
178 emac = get_emacbase_by_name(devname);
179 at91emac_read(emac , addr, reg, value);
184 int at91emac_mii_write(char *devname, unsigned char addr,
185 unsigned char reg, unsigned short value)
189 emac = get_emacbase_by_name(devname);
190 at91emac_write(emac, addr, reg, value);
196 static int at91emac_phy_reset(struct eth_device *netdev)
202 emac = (at91_emac_t *) netdev->iobase;
204 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
205 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
207 VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
208 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
209 (BMCR_ANENABLE | BMCR_ANRESTART));
211 for (i = 0; i < 100000 / 100; i++) {
212 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
214 if (status & BMSR_ANEGCOMPLETE)
219 if (status & BMSR_ANEGCOMPLETE) {
220 VERBOSEP("%s: Autonegotiation complete\n", netdev->name);
222 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
223 netdev->name, status);
229 static int at91emac_phy_init(struct eth_device *netdev)
231 u16 phy_id, status, adv, lpa;
232 int media, speed, duplex;
236 emac = (at91_emac_t *) netdev->iobase;
238 /* Check if the PHY is up to snuff... */
239 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
240 MII_PHYSID1, &phy_id);
241 if (phy_id == 0xffff) {
242 printf("%s: No PHY present\n", netdev->name);
246 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
249 if (!(status & BMSR_LSTATUS)) {
250 /* Try to re-negotiate if we don't have link already. */
251 if (at91emac_phy_reset(netdev))
254 for (i = 0; i < 100000 / 100; i++) {
255 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
257 if (status & BMSR_LSTATUS)
262 if (!(status & BMSR_LSTATUS)) {
263 VERBOSEP("%s: link down\n", netdev->name);
266 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
267 MII_ADVERTISE, &adv);
268 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
270 media = mii_nway_result(lpa & adv);
271 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
273 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
274 VERBOSEP("%s: link up, %sMbps %s-duplex\n",
276 speed ? "100" : "10",
277 duplex ? "full" : "half");
282 int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
284 unsigned short stat1;
286 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
288 if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
291 if (stat1 & BMSR_100FULL) {
292 /*set Emac for 100BaseTX and Full Duplex */
293 writel(readl(&emac->cfg) |
294 AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
299 if (stat1 & BMSR_10FULL) {
300 /*set MII for 10BaseT and Full Duplex */
301 writel((readl(&emac->cfg) &
302 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
303 ) | AT91_EMAC_CFG_FD,
308 if (stat1 & BMSR_100HALF) {
309 /*set MII for 100BaseTX and Half Duplex */
310 writel((readl(&emac->cfg) &
311 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
312 ) | AT91_EMAC_CFG_SPD,
317 if (stat1 & BMSR_10HALF) {
318 /*set MII for 10BaseT and Half Duplex */
319 writel((readl(&emac->cfg) &
320 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
327 static int at91emac_init(struct eth_device *netdev, bd_t *bd)
333 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
334 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
336 emac = (at91_emac_t *) netdev->iobase;
337 dev = (emac_device *) netdev->priv;
339 /* PIO Disable Register */
340 value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC |
341 AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 |
342 AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS |
343 AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 |
344 AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK;
346 writel(value, &pio->pioa.pdr);
347 writel(value, &pio->pioa.asr);
350 value = AT91_PMX_BA_ERXCK;
352 value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL |
353 AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 |
354 AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER |
355 AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2;
357 writel(value, &pio->piob.pdr);
358 writel(value, &pio->piob.bsr);
360 writel(1 << AT91_ID_EMAC, &pmc->pcer);
361 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
363 /* Init Ethernet buffers */
364 for (i = 0; i < RBF_FRAMEMAX; i++) {
365 dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
366 dev->rbfdt[i].size = 0;
368 dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
370 writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
372 writel(readl(&emac->rsr) &
373 ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
376 value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
379 value |= AT91_EMAC_CFG_RMII;
381 writel(value, &emac->cfg);
383 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
386 if (!at91emac_phy_init(netdev)) {
387 at91emac_UpdateLinkSpeed(emac);
393 static void at91emac_halt(struct eth_device *netdev)
397 emac = (at91_emac_t *) netdev->iobase;
398 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
400 DEBUG_AT91EMAC("halt MAC\n");
403 static int at91emac_send(struct eth_device *netdev, volatile void *packet,
408 emac = (at91_emac_t *) netdev->iobase;
410 while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
412 writel((u32) packet, &emac->tar);
413 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
414 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
416 DEBUG_AT91EMAC("Send %d \n", length);
417 writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
421 static int at91emac_recv(struct eth_device *netdev)
428 emac = (at91_emac_t *) netdev->iobase;
429 dev = (emac_device *) netdev->priv;
431 rbfp = &dev->rbfdt[dev->rbindex];
432 while (rbfp->addr & RBF_OWNER) {
433 size = rbfp->size & RBF_SIZE;
434 NetReceive(NetRxPackets[dev->rbindex], size);
436 DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n",
437 dev->rbindex, size, rbfp->addr);
439 rbfp->addr &= ~RBF_OWNER;
441 if (dev->rbindex < (RBF_FRAMEMAX-1))
446 rbfp = &(dev->rbfdt[dev->rbindex]);
447 if (!(rbfp->addr & RBF_OWNER))
448 writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
452 if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
453 /* EMAC silicon bug 41.3.1 workaround 1 */
454 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
455 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
457 printf("%s: reset receiver (EMAC dead lock bug)\n",
463 static int at91emac_write_hwaddr(struct eth_device *netdev)
467 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
468 emac = (at91_emac_t *) netdev->iobase;
469 dev = (emac_device *) netdev->priv;
471 writel(1 << AT91_ID_EMAC, &pmc->pcer);
472 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
473 cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
474 cpu_to_le32(*((u32 *)netdev->enetaddr)));
475 writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
476 writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
477 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
478 readl(&emac->sa2h), readl(&emac->sa2l));
482 int at91emac_register(bd_t *bis, unsigned long iobase)
485 emac_device *emacfix;
486 struct eth_device *dev;
489 iobase = AT91_EMAC_BASE;
490 emac = malloc(sizeof(*emac)+512);
493 dev = malloc(sizeof(*dev));
498 /* alignment as per Errata (64 bytes) is insufficient! */
499 emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
500 memset(emacfix, 0, sizeof(emac_device));
502 memset(dev, 0, sizeof(*dev));
504 sprintf(dev->name, "AT91 EMAC");
506 sprintf(dev->name, "AT91 EMAC RMII");
508 dev->iobase = iobase;
510 dev->init = at91emac_init;
511 dev->halt = at91emac_halt;
512 dev->send = at91emac_send;
513 dev->recv = at91emac_recv;
514 dev->write_hwaddr = at91emac_write_hwaddr;
518 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
519 miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);