drivers/net/at91_emac.c

   1 /*
   2  * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
   3  * Jens Scharsig (esw@bus-elektronik.de)
   4  *
   5  * (C) Copyright 2003
   6  * Author : Hamid Ikdoumi (Atmel)
   7
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #ifndef CONFIG_AT91_LEGACY
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/at91_emac.h>
  16 #include <asm/arch/at91_pmc.h>
  17 #include <asm/arch/at91_pio.h>
  18 #else
  19 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */
  20 #include <asm/arch-at91/at91rm9200.h>
  21 #include <asm/arch-at91/hardware.h>
  22 #include <asm/arch-at91/at91_emac.h>
  23 #include <asm/arch-at91/at91_pmc.h>
  24 #include <asm/arch-at91/at91_pio.h>
  25 #endif
  26 #include <net.h>
  27 #include <netdev.h>
  28 #include <malloc.h>
  29 #include <miiphy.h>
  30 #include <linux/mii.h>
  31
  32 #undef MII_DEBUG
  33 #undef ET_DEBUG
  34
  35 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
  36 #error AT91 EMAC supports max 1024 RX buffers. \
  37         Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
  38 #endif
  39
  40 #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
  41 #define CONFIG_DRIVER_AT91EMAC_PHYADDR  0
  42 #endif
  43
  44 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
  45 #if (AT91C_MASTER_CLOCK > 80000000)
  46         #define HCLK_DIV        AT91_EMAC_CFG_MCLK_64
  47 #elif (AT91C_MASTER_CLOCK > 40000000)
  48         #define HCLK_DIV        AT91_EMAC_CFG_MCLK_32
  49 #elif (AT91C_MASTER_CLOCK > 20000000)
  50         #define HCLK_DIV        AT91_EMAC_CFG_MCLK_16
  51 #else
  52         #define HCLK_DIV        AT91_EMAC_CFG_MCLK_8
  53 #endif
  54
  55 #ifdef ET_DEBUG
  56 #define DEBUG_AT91EMAC  1
  57 #else
  58 #define DEBUG_AT91EMAC  0
  59 #endif
  60
  61 #ifdef MII_DEBUG
  62 #define DEBUG_AT91PHY   1
  63 #else
  64 #define DEBUG_AT91PHY   0
  65 #endif
  66
  67 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
  68 #define VERBOSEP        1
  69 #else
  70 #define VERBOSEP        0
  71 #endif
  72
  73 #define RBF_ADDR      0xfffffffc
  74 #define RBF_OWNER     (1<<0)
  75 #define RBF_WRAP      (1<<1)
  76 #define RBF_BROADCAST (1<<31)
  77 #define RBF_MULTICAST (1<<30)
  78 #define RBF_UNICAST   (1<<29)
  79 #define RBF_EXTERNAL  (1<<28)
  80 #define RBF_UNKNOWN   (1<<27)
  81 #define RBF_SIZE      0x07ff
  82 #define RBF_LOCAL4    (1<<26)
  83 #define RBF_LOCAL3    (1<<25)
  84 #define RBF_LOCAL2    (1<<24)
  85 #define RBF_LOCAL1    (1<<23)
  86
  87 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
  88 #define RBF_FRAMELEN 0x600
  89
  90 typedef struct {
  91         unsigned long addr, size;
  92 } rbf_t;
  93
  94 typedef struct {
  95         rbf_t           rbfdt[RBF_FRAMEMAX];
  96         unsigned long   rbindex;
  97 } emac_device;
  98
  99 void at91emac_EnableMDIO(at91_emac_t *at91mac)
 100 {
 101         /* Mac CTRL reg set for MDIO enable */
 102         writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
 103 }
 104
 105 void at91emac_DisableMDIO(at91_emac_t *at91mac)
 106 {
 107         /* Mac CTRL reg set for MDIO disable */
 108         writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
 109 }
 110
 111 int  at91emac_read(at91_emac_t *at91mac, unsigned char addr,
 112                 unsigned char reg, unsigned short *value)
 113 {
 114         unsigned long netstat;
 115         at91emac_EnableMDIO(at91mac);
 116
 117         writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
 118                 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
 119                 AT91_EMAC_MAN_PHYA(addr),
 120                 &at91mac->man);
 121
 122         do {
 123                 netstat = readl(&at91mac->sr);
 124                 debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
 125         } while (!(netstat & AT91_EMAC_SR_IDLE));
 126
 127         *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
 128
 129         at91emac_DisableMDIO(at91mac);
 130
 131         debug_cond(DEBUG_AT91PHY,
 132                 "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
 133
 134         return 0;
 135 }
 136
 137 int  at91emac_write(at91_emac_t *at91mac, unsigned char addr,
 138                 unsigned char reg, unsigned short value)
 139 {
 140         unsigned long netstat;
 141         debug_cond(DEBUG_AT91PHY,
 142                 "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
 143
 144         at91emac_EnableMDIO(at91mac);
 145
 146         writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
 147                 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
 148                 AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
 149                 &at91mac->man);
 150
 151         do {
 152                 netstat = readl(&at91mac->sr);
 153                 debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
 154         } while (!(netstat & AT91_EMAC_SR_IDLE));
 155
 156         at91emac_DisableMDIO(at91mac);
 157
 158         return 0;
 159 }
 160
 161 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 162
 163 at91_emac_t *get_emacbase_by_name(const char *devname)
 164 {
 165         struct eth_device *netdev;
 166
 167         netdev = eth_get_dev_by_name(devname);
 168         return (at91_emac_t *) netdev->iobase;
 169 }
 170
 171 int  at91emac_mii_read(const char *devname, unsigned char addr,
 172                 unsigned char reg, unsigned short *value)
 173 {
 174         at91_emac_t *emac;
 175
 176         emac = get_emacbase_by_name(devname);
 177         at91emac_read(emac , addr, reg, value);
 178         return 0;
 179 }
 180
 181
 182 int  at91emac_mii_write(const char *devname, unsigned char addr,
 183                 unsigned char reg, unsigned short value)
 184 {
 185         at91_emac_t *emac;
 186
 187         emac = get_emacbase_by_name(devname);
 188         at91emac_write(emac, addr, reg, value);
 189         return 0;
 190 }
 191
 192 #endif
 193
 194 static int at91emac_phy_reset(struct eth_device *netdev)
 195 {
 196         int i;
 197         u16 status, adv;
 198         at91_emac_t *emac;
 199
 200         emac = (at91_emac_t *) netdev->iobase;
 201
 202         adv = ADVERTISE_CSMA | ADVERTISE_ALL;
 203         at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 204                 MII_ADVERTISE, adv);
 205         debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
 206         at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
 207                 (BMCR_ANENABLE | BMCR_ANRESTART));
 208
 209         for (i = 0; i < 30000; i++) {
 210                 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 211                         MII_BMSR, &status);
 212                 if (status & BMSR_ANEGCOMPLETE)
 213                         break;
 214                 udelay(100);
 215         }
 216
 217         if (status & BMSR_ANEGCOMPLETE) {
 218                 debug_cond(VERBOSEP,
 219                         "%s: Autonegotiation complete\n", netdev->name);
 220         } else {
 221                 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
 222                        netdev->name, status);
 223                 return -1;
 224         }
 225         return 0;
 226 }
 227
 228 static int at91emac_phy_init(struct eth_device *netdev)
 229 {
 230         u16 phy_id, status, adv, lpa;
 231         int media, speed, duplex;
 232         int i;
 233         at91_emac_t *emac;
 234
 235         emac = (at91_emac_t *) netdev->iobase;
 236
 237         /* Check if the PHY is up to snuff... */
 238         at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 239                 MII_PHYSID1, &phy_id);
 240         if (phy_id == 0xffff) {
 241                 printf("%s: No PHY present\n", netdev->name);
 242                 return -1;
 243         }
 244
 245         at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 246                 MII_BMSR, &status);
 247
 248         if (!(status & BMSR_LSTATUS)) {
 249                 /* Try to re-negotiate if we don't have link already. */
 250                 if (at91emac_phy_reset(netdev))
 251                         return -2;
 252
 253                 for (i = 0; i < 100000 / 100; i++) {
 254                         at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 255                                 MII_BMSR, &status);
 256                         if (status & BMSR_LSTATUS)
 257                                 break;
 258                         udelay(100);
 259                 }
 260         }
 261         if (!(status & BMSR_LSTATUS)) {
 262                 debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
 263                 return -3;
 264         } else {
 265                 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 266                         MII_ADVERTISE, &adv);
 267                 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 268                         MII_LPA, &lpa);
 269                 media = mii_nway_result(lpa & adv);
 270                 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
 271                          ? 1 : 0);
 272                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
 273                 debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
 274                        netdev->name,
 275                        speed ? "100" : "10",
 276                        duplex ? "full" : "half");
 277         }
 278         return 0;
 279 }
 280
 281 int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
 282 {
 283         unsigned short stat1;
 284
 285         at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
 286
 287         if (!(stat1 & BMSR_LSTATUS))    /* link status up? */
 288                 return -1;
 289
 290         if (stat1 & BMSR_100FULL) {
 291                 /*set Emac for 100BaseTX and Full Duplex  */
 292                 writel(readl(&emac->cfg) |
 293                         AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
 294                         &emac->cfg);
 295                 return 0;
 296         }
 297
 298         if (stat1 & BMSR_10FULL) {
 299                 /*set MII for 10BaseT and Full Duplex  */
 300                 writel((readl(&emac->cfg) &
 301                         ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
 302                         ) | AT91_EMAC_CFG_FD,
 303                         &emac->cfg);
 304                 return 0;
 305         }
 306
 307         if (stat1 & BMSR_100HALF) {
 308                 /*set MII for 100BaseTX and Half Duplex  */
 309                 writel((readl(&emac->cfg) &
 310                         ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
 311                         ) | AT91_EMAC_CFG_SPD,
 312                         &emac->cfg);
 313                 return 0;
 314         }
 315
 316         if (stat1 & BMSR_10HALF) {
 317                 /*set MII for 10BaseT and Half Duplex  */
 318                 writel((readl(&emac->cfg) &
 319                         ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
 320                         &emac->cfg);
 321                 return 0;
 322         }
 323         return 0;
 324 }
 325
 326 static int at91emac_init(struct eth_device *netdev, bd_t *bd)
 327 {
 328         int i;
 329         u32 value;
 330         emac_device *dev;
 331         at91_emac_t *emac;
 332         at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
 333         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 334
 335         emac = (at91_emac_t *) netdev->iobase;
 336         dev = (emac_device *) netdev->priv;
 337
 338         /* PIO Disable Register */
 339         value = ATMEL_PMX_AA_EMDIO |    ATMEL_PMX_AA_EMDC |
 340                 ATMEL_PMX_AA_ERXER |    ATMEL_PMX_AA_ERX1 |
 341                 ATMEL_PMX_AA_ERX0 |     ATMEL_PMX_AA_ECRS |
 342                 ATMEL_PMX_AA_ETX1 |     ATMEL_PMX_AA_ETX0 |
 343                 ATMEL_PMX_AA_ETXEN |    ATMEL_PMX_AA_EREFCK;
 344
 345         writel(value, &pio->pioa.pdr);
 346         writel(value, &pio->pioa.asr);
 347
 348 #ifdef CONFIG_RMII
 349         value = ATMEL_PMX_BA_ERXCK;
 350 #else
 351         value = ATMEL_PMX_BA_ERXCK |    ATMEL_PMX_BA_ECOL |
 352                 ATMEL_PMX_BA_ERXDV |    ATMEL_PMX_BA_ERX3 |
 353                 ATMEL_PMX_BA_ERX2 |     ATMEL_PMX_BA_ETXER |
 354                 ATMEL_PMX_BA_ETX3 |     ATMEL_PMX_BA_ETX2;
 355 #endif
 356         writel(value, &pio->piob.pdr);
 357         writel(value, &pio->piob.bsr);
 358
 359         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 360         writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
 361
 362         /* Init Ethernet buffers */
 363         for (i = 0; i < RBF_FRAMEMAX; i++) {
 364                 dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
 365                 dev->rbfdt[i].size = 0;
 366         }
 367         dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
 368         dev->rbindex = 0;
 369         writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
 370
 371         writel(readl(&emac->rsr) &
 372                 ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
 373                 &emac->rsr);
 374
 375         value = AT91_EMAC_CFG_CAF |     AT91_EMAC_CFG_NBC |
 376                 HCLK_DIV;
 377 #ifdef CONFIG_RMII
 378         value |= AT91_EMAC_CFG_RMII;
 379 #endif
 380         writel(value, &emac->cfg);
 381
 382         writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
 383                 &emac->ctl);
 384
 385         if (!at91emac_phy_init(netdev)) {
 386                 at91emac_UpdateLinkSpeed(emac);
 387                 return 0;
 388         }
 389         return -1;
 390 }
 391
 392 static void at91emac_halt(struct eth_device *netdev)
 393 {
 394         at91_emac_t *emac;
 395
 396         emac = (at91_emac_t *) netdev->iobase;
 397         writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
 398                 &emac->ctl);
 399         debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
 400 }
 401
 402 static int at91emac_send(struct eth_device *netdev, void *packet, int length)
 403 {
 404         at91_emac_t *emac;
 405
 406         emac = (at91_emac_t *) netdev->iobase;
 407
 408         while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
 409                 ;
 410         writel((u32) packet, &emac->tar);
 411         writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
 412         while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
 413                 ;
 414         debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
 415         writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
 416         return 0;
 417 }
 418
 419 static int at91emac_recv(struct eth_device *netdev)
 420 {
 421         emac_device *dev;
 422         at91_emac_t *emac;
 423         rbf_t *rbfp;
 424         int size;
 425
 426         emac = (at91_emac_t *) netdev->iobase;
 427         dev = (emac_device *) netdev->priv;
 428
 429         rbfp = &dev->rbfdt[dev->rbindex];
 430         while (rbfp->addr & RBF_OWNER)  {
 431                 size = rbfp->size & RBF_SIZE;
 432                 NetReceive(NetRxPackets[dev->rbindex], size);
 433
 434                 debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
 435                         dev->rbindex, size, rbfp->addr);
 436
 437                 rbfp->addr &= ~RBF_OWNER;
 438                 rbfp->size = 0;
 439                 if (dev->rbindex < (RBF_FRAMEMAX-1))
 440                         dev->rbindex++;
 441                 else
 442                         dev->rbindex = 0;
 443
 444                 rbfp = &(dev->rbfdt[dev->rbindex]);
 445                 if (!(rbfp->addr & RBF_OWNER))
 446                         writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
 447                                 &emac->rsr);
 448         }
 449
 450         if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
 451                 /* EMAC silicon bug 41.3.1 workaround 1 */
 452                 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
 453                 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
 454                 dev->rbindex = 0;
 455                 printf("%s: reset receiver (EMAC dead lock bug)\n",
 456                         netdev->name);
 457         }
 458         return 0;
 459 }
 460
 461 static int at91emac_write_hwaddr(struct eth_device *netdev)
 462 {
 463         at91_emac_t *emac;
 464         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 465         emac = (at91_emac_t *) netdev->iobase;
 466
 467         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 468         debug_cond(DEBUG_AT91EMAC,
 469                 "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
 470                 netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
 471                 netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
 472         writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
 473                         netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
 474                         &emac->sa2l);
 475         writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
 476         debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
 477                 readl(&emac->sa2h), readl(&emac->sa2l));
 478         return 0;
 479 }
 480
 481 int at91emac_register(bd_t *bis, unsigned long iobase)
 482 {
 483         emac_device *emac;
 484         emac_device *emacfix;
 485         struct eth_device *dev;
 486
 487         if (iobase == 0)
 488                 iobase = ATMEL_BASE_EMAC;
 489         emac = malloc(sizeof(*emac)+512);
 490         if (emac == NULL)
 491                 return -1;
 492         dev = malloc(sizeof(*dev));
 493         if (dev == NULL) {
 494                 free(emac);
 495                 return -1;
 496         }
 497         /* alignment as per Errata (64 bytes) is insufficient! */
 498         emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
 499         memset(emacfix, 0, sizeof(emac_device));
 500
 501         memset(dev, 0, sizeof(*dev));
 502         sprintf(dev->name, "emac");
 503         dev->iobase = iobase;
 504         dev->priv = emacfix;
 505         dev->init = at91emac_init;
 506         dev->halt = at91emac_halt;
 507         dev->send = at91emac_send;
 508         dev->recv = at91emac_recv;
 509         dev->write_hwaddr = at91emac_write_hwaddr;
 510
 511         eth_register(dev);
 512
 513 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 514         miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
 515 #endif
 516         return 1;
 517 }