2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #include <asm/cache.h>
17 #include <asm/dma-mapping.h>
19 #include "altera_tse.h"
21 /* sgdma debug - print descriptor */
22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc)
24 debug("SGDMA DEBUG :\n");
25 debug("desc->source : 0x%x \n", (unsigned int)desc->source);
26 debug("desc->destination : 0x%x \n", (unsigned int)desc->destination);
27 debug("desc->next : 0x%x \n", (unsigned int)desc->next);
28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad);
29 debug("desc->destination_pad : 0x%x \n",
30 (unsigned int)desc->destination_pad);
31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad);
32 debug("desc->bytes_to_transfer : 0x%x \n",
33 (unsigned int)desc->bytes_to_transfer);
34 debug("desc->actual_bytes_transferred : 0x%x \n",
35 (unsigned int)desc->actual_bytes_transferred);
36 debug("desc->descriptor_status : 0x%x \n",
37 (unsigned int)desc->descriptor_status);
38 debug("desc->descriptor_control : 0x%x \n",
39 (unsigned int)desc->descriptor_control);
42 /* This is a generic routine that the SGDMA mode-specific routines
43 * call to populate a descriptor.
44 * arg1 :pointer to first SGDMA descriptor.
45 * arg2 :pointer to next SGDMA descriptor.
46 * arg3 :Address to where data to be written.
47 * arg4 :Address from where data to be read.
48 * arg5 :no of byte to transaction.
49 * arg6 :variable indicating to generate start of packet or not
54 * arg11 :atlantic_channel number
56 static void alt_sgdma_construct_descriptor_burst(
57 volatile struct alt_sgdma_descriptor *desc,
58 volatile struct alt_sgdma_descriptor *next,
59 unsigned int *read_addr,
60 unsigned int *write_addr,
61 unsigned short length_or_eop,
64 int write_fixed_or_sop,
67 unsigned char atlantic_channel)
70 * Mark the "next" descriptor as "not" owned by hardware. This prevents
71 * The SGDMA controller from continuing to process the chain. This is
72 * done as a single IO write to bypass cache, without flushing
73 * the entire descriptor, since only the 8-bit descriptor status must
77 debug("Next descriptor not defined!!\n");
79 next->descriptor_control = (next->descriptor_control &
80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);
82 desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF);
84 (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF);
85 desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF);
86 desc->source_pad = 0x0;
87 desc->destination_pad = 0x0;
89 desc->bytes_to_transfer = length_or_eop;
90 desc->actual_bytes_transferred = 0;
91 desc->descriptor_status = 0x0;
93 /* SGDMA burst not currently supported */
95 desc->write_burst = 0;
98 * Set the descriptor control block as follows:
99 * - Set "owned by hardware" bit
100 * - Optionally set "generate EOP" bit
101 * - Optionally set the "read from fixed address" bit
102 * - Optionally set the "write to fixed address bit (which serves
103 * serves as a "generate SOP" control bit in memory-to-stream mode).
104 * - Set the 4-bit atlantic channel, if specified
106 * Note this step is performed after all other descriptor information
107 * has been filled out so that, if the controller already happens to be
108 * pointing at this descriptor, it will not run (via the "owned by
109 * hardware" bit) until all other descriptor has been set up.
112 desc->descriptor_control =
113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) |
115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) |
117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) |
118 (write_fixed_or_sop ?
119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) |
120 (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0)
124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev,
125 volatile struct alt_sgdma_descriptor *desc)
130 /* Wait for any pending transfers to complete */
131 alt_sgdma_print_desc(desc);
132 status = dev->status;
135 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
136 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
140 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
141 debug("Timeout waiting sgdma in do sync!\n");
144 * Clear any (previous) status register information
145 * that might occlude our error checking later.
149 /* Point the controller at the descriptor */
150 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
151 debug("next desc in sgdma 0x%x\n",
152 (unsigned int)dev->next_descriptor_pointer);
155 * Set up SGDMA controller to:
156 * - Disable interrupt generation
157 * - Run once a valid descriptor is written to controller
158 * - Stop on an error with any particular descriptor
160 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
163 /* Wait for the descriptor (chain) to complete */
164 status = dev->status;
165 debug("wait for sgdma....");
166 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK)
171 dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK));
173 /* Get & clear status register contents */
174 status = dev->status;
177 /* we really should check if the transfer completes properly */
178 debug("tx sgdma status = 0x%x", status);
182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
183 volatile struct alt_sgdma_descriptor *desc)
188 /* Wait for any pending transfers to complete */
189 alt_sgdma_print_desc(desc);
190 status = dev->status;
193 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
194 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
198 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
199 debug("Timeout waiting sgdma in do async!\n");
202 * Clear the RUN bit in the control register. This is needed
203 * to restart the SGDMA engine later on.
208 * Clear any (previous) status register information
209 * that might occlude our error checking later.
213 /* Point the controller at the descriptor */
214 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
217 * Set up SGDMA controller to:
218 * - Disable interrupt generation
219 * - Run once a valid descriptor is written to controller
220 * - Stop on an error with any particular descriptor
222 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
225 /* we really should check if the transfer completes properly */
229 /* u-boot interface */
230 static int tse_adjust_link(struct altera_tse_priv *priv)
234 refvar = priv->mac_dev->command_config.image;
236 if (!(priv->duplexity))
237 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
239 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
241 switch (priv->speed) {
243 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
244 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
247 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
248 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
251 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
252 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
255 priv->mac_dev->command_config.image = refvar;
260 static int tse_eth_send(struct eth_device *dev,
261 volatile void *packet, int length)
263 struct altera_tse_priv *priv = dev->priv;
264 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
265 volatile struct alt_sgdma_descriptor *tx_desc =
266 (volatile struct alt_sgdma_descriptor *)priv->tx_desc;
268 volatile struct alt_sgdma_descriptor *tx_desc_cur =
269 (volatile struct alt_sgdma_descriptor *)&tx_desc[0];
271 flush_dcache_range((unsigned long)packet,
272 (unsigned long)packet + length);
273 alt_sgdma_construct_descriptor_burst(
274 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
275 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
276 (unsigned int *)packet, /* read addr */
278 length, /* length or EOP ,will change for each tx */
280 0x0, /* read fixed */
281 0x1, /* write fixed or sop */
282 0x0, /* read burst */
283 0x0, /* write burst */
286 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length);
288 /* send the packet */
289 debug("sending packet\n");
290 alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur);
291 debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred);
292 return tx_desc_cur->actual_bytes_transferred;
295 static int tse_eth_rx(struct eth_device *dev)
297 int packet_length = 0;
298 struct altera_tse_priv *priv = dev->priv;
299 volatile struct alt_sgdma_descriptor *rx_desc =
300 (volatile struct alt_sgdma_descriptor *)priv->rx_desc;
301 volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0];
303 if (rx_desc_cur->descriptor_status &
304 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
305 debug("got packet\n");
306 packet_length = rx_desc->actual_bytes_transferred;
307 NetReceive(NetRxPackets[0], packet_length);
309 /* start descriptor again */
310 flush_dcache_range((unsigned long)(NetRxPackets[0]),
311 (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN);
312 alt_sgdma_construct_descriptor_burst(
313 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
314 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
315 (unsigned int)0x0, /* read addr */
316 (unsigned int *)NetRxPackets[0],
317 0x0, /* length or EOP */
319 0x0, /* read fixed */
320 0x0, /* write fixed or sop */
321 0x0, /* read burst */
322 0x0, /* write burst */
326 /* setup the sgdma */
327 alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]);
329 return packet_length;
335 static void tse_eth_halt(struct eth_device *dev)
337 /* don't do anything! */
338 /* this gets called after each uboot */
339 /* network command. don't need to reset the thing all of the time */
342 static void tse_eth_reset(struct eth_device *dev)
344 /* stop sgdmas, disable tse receive */
345 struct altera_tse_priv *priv = dev->priv;
346 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
347 volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
348 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
350 volatile struct alt_sgdma_descriptor *rx_desc =
351 (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0];
353 /* clear rx desc & wait for sgdma to complete */
354 rx_desc->descriptor_control = 0;
355 rx_sgdma->control = 0;
357 while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
358 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
362 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
363 debug("Timeout waiting for rx sgdma!\n");
364 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
365 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
369 tx_sgdma->control = 0;
370 while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
371 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
375 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
376 debug("Timeout waiting for tx sgdma!\n");
377 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
378 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
381 mac_dev->command_config.bits.transmit_enable = 1;
382 mac_dev->command_config.bits.receive_enable = 1;
383 mac_dev->command_config.bits.software_reset = 1;
386 while (mac_dev->command_config.bits.software_reset) {
387 if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR)
391 if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR)
392 debug("TSEMAC SW reset bit never cleared!\n");
395 static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum)
397 volatile struct alt_tse_mac *mac_dev;
398 unsigned int *mdio_regs;
402 mac_dev = priv->mac_dev;
404 /* set mdio address */
405 mac_dev->mdio_phy1_addr = priv->phyaddr;
406 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
409 data = mdio_regs[regnum];
411 value = data & 0xffff;
416 static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum,
419 volatile struct alt_tse_mac *mac_dev;
420 unsigned int *mdio_regs;
423 mac_dev = priv->mac_dev;
425 /* set mdio address */
426 mac_dev->mdio_phy1_addr = priv->phyaddr;
427 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
430 data = (unsigned int)value;
432 mdio_regs[regnum] = data;
437 /* MDIO access to phy */
438 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
439 static int altera_tse_miiphy_write(const char *devname, unsigned char addr,
440 unsigned char reg, unsigned short value)
442 struct eth_device *dev;
443 struct altera_tse_priv *priv;
444 dev = eth_get_dev_by_name(devname);
447 tse_mdio_write(priv, (uint) reg, (uint) value);
452 static int altera_tse_miiphy_read(const char *devname, unsigned char addr,
453 unsigned char reg, unsigned short *value)
455 struct eth_device *dev;
456 struct altera_tse_priv *priv;
457 volatile struct alt_tse_mac *mac_dev;
458 unsigned int *mdio_regs;
460 dev = eth_get_dev_by_name(devname);
463 mac_dev = priv->mac_dev;
464 mac_dev->mdio_phy1_addr = (int)addr;
465 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
467 *value = 0xffff & mdio_regs[reg];
475 * Also copied from tsec.c
477 /* Parse the status register for link, and then do
480 static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv)
483 * Wait if the link is up, and autonegotiation is in progress
484 * (ie - we're capable and it's not done)
486 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
488 if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE)
489 && !(mii_reg & BMSR_ANEGCOMPLETE)) {
492 puts("Waiting for PHY auto negotiation to complete");
493 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
497 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
498 puts(" TIMEOUT !\n");
503 if ((i++ % 1000) == 0)
505 udelay(1000); /* 1 ms */
506 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
510 udelay(500000); /* another 500 ms (results in faster booting) */
512 if (mii_reg & MIIM_STATUS_LINK) {
513 debug("Link is up\n");
516 debug("Link is down\n");
524 /* Parse the 88E1011's status register for speed and duplex
527 static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv)
531 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
533 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
534 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
537 puts("Waiting for PHY realtime link");
538 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
539 /* Timeout reached ? */
540 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
541 puts(" TIMEOUT !\n");
546 if ((i++ == 1000) == 0) {
550 udelay(1000); /* 1 ms */
551 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
554 udelay(500000); /* another 500 ms (results in faster booting) */
556 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
562 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
567 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
570 case MIIM_88E1011_PHYSTAT_GBIT:
572 debug("PHY Speed is 1000Mbit\n");
574 case MIIM_88E1011_PHYSTAT_100:
575 debug("PHY Speed is 100Mbit\n");
579 debug("PHY Speed is 10Mbit\n");
586 static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv)
588 uint mii_data = tse_mdio_read(priv, mii_reg);
590 if ((priv->flags >= 1) && (priv->flags <= 4))
592 else if (priv->flags == 5)
598 static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv)
600 uint mii_data = tse_mdio_read(priv, mii_reg);
602 if ((priv->flags >= 1) && (priv->flags <= 4))
609 * Returns which value to write to the control register.
610 * For 10/100, the value is slightly different
612 static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv)
614 return MIIM_CONTROL_INIT;
619 * Need to add SGMII stuff
623 static struct phy_info phy_info_M88E1111S = {
627 (struct phy_cmd[]){ /* config */
628 /* Reset and configure the PHY */
629 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
630 {MIIM_88E1111_PHY_EXT_SR, 0x848f,
631 &mii_m88e1111s_setmode_sr},
632 /* Delay RGMII TX and RX */
633 {MIIM_88E1111_PHY_EXT_CR, 0x0cd2,
634 &mii_m88e1111s_setmode_cr},
635 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
636 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
637 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
638 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
641 (struct phy_cmd[]){ /* startup */
642 /* Status is read once to clear old link state */
643 {MIIM_STATUS, miim_read, NULL},
645 {MIIM_STATUS, miim_read, &mii_parse_sr},
646 /* Read the status */
647 {MIIM_88E1011_PHY_STATUS, miim_read,
648 &mii_parse_88E1011_psr},
651 (struct phy_cmd[]){ /* shutdown */
656 /* a generic flavor. */
657 static struct phy_info phy_info_generic = {
659 "Unknown/Generic PHY",
661 (struct phy_cmd[]){ /* config */
662 {MII_BMCR, BMCR_RESET, NULL},
663 {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL},
666 (struct phy_cmd[]){ /* startup */
667 {MII_BMSR, miim_read, NULL},
668 {MII_BMSR, miim_read, &mii_parse_sr},
671 (struct phy_cmd[]){ /* shutdown */
676 static struct phy_info *phy_info[] = {
681 /* Grab the identifier of the device's PHY, and search through
682 * all of the known PHYs to see if one matches. If so, return
683 * it, if not, return NULL
685 static struct phy_info *get_phy_info(struct eth_device *dev)
687 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
688 uint phy_reg, phy_ID;
690 struct phy_info *theInfo = NULL;
692 /* Grab the bits from PHYIR1, and put them in the upper half */
693 phy_reg = tse_mdio_read(priv, MIIM_PHYIR1);
694 phy_ID = (phy_reg & 0xffff) << 16;
696 /* Grab the bits from PHYIR2, and put them in the lower half */
697 phy_reg = tse_mdio_read(priv, MIIM_PHYIR2);
698 phy_ID |= (phy_reg & 0xffff);
700 /* loop through all the known PHY types, and find one that */
701 /* matches the ID we read from the PHY. */
702 for (i = 0; phy_info[i]; i++) {
703 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
704 theInfo = phy_info[i];
709 if (theInfo == NULL) {
710 theInfo = &phy_info_generic;
711 debug("%s: No support for PHY id %x; assuming generic\n",
714 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
719 /* Execute the given series of commands on the given device's
720 * PHY, running functions as necessary
722 static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd)
727 for (i = 0; cmd->mii_reg != miim_end; i++) {
728 if (cmd->mii_data == miim_read) {
729 result = tse_mdio_read(priv, cmd->mii_reg);
731 if (cmd->funct != NULL)
732 (*(cmd->funct)) (result, priv);
735 if (cmd->funct != NULL)
736 result = (*(cmd->funct)) (cmd->mii_reg, priv);
738 result = cmd->mii_data;
740 tse_mdio_write(priv, cmd->mii_reg, result);
748 static int init_phy(struct eth_device *dev)
750 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
751 struct phy_info *curphy;
753 /* Get the cmd structure corresponding to the attached
755 curphy = get_phy_info(dev);
757 if (curphy == NULL) {
758 priv->phyinfo = NULL;
759 debug("%s: No PHY found\n", dev->name);
763 debug("%s found\n", curphy->name);
764 priv->phyinfo = curphy;
766 phy_run_commands(priv, priv->phyinfo->config);
771 static int tse_set_mac_address(struct eth_device *dev)
773 struct altera_tse_priv *priv = dev->priv;
774 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
776 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
777 dev->enetaddr[5], dev->enetaddr[4],
778 dev->enetaddr[3], dev->enetaddr[2],
779 dev->enetaddr[1], dev->enetaddr[0]);
780 mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 |
781 (dev->enetaddr[2]) << 16 |
782 (dev->enetaddr[1]) << 8 | (dev->enetaddr[0]));
784 mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 |
785 (dev->enetaddr[4])) & 0xFFFF);
787 /* Set the MAC address */
788 mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0;
789 mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1;
791 /* Set the MAC address */
792 mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0;
793 mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1;
795 /* Set the MAC address */
796 mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0;
797 mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1;
799 /* Set the MAC address */
800 mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0;
801 mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1;
805 static int tse_eth_init(struct eth_device *dev, bd_t * bd)
808 struct altera_tse_priv *priv = dev->priv;
809 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
810 volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
811 volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
812 volatile struct alt_sgdma_descriptor *rx_desc_cur =
813 (volatile struct alt_sgdma_descriptor *)&rx_desc[0];
815 /* stop controller */
816 debug("Reseting TSE & SGDMAs\n");
820 debug("Configuring PHY\n");
821 phy_run_commands(priv, priv->phyinfo->startup);
823 /* need to create sgdma */
824 debug("Configuring tx desc\n");
825 alt_sgdma_construct_descriptor_burst(
826 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
827 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
828 (unsigned int *)NULL, /* read addr */
830 0, /* length or EOP ,will change for each tx */
832 0x0, /* read fixed */
833 0x1, /* write fixed or sop */
834 0x0, /* read burst */
835 0x0, /* write burst */
838 debug("Configuring rx desc\n");
839 flush_dcache_range((unsigned long)(NetRxPackets[0]),
840 (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN);
841 alt_sgdma_construct_descriptor_burst(
842 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
843 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
844 (unsigned int)0x0, /* read addr */
845 (unsigned int *)NetRxPackets[0],
846 0x0, /* length or EOP */
848 0x0, /* read fixed */
849 0x0, /* write fixed or sop */
850 0x0, /* read burst */
851 0x0, /* write burst */
854 /* start rx async transfer */
855 debug("Starting rx sgdma\n");
856 alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur);
859 debug("Configuring TSE Mac\n");
860 /* Initialize MAC registers */
861 mac_dev->max_frame_length = PKTSIZE_ALIGN;
862 mac_dev->rx_almost_empty_threshold = 8;
863 mac_dev->rx_almost_full_threshold = 8;
864 mac_dev->tx_almost_empty_threshold = 8;
865 mac_dev->tx_almost_full_threshold = 3;
866 mac_dev->tx_sel_empty_threshold =
867 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
868 mac_dev->tx_sel_full_threshold = 0;
869 mac_dev->rx_sel_empty_threshold =
870 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
871 mac_dev->rx_sel_full_threshold = 0;
874 mac_dev->rx_cmd_stat.bits.rx_shift16 = 0;
875 mac_dev->tx_cmd_stat.bits.tx_shift16 = 0;
879 dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
881 mac_dev->command_config.image = dat;
883 /* configure the TSE core */
884 /* -- output clocks, */
885 /* -- and later config stuff for SGMII */
887 debug("Adjusting TSE to link speed\n");
888 tse_adjust_link(priv);
891 return priv->link ? 0 : -1;
895 int altera_tse_initialize(u8 dev_num, int mac_base,
896 int sgdma_rx_base, int sgdma_tx_base,
897 u32 sgdma_desc_base, u32 sgdma_desc_size)
899 struct altera_tse_priv *priv;
900 struct eth_device *dev;
901 struct alt_sgdma_descriptor *rx_desc;
902 struct alt_sgdma_descriptor *tx_desc;
903 unsigned long dma_handle;
905 dev = (struct eth_device *)malloc(sizeof *dev);
910 memset(dev, 0, sizeof *dev);
912 priv = malloc(sizeof(*priv));
918 if (sgdma_desc_size) {
919 if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) {
920 printf("ALTERA_TSE-%hu: "
921 "descriptor memory is too small\n", dev_num);
926 tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base;
928 tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX),
932 rx_desc = tx_desc + 2;
933 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc);
934 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc);
941 memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1));
942 memset(tx_desc, 0, (sizeof *tx_desc) * 2);
944 /* initialize tse priv */
945 priv->mac_dev = (volatile struct alt_tse_mac *)mac_base;
946 priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base;
947 priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base;
948 priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR;
949 priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS;
950 priv->rx_desc = rx_desc;
951 priv->tx_desc = tx_desc;
953 /* init eth structure */
955 dev->init = tse_eth_init;
956 dev->halt = tse_eth_halt;
957 dev->send = tse_eth_send;
958 dev->recv = tse_eth_rx;
959 dev->write_hwaddr = tse_set_mac_address;
960 sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num);
964 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
965 miiphy_register(dev->name, altera_tse_miiphy_read,
966 altera_tse_miiphy_write);