2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #include <fdt_support.h>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <linux/dma-mapping.h>
24 #include "altera_tse.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 static inline void alt_sgdma_construct_descriptor(
29 struct alt_sgdma_descriptor *desc,
30 struct alt_sgdma_descriptor *next,
36 int write_fixed_or_sop)
41 * Mark the "next" descriptor as "not" owned by hardware. This prevents
42 * The SGDMA controller from continuing to process the chain.
44 next->descriptor_control = next->descriptor_control &
45 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
47 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
48 desc->source = virt_to_phys(read_addr);
49 desc->destination = virt_to_phys(write_addr);
50 desc->next = virt_to_phys(next);
51 desc->bytes_to_transfer = length_or_eop;
54 * Set the descriptor control block as follows:
55 * - Set "owned by hardware" bit
56 * - Optionally set "generate EOP" bit
57 * - Optionally set the "read from fixed address" bit
58 * - Optionally set the "write to fixed address bit (which serves
59 * serves as a "generate SOP" control bit in memory-to-stream mode).
60 * - Set the 4-bit atlantic channel, if specified
62 * Note this step is performed after all other descriptor information
63 * has been filled out so that, if the controller already happens to be
64 * pointing at this descriptor, it will not run (via the "owned by
65 * hardware" bit) until all other descriptor has been set up.
67 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
69 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
71 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
72 if (write_fixed_or_sop)
73 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
74 desc->descriptor_control = val;
77 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
82 /* Wait for the descriptor (chain) to complete */
85 status = readl(®s->status);
86 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
88 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
90 debug("sgdma timeout\n");
96 writel(0, ®s->control);
98 writel(0xff, ®s->status);
103 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
104 struct alt_sgdma_descriptor *desc)
108 /* Point the controller at the descriptor */
109 writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
112 * Set up SGDMA controller to:
113 * - Disable interrupt generation
114 * - Run once a valid descriptor is written to controller
115 * - Stop on an error with any particular descriptor
117 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
118 writel(val, ®s->control);
123 static void tse_adjust_link(struct altera_tse_priv *priv,
124 struct phy_device *phydev)
126 struct alt_tse_mac *mac_dev = priv->mac_dev;
130 debug("%s: No link.\n", phydev->dev->name);
134 refvar = readl(&mac_dev->command_config);
137 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
139 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
141 switch (phydev->speed) {
143 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
144 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
147 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
148 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
151 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
152 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
155 writel(refvar, &mac_dev->command_config);
158 static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
160 struct altera_tse_priv *priv = dev_get_priv(dev);
161 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
163 alt_sgdma_construct_descriptor(
166 packet, /* read addr */
167 NULL, /* write addr */
168 length, /* length or EOP ,will change for each tx */
171 1 /* write fixed or sop */
174 /* send the packet */
175 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
176 alt_sgdma_wait_transfer(priv->sgdma_tx);
177 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
179 return tx_desc->actual_bytes_transferred;
182 static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
185 struct altera_tse_priv *priv = dev_get_priv(dev);
186 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
189 if (rx_desc->descriptor_status &
190 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
191 alt_sgdma_wait_transfer(priv->sgdma_rx);
192 packet_length = rx_desc->actual_bytes_transferred;
193 debug("recv %d bytes\n", packet_length);
194 *packetp = priv->rx_buf;
196 return packet_length;
202 static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
205 struct altera_tse_priv *priv = dev_get_priv(dev);
206 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
208 alt_sgdma_construct_descriptor(
211 NULL, /* read addr */
212 priv->rx_buf, /* write addr */
213 0, /* length or EOP */
216 0 /* write fixed or sop */
219 /* setup the sgdma */
220 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
221 debug("recv setup\n");
226 static void altera_tse_stop_mac(struct altera_tse_priv *priv)
228 struct alt_tse_mac *mac_dev = priv->mac_dev;
233 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
234 ctime = get_timer(0);
236 status = readl(&mac_dev->command_config);
237 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
239 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
240 debug("Reset mac timeout\n");
246 static void altera_tse_stop_sgdma(struct udevice *dev)
248 struct altera_tse_priv *priv = dev_get_priv(dev);
249 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
250 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
251 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
254 /* clear rx desc & wait for sgdma to complete */
255 rx_desc->descriptor_control = 0;
256 writel(0, &rx_sgdma->control);
257 ret = alt_sgdma_wait_transfer(rx_sgdma);
258 if (ret == -ETIMEDOUT)
259 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
262 writel(0, &tx_sgdma->control);
263 ret = alt_sgdma_wait_transfer(tx_sgdma);
264 if (ret == -ETIMEDOUT)
265 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
269 static void msgdma_reset(struct msgdma_csr *csr)
275 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
276 writel(MSGDMA_CSR_CTL_RESET, &csr->control);
277 ctime = get_timer(0);
279 status = readl(&csr->status);
280 if (!(status & MSGDMA_CSR_STAT_RESETTING))
282 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
283 debug("Reset msgdma timeout\n");
288 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
291 static u32 msgdma_wait(struct msgdma_csr *csr)
296 /* Wait for the descriptor to complete */
297 ctime = get_timer(0);
299 status = readl(&csr->status);
300 if (!(status & MSGDMA_CSR_STAT_BUSY))
302 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
303 debug("sgdma timeout\n");
308 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
313 static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
316 struct altera_tse_priv *priv = dev_get_priv(dev);
317 struct msgdma_extended_desc *desc = priv->tx_desc;
318 u32 tx_buf = virt_to_phys(packet);
321 writel(tx_buf, &desc->read_addr_lo);
322 writel(0, &desc->read_addr_hi);
323 writel(0, &desc->write_addr_lo);
324 writel(0, &desc->write_addr_hi);
325 writel(length, &desc->len);
326 writel(0, &desc->burst_seq_num);
327 writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
328 writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
329 status = msgdma_wait(priv->sgdma_tx);
330 debug("sent %d bytes, status %08x\n", length, status);
335 static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
338 struct altera_tse_priv *priv = dev_get_priv(dev);
339 struct msgdma_csr *csr = priv->sgdma_rx;
340 struct msgdma_response *resp = priv->rx_resp;
341 u32 level, length, status;
343 level = readl(&csr->resp_fill_level);
344 if (level & 0xffff) {
345 length = readl(&resp->bytes_transferred);
346 status = readl(&resp->status);
347 debug("recv %d bytes, status %08x\n", length, status);
348 *packetp = priv->rx_buf;
356 static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
359 struct altera_tse_priv *priv = dev_get_priv(dev);
360 struct msgdma_extended_desc *desc = priv->rx_desc;
361 u32 rx_buf = virt_to_phys(priv->rx_buf);
363 writel(0, &desc->read_addr_lo);
364 writel(0, &desc->read_addr_hi);
365 writel(rx_buf, &desc->write_addr_lo);
366 writel(0, &desc->write_addr_hi);
367 writel(PKTSIZE_ALIGN, &desc->len);
368 writel(0, &desc->burst_seq_num);
369 writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
370 writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
371 debug("recv setup\n");
376 static void altera_tse_stop_msgdma(struct udevice *dev)
378 struct altera_tse_priv *priv = dev_get_priv(dev);
380 msgdma_reset(priv->sgdma_rx);
381 msgdma_reset(priv->sgdma_tx);
384 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
386 struct altera_tse_priv *priv = bus->priv;
387 struct alt_tse_mac *mac_dev = priv->mac_dev;
390 /* set mdio address */
391 writel(addr, &mac_dev->mdio_phy1_addr);
393 value = readl(&mac_dev->mdio_phy1[reg]);
395 return value & 0xffff;
398 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
401 struct altera_tse_priv *priv = bus->priv;
402 struct alt_tse_mac *mac_dev = priv->mac_dev;
404 /* set mdio address */
405 writel(addr, &mac_dev->mdio_phy1_addr);
407 writel(val, &mac_dev->mdio_phy1[reg]);
412 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
414 struct mii_dev *bus = mdio_alloc();
417 printf("Failed to allocate MDIO bus\n");
421 bus->read = tse_mdio_read;
422 bus->write = tse_mdio_write;
423 snprintf(bus->name, sizeof(bus->name), "%s", name);
425 bus->priv = (void *)priv;
427 return mdio_register(bus);
430 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
432 struct phy_device *phydev;
433 unsigned int mask = 0xffffffff;
436 mask = 1 << priv->phyaddr;
438 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
442 phy_connect_dev(phydev, dev);
444 phydev->supported &= PHY_GBIT_FEATURES;
445 phydev->advertising = phydev->supported;
447 priv->phydev = phydev;
453 static int altera_tse_write_hwaddr(struct udevice *dev)
455 struct altera_tse_priv *priv = dev_get_priv(dev);
456 struct alt_tse_mac *mac_dev = priv->mac_dev;
457 struct eth_pdata *pdata = dev_get_plat(dev);
458 u8 *hwaddr = pdata->enetaddr;
461 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
462 (hwaddr[1] << 8) | hwaddr[0];
463 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
464 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
466 writel(mac_lo, &mac_dev->mac_addr_0);
467 writel(mac_hi, &mac_dev->mac_addr_1);
468 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
469 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
470 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
471 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
472 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
473 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
474 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
475 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
480 static int altera_tse_send(struct udevice *dev, void *packet, int length)
482 struct altera_tse_priv *priv = dev_get_priv(dev);
483 unsigned long tx_buf = (unsigned long)packet;
485 flush_dcache_range(tx_buf, tx_buf + length);
487 return priv->ops->send(dev, packet, length);
490 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
492 struct altera_tse_priv *priv = dev_get_priv(dev);
494 return priv->ops->recv(dev, flags, packetp);
497 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
500 struct altera_tse_priv *priv = dev_get_priv(dev);
501 unsigned long rx_buf = (unsigned long)priv->rx_buf;
503 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
505 return priv->ops->free_pkt(dev, packet, length);
508 static void altera_tse_stop(struct udevice *dev)
510 struct altera_tse_priv *priv = dev_get_priv(dev);
512 priv->ops->stop(dev);
513 altera_tse_stop_mac(priv);
516 static int altera_tse_start(struct udevice *dev)
518 struct altera_tse_priv *priv = dev_get_priv(dev);
519 struct alt_tse_mac *mac_dev = priv->mac_dev;
523 /* need to create sgdma */
524 debug("Configuring rx desc\n");
525 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
527 debug("Configuring TSE Mac\n");
528 /* Initialize MAC registers */
529 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
530 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
531 writel(0, &mac_dev->rx_sel_full_threshold);
532 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
533 writel(0, &mac_dev->tx_sel_full_threshold);
534 writel(8, &mac_dev->rx_almost_empty_threshold);
535 writel(8, &mac_dev->rx_almost_full_threshold);
536 writel(8, &mac_dev->tx_almost_empty_threshold);
537 writel(3, &mac_dev->tx_almost_full_threshold);
540 writel(0, &mac_dev->rx_cmd_stat);
541 writel(0, &mac_dev->tx_cmd_stat);
544 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
545 writel(val, &mac_dev->command_config);
547 /* Start up the PHY */
548 ret = phy_startup(priv->phydev);
550 debug("Could not initialize PHY %s\n",
551 priv->phydev->dev->name);
555 tse_adjust_link(priv, priv->phydev);
557 if (!priv->phydev->link)
563 static const struct tse_ops tse_sgdma_ops = {
564 .send = altera_tse_send_sgdma,
565 .recv = altera_tse_recv_sgdma,
566 .free_pkt = altera_tse_free_pkt_sgdma,
567 .stop = altera_tse_stop_sgdma,
570 static const struct tse_ops tse_msgdma_ops = {
571 .send = altera_tse_send_msgdma,
572 .recv = altera_tse_recv_msgdma,
573 .free_pkt = altera_tse_free_pkt_msgdma,
574 .stop = altera_tse_stop_msgdma,
577 static int altera_tse_probe(struct udevice *dev)
579 struct eth_pdata *pdata = dev_get_plat(dev);
580 struct altera_tse_priv *priv = dev_get_priv(dev);
581 void *blob = (void *)gd->fdt_blob;
582 int node = dev_of_offset(dev);
583 const char *list, *end;
585 void *base, *desc_mem = NULL;
586 unsigned long addr, size;
587 int parent, addrc, sizec;
591 priv->dma_type = dev_get_driver_data(dev);
592 if (priv->dma_type == ALT_SGDMA)
593 priv->ops = &tse_sgdma_ops;
595 priv->ops = &tse_msgdma_ops;
597 * decode regs. there are multiple reg tuples, and they need to
598 * match with reg-names.
600 parent = fdt_parent_offset(blob, node);
601 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
602 list = fdt_getprop(blob, node, "reg-names", &len);
606 cell = fdt_getprop(blob, node, "reg", &len);
611 addr = fdt_translate_address((void *)blob,
613 size = fdt_addr_to_cpu(cell[idx + addrc]);
614 base = map_physmem(addr, size, MAP_NOCACHE);
616 if (strcmp(list, "control_port") == 0)
617 priv->mac_dev = base;
618 else if (strcmp(list, "rx_csr") == 0)
619 priv->sgdma_rx = base;
620 else if (strcmp(list, "rx_desc") == 0)
621 priv->rx_desc = base;
622 else if (strcmp(list, "rx_resp") == 0)
623 priv->rx_resp = base;
624 else if (strcmp(list, "tx_csr") == 0)
625 priv->sgdma_tx = base;
626 else if (strcmp(list, "tx_desc") == 0)
627 priv->tx_desc = base;
628 else if (strcmp(list, "s1") == 0)
630 idx += addrc + sizec;
633 /* decode fifo depth */
634 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
636 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
639 addr = fdtdec_get_int(blob, node,
641 addr = fdt_node_offset_by_phandle(blob, addr);
642 priv->phyaddr = fdtdec_get_int(blob, addr,
645 if (priv->dma_type == ALT_SGDMA) {
646 len = sizeof(struct alt_sgdma_descriptor) * 4;
648 desc_mem = dma_alloc_coherent(len, &addr);
652 memset(desc_mem, 0, len);
653 priv->tx_desc = desc_mem;
654 priv->rx_desc = priv->tx_desc +
655 2 * sizeof(struct alt_sgdma_descriptor);
657 /* allocate recv packet buffer */
658 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
662 /* stop controller */
663 debug("Reset TSE & SGDMAs\n");
664 altera_tse_stop(dev);
667 priv->interface = pdata->phy_interface;
668 tse_mdio_init(dev->name, priv);
669 priv->bus = miiphy_get_dev_by_name(dev->name);
671 ret = tse_phy_init(priv, dev);
676 static int altera_tse_of_to_plat(struct udevice *dev)
678 struct eth_pdata *pdata = dev_get_plat(dev);
679 const char *phy_mode;
681 pdata->phy_interface = -1;
682 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
685 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
686 if (pdata->phy_interface == -1) {
687 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
694 static const struct eth_ops altera_tse_ops = {
695 .start = altera_tse_start,
696 .send = altera_tse_send,
697 .recv = altera_tse_recv,
698 .free_pkt = altera_tse_free_pkt,
699 .stop = altera_tse_stop,
700 .write_hwaddr = altera_tse_write_hwaddr,
703 static const struct udevice_id altera_tse_ids[] = {
704 { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
705 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
709 U_BOOT_DRIVER(altera_tse) = {
710 .name = "altera_tse",
712 .of_match = altera_tse_ids,
713 .ops = &altera_tse_ops,
714 .of_to_plat = altera_tse_of_to_plat,
715 .plat_auto = sizeof(struct eth_pdata),
716 .priv_auto = sizeof(struct altera_tse_priv),
717 .probe = altera_tse_probe,