1 // SPDX-License-Identifier: GPL-2.0+
3 * Atheros AR71xx / AR9xxx GMAC driver
5 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
10 #include <clock_legacy.h>
16 #include <linux/compiler.h>
17 #include <linux/err.h>
18 #include <linux/mii.h>
22 #include <mach/ath79.h>
24 DECLARE_GLOBAL_DATA_PTR;
33 /* MAC Configuration 1 */
34 #define AG7XXX_ETH_CFG1 0x00
35 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
36 #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
37 #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
38 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
39 #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
40 #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
42 /* MAC Configuration 2 */
43 #define AG7XXX_ETH_CFG2 0x04
44 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
45 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
46 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
47 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
48 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
49 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
50 #define AG7XXX_ETH_CFG2_FDX BIT(0)
52 /* MII Configuration */
53 #define AG7XXX_ETH_MII_MGMT_CFG 0x20
54 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
57 #define AG7XXX_ETH_MII_MGMT_CMD 0x24
58 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
61 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
62 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
65 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
68 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
71 #define AG7XXX_ETH_MII_MGMT_IND 0x34
72 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
73 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
75 /* STA Address 1 & 2 */
76 #define AG7XXX_ETH_ADDR1 0x40
77 #define AG7XXX_ETH_ADDR2 0x44
79 /* ETH Configuration 0 - 5 */
80 #define AG7XXX_ETH_FIFO_CFG_0 0x48
81 #define AG7XXX_ETH_FIFO_CFG_1 0x4c
82 #define AG7XXX_ETH_FIFO_CFG_2 0x50
83 #define AG7XXX_ETH_FIFO_CFG_3 0x54
84 #define AG7XXX_ETH_FIFO_CFG_4 0x58
85 #define AG7XXX_ETH_FIFO_CFG_5 0x5c
87 /* DMA Transfer Control for Queue 0 */
88 #define AG7XXX_ETH_DMA_TX_CTRL 0x180
89 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
91 /* Descriptor Address for Queue 0 Tx */
92 #define AG7XXX_ETH_DMA_TX_DESC 0x184
95 #define AG7XXX_ETH_DMA_TX_STATUS 0x188
98 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
99 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
101 /* Pointer to Rx Descriptor */
102 #define AG7XXX_ETH_DMA_RX_DESC 0x190
105 #define AG7XXX_ETH_DMA_RX_STATUS 0x194
107 /* Custom register at 0x1805002C */
108 #define AG7XXX_ETH_XMII 0x2C
109 #define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
110 #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
111 #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
112 #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
113 (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
114 #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
115 #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
116 #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
117 (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
118 #define AG7XXX_ETH_XMII_GIGE BIT(25)
120 /* Custom register at 0x18070000 */
121 #define AG7XXX_GMAC_ETH_CFG 0x00
122 #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
123 #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
124 #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
125 (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
126 #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
127 #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
128 #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
129 (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
130 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
131 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
132 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
133 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
134 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
135 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
136 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
137 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
138 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
140 #define CONFIG_TX_DESCR_NUM 8
141 #define CONFIG_RX_DESCR_NUM 8
142 #define CONFIG_ETH_BUFSIZE 2048
143 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
144 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
146 /* DMA descriptor. */
147 struct ag7xxx_dma_desc {
149 #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
150 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
151 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
152 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
158 struct ar7xxx_eth_priv {
159 struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
160 struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
161 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
162 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
165 void __iomem *phyregs;
167 struct eth_device *dev;
168 struct phy_device *phydev;
174 enum ag7xxx_model model;
178 * Switch and MDIO access
180 static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
182 struct ar7xxx_eth_priv *priv = bus->priv;
183 void __iomem *regs = priv->phyregs;
186 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
187 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
188 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
189 writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
190 regs + AG7XXX_ETH_MII_MGMT_CMD);
192 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
193 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
197 *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
198 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
203 static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
205 struct ar7xxx_eth_priv *priv = bus->priv;
206 void __iomem *regs = priv->phyregs;
209 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
210 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
211 writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
213 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
214 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
219 static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
221 struct ar7xxx_eth_priv *priv = bus->priv;
226 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
230 if (priv->model == AG7XXX_MODEL_AG933X ||
231 priv->model == AG7XXX_MODEL_AG953X) {
234 } else if (priv->model == AG7XXX_MODEL_AG934X ||
235 priv->model == AG7XXX_MODEL_AG956X) {
241 if (priv->model == AG7XXX_MODEL_AG956X)
242 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
244 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
248 phy_temp = ((reg >> 6) & 0x7) | 0x10;
249 if (priv->model == AG7XXX_MODEL_AG956X)
250 reg_temp = reg_temp_w & 0x1f;
252 reg_temp = (reg >> 1) & 0x1e;
255 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
260 if (priv->model == AG7XXX_MODEL_AG956X) {
261 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
262 reg_temp = (reg_temp_w + 1) & 0x1f;
263 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
265 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
274 static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
276 struct ar7xxx_eth_priv *priv = bus->priv;
281 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
284 if (priv->model == AG7XXX_MODEL_AG933X ||
285 priv->model == AG7XXX_MODEL_AG953X) {
288 } else if (priv->model == AG7XXX_MODEL_AG934X ||
289 priv->model == AG7XXX_MODEL_AG956X) {
295 if (priv->model == AG7XXX_MODEL_AG956X)
296 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
298 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
302 if (priv->model == AG7XXX_MODEL_AG956X) {
303 reg_temp = (reg_temp_w + 1) & 0x1f;
304 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
306 phy_temp = ((reg >> 6) & 0x7) | 0x10;
307 reg_temp = (reg >> 1) & 0x1e;
311 * The switch on AR933x has some special register behavior, which
312 * expects particular write order of their nibbles:
313 * 0x40 ..... MSB first, LSB second
314 * 0x50 ..... MSB first, LSB second
315 * 0x98 ..... LSB first, MSB second
316 * others ... don't care
318 if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
319 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
323 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
327 if (priv->model == AG7XXX_MODEL_AG956X)
328 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
330 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
334 if (priv->model == AG7XXX_MODEL_AG956X) {
335 phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
336 reg_temp = reg_temp_w & 0x1f;
339 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
347 static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
352 /* No idea if this is long enough or too long */
353 int timeout_ms = 1000;
355 /* Dummy read followed by PHY read/write command. */
356 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
359 data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
360 ret = ag7xxx_switch_reg_write(bus, 0x98, data);
364 start = get_timer(0);
366 /* Wait for operation to finish */
368 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
372 if (get_timer(start) > timeout_ms)
374 } while (data & BIT(31));
376 return data & 0xffff;
379 static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
381 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
384 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
389 ret = ag7xxx_mdio_rw(bus, addr, reg, val);
398 static void ag7xxx_dma_clean_tx(struct udevice *dev)
400 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
401 struct ag7xxx_dma_desc *curr, *next;
405 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
406 curr = &priv->tx_mac_descrtable[i];
407 next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
409 curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
410 curr->config = AG7XXX_DMADESC_IS_EMPTY;
411 curr->next_desc = virt_to_phys(next);
414 priv->tx_currdescnum = 0;
416 /* Cache: Flush descriptors, don't care about buffers. */
417 start = (u32)(&priv->tx_mac_descrtable[0]);
418 end = start + sizeof(priv->tx_mac_descrtable);
419 flush_dcache_range(start, end);
422 static void ag7xxx_dma_clean_rx(struct udevice *dev)
424 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
425 struct ag7xxx_dma_desc *curr, *next;
429 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
430 curr = &priv->rx_mac_descrtable[i];
431 next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
433 curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
434 curr->config = AG7XXX_DMADESC_IS_EMPTY;
435 curr->next_desc = virt_to_phys(next);
438 priv->rx_currdescnum = 0;
440 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
441 start = (u32)(&priv->rx_mac_descrtable[0]);
442 end = start + sizeof(priv->rx_mac_descrtable);
443 flush_dcache_range(start, end);
444 invalidate_dcache_range(start, end);
446 start = (u32)&priv->rxbuffs;
447 end = start + sizeof(priv->rxbuffs);
448 invalidate_dcache_range(start, end);
454 static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
456 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
457 struct ag7xxx_dma_desc *curr;
460 curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
462 /* Cache: Invalidate descriptor. */
464 end = start + sizeof(*curr);
465 invalidate_dcache_range(start, end);
467 if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
468 printf("ag7xxx: Out of TX DMA descriptors!\n");
472 /* Copy the packet into the data buffer. */
473 memcpy(phys_to_virt(curr->data_addr), packet, length);
474 curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
476 /* Cache: Flush descriptor, Flush buffer. */
478 end = start + sizeof(*curr);
479 flush_dcache_range(start, end);
480 start = (u32)phys_to_virt(curr->data_addr);
481 end = start + length;
482 flush_dcache_range(start, end);
484 /* Load the DMA descriptor and start TX DMA. */
485 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
486 priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
488 /* Switch to next TX descriptor. */
489 priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
494 static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
496 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
497 struct ag7xxx_dma_desc *curr;
498 u32 start, end, length;
500 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
502 /* Cache: Invalidate descriptor. */
504 end = start + sizeof(*curr);
505 invalidate_dcache_range(start, end);
507 /* No packets received. */
508 if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
511 length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
513 /* Cache: Invalidate buffer. */
514 start = (u32)phys_to_virt(curr->data_addr);
515 end = start + length;
516 invalidate_dcache_range(start, end);
518 /* Receive one packet and return length. */
519 *packetp = phys_to_virt(curr->data_addr);
523 static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
526 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
527 struct ag7xxx_dma_desc *curr;
530 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
532 curr->config = AG7XXX_DMADESC_IS_EMPTY;
534 /* Cache: Flush descriptor. */
536 end = start + sizeof(*curr);
537 flush_dcache_range(start, end);
539 /* Switch to next RX descriptor. */
540 priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
545 static int ag7xxx_eth_start(struct udevice *dev)
547 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
549 /* FIXME: Check if link up */
551 /* Clear the DMA rings. */
552 ag7xxx_dma_clean_tx(dev);
553 ag7xxx_dma_clean_rx(dev);
555 /* Load DMA descriptors and start the RX DMA. */
556 writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
557 priv->regs + AG7XXX_ETH_DMA_TX_DESC);
558 writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
559 priv->regs + AG7XXX_ETH_DMA_RX_DESC);
560 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
561 priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
566 static void ag7xxx_eth_stop(struct udevice *dev)
568 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
570 /* Stop the TX DMA. */
571 writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
572 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
575 /* Stop the RX DMA. */
576 writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
577 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
584 static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
586 struct eth_pdata *pdata = dev_get_platdata(dev);
587 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
588 unsigned char *mac = pdata->enetaddr;
589 u32 macid_lo, macid_hi;
591 macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
592 macid_lo = (mac[5] << 16) | (mac[4] << 24);
594 writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
595 writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
600 static void ag7xxx_hw_setup(struct udevice *dev)
602 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
605 setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
606 AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
607 AG7XXX_ETH_CFG1_SOFT_RST);
611 writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
612 priv->regs + AG7XXX_ETH_CFG1);
614 if (priv->interface == PHY_INTERFACE_MODE_RMII)
615 speed = AG7XXX_ETH_CFG2_IF_10_100;
617 speed = AG7XXX_ETH_CFG2_IF_1000;
619 clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
620 AG7XXX_ETH_CFG2_IF_SPEED_MASK,
621 speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
622 AG7XXX_ETH_CFG2_LEN_CHECK);
624 writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
625 writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
627 writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
628 setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
629 writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
630 writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
631 writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
632 writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
635 static int ag7xxx_mii_get_div(void)
637 ulong freq = get_bus_freq(0);
639 switch (freq / 1000000) {
640 case 150: return 0x7;
641 case 175: return 0x5;
642 case 200: return 0x4;
643 case 210: return 0x9;
644 case 220: return 0x9;
649 static int ag7xxx_mii_setup(struct udevice *dev)
651 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
652 int i, ret, div = ag7xxx_mii_get_div();
655 if (priv->model == AG7XXX_MODEL_AG933X) {
656 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
657 if (priv->interface == PHY_INTERFACE_MODE_RMII)
661 if (priv->model == AG7XXX_MODEL_AG934X)
663 else if (priv->model == AG7XXX_MODEL_AG953X)
665 else if (priv->model == AG7XXX_MODEL_AG956X)
668 if (priv->model == AG7XXX_MODEL_AG934X ||
669 priv->model == AG7XXX_MODEL_AG953X ||
670 priv->model == AG7XXX_MODEL_AG956X) {
671 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
672 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
673 writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
677 for (i = 0; i < 10; i++) {
678 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
679 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
680 writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
682 /* Check the switch */
683 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®);
687 if (reg != 0x18007fff)
696 static int ag933x_phy_setup_wan(struct udevice *dev)
698 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
700 /* Configure switch port 4 (GMAC0) */
701 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
704 static int ag933x_phy_setup_lan(struct udevice *dev)
706 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
710 /* Reset the switch */
711 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
715 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
720 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
723 } while (reg & BIT(31));
725 /* Configure switch ports 0...3 (GMAC1) */
726 for (i = 0; i < 4; i++) {
727 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
732 /* Enable CPU port */
733 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
737 for (i = 0; i < 4; i++) {
738 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
744 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
748 /* Disable Atheros header */
749 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
753 /* Tag priority mapping */
754 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
758 /* Enable ARP packets to the CPU */
759 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
763 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
770 static int ag953x_phy_setup_wan(struct udevice *dev)
774 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
776 /* Set wan port connect to GE0 */
777 ret = ag7xxx_switch_reg_read(priv->bus, 0x8, ®);
781 ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
785 /* Configure switch port 4 (GMAC0) */
786 ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
793 static int ag953x_phy_setup_lan(struct udevice *dev)
795 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
799 /* Reset the switch */
800 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
804 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
809 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
812 } while (reg & BIT(31));
814 ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
819 ret = ag7xxx_switch_reg_read(priv->bus, 0x4, ®);
823 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
827 /* Configure switch ports 0...4 (GMAC1) */
828 for (i = 0; i < 5; i++) {
829 ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
834 for (i = 0; i < 5; i++) {
835 ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
841 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
845 /* Disable Atheros header */
846 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
850 /* Tag priority mapping */
851 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
855 /* Enable ARP packets to the CPU */
856 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
860 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
864 /* Enable broadcast packets to the CPU */
865 ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, ®);
869 ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
876 static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
878 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
881 if (priv->model == AG7XXX_MODEL_AG953X ||
882 priv->model == AG7XXX_MODEL_AG956X) {
883 ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
886 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
887 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
888 ADVERTISE_PAUSE_ASYM);
893 if (priv->model == AG7XXX_MODEL_AG934X) {
894 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
898 } else if (priv->model == AG7XXX_MODEL_AG956X) {
899 ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
905 if (priv->model == AG7XXX_MODEL_AG953X ||
906 priv->model == AG7XXX_MODEL_AG956X)
907 return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
908 BMCR_ANENABLE | BMCR_RESET);
910 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
911 BMCR_ANENABLE | BMCR_RESET);
914 static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
916 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
920 if (priv->model == AG7XXX_MODEL_AG953X ||
921 priv->model == AG7XXX_MODEL_AG956X) {
923 ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, ®);
927 } while (reg & BMCR_RESET);
930 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
934 } while (ret & BMCR_RESET);
940 static int ag933x_phy_setup_common(struct udevice *dev)
942 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
946 if (priv->model == AG7XXX_MODEL_AG933X)
948 else if (priv->model == AG7XXX_MODEL_AG934X ||
949 priv->model == AG7XXX_MODEL_AG953X ||
950 priv->model == AG7XXX_MODEL_AG956X)
955 if (priv->interface == PHY_INTERFACE_MODE_RMII) {
956 ret = ag933x_phy_setup_reset_set(dev, phymax);
960 ret = ag933x_phy_setup_reset_fin(dev, phymax);
964 /* Read out link status */
965 if (priv->model == AG7XXX_MODEL_AG953X)
966 ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, ®);
968 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
976 for (i = 0; i < phymax; i++) {
977 ret = ag933x_phy_setup_reset_set(dev, i);
982 for (i = 0; i < phymax; i++) {
983 ret = ag933x_phy_setup_reset_fin(dev, i);
988 for (i = 0; i < phymax; i++) {
989 /* Read out link status */
990 if (priv->model == AG7XXX_MODEL_AG953X ||
991 priv->model == AG7XXX_MODEL_AG956X)
992 ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, ®);
994 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
1002 static int ag934x_phy_setup(struct udevice *dev)
1004 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1008 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1011 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
1014 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
1017 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
1020 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1024 /* AR8327/AR8328 v1.0 fixup */
1025 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
1028 if ((reg & 0xffff) == 0x1201) {
1029 for (i = 0; i < 5; i++) {
1030 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
1033 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
1036 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
1039 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
1045 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®);
1049 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
1056 static int ag956x_phy_setup(struct udevice *dev)
1058 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1062 ret = ag7xxx_switch_reg_read(priv->bus, 0x0, ®);
1065 if ((reg & 0xffff) >= 0x1301)
1070 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
1074 ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
1078 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1083 * Values suggested by the switch team when s17 in sgmii
1084 * configuration. 0x10(S17_PWS_REG) = 0x602613a0
1086 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
1090 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1094 /* AR8337/AR8334 v1.0 fixup */
1095 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
1098 if ((reg & 0xffff) == 0x1301) {
1099 for (i = 0; i < 5; i++) {
1100 /* Turn on Gigabit clock */
1101 ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
1104 ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
1113 static int ag7xxx_mac_probe(struct udevice *dev)
1115 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1118 ag7xxx_hw_setup(dev);
1119 ret = ag7xxx_mii_setup(dev);
1123 ag7xxx_eth_write_hwaddr(dev);
1125 if (priv->model == AG7XXX_MODEL_AG933X) {
1126 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1127 ret = ag933x_phy_setup_wan(dev);
1129 ret = ag933x_phy_setup_lan(dev);
1130 } else if (priv->model == AG7XXX_MODEL_AG953X) {
1131 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1132 ret = ag953x_phy_setup_wan(dev);
1134 ret = ag953x_phy_setup_lan(dev);
1135 } else if (priv->model == AG7XXX_MODEL_AG934X) {
1136 ret = ag934x_phy_setup(dev);
1137 } else if (priv->model == AG7XXX_MODEL_AG956X) {
1138 ret = ag956x_phy_setup(dev);
1146 return ag933x_phy_setup_common(dev);
1149 static int ag7xxx_mdio_probe(struct udevice *dev)
1151 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1152 struct mii_dev *bus = mdio_alloc();
1157 bus->read = ag7xxx_mdio_read;
1158 bus->write = ag7xxx_mdio_write;
1159 snprintf(bus->name, sizeof(bus->name), dev->name);
1161 bus->priv = (void *)priv;
1163 return mdio_register(bus);
1166 static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
1170 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
1172 debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
1176 offset = fdt_parent_offset(gd->fdt_blob, offset);
1178 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
1183 offset = fdt_parent_offset(gd->fdt_blob, offset);
1185 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
1193 static int ag7xxx_eth_probe(struct udevice *dev)
1195 struct eth_pdata *pdata = dev_get_platdata(dev);
1196 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1197 void __iomem *iobase, *phyiobase;
1200 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1201 ret = ag7xxx_get_phy_iface_offset(dev);
1204 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
1206 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
1207 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
1209 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
1210 __func__, iobase, phyiobase, priv);
1211 priv->regs = iobase;
1212 priv->phyregs = phyiobase;
1213 priv->interface = pdata->phy_interface;
1214 priv->model = dev_get_driver_data(dev);
1216 ret = ag7xxx_mdio_probe(dev);
1220 priv->bus = miiphy_get_dev_by_name(dev->name);
1222 ret = ag7xxx_mac_probe(dev);
1223 debug("%s, ret=%d\n", __func__, ret);
1228 static int ag7xxx_eth_remove(struct udevice *dev)
1230 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1233 mdio_unregister(priv->bus);
1234 mdio_free(priv->bus);
1239 static const struct eth_ops ag7xxx_eth_ops = {
1240 .start = ag7xxx_eth_start,
1241 .send = ag7xxx_eth_send,
1242 .recv = ag7xxx_eth_recv,
1243 .free_pkt = ag7xxx_eth_free_pkt,
1244 .stop = ag7xxx_eth_stop,
1245 .write_hwaddr = ag7xxx_eth_write_hwaddr,
1248 static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
1250 struct eth_pdata *pdata = dev_get_platdata(dev);
1251 const char *phy_mode;
1254 pdata->iobase = devfdt_get_addr(dev);
1255 pdata->phy_interface = -1;
1257 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1258 ret = ag7xxx_get_phy_iface_offset(dev);
1262 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
1264 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1265 if (pdata->phy_interface == -1) {
1266 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1273 static const struct udevice_id ag7xxx_eth_ids[] = {
1274 { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
1275 { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
1276 { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
1277 { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
1281 U_BOOT_DRIVER(eth_ag7xxx) = {
1282 .name = "eth_ag7xxx",
1284 .of_match = ag7xxx_eth_ids,
1285 .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
1286 .probe = ag7xxx_eth_probe,
1287 .remove = ag7xxx_eth_remove,
1288 .ops = &ag7xxx_eth_ops,
1289 .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
1290 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1291 .flags = DM_FLAG_ALLOC_PRIV_DMA,